What are Flip-Flops?

The flip-flops are basically the circuits that maintain a certain state unless and until directed by
the input for changing that state. We can construct a basic flip-flop using four-NOR and four-
NAND gates. A flip-flop in digital electronics is a circuit with two stable states that can be used
to store binary data. The stored data can be changed by applying varying inputs. Flip-flops and
latches are fundamental building blocks of digital electronics systems used in computers,
communications, and many other types of systems. Both are used as data storage elements. It is
the basic storage element in sequential logic. But first, let’s clarify the difference between a latch
and flip-flops.
Flip-Flop v/s Latch

The primary difference between a latch and a flip-flop is a gating or clocking mechanism. In
Simple words. Flip Flops are edge-triggered and a latch is level-triggered. If you are confused
between latch and flip-flop, then you should check this detailed article where we discussed
the difference between Latch and Flip Flop. For example, let us talk about SR latch and SR flip-
flops. In this circuit when you Set S as active, the output Q will be high and Q’ will be Low. This
is irrespective of anything else. (This is an active-low circuit; so active here means low, but for
an active high circuit, active would mean high)

A flip-flop, on the other hand, is a synchronous Circuit and is also known as a gated or clocked
SR latch.
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In this circuit diagram, the output is changed (i.e. the stored data is changed) only when you give
an active clock signal. Otherwise, even if the S or R is active, the data will not change. Let’s
understand the flip-flop in detail with the truth table and circuits.

Types

There are basically 4 types of flip-flops:

1. SR Flip-Flop
2. JK Flip-Flop
3. D Flip-Flop
4. T Flip-Flop

SR Flip Flop

This is the most common flip-flop among all. This simple flip-flop circuit has a set input (S) and
a reset input (R). In this system, when you Set “S” as active, the output “Q” would be high, and
“Q ‘” would be low. Once the outputs are established, the wiring of the circuit is maintained until
“S” or “R” go high, or power is turned off. As shown above, it is the simplest and easiest to
understand. The two outputs, as shown above, are the inverse of each other. The truth table of
SR Flip-Flop is highlighted below.

S R Q Q’

0 0 0 1

0 1 0 1

1 0 1 0

1 1 ∞ ∞

JK Flip-Flop

Due to the undefined state in the SR flip-flops, another flip-flop is required in electronics. The
JK flip-flop is an improvement on the SR flip-flop where S=R=1 is not a problem.

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JK Flip Flop Circuit

The input condition of J=K=1, gives an output inverting the output state. However, the outputs
are the same when one tests the circuit practically. In simple words, If J and K data input are
different (i.e. high and low), then the output Q takes the value of J at the next clock edge. If J and
K are both low, then no change occurs. If J and K are both high at the clock edge, then the output
will toggle from one state to the other. JK Flip-Flops can function as Set or Reset Flip-flops.

Truth Table:

J K Q Q’

0 0 0 0

0 1 0 0

1 0 0 1

1 1 0 1

0 0 1 1

0 1 1 0

1 0 1 1

1 1 1 0

D Flip-Flop

D flip-flop is a better alternative that is very popular with digital electronics. They are commonly
used for counters and shift registers and input synchronization.

D Flip-Flop

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In the D flip-flops, the output can only be changed at the clock edge, and if the input changes at
other times, the output will be unaffected.

Truth Table:

Clock D Q Q’

↓»0 0 0 1

↑»1 0 0 1

↓»0 1 0 1

↑»1 1 1 0

The change of state of the output is dependent on the rising edge of the clock. The output (Q) is
the same as the input and can only change at the rising edge of the clock.

T Flip-Flop

A T flip-flop is like a JK flip-flop. These are basically single-input versions of JK flip-flops. This
modified form of the JK is obtained by connecting inputs J and K together. It has only one input
along with the clock input.

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These flip-flops are called T flip-flops because

of their ability to complement their state i.e. Toggle, hence they are named Toggle flip-flops.

T Q Q (t+1)

0 0 0

1 0 1

0 1 1

1 1 0

Applications

These are the various types of flip-flops being used in digital electronic circuits and the
applications of Flip-flops are as specified below.

 Counters
 Frequency Dividers
 Shift Registers
 Storage Registers

Applications of Flip-Flops
In this article, we have summed up the different types of flip-flops that we use in digital
electronic circuits. You can find the various applications of the flip-flops below:

 Frequency dividers
 Counters
 Storage registers
 Shift registers
 Data storage
 Bounce elimination switch
 Latch
 Data transfer
 Memory

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 Registers

Practice Questions on Flip-Flops

1. We can construct a basic S-R flip-flop by cross-coupling which of these basic logic gates?
A. OR or AND gates
B. XNOR or XOR gates
C. NAND or NOR gates
D. NOR or AND gates
Answer – C. NAND or NOR gates
2. The sequential circuits are of how many types?
A. 5
B. 4
C. 3
D. 2
Answer – D. 2
3. Which of these operations are faster as compared to the other options?
A. Sequential Circuits
B. Combinational Circuits
C. Flip-flops
D. Latches
Answer: B. Combinational Circuits
4. The sequential circuits are also known as:
A. Latch
B. Flip-flop
C. Adder
D. Strobe
Answer – A. Latch

Frequently Asked Questions

How many flip-flop types are there? What are they?

There are four basic types of flip-flops. They are:

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 Latch or Set-Reset (SR) flip-flop

 JK flip-flop
 T (Toggle) flip-flop
 D (Delay or Data) flip-flop

Is SR flip-flop and RS flip-flop the very same?

Theoretically, the RS and SR flip-flops are the same. Whenever both inputs of S & R are fairly
high, the output happens to be indeterminate. In PLC, as well as other programming
environments, we need to allocate determinate outputs to all of the conditions of a flip-flop.
Thus, the SR and the RS flip-flops are designed.

Why is the NAND gate used in a flip-flop?

The word flip-flop means that we can easily “FLIP” it either into a given logic state or “FLOP” it
back into another one. We use the basic RS Flip Flop NAND gate circuit to store the
information, and thus, it supplies feedback from both the outputs back to the inputs.

What is the primary difference between the SR latch and the SR flip-flop?
The primary difference between a flip-flop and a latch is a clocking or gating mechanism. A flip
flop is synchronous and known as a gated or clocked SR latch.

What is a clock in a flip-flop?

The clock pulses in flip-flops refer to the time-varying voltage signal that is applied so as to
control the operation (or triggering) of a flip-flop. For example, if we have a clock pulse with a 1
Hz frequency, the voltage that it would supply would oscillate between A and B Volts (A and B
refer to any DC voltages), and this type of change appears every half of a second.
Latches

A Latch is a special type of logical circuit. The latches have low and high two stable states. Due
to these states, latches also refer to as bistable-multivibrators. A latch is a storage device that
holds the data using the feedback lane. The latch stores 1 -bit until the device set to 1. The latch
changes the stored data and constantly trials the inputs when the enable input set to 1. Based on
the enable signal, the circuit works in two states. When the enable input is high, then both the
inputs are low, and when the enable input is low, both the inputs are high.

Types of Latches

There are various types of latches used in digital circuits which are as follows:

o SR Latch
o Gated S-R Latch
o D latch

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o Gated D Latch
o JK Latch
o T Latch.

SR Latch

The SR latch is a special type of asynchronous device which works separately for control signals.
It depends on the S-states and R-inputs. The SR latch design by connecting two NOR gates

with a cross loop connection. The SR latch can also be designed using the NAND gate
.Below are the circuit diagram and the truth table of the SR latch.

Truth Table

S R Q Q'

0 0 latch Latch

0 1 0 1

1 0 1 0

1 1 0 0

Circuit Diagram 

Gated SR Latch

A Gated SR Latch is a special type of SR Latch having three inputs, i.e., Set, Reset, and
Enable. The enable input must be active for the SET and RESET inputs to be
effective.The ENABLE input of gated SR Latch enables the operation of the SET and RESET
inputs.This ENABLE input connects with a switch. The Set-Reset inputs are enabled when this
switch is on. Otherwise, all the changes are ignored in the set and reset inputs. Below are the
circuit diagram and the truth table of the Gated SR latch.

Truth Table Circuit Diagram

D Latch

The D latch is the same as D flip flop

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The only difference between these two is the ENABLE input. The output of the latch is the same
as the input passed to the Data input when the ENABLE input set to 1. At that time, the latch is
open, and the path is transparent from input to output. If the ENABLE input is set to 0, the D
latch's output is the last value of the latch, i.e., independent from the input D, and the latch is
closed. Below are the circuit diagram and the truth table of the D latch.

Truth Table  Circuit Diagram

Gated D Latch

The Gated D Latch is another special type of gated latch having two inputs, i.e., DATA and
ENABLE. When the enable input set to 1, the input is the same as the Data input.
Otherwise, there is no change in output. We can design the gated D latch by using gated SR
latch. The set and reset inputs are connected together using an inverter. By doing this, the
outputs will be opposite to each other. Below is the circuit diagram of the Gated D latch.

Circuit Diagram

JK Latch

The JK Latch is the same as the SR Latch. In JK latch, the unclear states are removed, and
the output is toggled when the JK inputs are high. The only difference between SR latch JK
latches is that there is no output feedback towards the inputs in the SR latch, but it is
present in the JK latch. The circuit diagram and truth table of the JK latch are as follows:

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Truth Table Circuit Diagram

T Latch

The T latch forms by shorting the JK latch inputs. The output of the T latch toggle when
the input set to 1 or high. Below is the circuit diagram of the T latch.

Circuit Diagram

What is the Difference Between Latch and Flip Flop

The major difference between flip-flop and latch is that the flip-flop is an edge-triggered type of
memory circuit while the latch is a level-triggered type. It means that the output of a latch
changes whenever the input changes. On the other hand, the latch only changes its state
whenever the control signal goes from low to high and high to low.

What is a Flip-Flop?
A flip-flop is a digital memory circuit that stores one bit of data. They are the primary blocks of
the most sequential circuits. It is also called one-bit memory, binary, or a bistable multivibrator.
Flip-flops act as memory elements in a sequential circuit. You can obtain the output in the
sequential circuits using a flip-flop, a combinational circuit, or both.
A flip-flop state repeatedly changes at an active state of the clock pulses. They remain unaffected
even when the clock pulse does not stay active. The clocked flip-flops particularly act as the
memory elements of the synchronous sequential circuit- while the un-clocked ones (latches)
function as the memory elements of asynchronous sequential circuits.
There are mainly four types of flip-flops:

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 JK Flip-Flop
 SR (Set-Reset) Flip-Flop
 Data or Delay (D) Flip-Flop
 Toggle (T) Flip-Flop

What Is a Latch?
A latch is an electronic device that changes its output immediately on the basis of the applied
input. One can use it to store either 0 or 1 at a specified time. A latch contains two inputs- SET
and RESET, and it also has two outputs. They complement each other. One can use a latch for
storing one bit of data. It is a memory device- just like the flip-flop. But it is not synchronous,
and it does not work on the edges of the clock like the flip-flop.
Difference Between Flip-flop and Latch

Parameter Flip-Flop Latch

Basic Principle Flip-flop utilizes an edge triggering Latch follows a level triggering approach.
approach.

Clock Signal The clock signal is present. The clock signal is absent.

Designed Using You can design it using Latches along You can design it using Logic gates.
with a clock.

Sensitivity Flip-flop is sensitive to the applied Latches are sensitive to the applied input
input and the clock signal. signal- only when enabled.

Operating Speed It has a slow operating speed. It has comparatively fast operating speed.

Classification You can classify a flip-flop into a A user cannot classify the Latch this way.
synchronous or asynchronous flip-
flop.

Working Flip-Flops work using the binary input Latches operate only using binary inputs.
and the clock signal.

Power Requirement It requires more power. It requires comparatively less power.

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Analysis of Circuit It is quite easy to perform circuit Analyzing the circuit is quite complex.
analysis.

Type of Operation Flip-flop performs Synchronous Latch performs Asynchronous operations.

Performed operations.

Robustness Flip-flops are comparatively more Latches are comparatively less robust.
robust.

Dependency of Operation The operation relies on the present The operation depends on the present and
and past input bits along with the past past input along with the past output binary
output and clock pulses. values.

Usage as a Register A flip-flop is capable of working as a A latch cannot serve as a register as the
register as it contains clock signals in register requires further advanced electronic
its input. circuits (EC). Time also plays an essential
role here.

Types J-K, S-R, D, and T Flip-flops. J-K, S-R, D, and T Latches.

Area Required It requires more area. It requires comparatively less area.

Uses They constitute the building blocks of Users can utilize these for designing
many sequential circuits such as sequential circuits. But they are still not
counters. generally preferred.

Input and Output A flip-flop checks the inputs. It only The latch responds to the changes in inputs
changes the output at times defined by continuously as soon as it checks the inputs.
any control signal like the clock
signal.

Synchronicity A flip-flop is synchronous. It works A latch is asynchronous. It does not work

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based on the clock signal. based on the time signal.

Faults Flip-Flops stay protected against any The latches are responsive to any occurring
fault. faults on the enable pin.

Difference between JK flip flop and D flip flop?

JK flip-flop is same as S-R flip-flop but without any restricted input. The restricted input of S-R
latch toggles the output of JK flip-flop. JK flip-flop is modified version of D flip-flop. We
attach a combinational circuit to a D flip-flop to convert it into JK flip-flop.
Asynchronous circuit
Asynchronous circuit (clockless or self-timed circuit) is a sequential digital logic circuit that
does not use a global clock circuit or signal generator to synchronize its components.
Instead, the components are driven by a handshaking circuit which indicates a completion of a
set of instructions.

1. Introduction
 Asynchronous sequential circuit works without Clock.
 Asynchronous sequential circuit works based on memory concept
 Feedback is present as delay line, and Delay of feedback is not predictable so application of
asynchronous sequential circuit is limited.
 Changes in inputs cause changes in output (State changes)
 Asynchronous sequential circuit design is more complicated than synchronous sequential
circuit design
 The memory of the asynchronous sequential circuit may include flip-flops or time-delay
devices.
2. Block diagram

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 Here changes in inputs cause changes in output (State changes)

 Here in Block Diagram, Clock is not used but output is directly connected to inputs through
some calculated delay (Feedback)
 when Inputs changes then output changes and like this stability is achieved
 When stability is achieved that state is called stable state. Rests of states are unstable states.
3. Modes of asynchronous sequential circuit
 Fundamental Mode
o Only One input can be change at a time after stable state
o This mode is widely used for design.
 Pulse mode: - More than one input can be change at a time after stable state.
4. Design Flow
o Nomenclature
o (a),0 :- Here a is a stable state and 0 is output
o a  :-  Here a is unstable state and output remain same as previous
o Write word statement from problem statement
o Derive primitive flow table
o Design merger diagram
o Adjacent diagram
o Derive synthesis equation
7. Application
 Asynchronous sequential circuits are useful when circuit system must respond quickly
without waiting for clock.
 Asynchronous sequential circuit is important for small circuit which behaves
independently and contain few components
8. Advantages
 Robust handling of metastability and higher performance compare to synchronous
sequential circuit.
 Faster than Synchronous sequential circuit
 Lower power consumption
 Clock driver can be removed in this case because Clock is not used here so power
consumption of clock drivers and controller can be avoided.
 few assumptions are needed in manufacture process
 system speed adapts changes in environment and voltage levels
 Designing of power distribution network is easy here because here leakage current will
be less compare to synchronous sequential circuit
9. Disadvantages
 When some encoding is performed then asynchronous circuit requires more area then
synchronous circuit and because of the same power consumption may increase
 Area of circuit is increased. No. of Transistors may be double here because of addition of
completion detection circuit and design for test circuit
  synchronous sequential circuits are easier to test and debug compare to asynchronous
sequential circuit

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  Performance of asynchronous sequential circuits may be reducing in architecture which

includes complex data paths and feedbacks.
  Race conditions are generated internally and cannot be handling by outside.
Synchronous circuit
In digital electronics, a synchronous circuit is a digital circuit in which the changes in the
state of memory elements are synchronized by a clock signal. In a sequential digital logic
circuit, data are stored in memory devices called flip-flops or latches.

Synchronous Mode.
In synchronous mode, the requestor (in this case, the operation) waits for a reply from the
server in the form of an output parameter. On the Workstation Objects window, synchronous
services are shown with input and output parameters. Synchronous objects are the default view.
What are the advantages of synchronous circuits?
In addition, synchronous designs can be tested more easily and run statically, with the clock
input driven by a test signal. They can be made virtually immune to noise. Therefore, finding
errors in a design will not be a cross between identifying logic errors and tracking down noise-
induced errors.

What is the major advantage of the synchronous circuit?

The state of the synchronous circuit only changes on clock pulses. At each cycle, the next state is
determined by the current state and the value of the input signals when the clock pulse occurs.
The main advantage of synchronous logic is its simplicity.

Counters in Digital Logic

A Counter is a device which stores (and sometimes displays) the number of times a particular
event or process has occurred, often in relationship to a clock signal. Counters are used in digital
electronics for counting purpose, they can count specific event happening in the circuit. For
example, in UP counter a counter increases count for every rising edge of clock. Not only
counting, a counter can follow the certain sequence based on our design like any random
sequence 0,1,3,2… .They can also  be designed with the help of flip flops. They are used as
frequency dividers where the frequency of given pulse waveform is divided. Counters are
sequential circuit that count the number of pulses can be either in binary code or BCD form. The
main properties of a counter are timing , sequencing , and counting.

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Counter works in two mode:

 Up counter
 Down counter
Counter Classification
Counters are broadly divided into two categories
 Asynchronous counter
 Synchronous counter
Asynchronous Counter
In asynchronous counter we don’t use universal clock, only first flip flop is driven by main clock
and the clock input of rest of the following flip flop is driven by output of previous flip flops. We
can understand it by following diagram-

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It is evident from timing diagram that Q0 is changing as soon as the rising edge of clock pulse is
encountered, Q1 is changing when rising edge of Q0 is encountered(because Q0 is like clock
pulse for second flip flop) and so on. In this way ripples are generated through Q0,Q1,Q2,Q3
hence it is also called RIPPLE counter. A ripple counter is a cascaded arrangement of flip flops
where the output of one flip flop drives the clock input of the following flip flop.
Synchronous Counter
Unlike the asynchronous counter, synchronous counter has one global clock which drives each
flip flop so output changes in parallel. The one advantage of synchronous counter over
asynchronous counter is, it can operate on higher frequency than asynchronous counter as it does
not have cumulative delay because of same clock is given to each flip flop.
Timing Diagram synchronous counter

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From circuit diagram we see that Q0 bit gives response to each falling edge of clock while Q1 is
dependent on Q0, Q2 is dependent on Q1 and Q0 , Q3 is dependent on Q2,Q1 and Q0.
Decade Counter
A decade counter counts ten different states and then reset to its initial states. A simple decade
counter will count from 0 to 9 but we can also make the decade counters which can go through
any ten states between 0 to 15(for 4 bit counter).
Truth Table of Decade Counter
Clock pulse Q3 Q2 Q1 Q0
0 0 0 0 0
1 0 0 0 1

2 0 0 1 0

3 0 0 1 1

4 0 1 0 0

5 0 1 0 1

6 0 1 1 0

7 0 1 1 1

8 1 0 0 0

9 1 0 0 1

10 0 0 0 0

Decade counter circuit diagram

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We see from circuit diagram that we have used nand gate for Q3 and Q1 and feeding this to clear
input line because binary representation of 10 is 1010.

And we see Q3 and Q1 are 1 here, if we give NAND of these two bits to clear input then counter
will be clear at 10 and again start from beginning.

Important point: Number of flip flops used in counter are always greater than equal to (log2
n) where n=number of states in counter.

Q2. The control signal functions of a 4-bit binary counter are given below (where X is
“don’t care”)
The counter is connected as follows:

Solution:

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Initially A1 A2 A3 A4 =0000 

Clr=A1 and A3 

So when A1 and A3 both are 1 it again goes to 0000 

Hence 0000(init.) -> 0001(A1 and A3=0)->0010 (A1 and A3=0) -> 0011(A1 and A3=0) -> 0100
(A1 and A3=1)[ clear condition satisfied] ->0000(int) so it goes through 0->1->2->3->4 

MCQS.

1. How many bits must each word have in one-to-four line de-multiplexer to be
implemented using a memory?

A. 8 bit
B. 4 bits
C. 2 bits
D. 1 bits

Answer - Click Here:

D
2. The total amount of memory is depends upon _________

A. The organization of memory

B. The size of the address bus of the microprocessor
C. The size of the decoding unit
D. The structure of memory

Answer - Click Here:

B
 

3. _____________ can be determined the Instability condition.

A. table
B. logic diagram
C. map
D. graph

Answer - Click Here:

B
 

4. If we add an inverter at the output of AND gate, what function is produced?

A. NAND
B. XOR

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C. OR
D. NOR

Answer - Click Here:

A
5. Which is also known as coincidence detector?

A. OR gate
B. NOT gate
C. AND gate
D. NAND gate

Answer - Click Here:

C
6. Transition table include ________________

A. squares
B. oval
C. rectangles
D. circles

Answer - Click Here:

A
 

7. For every possible combination of logical states in the inputs, which table shows the
logical state of a digital circuit output?
A. Function table
B. ASCII table
C. Truth table
D. Routing table

Answer - Click Here:

C
8. Stack is an acronym for _______________

A. Flash Memory
B. LIFO memory
C. FIFO memory
D. Bust Flash Memory

Answer - Click Here:

B
 

9. When an Asynchronous sequential circuit changes two or more binary states variables a
Condition occurs called ____________

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A. Race condition
B. deadlock condition
C. Running condition
D. None of these

Answer - Click Here:

A
 

10. A positive OR gate is also a negative

A. NAND gate
B. OR gate
C. NOR gate
D. AND gate

Answer - Click Here:

D
11. Sum of two octal numbers

“71” and “36” = __________________

A. 123
B. 127
C. 213
D. 345
Answer - Click Here:
B
12. Time delay device is memory element of______________

A. asynchronous circuits
B. synchronous circuits
C. clocked flip-flops
D. Unlocked flip-flops

Answer - Click Here:

A

SET 2: DLD MCQs

1. Boolean algebra is also called

A. arithmetic algebra
B. switching algebra
C. Both A & B
D. linear algebra
E. algebra
F. None of there

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Answer - Click Here:

B
2. Boolean function must be brought into________ To perform product of max terms

A. OR terms
B. AND terms
C. Both A & B
D. NOT terms
E. NAND terms
F. None of these

Answer - Click Here:

A
3. The binary number 10101 is equivalent to the decimal number …………..

A. 12
B. 19
C. Both A & B
D. 27
E. 21
F. None of these

Answer - Click Here:

E
4. The universal gate is ………………

A. OR gate
B. NAND gate
C. Both A & B
D. AND gate
E. None of the above
F. None of these

Answer - Click Here:

B
5. According to boolean algebra absorption law, which of the following is correct?

A. (x+y)=xy
B. x+xy=x
C. Both A & B
D. xy+y=x
E. x+y=y
F. None of these

Answer - Click Here:

D
6. A Boolean function may be transformed into

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A. logical graph
B. logical diagram
C. Both A & B
D. map
E. matrix
F. None of these

Answer - Click Here:

B
7. The inverter is ……………

A. OR gate
B. NOT gate
C. Both A & B
D. AND gate
E. None of the above

Answer - Click Here:

B
8. The resulting circuit of a NAND gate are connected together is_______

A. AND gate
B. OR gate
C. Both A & B
D. NOT gate
E. None of the above

Answer - Click Here:

D
9. x*y = y*x is the

A. inverse property
B. commutative law
C. Both A & B
D. associative law
E. identity element
F. None of these

Answer - Click Here:

E
10. Minterms are also called

A. standard product
B. standard sum
C. Both A & B
D. standard division
E. standard subtraction
F. None of these
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Notes Digital logic design

Answer - Click Here:

A
11. OR gate and __________ will form The NOR gate?

A. NAND gate
B. AND gate
C. Both A & B
D. NOT gate
E. None of the above

Answer - Click Here:

D
12. The NAND gate is AND gate followed by …………………

A. OR gate
B. NOT gate
C. Both A & B
D. AND gate
E. None of the above

Answer - Click Here:

B
13. Max terms are also called

A. standard product
B. standard sum
C. Both A & B
D. standard division
E. standard subtraction
F. None of these

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B
14. In Boolean algebra Multiplicative inverse is

A. 1
B. 0
C. Both A & B
D. 1/a
E. a
F. None of these

Answer - Click Here:

E
15.By the repeated use of ……………… Digital circuit can be made

A. NOT gates
B. OR gates

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Notes Digital logic design

C. Both A & B
D. NAND gates
E. None of the above

Answer - Click Here:

D
16. The only function of NOT gate is …………….. of the following

A. Invert input signal

B . Stop signal
C. both A & B
D. Act as a universal gate
E. None of the above

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A
17. Boolean algebra is defined as a set of

A. two values
B. three values
C. Both A & B
D. four values
E. five values
F. None of these

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A
18. First operator precedence for evaluating Boolean expressions is

A. AND
B. parenthesis
C. Both A & B
D. OR
E. NOT
F. None of these

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B
19. The output is……………… When an input signal 1 is applied to a NOT gate

A. 1
B. 0
C. Both A & B
D. Either 0 & 1
E. None of the above

Answer - Click Here:

B

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Notes Digital logic design

20. The bar sign (-) indicates ……………….., In Boolean algebra?

A. AND operation
B. OR operation
C. Both A & B
D. NOT operation
E. None of the above

Answer - Click Here:

D
21. The value of n is ……. when the resolution of an n bit DAC with a maximum input of
5 V is 5 mV.

A. 9
B. 8
C. Both A & B
D. 10
E. 11
F. None of these

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D
22. 2’s complement of binary number 0101 is ………..

A. 1111
B. 1011
C. Both A & B
D. 1101
E. 1110
F. None of these

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B

23. An OR gate has 4 inputs. The output is ……. When One input is high and the other
three are low.
A. High
B. Low
C. Both A & B
D. alternately high and low
E. may be high or low depending on the relative magnitude of inputs
F. None of these

Answer - Click Here:

A
24. To convert BCD to seven segments ……………… device is used.

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Notes Digital logic design

A. Decoder
B. Encoder
C. Both A & B
D. Multiplexer
E. None of these

Answer - Click Here:

A
25. Decimal number 10 is equal to binary number ……………

A. 1010
B. 1110
C. Both A & B
D. 1001
E. 1000
F. None of these

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A
26. In 2’s complement representation the number 11100101 represents the decimal
number ……………

A. -31
B. +37
C. Both A & B
D. +27
E. -27
F. None of these

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E
27. BCD input 1000 is fed to a 7 segment display through a BCD to 7 segment
decoder/driver. The segments which will lit up are ………….

A. a, b, c
B. a, b, d
C. Both A & B
D. all
E. a, b, g, c, d
F. None of these

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D
28. A decade counter skips ………..

A. binary states 0000 to 0011

B. binary states 1000 to 1111
C. Both A & B

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Notes Digital logic design

D. binary states 1010 to 1111

E. binary states 1111 to higher
F. None of these

Answer - Click Here:

D
29. ……………. Number of States A ring counter with 5 flip flops will have?

A. 10
B. 5
C. Both A & B
D. 32
E. Infinite
F. None of these

Answer - Click Here:

B

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