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2's Complement

The document describes designing a combinational circuit to produce the 2's complement of a 4-bit binary number using 74LS04, 74LS08, and 74LS32 ICs. It provides a truth table and derives the Boolean logic functions F1, F2, F3, and F4 from the truth table, where F1 is w'(y+z)+x'y'z', F2 is x'(y+z)+x'y'z', F3 is y'z+yz', and F4 is z.

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Kwon Jiralll
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49 views4 pages

2's Complement

The document describes designing a combinational circuit to produce the 2's complement of a 4-bit binary number using 74LS04, 74LS08, and 74LS32 ICs. It provides a truth table and derives the Boolean logic functions F1, F2, F3, and F4 from the truth table, where F1 is w'(y+z)+x'y'z', F2 is x'(y+z)+x'y'z', F3 is y'z+yz', and F4 is z.

Uploaded by

Kwon Jiralll
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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A.

Problem:

Design a combinational circuit that will produce the 2’s complement of a binary no. of 4 bits.
Use only 74LS04,& 74LS08 and 74LS32 ICs.

B. Truth Table

# W X Y Z F1 F2 F3 F4
0 0 0 0 0 0 0 0 0
1 0 0 0 1 1 1 1 1
2 0 0 1 0 1 1 1 0
3 0 0 1 1 1 1 0 1
4 0 1 0 0 1 1 0 0
5 0 1 0 1 1 0 1 1
6 0 1 1 0 1 0 1 0
7 0 1 1 1 1 0 0 1
8 1 0 0 0 1 0 0 0
9 1 0 0 1 0 1 1 1
10 1 0 1 0 0 1 1 0
11 1 0 1 1 0 1 0 1
12 1 1 0 0 0 1 0 0
13 1 1 0 1 0 0 1 1
14 1 1 1 0 0 0 1 0
15 1 1 1 1 0 0 0 1
C. Boolean Functions
F1 = w’x’y’z+w’x’yz’+w’x’yz+w’xy’z’+w’xy’z+w’xyz’+w’xyz+wx’y’z’
= w’x’(y’z +yz’+ yz)+ w’y’(xz’+ xz)+ w’y (xz’+ xz) +wx’y’z’
= w’(x’(y’z +yz’+yz)+y’(xz’+xz)+y (xz’+xz))+wx’y’z’
= w’(x’(y’z + yz’+yz) + (xz’+xz)(y’+ y)1)+ wx’y’z’
= w’(x’(y’z + yz’+yz) + (xz’+xz))+wx’y’z’
= w’ (x’ (y’z+y(z’+z)1)+x(z’ +z)1)+wx’y’z’
= w’(x’(y’z+ y)+ x) +wx’y’z’
= w’(x’((y’+y)1(z +y)) +x)+wx’y’z’
= w’(x’(z + y)+x) +wx’y’z’
= w’ ((x’ +x)1((y+z)+x))+wx’y’z’
F1=w’((y+z)+x)+wx’y’z’

F2 = w’x’y’z+w’x’yz’+w’x’yz+w’xy’z’+wx’y’z+wx’yz’+wx’yz+wxy’z’
= w’x’(y’z + yz’+ yz)+w’xy’z’+ wx’(y’z + yz’+ yz) + wxy’z’
= (w’x’+wx’)(y’z +yz’+ yz)+ y’z’(w’x+ wx)
= x’(w’+ w) (y’z +y(z’+ z)1) +y’z’(x (w’+ w))
= x’(y’z +y) + x(y’z’)
= x’((y’+y)1(z+y)) +x(y’z’)
F2=x’(y+z)+x(y’z’)

F3 = w’x’y’z+w’x’yz’+w’xy’z+w’xyz’ +wx’y’z+wx’yz’+wxy’z+wxyz’
= w’x’(y’z +yz’) +w’x (y’z+ yz’)+wx’(y’z+ yz’)+ wx(y’z +yz’)
= (w’x’+w’x +wx’+wx) (y’z+yz’)
= ((w’ (x’+ x)1+w(x’+ x)1) (y’z + yz’)(w’
= +w)1(y’z+yz’)
F3=y’z+yz’
F4 = w’x’y’z+w’x’yz+w’xy’z+w’xyz+wx’y’z+wx’yz+wxy’z+wxyz
= w’x’(y’z + yz)+w’x (y’z+ yz) + wx’(y’z + yz)+ wx (y’z+ yz)
= (w’x’+ w’x + wx’+ wx) (y’z + yz)
= ((w’ (x’+x)1+w (x’+x)1)z y’+y)1
= (w’ +w)1z
F4=z

D. Logic Diagram

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