High-speed CMOS ramp generator using proteretic

comparator
Salma Khan Syed Azeemuddin Mohammed Arifuddin Sohel
Center for VLSI and Embedded Systems(CVEST) CVEST ECE Department
IIIT IIIT Muffakhan Jah College of Engg and Tech
Hyderabad, India Hyderabad, India Hyderabad, India
[email protected] [email protected] [email protected]

Abstract—The ramp generator is a crucial circuit component in characteristics and presents the CMOS design for both cir-
the design of switching power supply, analog to digital converters, cuits. Section III discusses the circuit level design, analysis,
CMOS image sensors, and many other essential circuits. Conven- and implementation of a ramp generator using a hysteretic
tionally, the ramp generator has been implemented with a CMOS
comparator that works on the hysteresis principle, which leads comparator and then a proteretic comparator and presents the
to an inherent systemic delay. This paper aims at improving the post-layout simulation results of the design. The conclusion is
overall circuit speed by proposing the design of a ramp generator discussed in section IV.
using CMOS proteretic comparator in 180nm TSMC process. It
is established from the post-layout simulation that a speedup of
25% is achieved by replacing a hysteretic comparator with a
proteretic comparator, and this is done with a trade-off in power
consumption and circuit area.
Index Terms—Hysteresis, Proteresis, Comparators, Ramp gen-
erators

I. I NTRODUCTION
Ramp generators are widely used in various applications like
switching power supply [1], analog to digital converters [2],
CMOS Image sensors [3], and others. The frequency, linearity,
and stability of ramp generators are essential criteria that Fig. 1. Voltage transfer characteristics of (a) hysteretic devices (b) proteretic
decide the applications in which they can be employed. It has devices
been observed that the operational speed of the overall circuit
is restricted by the operating speed of the ramp generator and
various techniques have been proposed to speed up the ramp II. INTRODUCTION TO HYSTERETIC AND
generator [4]. A critical component of the ramp generator is PROTERETIC DEVICES
the comparator circuit, primarily a schmitt triggerbased circuit
with hysteretic properties [5]. While efforts have been made A. Voltage transfer characteristics
to speed up this circuit by various methodologies, this paper
proposes a new approach of replacing a hysteretic comparator The ideal voltage transfer characteristics (VTC) of an in-
with a proteretic one. verting circuit following hysteresis and proteresis are shown in
Hysteresis refers to a time-lapse phenomenon between the Fig. 1. The hysteretic operation of an inverter is demonstrated
cause and effect, and all Schmitt trigger circuits demonstrate in Fig. 1(a). When the input signal varies from 0V to VDD,
hysteresis. Proteresis is when the cause has an early effect the output goes from VDD to 0V and the falling edge V2H
or response and is also referred to as reverse hysteresis occurs after a significant delay. Similarly, when the input
[6]. A proteretic comparator maintains noise immunity and signal varies from VDD to 0V, the output changes from 0V
provides circuit speed-up at the same time [5]. Proteretic to VDD , and the rising edge V1H occurs after a marked delay.
comparators have not been extensively studied and employed This is a commonly observed characteristic in most of the
in the literature. It is challenging to maintain their operational circuits and is termed hysteresis. Fig. 1(b) demonstrates the
stability with well-defined constraints and may result in a high reverse hysteretic or proteretic operation in which the output
impedance state [7]. This paper focuses on the designing a falls from VDD to 0V at an early stage V1P . Similarly, the
stable proteretic comparator, and its efficiency is demonstrated change in the output from 0V to VDD is also advanced at
by using it in a ramp generator circuit. V2P , indicating that the output responds immediately to input
The paper is organized as follows - section II compares changes. Hence, this phenomenon is based on the greek word
hysteresis and proteresis devices using their voltage transfer “proto” meaning “early” and is titled proteresis.
 Fig. 3. VTC of hysteretic Schmitt Trigger circuit

Fig. 2. Schmitt Trigger Circuit

of triggering voltages, thus leading to unstable operation of
proteretic device. This stability issue is resolved by including
a final stage inverter that maintains the output at stable 1 or 0
B. Implementation of Hysteretic Device without allowing it to slip into a high impedance state [7].
The most common CMOS circuit that implements hysteretic
operation is the Schmitt trigger circuit [8] shown in Fig. 2.
It is a six transistor implementation, but the aspect ratio of
transistors MN3 and MP3 is crucial in deciding the falling
edge and rising edge, respectively. The analysis of the given
circuit shows the reliance of rising edge V1H and falling edge
V2H on MN3 and MP3 given by equation (1) and equation (2).
Finally, the hysteresis loop voltage VH is given in equation (3).
q
VDD + VT P 3 + 2β βp V T N 3
n
VDD + VT P 3
V1H = q − q (1)
2βn 2βn
p
(1 + βp ) (1 + Kp )(1 + βp )
q Fig. 4. Design of CMOS Proteretic circuit
VDD + VT P 3 + 2β n
V
βp T N 3
V2H = q (2) The relationship of device dimensions on the triggering op-
2βn eration in threshold voltages is distinctly laid out in equations
(1 + βp )
(5) and (6).
VDD + VT P 3  2
VH = V2H − V1H = (3) KM P 1 VL
= (5)
q
(1 + Kp )(1 + 2β
p
βp )
n
KM P 3 VDD − VL − |VT P |
2
Where, VTP and VTN are n-channel and p-channel threshold

KM N 2 VDD − VH
voltages and Ki is the parameter that depends on transistor = (6)
KM N 3 VH − VT N
aspect ratio as shown in equation (4).
Where VL and H are upper and lower triggering voltage of
wi the first stage of the proteretic circuit.
Ki = 0.5(µn/p Cox ) (4)
li The conditions are given in equations (7) and (8) that govern
Based on the above equation, the circuit is designed, and the stable operation of the proteretic circuit and its triggering
suitable aspect ratio values are calculated and implemented in voltages.
CMOS 180nm technology. The voltage transfer characteristics
of the Schmitt trigger circuit are as seen in Fig. 3, with the 0 < VL < VT N (7)
rising edge at 0.5V and the falling edge at 1.4V.
C. Implementation of Proteretic Device (VDD − |VT P |) < VH < VDD (8)
The Proteretic device has three stages – Schmitt trigger, The voltage transfer characteristics of the proteretic circuit
Summer and inverter, as shown in Fig. 4. The input is con- shown in Fig. 5 complement the hysteretic circuit with the
nected in feed-forward mode to the second stage and combined falling edge at 0.8V and rising edge at 1V. It also indicates the
with the output of the first stage leading to a proteretic result proteretic loop width is shorter when compared to hysteretic
at output of second stage itself. However, the output is present loop width giving an added advantage.
in the undefined region of High Impedance for a specific This section establishes that the proteretic circuit gives an
range of input signal, putting constraints on the design values advanced response when compared to the hysteretic one and
 Fig. 5. VTC of proteretic circuit

Fig. 7. Ramp generator using Schmitt trigger (Hysteretic) circuit

that the proteretic loop is smaller than the hysteretic loop. Both
these features are essential for the design of a comparator. The
simulation is done at 27°C at VDD = 1.8V. A. Ramp generator using hysteretic circuit
The operation of the ramp generator using the Schmitt
III. DESIGN OF RAMP GENERATOR trigger circuit shown in Fig. 7 is explained as follows. Initially,
The ramp generator circuit shown in Fig. 6 consists of the transistor MFB is presumed OFF and the capacitor Ct is
an operation amplifier driving an NMOS transistor MOP of charging. Due to this, the voltage VRamp gradually increases.
the current mirror circuit in which the transistor MFB and Till VRamp is less than the voltage required to switch ON MN1
capacitor Ct play a vital role in ramp generation. The ramp and MN2, in this stage both MP1 and MP2 are ON and the
signal is generated by the charging and discharging of the output VHYS is VDD . This output of comparator is inverted,
capacitor, controlled by the switching of transistor MFB, and a logic 0 is present at the input of switching transistor
which is in-turn controlled by the comparator output. Thus, it MFB. As the voltage VRamp increases and crosses the upper
is evident that comparator performance determines the speed switching threshold of the Schmitt trigger, both MN1 and
of the ramp generator. MN2 will turn on, and output VHYS will be pulled down to
0V. It causes the voltage at the input of MFB to switch to
logic 1, and the transistor is turned ON. It leads to the quick
discharge of capacitor Ct and the voltage starts decreasing. On
its way back, as VRamp crosses the lower switching threshold,
the entire circuit returns to its initial operation and generates
the next cycle.

Fig. 6. Ramp generator circuit

The transistor MFB is turned ON and OFF based on the

output of the comparator, which compares the ramp voltage Fig. 8. Ramp signal output of hysteretic device at 5MHz
at its input to its internal pre-set threshold voltages (VH and
VL ) based on transistor dimensions and ultimately generates a The output of the ramp generator using a Schmitt trigger
square wave. The frequency of the ramp wave is determined circuit is shown in Fig. 8, where a ramp signal swing of 0 to
by equation (9) given below. 1.4V is observed and the time period of ramp wave is 0.2µsec,
indicating a ramp signal frequency of 5MHz.
Vref
f= (9) B. Ramp generator using proteretic circuit
Rt Ct (VH − VL )
This paper proposes replacing a hysteretic comparator with
It is evident from the above equation that the difference a proteretic comparator, as shown in Fig. 9. The area of the
between the triggering voltages is inversely proportional to comparator is increased as we are using 12 transistors in the
ramp signal frequency. The current paper exploits the demon- proteretic circuit instead of 6 transistors, as in the hysteretic
strated high-speed ramp signal’s dependency by replacing the circuit. The ramp generator’s overall operation is similar to the
hysteretic circuit with a proteretic one wherein the transition case of the hysteretic ramp generator, except that VPRO drives
of Vout takes place earlier compared to hysteretic circuits. MFB instead of VHys . However, a fast switching proteretic
 Fig. 9. Ramp generator using proteretic circuit
Fig. 12. Layout of ramp generator using proteretic comparator

comparator with a small proteretic loop is an ideal replacement

for the hysteretic circuit in applications where speed is of a ramp generator based on proteresis, a comparison with
essence and area and power can be compromised. the other state of art is not possible, hence comparison of
The speeding up effect is evident in Fig. 10, wherein hysteretic and proteretic ramp generators designed in this work
a ramp signal of frequency 6.25MHz is seen. The paper is given below in Table 1.
establishes that without making significant changes in the
overall system and replacing the hysteretic circuit with a TABLE I
proteretic circuit, frequency of the ramp signal is improved C OMPARISON OF HYSTERETIC AND PROTERETIC RAMP GENERATORS
from 5MHz to 6.25MHz. Fig. 11 demonstrates the ramp output
Parameter Hys Ramp Generator Pro Ramp Generator
of the proteretic ramp generator for a temperature range of Ramp Frequency 5MHz 6.25MHz
0°C to 80°C, indicating that the design is robust over the said Power Consumed 238µW 499µW
temperature range. Area Occupied 47µm X 43µm 47µm X 52µm

It is evident that the speed of the proteretic ramp generator is

25% more than the hysteretic. However, the increase in speed
is achieved with a trade-off in power and area of the proposed
design.
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This paper presents the implementation of a proteretic ramp
generator. As this paper is the first of its kind that proposes