UCC28063

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Natural Interleaving™ Transition-Mode PFC Controller

with Improved Audible Noise Immunity
Check for Samples: UCC28063

1NATURAL INTERLEAVING FEATURES SYSTEM FEATURES

• Input Filter and Output Capacitor • Advanced Audible Noise Performance
Ripple-Current Cancellation • Non-linear Error-Amplifier Gain
– Reduced current ripple for higher system • Soft Recovery on Overvoltage
reliability and smaller bulk capacitor • Integrated Brownout and Dropout Handling
– Reduced EMI filter size • Reduced Bias Currents
• Phase Management Capability • Improved Efficiency and Design Flexibility
• FailSafe OVP with Dual Paths Prevents Output over Traditional Single-Phase Continuous
Over-Voltage Conditions by Voltage-Sensing Conduction Mode (CCM)
Failures • Inrush-Safe Current Limiting:
• Sensorless Current-Shaping Simplifies Board – Prevents MOSFET conduction during
Layout and Improves Efficiency inrush
APPLICATIONS – Eliminates reverse recovery events in
output rectifiers
• 100-W to 800-W Power Supplies
• Enables Use of Low-Cost Diodes without
• Gaming Extensive Snubber Circuitry
• D-to-A Set-Top Boxes • Improved Light-Load Efficiency
• Adapters • Fast, Smooth Transient Response
• LCD, Plasma and DLP™ TVs • Expanded System-Level Protections
• Home Audio Systems • 1-A Source/1.8-A Sink Gate Drivers
• -40°C to 125°C Operating Temperature Range
in a 16-lead SOIC package
Typical Application Diagram
Ripple Current Reduction
400 VDC
EMI
– +
Filter
UCC28063
5
85 VAC to 265 VAC 12 VCC ZCDA 16
Capacitor ripple current (A)

10 CS GDA 14
POUT = 600 W
7 VINAC 4
ZCDB 1 VOUT = 400 V
1-phase TM

3 TSET GDB 11
Power Good to 3
PWMCNTL 9 Down Stream
Converter 1-phase CCM
VSENSE 2

PHB 4 Phase Management

2
COMP 5
15 VREF 2-phase TM Interleave

HVSEN 8
1
AGND PGND 70 120 170 220 270
6 13
Input Voltage (V)

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Copyright © 2011, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
UCC28063
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CONTENTS
• Electrical Characteristics 5
• Device Information 9
• Functional Block Diagram 12
• Typical Characteristics 13
• Application Information 19
• Design Example 33
• Additional References 41

DESCRIPTION
Optimized for consumer applications concerned with audible noise elimination, this solution extends the
advantages of transition mode – high efficiency with low-cost components – to higher power ratings than
previously possible. By utilizing a Natural Interleaving™ technique, both channels operate as masters (that is,
there is no slave channel) synchronized to the same frequency. This approach delivers inherently strong
matching, faster responses, and ensures that each channel operates in transition mode.
Expanded system level protections feature input brownout and dropout recovery, output over-voltage, open-loop,
overload, soft-start, phase-fail detection, and thermal shutdown. The additional FailSafe over-voltage protection
(OVP) feature protects against shorts to an intermediate voltage that, if undetected, could lead to catastrophic
device failure. Advanced non-linear gain results in rapid, yet smoother response to line and load transient events.
Reduced bias currents improve stand-by power efficiency. Special line-dropout handling avoids significant current
disruption and minimizes audible-noise generation.
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

ORDERING INFORMATION (1)

PART NUMBER PACKAGE (2) OPERATING TEMPERATURE RANGE, TA
UCC28063D SOIC 16-Pin (D) -40°C to +125°C

(1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
(2) SOIC (D) package is available taped and reeled by adding R to the above part number. Reeled quantities for UCC28063DR are 2,500
devices per reel.

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ABSOLUTE MAXIMUM RATINGS (1)

All voltages are with respect to GND, −40°C < TJ = TA < 125°C, currents are positive into and negative out of the specified
terminal, unless otherwise noted.
MIN MAX UNIT
VCC (2) −0.5 21
PWMCNTL −0.5 20
Continuous input voltage range COMP (3), PHB, HVSEN (4), VINAC (4), VSENSE (4) −0.5 7 V
ZCDA, ZCDB −0.5 4
CS (5) −0.5 3
VCC 20
Continuous input current PWMCNTL 10
ZCDA, ZCDB ±5
mA
Peak input current CS −30
Output current VREF −10
Continuous gate current GDA, GDB (6) ±25
Operating −40 125
Junction Temperature, TJ
Storage −65 150 °C
Lead Temperature, TSOL Soldering, 10s 260
Human Body Model (HBM) 2,000
V
Charged Device Model (CDM) 500

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other condition beyond those included under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods of time may affect device reliability.
(2) Voltage on VCC is internally clamped. VCC may exceed the continuous absolute maximum input voltage rating if the source is current
limited below the absolute maximum continuous VCC input current level.
(3) In normal use, COMP is connected to capacitors and resistors and is internally limited in voltage swing.
(4) In normal use, VINAC, VSENSE, and HVSEN are connected to high-value resistors and are internally limited in negative-voltage swing.
Although not recommended for extended use, VINAC, VSENSE, and HVSEN can survive input currents as high as -10mA from negative
voltage sources, and input currents as high as +0.5mA from positive voltage sources.
(5) In normal use, CS is connected to a series resistor to limit peak input current during brief system line-inrush conditions. In these
situations, negative voltage on CS may exceed the continuous absolute maximum rating.
(6) No GDA or GDB current limiting is required when driving a power MOSFET gate. However, a small series resistor may be required to
damp resonant ringing due to stray inductance.

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RECOMMENDED OPERATING CONDITIONS

All voltages are with respect to GND, −40°C < TJ = TA < 125°C, currents are positive into and negative out of the specified
terminal, unless otherwise noted.
PARAMETER MIN MAX UNIT
VCC input voltage from a low-impedance source 14 21 V
VCC input current from a high-impedance source 8 18
mA
VREF load current 0 −2
VINAC input voltage 0 6 V
ZCDA, ZCDB series resistor 20 80
kΩ
TSET resistor to program PWM on-time 66.5 400
HVSEN input voltage 0.8 4.5 V

THERMAL INFORMATION
UCC28063
THERMAL METRIC (1) SOIC (D) UNITS
16 PINS
θJA Junction-to-ambient thermal resistance (2) 91.6
θJCtop Junction-to-case (top) thermal resistance (3) 52.1
(4)
θJB Junction-to-board thermal resistance 48.6 °C/W
ψJT Junction-to-top characterization parameter (5) 14.9
ψJB Junction-to-board characterization parameter (6) 48.3

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
(3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific
JEDEC-standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
(5) The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7).
(6) The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θJA , using a procedure described in JESD51-2a (sections 6 and 7).

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ELECTRICAL CHARACTERISTICS
At VCC = 16 V, AGND = PGND = 0 V, VINAC = 3 V, VSENSE = 6 V, HVSEN = 3 V, PHB = 5 V, RTSET = 133 kΩ, all voltages
are with respect to GND, all outputs unloaded, −40°C < TJ = TA < 125°C, and currents are positive into and negative out of
the specified terminal, unless otherwise noted.
PARAMETER TEST CONDITION MIN TYP MAX UNIT
VCC Bias Supply
VCCSHUNT VCC shunt voltage (1) IVCC = 10 mA 22 24 26 V
IVCC(ULVO) VCC current, UVLO VCC = 11.4 V prior to turn-on 95 200
µA
IVCC(stby) VCC current, disabled VSENSE = 0 V 100 200
IVCC(on) VCC current, enabled VSENSE = 2 V 5 8 mA
Undervoltage Lockout (UVLO)
VCCON VCC turn-on threshold VCC rising 11.5 12.6 13.5
VCCOFF VCC turn-off threshold VCC falling 9.5 10.35 11.5 V
UVLO Hysteresis 1.85 2.15 2.45
Reference
VREF VREF output voltage, no load IVREF = 0 mA 5.82 6.00 6.18 V
VREF change with load 0 mA ≤ IVREF ≤ −2 mA - −1 −6
mV
VREF change with VCC 12 V ≤ VCC ≤ 20 V - +2 +10
Error Amplifier
VSENSEreg25 VSENSE input regulation TA = 25°C
5.85 6.00 6.15
voltage
V
VSENSEreg VSENSE input regulation
5.82 6.00 6.18
voltage
IVSENSE VSENSE input bias current In regulation 50 100 150 nA
VENAB VSENSE enable threshold,
1.15 1.25 1.35
rising
VSENSE enable hysteresis 0.02 0.07 0.15 V
VCOMPCLMP COMP high voltage, clamped VSENSE = VSENSEreg – 0.3 V 4.70 4.95 5.10
COMP low voltage, saturated VSENSE = VSENSEreg + 0.3 V 0.03 0.125
gM VSENSE to COMP 0.99(VSENSEreg) < VSENSE <
40 55 70 µS
transconductance, small signal 1.01(VSENSEreg), COMP = 3 V
VSENSE high-going threshold Relative to VSENSEreg, COMP = 3 V
to enable COMP large signal 3.25% 5% 6.75%
gain, percent
VSENSE low-going threshold to Relative to VSENSEreg, COMP = 3 V
enable COMP large signal gain, −3.25% −5% −6.75%
percent
VSENSE to COMP VSENSE = VSENSEreg – 0.4 V ,
210 290 370
transconductance, large signal COMP = 3 V
µS
VSENSE to COMP VSENSE = VSENSEreg + 0.4 V,
210 290 370
transconductance, large signal COMP = 3 V
COMP maximum source current VSENSE = 5.0 V, COMP = 3 V −80 −125 −170 µA
RCOMPDCHG COMP discharge resistance HVSEN = 5.2 V, COMP = 3 V 1.6 2.0 2.4 kΩ
IDODCHG COMP discharge current during VSENSE = 5.0 V, VINAC = 0.3 V
3.2 4 4.8 µA
Dropout
VLOW_OV VSENSE over-voltage Relative to VSENSEreg
7% +8% 10%
threshold, rising
VSENSE over-voltage Relative to VLOW_OV
−1.5% −2% −3%
hysteresis
VHIGH_OV VSENSE 2nd over-voltage Relative to VSENSEreg
10.5% 11.3% 14%
threshold, rising

(1) Excessive VCC input voltage and current will damage the device. This clamp will not protect the device from an unregulated bias supply.
If an unregulated bias supply is used, a series-connected Fixed Positive-Voltage Regulator such as the UA78L15A is recommended.
See the Absolute Maximum Ratings table for the limits on VCC voltage, current, and junction temperature.

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ELECTRICAL CHARACTERISTICS (continued)

At VCC = 16 V, AGND = PGND = 0 V, VINAC = 3 V, VSENSE = 6 V, HVSEN = 3 V, PHB = 5 V, RTSET = 133 kΩ, all voltages
are with respect to GND, all outputs unloaded, −40°C < TJ = TA < 125°C, and currents are positive into and negative out of
the specified terminal, unless otherwise noted.
PARAMETER TEST CONDITION MIN TYP MAX UNIT
Soft Start
VSSTHR COMP Soft-Start threshold, VSENSE = 1.5 V
15 23 30 mV
falling
ISS,FAST COMP Soft-Start current, fast SS-state, VENAB < VSENSE < VREF/2 −80 −125 −170
µA
ISS,SLOW COMP Soft-Start current, slow SS-state, VREF/2 < VSENSE < 0.88VREF −11.5 −16 −20
KEOSS VSENSE End-of-Soft-Start Percent of VSENSEreg
96.5% 98.3% 99.8%
threshold factor
Output Monitoring
VPWMCNTL HVSEN threshold to PWMCNTL HVSEN rising 2.35 2.50 2.65 V
IHVSEN HVSEN input bias current, high HVSEN = 3 V ±0.03 ±0.5
IHV_HYS HVSEN hysteresis bias current, HVSEN = 2 V µA
9.2 11.4 14.0
low
VHV_OV_FLT HVSEN threshold to HVSEN rising
4.64 4.87 5.10
over-voltage fault
VHV_OV_CLR HVSEN threshold to HVSEN falling
4.45 4.67 4.80
over-voltage clear
VCOMP_PHFOFF Phase Fail monitoring-disable COMP falling
0.21 0.225 0.25 V
threshold
VCOMP_PHFHYS Phase Fail monitoring COMP rising
0.051
hysteresis
PWMCNTL output voltage low HVSEN = 3 V, IPWMCNTL = 5 mA,
0.2 0.5
COMP = 0 V
tPHFDLY Phase Fail filter time to PHB = 5 V, ZCDA switching,
7.9 12 17 ms
PWMCNTL high ZCDB = 0.5 V, COMP = 3 V
IPWMCNTL_LEAK PWMCNTL leakage current, HVSEN = 2 V, PWMCNTL = 15 V
±0.03 ±0.5 µA
high

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ELECTRICAL CHARACTERISTICS (continued)

At VCC = 16 V, AGND = PGND = 0 V, VINAC = 3 V, VSENSE = 6 V, HVSEN = 3 V, PHB = 5 V, RTSET = 133 kΩ, all voltages
are with respect to GND, all outputs unloaded, −40°C < TJ = TA < 125°C, and currents are positive into and negative out of
the specified terminal, unless otherwise noted.
PARAMETER TEST CONDITION MIN TYP MAX UNIT
Gate Drive (2)
GDA, GDB output voltage, high IGDA, IGDB = −100 mA 11.5 12.4 15 V
GDA, GDB on-resistance, high IGDA, IGDB = −100 mA 8.8 14 Ω
GDA, GDB output voltage, low IGDA, IGDB = 100 mA 0.18 0.32 V
GDA, GDB on-resistance, low IGDA, IGDB = 100 mA 2 3.2 Ω
GDA, GDB output voltage high, VCC = 20 V, IGDA, IGDB = −5 mA
12 13.5 15
clamped
V
GDA, GDB output voltage high, VCC = 12 V, IGDA, IGDB = −5 mA
10 10.5 11.5
low VCC
Rise time 1 V to 9 V, CLOAD = 1 nF 18 30
ns
Fall time 9 V to 1 V, CLOAD = 1 nF 12 25
GDA, GDB output voltage, VCC = 3.0 V, IGDA, IGDB = 2.5 mA
100 200 mV
UVLO
Zero Current Detector
ZCDA, ZCDB voltage threshold,
0.8 1.0 1.2
falling
ZCDA, ZCDB voltage threshold,
1.5 1.7 1.9 V
rising
ZCDA, ZCDB clamp, high IZCDA = +2 mA, IZCDB = +2 mA 2.6 3.0 3.4
ZCDA, ZCDB clamp, low IZCDA = −2 mA, IZCDB = −2 mA 0 −0.2 −0.4
ZCDA, ZCDB input bias current ZCDA = 1.4 V, ZCDB = 1.4 V ±0.03 ±0.5 µA
ZCDA, ZCDB delay to GDA, From ZCDx input falling to 1 V to
50 100
GDB outputs (2) respective gate drive output rising 10%
ns
ZCDA blanking time (3) From GDA rising and GDA falling 100
ZCDB blanking time (3) From GDB rising and GDB falling 100
Current Sense
CS input bias current, At rising threshold
−120 −166 −200 µA
dual-phase
CS current-limit rising threshold, PHB = 5 V
−0.180 −0.200 −0.220
dual-phase
CS current-limit rising threshold, PHB = 0 V
−0.149 −0.166 −0.183 V
single-phase
CS current-limit reset falling
−0.003 −0.015 −0.025
threshold
CS current-limit response From CS exceeding threshold−0.05 V to
60 100
time (2) GDx dropping 10% ns
CS blanking time From GDx rising and falling edges 100

(2) Refer to Figure 13, Figure 14, Figure 15, and Figure 16 of the Typical Characteristics for typical gate drive waveforms.
(3) ZCD blanking times are ensured by design.

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ELECTRICAL CHARACTERISTICS (continued)

At VCC = 16 V, AGND = PGND = 0 V, VINAC = 3 V, VSENSE = 6 V, HVSEN = 3 V, PHB = 5 V, RTSET = 133 kΩ, all voltages
are with respect to GND, all outputs unloaded, −40°C < TJ = TA < 125°C, and currents are positive into and negative out of
the specified terminal, unless otherwise noted.
PARAMETER TEST CONDITION MIN TYP MAX UNIT
VINAC Input
IVINAC VINAC input bias current, VINAC = 2 V
±0.03 ±0.5 µA
above brownout
VBODET VINAC brownout detection VINAC falling
1.33 1.39 1.44 V
threshold
tBODLY VINAC brownout filter time VINAC below the brownout detection
340 440 540 ms
threshold for the brownout filter time
VBOHYS VINAC brownout threshold VINAC rising
30 62 75 mV
hysteresis
IBOHYS VINAC brownout hysteresis VINAC = 1 V for > tBODLY
1.6 2 2.5 µA
current
VDODET VINAC dropout detection VINAC falling
0.315 0.35 0.38 V
threshold
tDODLY VINAC dropout filter time VINAC below the dropout detection
3.5 5 7.0 ms
threshold for the dropout filter time
VDOCLR VINAC dropout clear threshold VINAC rising 0.67 0.71 0.75 V
Pulse-Width Modulator
KT On-time factor, phases A and B VSENSE = 5.8 V (4) 3.6 4.0 4.4
µs/V
KTS On-time factor, single-phase, A VSENSE = 5.8 V, PHB = 0 V (4) 7.2 8.0 8.9
Phase B to phase A on-time VSENSE = 5.8 V
±2% ±6%
matching error
Zero-crossing distortion COMP = 0.25 V, VINAC = 1 V 1.2 2 2.8
correction additional on time µs
COMP = 0.25 V, VINAC = 0.1 V 12.6 20 29
VPHBF PHB threshold falling, to To GDB output shutdown, VINAC = 1.5 V
0.7 0.8 0.9
single-phase operation
V
VPHBR PHB threshold rising, to To GDB output running, VINAC = 1.5 V
0.9 1.0 1.1
two-phase operation
TMIN Minimum switching period RTSET = 133 kΩ (4) 1.7 2.2 3.0
µs
TSTART PWM restart time ZCDA = ZCDB = 2 V (5) 165 210 265
Thermal Shutdown
TJ Thermal shutdown temperature Temperature rising (6) 160
°C
TJ Thermal restart temperature Temperature falling (6) 140

(4) Gate drive on-time is proportional to (VCOMP – 0.125 V). The on-time proportionality factor, KT, scales linearly with the value of RTSET
and is different in two-phase and single-phase modes. The minimum switching period is proportional to RTSET.
(5) An output on-time is generated at both GDA and GDB if both ZCDA and ZCDB negative-going edges are not detected for the restart
time. In single-phase mode, the restart time applies for the ZCDA input and the GDA output.
(6) Thermal shutdown occurs at temperatures higher than the normal operating range. Device performance above the normal operating
temperature is not specified or assured.

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DEVICE INFORMATION

UCC28063D
SOIC 16-Pin (D)
ZCDB 1 16 ZCDA
VSENSE 2 15 VREF
TSET 3 14 GDA
PHB 4 13 PGND
COMP 5 12 VCC
AGND 6 11 GDB
VINAC 7 10 CS
HVSEN 8 9 PWMCNTL

TERMINAL FUNCTIONS
TERMINAL
I/O DESCRIPTION
NAME NO.
AGND 6 - Analog Ground
COMP 5 O Error Amplifier Output
CS 10 I Current Sense Input
GDA 14 O
Channel A and Channel B Gate Drive Output
GDB 11 O
HVSEN 8 I High Voltage Output Sense
PHB 4 I Phase-B Enable/Disable
PWMCNTL 9 O PWM-Control Output
TSET 3 I Timing Set
VCC 12 - Bias Supply Input
VINAC 7 I Input AC Voltage Sense
VREF 15 O Voltage Reference Output
VSENSE 2 I Output DC Voltage Sense
ZCDA 16 I
Zero Current Detection Inputs
ZCDB 1 I

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Detailed Pin Description

Analog Ground: Connect analog signal bypass capacitors, compensation components, and analog signal
returns to this pin. Connect the analog and power grounds at a single point to isolate high-current noise signals
of the power components from interference with the low-current analog circuits.
Error Amplifier Output: The error amplifier is a transconductance amplifier, so this output is a high-impedance
current source. Connect voltage-regulation loop-compensation components from this pin to AGND. The on-time
seen at the gate-drive outputs is proportional to the voltage at this pin minus an offset of approximately 125 mV.
During normal operation, the error amplifier maintains a transconductance of 55 μS for small-signal disturbances
on VSENSE, and shifts to ~290 μS when VSENSE deviates more than +/-5% from VSENSEreg. During an
AC-line Dropout condition, the error amplifier output is disabled and an internal 4-μA source discharges COMP
for the duration of the Dropout condition. During a VSENSE-based OV event, an internal 2-kΩ resistor is applied
from COMP to GND until the OV condition clears. During soft-start triggering events (UVLO, Disable, Brownout,
HVSEN over-voltage, TSET-Fault, CS open-circuit, or Thermal Shutdown), the error-amp output is disabled and
COMP is pulled low by an internal 2-kΩ resistor. The soft-start condition begins only after the triggering event
clears and COMP has been discharged below 20 mV, ensuring that the circuit restarts with a low COMP voltage
and a short on-time. (Do not connect COMP to a low-impedance source that would interfere with COMP falling
below 20 mV.) During Soft-Start, the error amplifier high transconductance is enabled and COMP current is -125
μA as long as VSENSE < VREF/2. Once VSENSE exceeds VREF/2, the high gain is disabled and only the
small-signal gain capability is available with a maximum COMP current of approximately -16 μA. Normal
operation resumes once VSENSE > 0.983VREF (~5.9 V).
Current Sense Input: Connect the current-sense resistor and the negative terminal of the diode bridge to this
pin. Connect the return of the current sense resistor to the AGND pin with a separate trace. As input current
increases, the voltage on CS will go more negative. This cycle-by-cycle over-current protection limits input
current by turning off both gate driver outputs (GDx) when CS is more negative than the CS rising threshold
(approximately -200 mV in two-phase operation and approximately -167 mV in single-phase and phase-fail
condition). The gate drive outputs will remain low until CS falls to the CS falling threshold (approx. -15 mV).
Current sense is blanked for approximately 100 ns following the rising and falling edge of either GDx output. This
filters noise that may occur from gate-drive current or when inductor current switches from a power FET to a
boost diode. In most cases, no additional current sense filtering is required. If external filtering is deemed
necessary, or to prevent excessive negative voltage on the CS pin during AC-inrush conditions, a series resistor
is recommended to connect the current sensing resistor to the CS pin. Due to the CS bias current, this external
resistor should be less than 100 Ω to maintain accuracy. If the CS pin becomes open-circuited, the voltage on
CS floats up to about +1.5 V. This condition is detected and treated as a soft-start-triggering fault condition (CS
open-circuit).
Channel A and Channel B Gate Drive Output: Connect these pins to the gate of the power FET for each
phase through the shortest connection practicable. If it is necessary to use a trace longer than 0.5 inch (12.6
mm) for this connection, some ringing may occur due to trace series inductance. This ringing can be damped by
adding a low-value resistor in series with GDA and GDB.
High Voltage Output Sense: The UCC28063 incorporates FailSafe OVP so that any single failure does not
allow the output to boost above safe levels. Output over-voltage is monitored by both VSENSE and HVSEN but
their actions are different if either pin exceeds their respective over-voltage thresholds. Using two pins to monitor
for over-voltage provides redundant protection and fault tolerance. When HVSEN exceeds its over-voltage
threshold, it triggers a full soft-start of the controller. HVSEN can also be used to enable a downstream power
converter when the voltage on HVSEN is within the operating region. When HVSEN is greater than 2.5 V, the
PWMCNTL output may be driven Low (provided no other fault exists). When HVSEN falls below 2.5 V, the
PWMCNTL output becomes high-impedance. Select the HVSEN divider ratio for the desired over-voltage and
power-good thresholds. Select the HVSEN divider impedance for the desired power-good hysteresis based on
the hysteresis current. During operation, HVSEN must never fall below 0.8 V. Dropping HVSEN below 0.8 V puts
the UCC28063 into a special test mode, used only for factory testing. A bypass capacitor from HVSEN to AGND
is recommended to filter noise and avoid false over-voltage shutdown.
Phase-B Enable/Disable: When the voltage applied to this pin is below the Phase-B enable threshold, Phase B
of the boost converter and the Phase Fail detector are disabled. The commanded on-time for Phase A is
immediately doubled when Phase B is disabled, which helps keep COMP voltage constant during the
phase-management transient. The PHB pin allows the user to add external phase-management control circuitry,
if desired. To disable phase-management, connect the PHB pin to the VREF pin.

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PWM-Control Output: This open-drain output goes low when HVSEN is within the HVSEN-good region (HVSEN
> 2.5 V), there is no FailSafe OV, and there is no Phase-Fail condition when operating in two-phase mode (see
PHB pin). Otherwise, PWMCNTL is high-impedance.
Timing Set: PWM on-time programming input. Connect a resistor from TSET to AGND to set the on-time versus
COMP voltage and the minimum switching period at the gate-drive outputs. Protection circuits prevent the
controller from operating if the TSET input is in an open-circuit or short-circuit condition. As long as this pin is
open-circuited, it triggers a full soft-start condition. If this pin becomes shorted to GND, its current is limited and
also triggers a soft-start condition.
Bias Supply Input: Connect this pin to a controlled bias supply of between 14 V and 21 V. Also connect a
0.1-μF or larger ceramic bypass capacitor from this pin to PGND with the shortest possible board trace. This bias
supply powers all circuits within the device and must be capable of delivering the steady-state dc current plus the
transient power-MOSFET gate-charging current. Input bias current is very low during undervoltage-lockout
(UVLO) or stand-by conditions (VSENSE < 1.25 V).
Input AC Voltage Sense: For normal operation, connect this pin to a voltage divider across the rectified input
power mains. When the voltage on VINAC remains below the brownout threshold for longer than the brownout
filter time, the device enters a brownout mode, both output drivers are disabled and a full soft-start is triggered.
Select the input voltage divider ratio for the desired brownout threshold. Select the divider impedance for the
desired brownout hysteresis based on the hysteresis current. A dropout condition is triggered when VINAC
remains below the dropout threshold for longer than the dropout filter time. The error amplifier is disabled and an
internal 4-μA current source discharges COMP for the duration of the dropout condition. The dropout condition is
immediately cleared and normal operation resumes when VINAC exceeds the dropout-clear threshold.
Voltage Reference Output: Connect a 0.1-μF or larger ceramic bypass capacitor from this pin to AGND. VREF
turns off during UVLO and VSENSE-disable to save bias current and increase stand-by efficiency. This reference
output can be used to bias other circuits requiring less than a few milliamperes of non-pulsing total supply
current.
Output DC Voltage Sense: Connect this pin to a voltage divider across the output of the power converter. In a
closed-loop system, the voltage at VSENSE is regulated to the error amplifier reference voltage. Select the
output voltage divider ratio for the desired output voltage. Connect the ground side of this divider to analog
ground (AGND) through a separate short trace for best output regulation accuracy and noise immunity. Controller
operation may be enabled when VSENSE voltage exceeds the 1.25-V enable threshold. VSENSE can be pulled
low by an open-drain logic output, or >6-V logic output in series with a low-leakage diode, to disable the outputs
and reduce VCC current. Two levels of output overvoltage are detected at this input. If VSENSE exceeds the
first-level overvoltage protection threshold VLOW_OV, an internal 2-kΩ resistor is applied to COMP to quickly
reduce gate-drive on-time. If VSENSE continues to rise past the second-level threshold VHIGH_OV, GDA and GDB
are immediately latched off. This latch is cleared when VSENSE falls below the OV-clear threshold. If VSENSE
becomes disconnected, open-loop protection provides an internal current source to pull VSENSE low, which
disables the controller and triggers a soft-start condition.
Zero Current Detection Inputs: These inputs are used to detect a negative-going edge when the boost inductor
current in each respective phase goes to zero. The inputs are clamped between 0 V and 3 V. Connect each pin
through a current limiting resistor to the zero-crossing detection (ZCD) winding of the corresponding boost
inductor. The resistor value should be chosen to limit the clamping currents to less than ±3 mA. The inductor
winding polarity must be arranged so that this ZCD voltage falls when the inductor current decays to zero. When
the inductor current falls to zero, the ZCD input must drop below the falling threshold (approximately 1 V) to
cause the gate drive output to rise. Subsequently, when the power-MOSFET turns off, the ZCD input must rise
above the rising threshold (approximately 1.7 V) to arm the logic for another falling ZCD edge.

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Functional Block Diagram

-0.167 V / DSCHG _RST COMP_DSCHG

1-PHASE
-0.015V BROWNOUT
R Q STOP_GDA
-0.200 V / HVSEN_OV
Overcurrent UVLO
-0.015V + S Q
100ns
OC EN STOP_GDB
Blanking
CS 10 Open TSET_FLT OC
Detection
CS_OPEN CS_OPEN HIGH _OV
TSD PHASE_B_OFF
12 VCC
Brownout Detection UVLO 12.6V /
VINAC 7 +
440ms Delay 10.35V

6.00V
50mV BROWNOUT

Reg.

Reg.
VGD
1.4V + 24V

Thermal ShutDown
+ TJ 13.5V
2μA Dropout Detection TSD 160°C / 15 VREF
5ms Delay UVLO
0.70V / DROPOUT 140 °C
+ EN VREF
0.35V
13.5V

TON Basis
PHASE_B_OFF Phase A
TSET 3 Open/Short
STOP_GDA
TSET_FLT On-Time Control

PWMA
Detection

TON Modulation 14 GDA

1.7V / Trigger
+ 100ns
1.0V
Clamping

Blanking
ZCDA 16 ZCA PGND
Crossover Interleave
VINAC Notch
1.7V / Reduction Control
+ 13.5V
1.0V 100ns ZCB
Clamping

Blanking
ZCDB 1
Trigger
TON Modulation PWMB
11 GDB
TON Basis

DROPOUT
Phase B
On-Time Control STOP_GDB
DSCHG_RST 13 PGND
+ 20mV LOW_OV
VCC 2k COMP_DSCHG
4μA HVSEN_OV
+
HIGH_OV ZCA ZCB + 8 HVSEN
6.67V
4.87V /
4.67V
Phase Fail Detector

+ +
1-PHASE

12ms Filter

120mV LOW_OV
6.48V EA Gain Control
2.5V
and

for Soft-Start
and Dropout
50mV EN
1.25V + DIS_EA DIS_High_Gain
PhaseFail
12μA
VSENSE 2
272mV /
VREF +g 222 mV
+
M

50μS / 9 PWMCNTL
250μS
100nA 1.0V /
+
0.8V
PHASE_B_OFF
4.95V
6 5 4
AGND COMP PHB

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TYPICAL CHARACTERISTICS
At VCC = 16 V, AGND = PGND = 0 V, VINAC = 3 V, VSENSE = 6 V, HVSEN = 3 V, PHB = 5 V, RTSET = 133 kΩ;
all voltages are with respect to GND, all outputs unloaded, TJ = TA = +25°C, and currents are positive into and
negative out of the specified terminal, unless otherwise noted.
BIAS SUPPLY CURRENT BIAS SUPPLY CURRENT
vs vs
BIAS SUPPLY VOLTAGE TEMPERATURE
10 10

Enabled Enabled
IVCC − Bias Supply Current (mA)

IVCC − Bias Supply Current (mA)

1 1

VCC Turn OFF VCC Turn ON

0.1 0.1
Disabled Disabled

0.01 0.01
0 2 4 6 8 10 12 14 16 18 20 −40 −20 0 20 40 60 80 100 120
VCC − Bias Supply Voltage (V) TJ − Temperature (°C)
G000 G001

Figure 1. Figure 2.

REFERENCE VOLTAGE VSENSE INPUT BIAS CURRENT

vs vs
TEMPERATURE INPUT VOLTAGE
6.10 150

6.08 IVREF = 0 to −2 mA

125
6.06
IVSENSE − Input Bias Current (nA)
VREF Reference Voltage (V)

6.04
100
6.02

6.00 75

5.98
50
5.96

5.94
25
5.92

5.90 0
−40 −20 0 20 40 60 80 100 120 0 1 2 3 4 5 6
TJ − Temperature (°C) VVSENSE − Input Voltage (V)
G002 G003

Figure 3. Figure 4.

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TYPICAL CHARACTERISTICS (continued)

ERROR AMPLIFIER OUTPUT CURRENT ERROR AMPLIFIER TRANSCONDUCTANCE
vs vs
INPUT VOLTAGE VSENSE
150 300
Soft−start Completed

100 250

gM − Transconductance (µS)
ICOMP − Output Current (µA)

LOW_OV
50 Transconduction 54 µS Trigger 200

LOW_OV
0 Clear 150

−50 100

−100 50

−150 0
5.0 5.2 5.4 5.6 5.8 6.0 6.2 6.4 6.6 6.8 7.0 5.0 5.2 5.4 5.6 5.8 6.0 6.2 6.4 6.6 6.8 7.0
VVSENSE − Input Voltage (V) VVSENSE − Input Voltage (V)
G004 G005

Figure 5. Figure 6.

ERROR AMPLIFIER TRANSCONDUCTANCE ERROR AMPLIFIER OUTPUT CURRENT

vs vs
TEMPERATURE OUTPUT VOLTAGE
60 20
5.9 V < VVSENSE < 6.1 V
58
15
VVSENSE = 6.2 V
56
10
gM − Transconductance (µS)

ICOMP − Output Current (µA)

54 VVSENSE = 6.1 V
5
52

50 0

VVSENSE = 5.9 V
48
−5

46 VVSENSE = 5.8 V
−10
44

−15
42

40 −20
−40 −20 0 20 40 60 80 100 120 0 1 2 3 4 5
TJ − Temperature (°C) VCOMP − Output Voltage (V)
G006 G007

Figure 7. Figure 8.

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TYPICAL CHARACTERISTICS (continued)

ON-TIME FACTOR ON-TIME FACTOR PHASE A AND B
vs vs
TIME SETTING RESISTOR TEMPERATURE
10 9

9 8
RTSET = 266 kW
8
KTL 7

KTL - On-Time Factor - ms/V

KT - On-Time Factor - ms/V

7
6
6
5
5 RTSET = 133 kW
4
4
3
3
2
2
RTSET = 66 kW
1 1

0 0
60 80 100 120 140 160 180 200 220 240 260 280 -40 -20 0 20 40 60 80 100 120
RTSET - Time Setting Resistor - kW TJ - Temperature - °C
Figure 9. Figure 10.

ON-TIME FACTOR ADDITIONAL ON TIME

vs vs
PHASE ERROR VINAC
110 100
RTSET = 266 kW
GDA RTSET = 266 kW GDB
108
RTSET = 133 kW
106 RTSET = 133 kW
RTSET = 66 kW
Additional On-Time - ms

104
RTSET = 66 kW 10
102
KT/KT0 - %

100

98
1
96

94 2(KTA ´ KTB)
KT0 =
KTA + KTB
92

90 0.1
150 160 170 180 190 200 210 0 0.5 1.0 1.5 2.0 2.5 3.0
Phase Shift of GDA Relative to GDB - Degrees VVINAC - Input AC Voltage Sense - V
Figure 11. Figure 12.

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TYPICAL CHARACTERISTICS (continued)

GATE DRIVE RISING GATE DRIVE FALLING
vs vs
TIME TIME
14 3.0 14 3.0
VCC = 20 V and 12 V VCC = 20 V and 12 V
12 CLOAD = 4.7 nF 2.5 12 CLOAD = 4.7 nF 2.5

Gate Drive Source Current - A

Gate Drive Source Current - A

10 2.0 10 2.0
Gate Drive Output - V

Gate Drive Output - V

GD Voltage: GD Sink Current:
8 VCC = 20 V 1.5 8 VCC = 20 V 1.5
GD Source Current: VCC = 12 V VCC = 12 V
VCC = 20 V
6 VCC = 12 V 1.0 6 1.0

4 0.5 4 0.5

2 0 2 0
GD Voltage:
0 -0.5 0 VCC = 20 V -0.5
VCC = 12 V
-2 -1.0 -2 -1.0
0 50 100 150 200 250 300 350 0 20 40 60 80 100 120 140
Time - ns Time - ns
Figure 13. Figure 14.

GATE DRIVE RISING GATE DRIVE FALLING

AND DELAY FROM ZCD INPUT AND DELAY FROM CS INPUT
vs vs
TIME TIME
7 14 500 14
CLOAD = 4.7 nF CLOAD = 4.7 nF
6 12 400 12

5 10 300 10
Current Sense Input - mV

GD Output:

Gate Drive Output - V

Gate Drive Output - V

TJ = -40°C
4 8 200 8
ZCD Input - V

TJ = +25°C
TJ = +125°C CS Input
3 6 100 6
Voltage GD Output:
TJ = -40°C
2 4 0 4
TJ = +25°C
TJ = +125°C
-100 2
1 2

-200 0
0 0
ZCD Input Voltage
-300 -2
-1 -2
-25 0 50 100 150 200 250 300
-25 0 50 100 150 200 250 300
Time - ns
Time - ns
Figure 15. Figure 16.

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TYPICAL CHARACTERISTICS (continued)

GATE DRIVE OUTPUT HIGH GATE DRIVE HIGH VOLTAGE
vs vs
VCC TEMPERATURE
15 15
RLOAD = 2.7 kW
14
14
TJ = -40°C
13 Clamped VCC ³ 15 V
13
Gate Drive Voltage - V

Gate Drive Voltage - V

12
TJ = +25°C
TJ = +125°C 11
12
Unclamped VCC = 12 V
10
11
9

10 8

7
9
6
RLOAD = 2 kW
8 5
10 11 12 13 14 15 16 17 18 19 20 -40 -20 0 20 40 60 60 100 120
VVCC - Bias Supply Voltage - V TJ - Temperature - °C
Figure 17. Figure 18.

GATE DRIVE LOW VOLTAGE GATE DRIVE LOW VOLTAGE IN UVLO

vs vs
TEMPERATURE BIAS SUPPLY VOLTAGE
320 2.5
Load = 100 mA
Load = 10 mA
280
Load = 5 mA
2.0
240
VOL − Gate Drive Voltage (mV)

VOL − Gate Drive Voltage (V)

200
1.5

160

1.0
120
Load = 2.5 mA
Load = 1.0 mA
80
0.5

40

0 0.0
−40 −20 0 20 40 60 80 100 120 0 1 2 3 4
TJ − Temperature (°C) VCC − Bias Supply Voltage (V)
G008 G009

Figure 19. Figure 20.

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TYPICAL CHARACTERISTICS (continued)

VARIOUS DELAY TIMES ZERO CURRENT DETECT CLAMP VOLTAGE
vs vs
TEMPERATURE INPUT CURRENT
1000 3.5

3.0
Brownout Filter Delay

100 2.5

VZCD − Clamp Voltage (V)

2.0
Delay Time (ms)

Phase−Fail Filter Delay

10 1.5

1.0
Dropout Filter Delay

1 0.5

Restart Time Delay

0.0

0.1 −0.5
−40 −20 0 20 40 60 80 100 120 −5 −4 −3 −2 −1 0 1 2 3 4 5
TJ − Temperature (°C) IZCD − Input Current (mA)
G010 G011

Figure 21. Figure 22.

CURRENT SENSE INPUT BIAS CURRENT CURRENT SENSE INPUT BIAS CURRENT
vs vs
TEMPERATURE INPUT VOLTAGE
−150 0
VCS = −195 mV

−155

−50
−160
ICS − Input Bias Current (µA)

ICS − Input Current (µA)

−165
−100

−170

−150
−175
Single−Phase Mode
Dual−Phase Mode
−180
−200

−185

−190 −250
−40 −20 0 20 40 60 80 100 120 −300 −250 −200 −150 −100 −50 0
TJ − Temperature (°C) VCS − Input Voltage (mV)
G012 G013

Figure 23. Figure 24.

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APPLICATION INFORMATION

Principles of Operation
The UCC28063 contains the control circuits for two parallel-connected boost pulse-width modulated (PWM)
power converters. The boost PWM power converters ramp current in the boost inductors for a time period
proportional to the voltage on the error amplifier output. Each power converter then turns off the power MOSFET
until current in the boost inductor decays to zero, as sensed on the zero current detection inputs (ZCDA and
ZCDB). Once the inductor is demagnetized, the power converter starts another cycle. This on/off cycling
produces a triangle wave of current, with peak current set by the on-time and instantaneous power mains input
voltage, VIN(t), as shown in Equation 1.
V (t) ´ TON
IPEAK (t) = IN
L (1)
The average line current is exactly equal to half of the peak line current, as shown in Equation 2.
V (t) ´ TON
IAVG (t) = IN
2´L (2)
With TON and L being essentially constant during an AC-line period, the resulting triangular current waveform
during each switching cycle will have an average value proportional to the instantaneous value of the rectified
AC-line voltage. This architecture results in a resistive input impedance characteristic at the line frequency and a
near-unity power factor.

Natural Interleaving
Under normal operating conditions, the UCC28063 regulates the relative phasing of the channel A and channel B
inductor currents to be very close to 180°. This greatly reduces the switching-frequency ripple currents seen at
the line-filter and output capacitors, compared to the ripple current of each individual converter. This design
allows a reduction in the size and cost of input and output filtering. The phase-control function differentially
modulates the on-times of the A and B channels based on their phase and frequency relationship. The Natural
Interleaving method allows the converter to achieve 180° phase-shift and transition-mode operation for both
phases without tight requirements on boost inductor tolerance.
Ideally, the best current-sharing is achieved when both inductors are exactly the same value. Typically the
inductances are not the same, so the current-sharing of the A and B channels is proportional to the inductor
tolerance. Also, switching delays and resonances of each channel typically differ slightly, and the controller
allows some necessary phase-error deviation from 180° to maintain equal switching frequencies. Optimal phase
balance occurs if the individual power stages and the on-times are well matched. Mismatches in inductor values
do not affect the phase relationship.

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On-Time Control, Maximum Frequency Limiting, and Restart Timer

Gate-drive on-time varies proportionately with the error-amplifier output voltage by a factor called KT (in units of
μs/V), as shown in Equation 3.
TON = K T (VCOMP - 125mV ) (3)
Where:
• VCOMP is the output voltage of the error amplifier and 125 mV is a modulator offset voltage.
The maximum output of the error amplifier is limited to 4.95 V. This value, minus the 125-mV modulator offset,
limits maximum on-time as determined by Equation 4.
TON(max) = K T ´ 4.825 V
(4)
This on-time limit sets the maximum power that can be delivered by the converter at a given input voltage.
At lower power, one boost channel (phase) may be turned off to achieve efficiency benefits (see Phase
Management section, below). To provide a smooth transition between two-phase and single-phase operation, KT
increases by a factor of two in single-phase mode:
K TS = 2 ´ K T ; active during single-phase operation (5)
The maximum switching frequency of each phase is limited by minimum-period timers. If inductor current decays
to zero before the minimum-period timer elapses, the next turn-on will be delayed, resulting in discontinuous
phase current.
A restart timer ensures starting under all circumstances by restarting both phases if the ZCD input of either
phase has not transitioned from high-to-low within approximately 200 µs. To prevent the circuit from operating in
continuous conduction mode (CCM), the restart timer does not trigger turn-on until both phase-currents return to
zero.
The on-time factors (KT, KTS) and the minimum switching period, T(MIN), are proportional to the time-setting
resistor RTSET (the resistor from the TSET pin to ground), and these factors can be calculated by Equation 5,
Equation 6 and Equation 7:
R ms
K T = TSET ´ 4.0
133kW volt (6)
RTSET
T(MIN) = ´ 2.2 ms ; Minimum Switching Period
133kW (7)
The proper value of RTSET will result in the clamped maximum on-time, TON(max), required by the converter
operating at the minimum input line voltage and maximum load.

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Distortion Reduction
Due to the parasitic resonance between the drain-source capacitance of the switching MOSFET and the boost
inductor, conventional transition-mode PFC circuits may not be able to absorb power from the input line when the
input voltage is near zero. This limitation increases total harmonic distortion as a result of ac-line current
waveform distortion in the form of flat spots. To help reduce line-current distortion, the UCC28063 increases
switching MOSFET on-time when the input voltage is near 0 V to improve the power absorption capability and
compensate for this effect.
Figure 12 in the Typical Characteristics section shows the increase in on-time with respect to VINAC voltage.
Excessive filtering of the VINAC signal will nullify this function.

Zero-Current Detection and Valley Switching

In transition-mode PFC circuits, the MOSFET turns on when the boost inductor current reaches zero. Because of
the resonance between the boost inductor and the parasitic capacitance at the MOSFET drain node, part of the
energy stored in the MOSFET junction capacitor can be recovered, reducing switching losses. Furthermore,
when the rectified input voltage is less than half of the output voltage, all the energy stored in the MOSFET
junction capacitor can be recovered and zero-voltage switching (ZVS) can be realized. By adding an appropriate
delay, the MOSFET can be turned on at the valley of its resonating drain voltage (valley-switching). In this way,
the energy recovery can be maximized and switching loss is minimized.
The optimal time delay is generally derived empirically, but a good starting point is a value equal to 25% of the
resonant period of the drain circuit. The delay can be realized by a simple RC filter, as shown in Figure 25, but
the delay time increases slightly as the input voltage nears the output voltage. Because the ZCD pin is internally
clamped, a more accurate delay can also be realized by using the circuit shown in Figure 26.

ZCD
R
CT C

Figure 25. Simple RC Delay Circuit

ZCD
R1
CT C R2

Figure 26. More Accurate Time Delay Circuit

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Phase Management and Light-Load Operation

Under light-load conditions, switching losses may dominate over conduction losses and efficiency may be
improved if one phase (channel) is turned off. At a certain power level, the reduction of switching losses is
greater than the increase in conduction losses. Turning off one phase at light load is especially valuable for
meeting light-load efficiency standards. This is one of the major benefits of interleaved PFC and it is especially
valuable for meeting 80+ design requirements.
The PHB input can be used to force the UCC28063 to operate in single-phase mode. When PHB is driven below
0.8 V, channel B will stop switching and channel A on-time will automatically double to compensate. The device
will resume dual-phase mode when PHB is raised above 1.0 V. For customized phase management, an external
circuit can detect the conditions for switching to single-phase operation and drive PHB accordingly. To operate
continuously in two-phase mode (normal mode) when phase management is not desired, simply connect PHB to
VREF.
As load current decreases, the error amplifier commands less ac-line input current by lowering COMP voltage. In
applications where the ac-line is limited to the low-voltage range only, it may be advantageous to connect PHB
directly to COMP to allow automatic selection of single-phase operation without additional external circuitry.

External Disable
The UCC28063 can be externally disabled by purposefully grounding the VSENSE pin with an open-drain or
open-collector driver. When disabled, the device supply current drops significantly and COMP is actively pulled
low. This disable method forces the device into standby mode and minimizes its power consumption. This is
particularly useful when standby power is a key design aspect. When VSENSE is released, the device enters
soft-start mode.

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Improved Error Amplifier

The voltage-error amplifier is a transconductance amplifier. Voltage-loop compensation is connected from the
error amplifier output, COMP, to analog ground, AGND. The recommended Type-II compensation network is
shown in Figure 27. For loop-stability purposes, the compensation network values are calculated based on
small-signal perturbations of the output voltage using the nominal transconductance (gain) of 55 μS.
VREF

COMP
+
gM
VSENSE
CZ
CP
4.95V RZ

Figure 27. Transconductance Error Amplifier with Typical Compensation Network

To improve the transient response to large perturbations, the error amplifier gain increases by a factor of ~5X
when the error amp input deviates more than ±5% from the nominal regulation voltage, VSENSEreg. This
increase allows faster charging and discharging of the compensation components following sudden load-current
increases or decreases (also refer to Figure 5 in the Typical Characteristics).

IEA

VSENSE

VREF

Figure 28. Basic Voltage-Error Amplifier Transconductance Curve

NOTE
Basic voltage-error amplifier transconductance curve showing small-signal and
large-signal gain sections, with maximum current limitations.

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Soft Start
Soft-start is a process for boosting the output voltage of the PFC converter from the peak of the ac-line input
voltage to the desired regulation voltage under controlled conditions. Instead of a dedicated soft-start pin, the
UCC28063 uses the voltage error amplifier as a controlled current source to increase the PWM duty-cycle by
way of increasing the COMP voltage. To avoid excessive start-up time-delay when the ac-line voltage is low, a
higher current is applied until VSENSE exceeds 3 V at which point the current is reduced to minimize the
tendency for excess COMP voltage at no-load start-up.
The PWM gradually ramps from zero on-time to normal on-time as the compensation capacitor from COMP to
AGND charges from zero to near its final value. This process implements a soft-start, with timing set by the
output current of the error amplifier and the value of the compensation capacitors. In the event of a HVSEN
FailSafe OVP, brownout, external-disable, UVLO fault, or other protection faults, COMP is actively discharged
and the UCC28063 will soft-start after the triggering event is cleared. Even if a fault event happens very briefly,
the fault is latched into the soft-start state and soft-start is delayed until COMP is fully discharged to 20 mV and
the fault is cleared. See Figure 29 for details on the COMP current. See Figure 30 which illustrates an example
of typical system behavior during soft-start.

ICOMP
OVP1 trigger. 2k pull -down
applied to COMP .

+63μA OVP1 reset. 2k pull -down

removed from COMP .

+15μA 1.0 2.0 3.0 4.0 5.0 6.0 7.0

-15μA VSENSE
COMP current limit
during Soft -Start only
(high-gain disabled )
-111 μA

Figure 29. Expanded COMP Output Current Curve

NOTE
Expanded COMP output current curve including voltage-error amplifier transconductance
and modifications applicable to soft-start and over-voltage conditions.

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OVERSHOOT
V

VSENSEREG
VENDofSS
VSENSE

VCOMPCLMP

COMP

VSSTHR

I AC-LINE

ICOMP
ISS,SLOW
ISS,FAST

HIGH GAIN ENABLED

SOFTSTART

Figure 30. Soft-Start Timing with Illustrative System Behavior

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Brownout Protection
As the power line RMS voltage decreases, RMS input current must increase to maintain a constant output
voltage for a specific load. Brownout protection helps prevent excess system thermal stress (due to the higher
RMS input current) from exceeding a safe operating level. Power-line voltage is sensed at VINAC. When the
VINAC fails to exceed the brownout threshold for the brownout filter time, a brownout condition is detected and
both gate drive outputs are turned off. During brownout, COMP is actively pulled low and a soft-start condition is
initiated. Hysteresis is built into the brownout detection circuit to avoid chatter around the threshold. When VINAC
rises above the brownout threshold, the power stage soft-starts as COMP rises with controlled current.
The brownout detection threshold and its hysteresis are set by the voltage-divider ratio and resistor values.
Brownout protection is based on VINAC peak voltage; the threshold and hysteresis are also based on the line
peak voltage. Major hysteresis is provided by a 2-μA current-sink (IBOHYS) enabled whenever VINAC falls below
the brownout detection threshold. Minor hysteresis is also present in the form of a 50-mV offset (VBOHYS)
between the VINAC detection and clear thresholds. The peak VINAC voltage can be easily translated into an
RMS value. Example resistor values for the voltage divider are 8.61 MΩ ±1% from the rectified input voltage to
VINAC and 133 kΩ ±1% from VINAC to ground. These resistors set the typical thresholds for RMS line voltages,
as shown in Table 1.

Table 1. Brownout Thresholds (for conditions stated in the text)

THRESHOLD AC-LINE VOLTAGE (RMS)
Falling 66 V
Rising 78 V

Equation 8 and Equation 9 can be used to calculate the VINAC divider-resistor values based on desired
brownout detection and brownout clear voltage levels. VAC_OK is the desired RMS turn-on voltage, VAC_BO is the
desired RMS turn-off brownout voltage, and VLOSS is total series voltage drop due to wiring, EMI-filter, and
bridge-rectifier impedances at VAC_BO. VBODET, VBOHYS and IBOHYS are found in the data-tables of this datasheet.
æ 2(VAC _ OK - VAC _ BO ) - VBOHYS ö÷ æ VBOHYS ö
RA = ç ç 1+ ÷
ç IBOHYS ÷è VBODET ø
è ø (8)
RA
RB =
æ 2VAC _ BO - VLOSS ö
ç - 1÷
ç VBODET ÷
è ø (9)
Once standard values for the VINAC divider-resistors RA and RB are selected, the actual turn-on and brownout
threshold RMS voltages for the ac-line can be back-calculated with Equation 10 and Equation 11:
æ R öV V
VAC _ BO = ç 1 + A ÷ BODET + LOSS
è RB ø 2 2 (10)
R AIBOHYS VBOHYS
VAC _ OK = VAC _ BO + +
æ VBOHYS ö 2
2 ç 1+ ÷
ç
è VBODET ÷ø
(11)
An example of the timing for the brownout function is illustrated in Figure 31.
For a quick estimation of the turn-on and brownout voltages, simplify the foregoing equations by setting the VLOSS
and VBOHYS terms to zero.

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Dropout Detection
It is often the case that the ac-line voltage momentarily drops to zero or nearly zero, due to transient abnormal
events affecting the local ac power distribution network. Referred to as ac-line dropouts (or sometimes as
line-dips) the duration of such events usually extends to only 1 or 2 line cycles. During a dropout, the
down-stream power conversion stages depend on sufficient energy storage in the PFC output capacitance, which
is sized to provide the ride-through energy for a specified hold-up time. Typically while the PFC output voltage is
falling, the voltage-loop error amplifier output rises in an attempt to maintain regulation. As a consequence,
excess duty-cycle is commanded when the ac-line voltage returns and high peak current surges may saturate
the boost inductors with possible overstress and audible noise.
The UCC28063 incorporates a dropout detection feature which suspends the action of the error amplifier for the
duration of the dropout. If the VINAC voltage falls below 0.35 V for longer than 5 ms, a dropout condition is
detected and the error amplifier output is turned off. In addition, a 4-μA pull-down current is applied to COMP to
gently discharge the compensation network capacitors. In this way, when the ac-line voltage returns, the COMP
voltage (and corresponding duty-cycle setting) remains very near or even slightly below the level it was before
the dropout occurred. Current surges due to excess duty-cycle, and their undesired attendant effects, are
avoided. The dropout condition is cancelled and the error amplifier resumes normal operation when VINAC rises
above 0.71 V.
Based on the VINAC divider-resistor values calculated for brownout in the previous section, the input RMS
voltage thresholds for dropout detection VAC_DO and dropout clearing VDO_CLR can be determined using
Equation 12 and Equation 13, below.
æR ö
VDODET ç A + 1÷ + VLOSS
R
è B ø
VAC _ DO =
2 (12)
æR ö
VDOCLR ç A + 1÷ + VLOSS
VDO _ CLR = è RB ø
2 (13)
Avoid excessive filtering of the VINAC signal, or dropout detection may be delayed or defeated. An RC
time-constant of ≤ 100-μs should provide good performance. An example of the timing for the dropout function is
illustrated in Figure 32.

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VSENSE

COMP
IBOHYS
ON
VINAC

VBOCLR
VBODET

0V
t
BROWNOUT
DETECT

BROWNOUT
t BODLY
Figure 31. AC-Line Brownout Timing with Illustrative System Behavior

VSENSE

VINAC

COMP

VDOCLR
VDODET
0V t
DROPOUT
tDODLY
Figure 32. AC-Line Dropout Timing with Illustrative System Behavior

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VREF
VREF is an output which supplies a well-regulated reference voltage to circuits within the device as well as
serving as a limited source for external circuits. This output must be bypassed to GND with a low-impedance
0.1-μF or larger capacitor placed as close to the VREF and GND pins as possible. Current draw by external
circuits should not exceed a few milli-amperes and should not be pulsing.
The VREF output is disabled under the following conditions: when VCC is in UVLO, or when VSENSE is below
the Enable threshold. This output can only source current and is unable to accept current into the pin.

VCC
VCC is usually connected to a bias supply of between 13 V and 21 V. To minimize switching ripple voltage on
VCC, it should be by-passed with a low-impedance capacitor as close to the VCC and GND pins as possible.
The capacitance should be sized to adequately decouple the peak currents due to gate-drive switching at the
highest operating frequency. When powered from a poorly-regulated low-impedance supply, an external zener
diode is recommended to prevent excessive current into VCC.
The undervoltage-lockout (UVLO) condition is when VCC voltage has not yet reached the turn-on threshold or
has fallen below the turn-off threshold, having already been turned on. While in UVLO, the VREF output and
most circuits within the device are disabled and VCC current falls significantly below the normal operating level.
The same situation applies when VSENSE is below its Enable threshold. This helps minimize power loss during
pre-powerup and standby conditions.

Control of Downstream Converter

In the UCC28063, the PWMCNTL pin can be used to coordinate the PFC stage with a downstream converter.
Through the HVSEN pin, the PFC output voltage is monitored. A 12-μA current source (IHV_HYS) is enabled as
long as the output voltage remains below a programmed threshold. When the output voltage exceeds that
threshold, PWMCNTL pin is pulled to ground internally and can be used to enable a downstream converter. At
the same time the current source is disabled, providing hysteresis for a lower threshold at which the downstream
converter should be turned off. The enable/disable hysteresis is adjusted through the HVSEN voltage-divider
ratio and resistor values. The HVSEN pin is also used for the FailSafe over-voltage protection (OVP). When
designing the voltage divider, make sure this FailSafe OVP level is set above normal VSENSE OVP levels.
Because there are two thresholds associated with the HVSEN input detected through a single resistor divider,
the PWMCNTL turn-off voltage, VPWM-OFF, is linked to the FailSafe OVP voltage, VFLSF_OV, as shown by
Equation 14:
VPWM-OFF VFLSF _ OV
=
2.5 V 4.87 V (14)
Choosing either one first arbitrarily determines the other, so a trade-off may be necessary. The PWMCNTL
turn-on voltage, VPWM-ON, is programmed by choosing the upper divider resistor value in consideration with the
HVSEN hysteresis current, as shown in Equation 15 and Equation 16. The lower divider resistor is then
calculated as shown in Equation 17.
VPWM-ON = VPWM-OFF + IHV _ HYSRHV _ UPPER
(15)
V - VPWM-OFF
RHV _ UPPER = PWM-ON
IHV _ HYS
(16)
RHV _ UPPER
RHV _ LOWER =
æ VPWM-OFF ö
ç - 1÷
è 2.5 V ø (17)

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SYSTEM LEVEL PROTECTIONS

FailSafe OVP - Output Over-Voltage Protection

FailSafe OVP prevents any single failure from allowing the output to boost above safe levels. Redundant paths
for output voltage sensing provide additional protection against output over-voltage. Over-voltage protection is
implemented through two independent paths: VSENSE and HVSEN. The converter shuts down if either input
senses a severe over-voltage condition. The output voltage can still remain below a safe limit if either sense path
fails. The device is re-enabled when both sense inputs fall back into their normal ranges. At that time, the gate
drive outputs will resume switching under PWM control. A low-level over-voltage on VSENSE does not trigger
soft-start, but the COMP pin is discharged by an internal 2-kΩ resistance until the output voltage falls below the
2% hysteresis OV-clear threshold. A higher-level over-voltage on VSENSE additionally shuts off the gate-drive
outputs until the OV clears, but still does not trigger a soft-start. However, an overvoltage detected on HVSEN
does trigger a full soft-start and the COMP pin is fully discharged to 20 mV before the soft-start can begin.

Over-Current Protection
Under certain conditions (such as inrush, brownout-recovery, and output over-load) the PFC power stage sees
large currents. It is critical that the power devices be protected from switching during these conditions.
The conventional current-sensing method uses a shunt resistor in series with each MOSFET source leg to sense
the converter currents, resulting in multiple ground points and high power dissipation. Furthermore, since no
current information is available when the MOSFETs are off, the source-resistor current-sensing method results in
repeated turn-on of the MOSFETs during over-current (OC) conditions. Consequently, the converter may
temporarily operate in continuous conduction mode (CCM) and may experience failures induced by excessive
reverse-recovery currents in the boost diodes or other abnormal stresses.
The UCC28063 uses a single resistor to continuously sense the combined total inductor (input) current. This
way, turn-on of the MOSFETs is completely avoided when the inductor currents are excessive. The gate drive to
the MOSFETs is inhibited until total inductor current drops to near zero, precluding reverse-recovery-induced
failures (these failures are most likely to occur when the ac-line recovers from a brownout condition).
The nominal OC threshold voltage during two-phase operation is -200 mV, which helps minimize losses. This
threshold is automatically reduced to -166 mV during single-phase operation, either by detection of a phase
failure or because PHB is driven below 0.8 V. Note that the single-phase threshold is not simply 1/2 of the
dual-phase threshold, because the ratio of the single-phase peak current to the interleaved peak current is higher
than 1/2.
An OC condition immediately turns off both gate-drive outputs, but does not trigger a soft-start and does not
modify the error amplifier operation. The over-current condition is cleared when the total inductor current-sense
voltage falls below the OC-clear threshold (-15 mV).
Following an over-current condition, both MOSFETs are turned on simultaneously once the input current drops to
near zero. Because the two phase currents are temporarily operating in-phase, the current-sense resistance
should be chosen so that OC protection is not triggered with twice the maximum current peak value of either
phase in order to allow quick return to normal operation after an over-current event. Automatic phase-shift control
will re-establish interleaving within a few switching cycles.

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Open-Loop Protection
If the feedback loop is disconnected from the device, a 100-nA current source internal to the UCC28063 pulls the
VSENSE pin voltage towards ground. When VSENSE falls below 1.20 V, the device becomes disabled. When
disabled, the bias supply current decreases, both gate-drive outputs and COMP are actively pulled low, and a
soft-start condition is initiated. The device is re-enabled when VSENSE rises above 1.25 V. At that time, the gate
drive outputs will begin switching under soft-start PWM control.
If the feedback loop is disconnected from ground, the VSENSE voltage will be pulled high. When VSENSE rises
above the 2nd-level over-voltage protection threshold, both gate drive outputs are shut off and COMP is actively
pulled low. The device is re-enabled when VSENSE falls below the OV-clear threshold. The VSENSE input can
tolerate a limited amount of current into the device under abnormally high input voltage conditions. Refer to the
Absolute Maximum Ratings table near the beginning of this datasheet for details.

VCC Under-Voltage Lock-Out (UVLO) Protection

VCC must rise above the turn-on threshold for the PWM to begin functioning. If VCC drops below the UVLO
threshold during operation, both gate-drive outputs are actively pulled low, COMP is actively pulled low, and a
soft-start condition is triggered. VCC must again rise above the turn-on threshold for the PWM function to restart
in soft-start mode.

Phase-Fail Protection
The UCC28063 detects failure of either of the phases by monitoring the sequence of ZCD pulses. During normal
two-phase operation, if one ZCD input remains idle for longer than approximately 12 ms while the other ZCD
input switches normally, the over-current threshold is reduced and PWMCNTL goes to a high-impedance state,
indicating that the PFC power stage is not operating correctly. During normal single-phase operation (PHB < 0.8
V), phase failure is not monitored. Also on the UCC28063, phase failure is not monitored when COMP is below
approximately 222 mV.

CS-Open, TSET-Open & -Short Protection

In the event that the CS input becomes open-circuited, the UCC28063 detects this condition and will shutdown
the outputs and trigger a full-soft-start condition. In the event that the TSET input becomes either open-circuited
or short-circuited to GND, the UCC28063 detects these conditions and will shutdown the outputs and trigger a
full-soft-start condition. Normal operation will resume (with a soft-start) when the fault clears.

Thermal Shutdown Protection

Overloading of the gate-drive outputs and/or VREF can dissipate excess power within the device which may
raise the internal temperature of the circuits beyond a safe level. Even normal power dissipation can generate
excess heat if the thermal impedance is too high or the ambient temperature is too high. When the UCC28063
detects an internal over-temperature condition it will shutdown the outputs and trigger a full soft-start condition.
When the internal device junction temperature has cooled below the thermal hysteresis temperature, operation
will resume under soft-start control.

AC-Line Brownout and Dropout Protections

See specific discussions for each topic in previous sections (above) of this datasheet.

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Fault Logic Diagram

Figure 33 depicts the fault-handling logic involving VSENSE, COMP, and several internal states.
PHASE_B_OFF
STOP GDB

OC
STOP GDA

HIGH _OV

BROWNOUT HIGH_OV Latch

6.67V
HVSEN_OV COMP Discharge Latch S Q
UVLO +
S Q
EN R Q
TSET_FLT
CS_OPEN R Q
LOW _OV Latch
TSD 6.48V
S Q
+
+ 20mV
R Q
6.36V +
OV-Clear
COMP

4μA 2kΩ EN
1.25V +

LOW_OV

DIS _EA
DROPOUT
Gain -Disable Latch
S Q
VCC DIS _High_Gain
+
R Q
5.9V

VSENSE +
3.0V

Figure 33. Fault Logic with VSENSE Detections and Error Amplifier Control

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DESIGN EXAMPLE
An example of the UCC28063 PFC controller in a two-phase interleaved, transition-mode PFC pre-regulator is
shown in Figure 34.
D3

Bridge +

CIN
– RS
12V
R CA
100 RZA
F1 L1
2.2uF
20 k
D1
CF1 RP CF4 VOUT
VCC
1 nF 50 k ZCDA
CS 22pF RG1 Q1
RA GDA
PWMCNTL PWMCNTL 5
COUT RLOAD
RZB L2
VINAC
UCC28063 20 k
D2
CF5
CF2 RB VREF
ZCDB
CB PHB 22pF RG2 Q2
2.2uF GDB
COMP 5 RC RE

RZ HVSEN
TSET
VSENSE
CP
RT
CZ CF3 RD RF
AGND PGND

Figure 34. Typical Interleaved Transition-Mode PFC Pre-Regulator

Design Goals
The specifications for this design were chosen based on the power requirements of a typical 300-W LCD TV.
These specifications are shown in Table 2.

Table 2. Design Specifications

PARAMETER MIN TYP MAX UNIT
VIN RMS input voltage 85 265
VRMS
(VIN_MIN) (VIN_MAX)
VOUT Output voltage 390 V
fLINE AC-line frequency 47 63 Hz
PF Power factor at maximum load 0.90
POUT 300 W
η Full-load efficiency 92%
fMIN Minimum switching frequency 45 kHz

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Recommended PCB Device Layout

Interleaved transition-mode PFC system architecture dramatically reduces input and output ripple current,
allowing the circuit to use smaller and less expensive filters. To maximize the benefits of interleaving, the input
and output filter capacitors should be located after the two phase currents are combined together. Similar to
other power management devices, when laying out the printed circuit board (PCB) it is important to use star
grounding techniques and keep filter capacitors as close to device ground as possible. To minimize the
interference caused by capacitive coupling from the boost inductor, the device should be located at least 1 in
(25.4 mm) away from the boost inductor. It is also recommended that the device not be placed underneath
magnetic elements. Because of the precise timing requirement, timing-setting resistor RT should be placed as
close as possible to the TSET pin and returned to the analog ground. See Figure 35 for a recommended
component placement and layout.

CF4

Figure 35. Recommended PCB Layout

NOTE
PHB and VREF pins are connected by a jumper on the back of the board.

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Inductor Selection
The boost inductor is selected based on the inductor ripple current requirements at the peak of low line.
Selecting the inductor requires calculating the boost converter duty cycle at the peak of low line (DPEAK_LOW_LINE),
as shown in Equation 18.
VOUT - VIN_MIN 2 390 V - 85 V 2
DPEAK _ LOW _ LINE = = » 0.69
VOUT 390 V (18)
The minimum switching frequency of the converter (fMIN) under low line conditions occurs at the peak of low line
and is set between 25 kHz and 50 kHz to avoid audible noise. For this design example, fMIN is set to 45 kHz. For
a 2-phase interleaved design, L1 and L2 are determined as shown in Equation 19.
h ´ VIN _ MIN2 ´ DPEAK _ LOW _ LINE 0.92(85 V)2 0.69
L1 = L2 = = » 340 mH
POUT ´ fMIN 300 W ´ 45kHz (19)
The inductor for this design would have a peak current (ILPEAK) of 5.4 A, as shown in Equation 20, and an RMS
current (ILRMS) of 2.2 A, as shown in Equation 21.
POUT 2 300 W 2
ILPEAK = = » 5.4 Apk
VIN _ MIN ´ h 85 V ´ 0.92
(20)
ILPEAK 5.4 A
ILRMS = = » 2.2 Arms
6 6 (21)
This converter uses constant on time (TON) and zero-current detection (ZCD) to set up the converter timing.
Auxiliary windings on L1 and L2 detect when the inductor currents are zero. Selecting the turns ratio using
Equation 22 ensures that there will be at least 2 V at the peak of high line to reset the ZCD comparator after
every switching cycle.
The turns-ratio of each auxiliary winding is:
NP VOUT - VIN_MAX 2 390 V - 265 V 2
= = »8
Ns 2V 2V (22)

ZCD Resistor Selection (RZA, RZB)

The minimum value of the ZCD resistors is selected based on the internal clamps maximum current ratings of 3
mA, as shown in Equation 23.
V N 390 V
R ZA = R ZB ³ OUT S = » 16.3kW
NP ´ 3mA 8 ´ 3mA (23)
In this design the ZCD resistors are set to 20 kΩ, as shown in Equation 24.
R ZA = R ZB = 20kW (24)

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HVSENSE
The HVSENSE pin programs the PWMCNTL output of the UCC28063. The PWMCNTL open-drain output can be
used to disable a downstream converter while the PFC output capacitor is charging. PWMCNTL starts high
impedance and pulls to ground when HVSEN increases above 2.5 V. Setting the point where PWMCNTL
becomes active requires a voltage divider from the boost voltage to the HVSEN pin to ground. Equation 25 to
Equation 30 show how to set the PWMCNTL pin to activate when the output voltage is within 90% of its nominal
value.
VOUT _ OK = VOUT ´ 0.90 » 351 V
(25)
Resistor RE sets up the high side of the voltage divider and programs the hysteresis of the PWMCNTL signal.
For this example, RE was selected to provide 99 V of hysteresis, as shown in Equation 26. Three resistors in
series were used to meet voltage requirements.
Hysteresis 99 V
RE = = = 8.25MW » 3 ´ 2.74MW
12 mA 12 mA (26)
Resistor RF is used to program the PWMCNTL active threshold, as shown in Equation 27.
2.5 V 2.5 V
RF = = = 82.25kW
VOUT _ OK - 2.5 V 351V - 2.5 V
- 12 mA - 12 mA
RE 8.22MW
(27)
Select a standard resistor value for RF.
RF = 82.5kW (28)
This PWMCNTL output will remain active until a minimum output voltage (VOUT_MIN) is reached, as shown in
Equation 29.
2.5 V (RE + RF ) 2.5 V (8.22MW + 82.5kW )
VOUT _ MIN = = » 252 V
RF 82.5kW (29)
According to these resistor values, the FailSafe OVP threshold will be set according to Equation 30
4.87 V (RE + RF ) 4.87 V (8.22MW + 82.5kW )
VOV _ FAILSAFE = = » 490 V
RF 82.5kW (30)

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Output Capacitor Selection

The output capacitor (COUT) is selected based on holdup requirements, as shown in Equation 31.
POUT 1 300 W 1
2 2
h fLINE 0.92 47Hz
COUT ³ 2 2
= » 156 mF
VOUT - (VOUT _ MIN ) 390 V 2 - (252 V)2
(31)
Two 100-μF capacitors were used in parallel for the output capacitor.
COUT = 200 mF (32)
For this size capacitor, the low-frequency peak-to-peak output voltage ripple (VRIPPLE) is approximately 14 V, as
shown in Equation 33:
2 ´ POUT 1 2 ´ 300 W
VRIPPLE = = » 14 Vppk
h VOUT ´ 4p ´ fLINE ´ COUT 0.92 ´ 390 V ´ 4p ´ 47Hz ´ 200 mF (33)
In addition to holdup requirements, a capacitor must be selected so that it can withstand the low-frequency RMS
current (ICOUT_100Hz) and the high-frequency RMS current (ICOUT_HF); see Equation 34 to Equation 36.
High-voltage electrolytic capacitors generally have both a low- and a high-frequency RMS current ratings on the
product data sheets.
POUT 300 W
ICOUT _100Hz = = = 0.591 Arms
VOUT ´ h ´ 2 390 V ´ 0.92 ´ 2 (34)
2
æ 4 2VIN _ MIN ö
POUT 2 2 2
ICOUT _ HF = ç ÷ - I
(
COUT _100Hz )
çç 2 ´ h ´ VIN _ MIN 9pVOUT ÷÷
è ø (35)
2
æ 300 W ´ 2 2 4 2 ´ 85 V ö
ICOUT _ HF = ç ÷ - (0.591A )2 » 0.966 Arms
ç 2 ´ 0.92 ´ 85 V 9p ´ 390 V ÷
è ø (36)

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Selecting (RS) for Peak Current Limiting

The UCC28063 peak limit comparator senses the total input current and is used to protect the MOSFETs during
inrush and over-load conditions. For reliability, the peak current limit (IPEAK) threshold in this design is set for
120% of the nominal maximum current that will be observed during power up, as shown in Equation 37.
2POUT 2(1.2) 2 ´ 300 W 2 ´ 1.2
IPEAK = = » 13 A
h ´ VIN _ MIN 0.92 ´ 85 V
(37)
A standard 15-mΩ metal-film current-sense resistor will be used for current sensing, as shown in Equation 38.
The estimated power loss of the current-sense resistor (PRS) is less than 0.25 W during normal operation, as
shown in Equation 39.
200mV 200mV
RS = = » 15mΩ
IPEAK 13 A (38)
2 2
æ POUT ö æ 300 W ö
PRS =ç ÷÷ RS = ç ÷ ´ 15mW » 0.22 W
çV è 85 V ´ 0.92 ø
è IN_MIN ´ h ø (39)
The most critical parameter in selecting a current-sense resistor is the surge rating. The resistor needs to
withstand a short-circuit current larger than the current required to open the fuse (F1). I2t (ampere-squared-
seconds) is a measure of thermal energy resulting from current flow required to melt the fuse, where I2t is equal
to RMS current squared times the duration of the current flow in seconds. A 4-A fuse with an I2t of 14 A2s was
chosen to protect the design from a short-circuit condition. To ensure the current-sense resistor has high-enough
surge protection, a 15-mΩ, 500-mW, metal-strip resistor was chosen for the design. The resistor has a 2.5-W
surge rating for 5 seconds. This result translates into 833 A2s and has a high-enough I2t rating to survive a
short-circuit before the fuse opens, as described in Equation 40.
2.5 W
I2 t = ´ 5s = 833 A 2 s
0.015 W (40)

Power Semiconductor Selection (Q1, Q2, D1, D2)

The selection of Q1, Q2, D1, and D2 are based on the power requirements of the design. Application note
SLUU138, UCC38050 100-W Critical Conduction Power Factor Corrected (PFC) Pre-regulator, explains how to
select power semiconductor components for transition-mode PFC pre-regulators.
The MOSFET (Q1, Q2) pulsed-drain maximum current is shown in Equation 41:
IDM ³ IPEAK = 13 A (41)
The MOSFET (Q1, Q2) RMS current calculation is shown in Equation 42:

IPEAK 1 4 2 VIN _ MIN 13 A 1 4 2 ´ 85 V

IDS = - = - » 2.3 A
2 6 9p ´ VOUT 2 6 9p ´ 390 V (42)
To meet the power requirements of the design, IRFB11N50A 500-V MOSFETs were chosen for Q1 and Q2.
The boost diode (D1, D2) RMS current is shown in Equation 43:
I 4 2 ´ VIN _ MIN 13 A 4 2 ´ 85 V
ID = PEAK = » 1.4 A
2 9p ´ VOUT 2 9p ´ 390 V (43)
To meet the power requirements of the design, MURS360T3, 600-V diodes were chosen for D1 and D2.

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Brownout Protection
Resistor RA and RB are selected to activate brownout protection at ~75% of the specified minimum-operating
input voltage. Resistor RA programs the brownout hysteresis comparator, which is selected to provide 17 V (~12
VRMS) of hysteresis. Calculations for RA and RB are shown in Equation 44 through Equation 47.
Hysteresis 17 V
RA = = = 8.5MW
2 mA 2 mA (44)
To meet voltage requirements, three 2.87-MΩ resistors were used in series for RA.
R A = 3 ´ 2.87MW = 8.61MW (45)
1.4 V ´ R A 1.4 V ´ 8.61MW
RB = = = 135.8kW
VIN _ MIN ´ 0.75 2 - 1.4 V 85 V ´ 0.75 2 - 1.4 V
(46)
Select a standard value for RB.
RB = 133kW (47)
In this design example, brownout becomes active (shuts down PFC) when the input drops below 66 VRMS for
longer than 440 ms and deactivates (restarts with a full soft start) when the input reaches 78 VRMS.

Converter Timing
The maximum on-time TON depends on fMIN as determined by Equation 48. To ensure proper operation, the
timing must be set based on the highest boost inductance (L1MAX) and output power (POUT). In this design
example, the boost inductor could be as high as 390 µH. Calculate the timing resistor RT as shown in
Equation 49.
2æ VIN _ MIN ´ 2 ö
÷ 0.92 ´ (85 V )2 ç 1 - 85 V ´ 2 ÷
æ ö
h ´ VIN _ MIN
( ) çç1 - VOUT ÷ ç 390 V ø ÷
fMIN = è ø= è = 39.2kHz
POUT ´ L1MAX 300 W ´ 390 mH (48)
æ VIN _ MIN ´ 2 ö
÷ 133kW ç 1 - 85 V ´ 2 ÷
æ ö
133kW ç 1 -
ç Vout ÷ ç 390 V ø ÷
RT = è ø= è » 121kW
4 ms 4 ms
4.85 V ´ ´ fMIN 4.85 V ´ ´ 39.2kHz
V V (49)
This result sets the maximum frequency clamp (fMAX), as shown in Equation 50, which improves efficiency at light
load.
133kW 133kW
fMAX = = » 550kHz
2 ms ´ RT 2 ms ´ 121kW (50)

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UCC28063
SLUSAO7 – SEPTEMBER 2011 www.ti.com

Programming VOUT
Resistor RC is selected to minimize loading on the power line when the PFC is disabled. Construct resistor RC
from two or more resistors in series to meet high-voltage requirements. Resistor RD is then calculated based on
RC, the reference voltage, VREF, and the required output voltage, VOUT. Based on the values shown in
Equation 51 to Equation 54, the primary output over-voltage protection threshold should be as shown in
Equation 55:
RC = 2.74MW + 2.74MW + 3.01MW = 8.49MW (51)
VREF = 6 V (52)
VREF ´ RC 6 V ´ 8.49MW
RD = = = 132.7kW
VOUT - VREF 390 V - 6 V (53)
Select a standard value for RD.
RD = 133kW (54)
R + RD 8.49MW + 133kW
VOVP = 6.48 V C = 6.48 V = 420.1V
RD 133kW (55)

Voltage Loop Compensation

Resistor RZ is sized to attenuate low-frequency ripple to less than 2% of the voltage amplifier output range. This
value ensures good power factor and low harmonic distortion on the input current.
The transconductance amplifier small-signal gain is shown in Equation 56:
gm = 50 mS (56)
The voltage-divider feedback gain is shown in Equation 57:
V 6V
H = REF = » 0.015
VOUT 390 V (57)
The value of RZ is calculated as shown in Equation 58:
100mV 100mV
RZ = = = 9.52 kW
VRIPPLE ´ H ´ gm 14 V ´ 0.015 ´ 50 mS (58)
CZ is then set to add 45° phase margin at 1/5th of the line frequency, as shown in Equation 59:
1 1
CZ = = = 1.78 mF
fLINE 47Hz
2p ´ ´ R Z 2p ´ ´ 9.52kW
5 5 (59)
CP is sized to attenuate high-frequency switching noise, as shown in Equation 60:
1 1
Cp = = = 770pF
f 45kHz
2p ´ MIN ´ R Z 2p ´ ´ 9.52kW
2 2 (60)
Standard values should be chosen for RZ, CZ and CP, as shown in Equation 61 to Equation 63.
R Z = 9.53kW (61)
CZ = 2.2 mF (62)
CP = 820pF (63)

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ADDITIONAL REFERENCES

Related Parts
Table 3 lists several TI parts that have characteristics similar to the UCC28063.

Table 3. TI Related Parts

DEVICE DESCRIPTION
UCC28050/51 Transition-mode PFC controller for low to medium power applications
UCC28019 8-pin continuous-conduction-mode (ccm) pfc controller (with slew-rate correction current)
UCC28019A 8-pin continuous-conduction-mode (ccm) pfc controller (with 2-level voltage-error gain)
UCC28060 Two-phase interleaved transition-mode pfc controller (with input voltage range gain change)
UCC28061 Two-phase interleaved transition-mode pfc controller (with no input voltage gain change)
UCC28070 Two-phase interleaved ccm (average current mode) pfc controller

References
These references, design tools, and links to additional references, including design software, may be found at
www.power.ti.com
1. Evaluation Module, UCC28063EVM 300W Interleaved PFC Pre-regulator, SLUU512 from Texas Instruments
2. Application Note, UCC38050 100-W Critical Conduction Power Factor Corrected (PFC) Pre-regulator,
SLUU138 from Texas Instruments

Copyright © 2011, Texas Instruments Incorporated Submit Documentation Feedback 41

Product Folder Link(s): UCC28063
 PACKAGE OPTION ADDENDUM

www.ti.com 24-Sep-2011

PACKAGING INFORMATION

Orderable Device Status

(1) Package Type Package Pins Package Qty Eco Plan
(2) Lead/ MSL Peak Temp
(3) Samples
Drawing Ball Finish (Requires Login)
UCC28063D ACTIVE SOIC D 16 40 Green (RoHS CU NIPDAU Level-1-260C-UNLIM
& no Sb/Br)
UCC28063DR ACTIVE SOIC D 16 2500 Green (RoHS CU NIPDAU Level-1-260C-UNLIM
& no Sb/Br)

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)

(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 21-Sep-2011

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
UCC28063DR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 21-Sep-2011

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
UCC28063DR SOIC D 16 2500 333.2 345.9 28.6

Pack Materials-Page 2
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