Memory Management 107

Unit 6: Memory Management

Notes
Structure
6.1 Introduction
6.2 Memory Management
6.2.1 Background
6.2.2 Binding of Instructions and Data to Memory
6.2.3 Dynamic Loading
6.2.4 Dynamic Linking
6.2.5 Overlays
6.2.6 Address Space
6.2.7 Memory-Management Unit (MMU)
6.3 Swapping
6.4 Memory Allocation Techniques
6.4.1 Single Partition Memory Allocation
6.4.2 Multiple Partitions Memory Allocation
6.5 Paging
6.5.1 Structure of Page Table
6.5.2 Hardware Support
6.5.3 Protection
6.5.4 Sharing
6.6 Segmentation
6.6.1 Implementation of Segment Tables
6.6.2 Protection and Sharing
6.7 Paged Segmentation
6.7.1 Segmentation with Paging
6.8 Summary
6.9 Check Your Progress
6.10 Questions and Exercises
6.11 Key Terms
6.12 Further Readings

Objectives
After studying this unit, you should be able to:
z Explain the concept of memory management
z Describe the process of memory swapping
z Identify different strategies used for contiguous memory allocation
z Describe the concept of Paging
z Explain Segmentation that supports user view of memory
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6.1 Introduction
Notes In the previous unit, you have studied about the methods used for handling deadlock.
In this unit, you will study memory management. Memory is the electronic holding
place for instructions and data that the computers microprocessor can reach quickly.
When the computer is in normal operation, its memory usually contains the main parts
of the operating system and some or all of the application programs and related data
that are being used. Memory is often used as a shorter synonym for Random Access
Memory (RAM). This lesson will cover the concept of swapping and contiguous memory
allocation. You will also learn about the concept of paging and segmentation.
Memory management is very significant operating system because the multi-tasking
can happen in the system which switches the memory space from one process to
another.

6.2 Memory Management

In this section, you will learn about the memory management. Memory is sometimes
distinguished from storage, or the physical medium that holds the much larger amounts
of data that won’t fit into RAM and may not be immediately needed there. Storage
devices include hard disks, floppy disks, CD-ROM, and tape backup systems. The
terms auxiliary storage, auxiliary memory, and secondary memory have also been used
for this kind of data repository.
Additional kinds of integrated and quickly accessible memory are read-only memory
(ROM), Programmable ROM (PROM), Erasable Programmable ROM (EPROM). These
are used to keep special programs and data, such as the basic input/output system,
that need to be in the computer all the time. The memory is a resource that needs to be
managed carefully. Most computers have a memory hierarchy, with a small amount of
very fast, expensive, volatile cache memory, some number of megabytes of medium-
speed, medium-price, volatile main memory (RAM), and hundreds of thousands of
megabytes of slow, cheap, non-volatile disk storage.
It is the job of the operating system to coordinate how these memories are used. In
addition to the responsibility of managing processes, the operating system must
efficiently manage the primary memory of the computer. The part of the operating
system which handles this responsibility is called the memory manager. Since every
process must have some amount of primary memory in order to execute, the
performance of the memory manager is crucial to the performance of the entire system.
The memory manager is responsible for allocating primary memory to processes and
for assisting the programmer in loading and storing the contents of the primary memory.
Managing the sharing of primary memory and minimising memory access time are the
basic goals of the memory manager.
When an operating system manages the computer memory, there are two broad
tasks to be accomplished:
1. Each process must have enough memory in which to execute, and it can neither
run into the memory space of another process nor be run into by another process.
2. The different types of memory in the system must be used properly so that each
process can run most effectively.
The first task requires the operating system to set up memory boundaries for types
of software and for individual applications.
In most computers, it’s possible to add memory beyond the original capacity.
Example: You might expand RAM from 1 to 2 megabytes. This works fine, but
tends to be relatively expensive. It also ignores a fundamental fact of computing - most
of the information that an application stores in memory is not being used at any given
moment.

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It is important to note that a processor can only access memory one location at a
time, so the vast majority of RAM is unused at any moment. Since disk space is cheap
compared to RAM, then moving information in RAM to hard disk can greatly expand Notes
RAM space at no cost. This technique is called virtual memory management.
Disk storage is only one of the memory types that must be managed by the
operating system, and is the slowest. Ranked in order of speed, the types of memory in
a computer system are:
1. High-speed cache: This is fast, relatively small amounts of memory that are
available to the CPU through the fastest connections. Cache controllers predict
which pieces of data the CPU will need next and pull it from main memory into high-
speed cache to speed up system performance.
2. Main memory: This is the RAM that you see measured in megabytes when you
buy a computer.
3. Secondary memory: This is most often some sort of rotating magnetic storage that
keeps applications and data available to be used, and serves as virtual RAM under
the control of the operating system.
The operating system must balance the needs of the various processes with the
availability of the different types of memories, moving data in blocks (called pages)
between available memories as the schedule of processes dictates. Systems for
managing memory can be divided into two categories: the system of moving processes
back and forth between main memory and disk during execution (known as swapping
and paging) and the process that does not do so.
You can see the process of memory management in figure 6.1.

Figure 6.1: Diagram of Memory Management

6.2.1 Background
The background of memory management, Memory is central to the operation of a
modern computer system. Memory consists of a large array of words or bytes, each
with its own address. The CPU fetches instructions from memory according to the value
of the program counter. These instructions may cause additional loading from and
storing to specific memory addresses.
A typical instruction-execution cycle, for example, first fetches an instruction from
memory. The instruction is then decoded and may cause operands to be fetched from
memory. After the instruction has been executed on the operands, results may be
stored back in memory. The memory unit sees only a stream of memory addresses; it
does not know how they are generated (by the instruction counter, indexing, indirection,
literal addresses, and so on) or what they are for (instructions or data).
Accordingly, you can ignore how a memory address is generated by a program. We
are interested in only the sequence of memory addresses generated by the running
program.

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6.2.2 Binding of Instructions and Data to Memory

Notes Usually, you must understand that a program resides on a disk as a binary executable
file. The program must be brought into memory and placed within a process for it to be
executed. Depending on the memory management in use, the process may be moved
between disk and memory during its execution. The input queue is formed by the
collection of processes on the disk that is waiting to be brought into memory for
execution.
The normal procedure is to select one of the processes in the input queue and to
load that process into memory. As the process is executed, it accesses instructions and
data from memory. Eventually, the process terminates, and its memory space is
declared available.
It is important to note that address binding of instructions and data to memory
addresses can happen at three different stages.
1. Compile Time: If you know at compile time where the process will reside in
memory, then absolute code can be generated. If, at some later time, the starting
location changes, then it will be necessary to recompile this code.
2. Load Time: If it is not known at compile time where the process will reside in
memory, then the compiler must generate relocatable code.
3. Execution Time: If the process can be moved during its execution from one
memory segment to another, then binding must be delayed until run time.
Figure 6.2 is a depiction of the multi-step processing of a user program.

Source
program

Compiler or Compile
assembler time

Object
Other module
object
modules
Linkage
editor

Load Load
module time
System
library

Loader
Dynamically
loaded
system
library In-memory
Executor
Dynamic binary
time (run
linking memory
time)
image

Figure 6.2: Multi-step Processing of a User Program

6.2.3 Dynamic Loading

It is important for you to understand that dynamic loading is the process in which one
can attach a shared library to the address space of the process during execution, look
up the address of a function in the library, call that function and then detach the shared
library when it is no longer needed. It is implemented as an interface to the services of
the dynamic linker.

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6.2.4 Dynamic Linking
Dynamic linking is accomplished by placing the name of a sharable library in the Notes
executable image. Actual linking with the library routines does not occur until the image
is run, when both the executable and the library are placed in memory. An advantage of
dynamic linking is that multiple programs can share a single copy of the library.

6.2.5 Overlays
Overlaying means replacement of a block of stored instructions or data with another.
Overlaying is a programming method that allows programs to be larger than the central
processing units main memory. It is essential to note that an embedded system would
normally use overlays because of the limitation of physical memory, which is internal
memory for a system- on-chip.
The method assumes dividing a program into self-contained object code blocks
called overlays. The size of an overlay is limited according to memory constraints. The
place in memory where an overlay is loaded is called an overlay region or destination
region. Although the idea is to reuse the same block of main memory, multiple region
systems could be defined. The regions can be of different sizes. An overlay manager,
possibly part of the operating system, will load the required overlay from external
memory into its destination region in order to be used. Some linkers provide support for
overlays.

6.2.6 Address Space

The comparison should also be noted between logical and physical address space. An
address generated by the CPU is commonly referred to as a logical address, whereas
an address seen by the memory unit-that is, the one loaded into the memory-address
register of the memory-is commonly referred to as a physical address. The compile-time
and load-time address-binding methods generate identical logical and physical
addresses. However, the execution-time address-binding scheme results in differing
logical and physical addresses. In this case, we usually refer to the logical address as a
virtual address. The set of all logical addresses generated by a program is a logical-
address space; the set of all physical addresses corresponding to these logical
addresses is a physical-address space. Thus, in the execution-time address-binding
scheme, the logical- and physical-address spaces differ.

6.2.7 Memory-Management Unit (MMU)

A memory management unit (MMU), sometimes called paged memory management
unit (PMMU), is a computer hardware component responsible for handling accesses to
memory requested by the CPU. Its functions include translation of virtual addresses to
physical addresses (i.e., virtual memory management), memory protection, cache
control, bus arbitration, and, in simpler computer architectures (especially 8-bit
systems), bank switching.

6.3 Swapping
In this section, you will study about the swapping mechanism. Any operating system
has a fixed amount of physical memory available. Usually, application need more than
the physical memory installed on your system, for that purpose the operating system
uses a swap mechanism: instead of storing data in physical memory, it uses a disk file.
Swapping is the act of moving processes between memory and a backing store.
This is done to free up available memory. Swapping is necessary when there are more
processes than available memory. At the coarsest level, swapping is done a process at
a time.
To move a program from fast-access memory to a slow-access memory is known
as "swap out", and the reverse operation is known as "swap in". The term often refers
specifically to the use of a hard disk (or a swap file) as virtual memory or "swap space".
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When a program is to be executed, possibly as determined by a scheduler, it is

swapped into core for processing; when it can no longer continue executing for out
Notes again.
You can see the process of memory swapping in figure 6.3.

Figure 6.3: The Memory Swapping

6.4 Memory Allocation Techniques

The real challenge of efficiently managing memory is seen in the case of a system
which has multiple processes running at the same time. Since primary memory can be
space-multiplexed, the memory manager can allocate a portion of primary memory to
each process for its own use. However, the memory manager must keep track of which
processes are running in which memory locations, and it must also determine how to
allocate and deallocate available memory when new processes are created and when
old processes complete execution. While various different strategies are used to
allocate space to processes competing for memory, three of the most popular are: Best
fit, Worst fit and First fit. Each of these strategies is described below:
1. Best fit: The allocator places a process in the smallest block of unallocated
memory in which it will fit.
Example: Suppose a process requests 12KB of memory and the memory manager
currently has a list of unallocated blocks of 6KB, 14KB, 19KB, 11KB, and 13KB
blocks. The best-fit strategy will allocate 12KB of the 13KB block to the process.
2. Worst fit: The memory manager places a process in the largest block of
unallocated memory available. The idea is that this placement will create the largest
hold after the allocations, thus increasing the possibility that compared to best fit;
another process can use the remaining space.
Example: Using the same example as above, worst fit will allocate 12KB of the
19KB block to the process, leaving a 7KB block for future use.
3. First fit: There may be many holes in the memory, so the operating system, to
reduce the amount of time it spends analysing the available spaces, begins at the
start of primary memory and allocates memory from the first hole it encounters large
enough to satisfy the request.
Example: Using the same example as above, first fit will allocate 12KB of the 14KB
block to the process.
In figure 6.4, the Best fit and first fit strategies both leave a tiny segment of memory
unallocated just beyond the new process. Since the amount of memory is small, it is not
likely that any new processes can be loaded here. This condition of splitting primary
memory into segments as the memory is allocated and deallocated is known as
fragmentation. The Worst fit strategy attempts to reduce the problem of fragmentation
by allocating the largest fragments to new processes. Thus, a larger amount of space
will be left as seen in the Figure 6.4.

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Notes

Figure 6.4: Diagram of Best Fit, Worst Fit and First Fit Memory Allocation Method

6.4.1 Single Partition Memory Allocation

It is important to note that the memory is divided into two partitions, one for the resident
operating system, and one for the user process. Since operating system is also a
program, it must also be loaded into the memory for its operation. For this purpose,
memory is divided into two partitions, one for the resident operating system and the
other for the user processes. The operating system may be either low memory (memory
having low addresses) or into the high memory as you can see in the Figure 6.5 below.

0 0
Operating system

User processes

User processes

Operating system

512K 512K

Figure 6.5: Operating System Loaded in (a) Low Memory (b) High Memory
Since, both the operating system and user processes reside in the memory, some
mechanism needs to be enforced to protect the memory allocated to the operating
system from being accessed by the user process. This protection may be enforced with
the help of two registers – relocation register and limit register. The relocation register
contains the value of the smallest physical address while limit register contains the

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range of the allowable logical address. The hardware support for this type of partitioning
is shown to you in Figure 6.6.
Notes
Limit register Relocation
register

Memory
logical physical
address yes address
CPU < +

no

Trap; addressing error

Figure 6.6: Hardware Support for Relocation and Limit Registers

With relocation and limit registers, each logical address must be less than the limit
register; the MMU maps the logical address dynamically by adding the value in the
relocation register. This mapped address is then sent to memory.
In a multi-programming environment, it is desirable that more than one user
processes may be brought into the memory. For this purpose, memory may be divided
into multiple partitions of fixed size. Each of these partitions may house one user
process. Thus, in this scheme, the number of processes residing in the memory is
limited by the number of partitions in the memory. When a partition is free, a process is
selected from the input queue and is loaded into the free partition. When the process
terminates, the partition becomes available for other processes.
The operating system keeps a table indicating which partitions of the memory are
free and which are occupied. In the beginning all the memory is available to the user
process. When a process arrives and needs memory, we search for a chunk of memory
(also called hole) large enough to accommodate the process. If we find one, we allocate
only as much memory as is needed.
Example: Assume a situation in which we have 2560K memory and the resident
operating system occupies 400K. This leaves 2160K for the user processes.

6.4.2 Multiple Partitions Memory Allocation

It must be kept in mind that multiple partitions memory allocation includes the following:

Fixed-Partition Memory Allocation

Memory is divided into a number of fixed sized partitions as shown to you in figure 6.7.
Each partition may contain exactly one process. When a partition is free, a process is
selected from the input Queue and is loaded into a free partition. Some features of fixed
partition memory allocation:
z very easy to implement
z common in old batch processing systems
z well suited to well-known job mix
z presumes largest possible process size
z must reconfigure system for larger processes

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Memory Management 115
z likely to use memory inefficiently
z large internal fragmentation losses
Notes
z swapping results in convoys on partitions

Figure 6.7: Fixed Partition Memory Allocation

Variable Memory Allocation

It is important to note that initially all memory is available for user processes, and is
considered as large block of available memory. When a process arrives and needs
memory, we search for a hole large enough for this process and allocate only as much.
Some features of variable memory allocation:
z start with one large "heap" of memory
z when a process requests more memory
z find a large enough chunk of memory
z carve off a piece of the requested size
z put the remainder back on the free list
z when a process frees memory
z put it back on the free list
z eliminates internal fragmentation losses

OS OS

P3
P2

P1

P1

P2

P3

Fixed partition Allocation Variable partition Allocation

Figure 6.8: Fixed and Variable Partition Allocation

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Figure 6.8 above shows comparison between fixed and variable partition allocation.

Notes It is important to note that fragmentation happens in a dynamic memory allocation

system when many of the free blocks are too small to satisfy any request.
External Fragmentation occurs when a dynamic memory allocation algorithm
allocates some memory and a small piece is left over that cannot be effectively used. If
too much external fragmentation occurs, the amount of usable memory is drastically
reduced. Total memory space exists to satisfy a request, but it is not contiguous.
Internal fragmentation is the space wasted inside of allocated memory blocks
because of restriction on the allowed sizes of allocated blocks. Allocated memory may
be slightly larger than requested memory; this size difference is memory internal to a
partition, but not being used.

6.5 Paging
In this section, you will learn about the concept and process of paging. A possible
solution to the external fragmentation problem is to permit the logical address space of
a process to be non-contiguous, thus allowing a process to be allocated physical
memory wherever the latter is available. One way of implementing this solution is
through the use of a paging scheme. Paging avoids the significant problem of fitting the
varying-sized memory chunks onto the backing store, from which most of the previous
memory-management schemes suffered.
When some code fragments or data residing in main memory need to be swapped
out, space must be found on the backing store.
The fragmentation problems discussed in connection with main memory are also
prevalent with backing store, except that access is much slower, so compaction is
impossible. Because of its advantages over the previous methods, paging in its various
forms is commonly used in many operating systems.
Physical memory is broken into fixed-sized blocks called frames. Logical memory is
also broken into blocks of the same size called pages. When a process is to be
executed, its pages are loaded into any available memory frames from the backing
store. The backing store is divided into fixed-sized blocks that are of the same size as
the memory frames.

Figure 6.9: Paging Hardware

The hardware support for paging is illustrated in Figure 6.9. Every address
generated by the CPU is divided into two parts: a page number (p) and a page offset
(d). The page number is used as an index into a page table. The page table contains
the base address of each page in physical memory. This base address combined with
the page offset to define the physical memory address that is sent to the memory unit.
The paging model of memory as is shown in Figure 6.10.

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Notes

Figure 6.10: Paging Model of Logical and Physical Memory

The page size (like the frame size) is defined by the hardware. The size of page is
typically a power of 2 varying between 512 bytes and 8,192 bytes per page, depending on
the computer architecture. The selection of a power of 2 as a page size makes the
translation of a logical address into a page number and page offset particularly easy. If the
size of logical address space is 2", and a page size is 2" addressing units (bytes or
words), then the high-order m – n bits of a logical address designate the page number,
and the n low-order bits designate the page offset. Thus, the logical address is as follows:
Table 6.1: Logical Address
Page Number Page Offset
p d
m–n n

where p is an index into the page table and d is the displacement within the page.
Example: For a concrete, although minuscule, consider the memory of Figure 6.11.
Using a page size of 4 bytes and a physical memory of 32 bytes (8 pages), we show an
example of how the user's view of memory can be mapped into physical memory.
Logical address 0 is page 0, offset 0, indexing into the page table; we find that page 0 is
in frame 5. Thus, logical address 0 maps to physical address 20 (= (5 × 4) + 0). Logical
address 3 (page 0, offset 3) maps to physical address 23 (= (5 × 4) + 3). Logical
address 4 is page 1, offset 0; according to the page table, page 1 is mapped to frame 6.
Thus, logical address 4 maps to physical address 24 (= (6 × 4) + 0). Logical address 13
maps to physical address 9.

Figure 6.11: Paging Example for a 32-byte Memory with 4-byte Pages

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Paging itself is a form of dynamic relocation.

Notes Every logical address is bound by the paging hardware to some physical address.
The observant reader will have realised that paging is similar to using a table of base
(relocation) registers, one for each frame of memory.
When using a paging scheme, you have no external fragmentation: Any free frame
can be allocated to a process that needs it. However, you may have some internal
fragmentation. Notice that frames are allocated as units. If the memory requirements of
a process do not happen to fall on page boundaries, the last frame allocated may not be
completely full.
Example: If pages are 2048 bytes, a process of 72,766 bytes would need 35 pages
plus 1,086 bytes. It would be allocated 36 frames, resulting in an internal fragmentation
of 2048 – 1086 = 962 bytes.
You will find it important to note that in the worst case, a process would need n
pages plus one byte. It would be allocated n + 1 frames, resulting in an internal
fragmentation of almost an entire frame. If process size is independent of page size, we
expect internal fragmentation to average one-half page per process. This consideration
suggests that small page sizes are desirable. Disk I/O is more efficient when the
number of data being transferred is larger. Generally, page sizes have grown over time
as processes, data sets, and main memory have become larger. Today, pages typically
are either 2 or 4 kilobytes.
You may already be aware that when a process arrives in the system to be
executed, its size, expressed in pages, is examined. Each page of the process needs
one frame. Thus, if the process requires n pages, there must be at least n frames
available in memory. If there are n frames available, they are allocated to this arriving
process. The first page of the process is loaded into one of the allocated frames, and
the frame number is put in the page table for this process. The next page is loaded into
another frame, and its frame number is put into the page table, and so on (Figure 6.12).

Free Frame Free Frame

List List
14 15
13
18 13 13 Page 1
20
15 14 14 Page 0

15 15

Page 0
16 16
Page 0 Page 1
Page 1 17 Page 2 17
Page 2 Page 3
Page 3 New Page 2
18 18
New

19 0 14 19
Page 3
20 1 13 20
2 18
21 21
(a) 3 20 (b)
New Process Page Table

Figure 6.12: Free Frames (a) Before Allocation, and (b) After Allocation

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An important aspect of paging is the clear separation between the user's view of
memory and the actual physical memory. The user program views that memory as one
single contiguous space, containing only this one program. In fact, the user program is Notes
scattered throughout physical memory, which also holds other programs. The difference
between the user's view of memory and the actual physical memory is reconciled by the
address-translation hardware. The logical addresses are translated into physical
addresses. This mapping is hidden from the user and is controlled by the operating
system.
You must notice that the user process by definition is unable to access memory it
does not own. It has no way of addressing memory outside of its page table, and the
table includes only those pages that the process owns.
Since the operating system is managing physical memory, it must be aware of the
allocation details of physical memory use; which frames are allocated? Which frames
are available? How many total frames there are? Etc. This information is generally kept
in a data structure called a frame table. The frame table has one entry for each physical
page frame, indicating whether the latter is free or allocated and, if it is allocated, to
which page of which process or processes.
In addition, you may say that the operating system must be aware that user
processes operate in user space, and all logical addresses must be mapped to produce
physical addresses. If a user makes a system call (to do I/O, for example) and provides
an address as a parameter (a buffer, for instance) that address must be mapped to
produce the correct physical address. The operating system maintains a copy of the
page table for each process, just as it maintains a copy of the instruction counter and
register contents. This copy is used to translate logical addresses to physical addresses
whenever the operating system must map a logical address to a physical address
manually. It is also used by the CPU dispatcher to define the hardware page table when
a process is to be allocated the CPU. Paging, therefore, increases the context-switch
time.

6.5.1 Structure of Page Table

It is essential to note that each operating system has its own methods for storing page
tables. Most allocate a page table for each process. A pointer to the page table is stored
with the other register values (like the instruction counter) in the process control block.
When the dispatcher is told to start a process, it must reload the user registers and
define the correct hardware page-table values from the stored user page table.

6.5.2 Hardware Support

You must understand that the hardware implementation of the page table can be done
in a number of different ways. In the simplest case, the page table is implemented as a
set of dedicated registers. These registers should be built with very high-speed logic to
make the paging address translation efficient. Every access to memory must go through
the paging map, so efficiency is a major consideration. The CPU dispatcher reloads
these registers, just as it reloads the other registers. Instructions to load or modify the
page-table registers are, of course, privileged, so that only the operating system can
change the memory map.
Example: The DEC PDP-11 is an example of such an architecture. The address
consists of 16 bits, and the page size is 8K. The page table, thus, consists of eight
entries that are kept in fast registers.
The use of registers for the page table is satisfactory if the page table is reasonably
small (for example, 256 entries). Most contemporary computers, however, allow the
page table to be very large (for example, 1 million entries). For these machines, the use
of fast registers to implement the page table is not feasible. Rather, the page table is
kept in main memory, and a page-table base register (PTBR) points to the page table.

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Changing page tables requires changing only this one register, substantially reducing
context-switch time.
Notes
The problem with this approach is the time required to access a user memory
location. If you want to access location i, you must first index into the page table, using
the value in the PTBR offset by the page number for 1. This task requires a memory
access. It provides us with the frame number, which is combined with the page offset to
produce the actual address. You can then access the desired place in memory. With
this scheme, two memory accesses are needed to access a byte (one for the page-
table entry, one for the byte).
Thus, memory access is slowed by a factor of 2. This delay would be intolerable
under most circumstances. We might as well resort to swapping. The standard solution
to this problem is to use a special, small, fast-lookup hardware cache, variously called
associative registers or translation look-aside buffers (TLBs). A set of associative
registers is built of especially high-speed memory. Each register consists of two parts: a
key and a value. When the associative registers are presented with an item, it is
compared with all keys simultaneously. If the item is found, the corresponding value
field is output. The search is fast; the hardware, however, is expensive. Typically, the
number of entries in a TLB varies between 8 and 2048.
Associative registers are used with page tables in the following way. The
associative registers contain only a few of the page-table entries. When a logical
address is generated by the CPU, its page number is presented to a set of associative
registers that contain page numbers and their corresponding frame numbers. If the
page number is found in the associative registers, its frame number is immediately
available and is used to access memory. The whole task may take less than 10%
longer than it would were an unmapped memory reference used.
If the page number is not in the associative registers, a memory reference to the
page table must be made. When the frame number is obtained, you can use it to
access memory. In addition, we add the page number and frame number to the
associative registers, so that they will be found quickly on the next reference. If the TLB
is already full of entries, the operating system must select one for replacement.
Unfortunately, every time a new page table is selected (for instance, each context
switch), the TLB must be flushed (erased) to ensure that the next executing process
does not use the wrong translation information. Otherwise, there could be old entries in
the TLB that contain valid virtual addresses but have incorrect or invalid physical
addresses left over from the previous process.
The percentage of times that a page number is found in the associative registers is
called the hit ratio. An 80% hit ratio means that you find the dared page number in the
associative registers 80% of the time.
Example: If it takes 20 nanoseconds to search the associative registers and 100
nanoseconds to access memory, then a mapped memory access takes 120
nanoseconds when the page number is in the associative registers. If you fail to find the
page number in associative registers (20 nanoseconds), then you must first access
memory for the page table and frame number (100 nanoseconds), and then access the
desired byte in memory (100 nanoseconds), for a total of 220 nanoseconds. To find the
effective memory-access time, you must weigh each case by its probability:
Effective access time = 0.80 × 120 + 0.20 × 220
= 140 nanoseconds.
In this example, you suffer a 40 per cent slowdown in memory access time (from
100 to 140 nanoseconds). This increased hit rate produces only a 22% slowdown in
memory also time.
You must be aware that the hit ratio is clearly related to the number of associative
registers. With the number of associative registers ranging between 16 and 512, a hit
ratio of 80% to 98% can be obtained.
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Example: The Motorola 68030 processor (used in AE: Macintosh systems) has a
22-entry TLB. The Intel 80486 CPU (found in some) has 32 registers, and claims a 98%
hit ratio. Notes
6.5.3 Protection
It is important to note that memory protection in a paged environment is accomplished
by protection bits that are associated with each frame. Normally, these bits are kept in
the page table. One bit can define a page to be read and write or read-only. Every
reference to memory goes through the page table to find the correct frame number. At
the same time that the physical address is being computed, the protection bits can be
checked to verify that no writes are being made to a read-only page. An attempt to write
to a read-only page causes a hardware trap the operating system (memory-protection
violation). This approach to protection can be expanded easily to provide a finer level of
protection. You can create hardware to provide read-only, read-write, or execute-only
protection. Or, by providing separate protection bits for each kind of access, any
combination of these accesses can be allowed, and illegal attempts will be trapped to
the operating system.
One more bit is generally attached to each entry in the page table: a valid-invalid
bit. When this bit is set to "valid," this value indicates that the associated page is in the
process's logical address space, and is thus a legal (valid) page. If the bit is set to
"invalid," this value indicates that the page is not in the process's logical address space.
Illegal addresses are trapped by using the valid-invalid bit. The operating system sets
this bit for each page to allow or disallow accesses to that page.
Example: In a system with a 14-bit address space (0 to 16,383), we may have a
program that should use only addresses 0 to 10,468. Given a page size of 2K, we get
the situation shown in Figure 6.12. Addresses in pages 0, 1, 2, 3, 4, and 5 are mapped
normally through the page table. Any attempt to generate an address in pages 6 or 7,
however, finds that the valid-invalid bit is.

6.5.4 Sharing
You need to know that in multi-programming or in multi-user environment it is common
for many users to be executing the same program. If individual copies of these
programs were given to each user, a significant part of the primary storage would be
wasted. The solution is to share those pages that can be shared.
The concept of shared pages is shown in figure 6.13.

Figure 6.13: Shared Pages

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Sharing must be carefully regulated to prevent one process from altering data that
another process is accessing.
Notes
In most systems the shared programs are divided into separate pages, i.e. coding
and data are kept separate. This is achieved by having page map table entries of
different processes point to the same page frame, that page frame is shared among
those processes.

6.6 Segmentation
In this section, you will understand the concept and meaning of segmentation. An
important aspect of memory management that became unavoidable with paging is the
separation of the user's view of memory and the actual physical memory. The user's
view of memory is not the same as the actual physical memory. The user's view is
mapped onto physical memory. The mapping allows differentiation between logical
memory and physical memory.
What is the user's view of memory? Does the user think of memory as a linear array
of bytes, some containing instructions and others containing data, or is there some
other preferred memory view? There is general agreement that the user or programmer
of a system does not think of memory as a linear array of bytes. Rather, the user
prefers to view memory as a collection of variable-sized segments, with no necessary
ordering among segments as you can see in figure 6.14.

Sub- Stack
routine

Symbol
Table

sqrt

Main
Program

Figure 6.14: User's View of a Program

You must consider how you think of a program when you are writing it. You think of
it as a main program with a set of subroutines, procedures, functions or modules. There
may also be various data structures: tables, arrays, stacks, variables and so on. Each of
these modules or data elements is referred to by mine. You talk about "the symbol
table," "function Sqrt," "the main program," without caring what addresses in memory
these elements occupy. You are not concerned with whether the symbol table is stored
before or after the Sqrt faction. Each of these segments is of variable length; the length
is intrinsically defined by the purpose of the segment in the program. Elements within an
augment are identified by their offset from the beginning of the segment: the first
statement of the program, the seventeenth entry in the symbol table, the fifth instruction
of the Sqrt functions, and so on.
It is important to note that segmentation is a memory-management scheme that
supports this user view of memory. A logical address space is a collection of segments.
Each segment has a name and a logical address space is a collection or segments,
each segment a name and a length. The addresses specify both the segment name
and offset within the segment. It is important to note that the user therefore specifies
each address by two quantities; a segment name and an offset. (Contrast this scheme
with the paging scheme, where the user specified only a single address, which was

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partitioned by the hardware into a page number and an offset, all invisible to the
programmer.)
Notes
For simplicity of implementation, segments are numbered and are referred to by a
segment number, rather than by a segment name. Thus, you may say that a logical
address consists of a two tuple:
<segment-number, offset>
Normally, the user program is compiled, and the compiler automatically constructs
reflecting the input program. A Pascal compiler might create separate segments for
The global variables;
The procedure call stack, to store parameters and return addresses;
The code portion of each procedure or function; and
The local variables of each procedure and function.
A FORTRAN compiler might create a separate segment for each common block.
Arrays might be assigned separate segments. The loader would take all these
segments and assign them segment numbers. Although the user can now refer to
objects in the program by a two-dimensional address, the actual physical memory is
still, of course, a one-dimensional sequence of bytes. Thus, you must define an
implementation to map two dimensional user-defined addresses into one-dimensional
physical addresses. This mapping is affected by a segment table. Each entry of the
segment table has a segment base and segment limit. The segment base contains the
starting physical address where the segment resides in memory, whereas the segment
limit specifies the length of the segment.

Limit Base

Segment Table

CPU s d

YES
< +

No

Physical Memory

TRAP: Address Error

Figure 6.15: Segmentation Hardware

The use of a segment table is illustrated in Figure 6.15. A logical address consists
of two parts: a segment number, s, and an offset into that segment, d. The segment
number is used as an index into the segment table. The offset of the logical address
must be between 0 and the segment limit. If it is not, we trap to the operating system. If
this offset is legal, it is added to the segment base to produce the address in physical

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memory of the desired byte. The segment table is thus essentially an array of base-limit
register pairs.
Notes
Example: Consider the situation shown in Figure 6.16. We have segments
numbered from 0 through 4. The segments are stored in physical memory as shown.
The segment table has a separate entry for each segment, giving the beginning
address of the segment in physical memory (the base) and the length of that segment
(the limit). For example, segment 2 is 400 bytes long, and begins at location 4300.
Thus, a reference to byte 53 of segment 2 is mapped onto location 4300 + 53 = 4353. A
reference to segment 3, byte 852, is mapped to 3200 (the base of segment 3) +852 =
4052. A reference to byte 1222 of segment 0 would result in a trap to the operating
system, as this segment is on bytes long.

Subroutine Stack 1400

Segment 0
Segment 3 2400

Symbol table
Segment 0
Limit Base
Sqrt
Segment 4 1000 1400 3200
Main 400 6300
Program Segment 3
400 4300
1100 3200
4700 4300
Segment 1 Segment 2 Segment 2
4700

Segment 4

5700
6300
Segment 1
6700

Figure 6.16: Examples of Segmentation

6.6.1 Implementation of Segment Tables

You must be aware that segmentation is closely related to the partition models of
memory management presented earlier, the main difference being that one program
may consist of segments. Segmentation is a more complex concept. Like the page
table, the segment table can be put either in fast registers or in memory.
A segment table in registers can be referenced quickly; the addition to the base
and comparison with the limit can be done simultaneously to save time.
In the case where a program may consist of a large number of segments, it is not
feasible to keep the segment table in registers, so you must keep it in memory.
Segment-table bases register (STBR) points to the segment table. Also, because the
number of segment used by a program may vary widely, a segment-table length
register (STLR) is used. For a logical address (s, d), we first check that the segment
number s is legal (that is, s < STLR). Then, we add the segment number to the STBR,
resulting in the address (STBR + s) in memory of the segment-table entry. The entry is
read from memory and we proceed as before: Check the offset against the segment
length and compute the physical address of the desired byte as the sum of the segment
base and offset.

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As occurs with paging, this mapping requires two memory references per logical
address, effectively slowing the computer system by a factor of 2 unless something is
done. The normal solution is to use a set of associative registers to hold the most Notes
recently used segment-table entries. Again, a small set of associative registers can
generally reduce the time required for memory accesses to 10 or 15% slower than
unmapped memory accesses.

6.6.2 Protection and Sharing

It is important to note that a particular advantage of segmentation is the association of
protection with the segments. Because the segments represent a semantically defined
portion of the program, it is likely that all entries in the segment will be used the same
way. Hence, we have some segments that are instructions, whereas other segments
are data. In a modern architecture, instructions are non-self-modifying, so instruction
segments can be defined as read-only or execute only. The memory mapping hardware
will check the protection bits associated with each segment table entry to prevent illegal
accesses to memory, such as attempts to write into a read-only segment, or to use an
execute-only segment as data.
By placing an array in its own segment, the memory-management hardware will
automatically check that array indices are legal and do not stray outside the array
boundaries. Thus, many common program errors will be detected by the hardware
before they can cause serious damage.
Another advantage of segmentation involves the sharing of code or data. Each
process has a segment table associated with it, which the dispatcher uses to define the
hardware segment table when this process is given the CPU. Segments are shared
when entries in the segment tables of two different processes point to the same
physical locations. Sharing of Segments in a Segmented Memory System is shown in
figure 6.17.

Editor
Limit Base
Segment 0
0 25286 43062
43062
1 4425 68348
Data 1 Segment Table Editor
Process P1
68348
Segment 1 Data 1
72773

Editor
90003
Segment 0 Data 2
Limit Base 98553
0 25286 43062
Data 1
1 8850 90003
Physical Memory
Segment Table
Segment 1 Process P2

Figure 6.17: Sharing of Segments in a Segmented Memory System

The sharing occurs at the segment level. Thus, any information can be shared if it is
defined to be a segment. Several segments can be shared, so program composed of
several segments can be shared.
Example: Consider the use of a text editor in a time-sharing system. A complete
editor might be quite large, composed of many segments. The segments can be shared
among all users, limiting the physical memory needed to support editing tasks. Rather
than n copies of the editor, we need only one copy. For each user, we still need

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separate, unique segments to store local variables. These segments, of course, would
not be shared.
Notes
It is also possible to share only parts of programs.
Example: Common subroutine packages can be shared among many users if they
are defined sharable, read-only segments. Two FORTRAN programs, for instance, may
use the same Sqrt subroutine, but only one physical copy of the Sqrt routine would be
needed.
Although this sharing appears simple, there are subtle considerations. Code
segments typically contain references to themselves.
Example: A conditional jump normally has a transfer address.
The transfer address is a segment number and offset. The segment number of the
transfer address will be the segment number of the code segment. If you try to share
this segment, all sharing processes must define the shared code segment to have the
same segment number.
Example: If you want to share the Sqrt routine, and one process wants to make
segment 4 and another wants to make it segment 17, how should the Sqrt routine refer
to itself? Because there is only one physical copy of Sqrt, it must refer to itself in the
same way for both users – it must have a unique segment number.
As the number of users sharing the segment increases, so does the difficulty of
finding an acceptable segment number. Read-only data segments that contain no
physical pointers may be shown as different segment numbers, as may code segments
that refer to them not directly, but rather only indirectly.
Example: Conditional branches that specify the branch address as an offset from
the current program counter or relative to a register containing the current segment
number would allow code to avoid direct reference to the current segment number.

6.7 Paged Segmentation

In this section, you will learn about the paged segmentation. One solution to the
problems with pure segmentation is the same applied to variable partitions: paging. In
this case each segment is paged just like address spaces are in pure paging systems.
To resolve a memory reference, the MMU:
Masks off the segment ID and uses it to find the relevant segment table. The
segment table points to the page table for the segment.
The page ID is masked off and used to find the physical frame on which the page
resides.
If the frame is not in memory, it is faulted in.
The offset is added to the page and the relevant physical address fetched (subject
to permission constraints).
The multilevel page tables (and even multi-level segment tables) can make the
memory usage more efficient.
Example: The Multics system implemented such a paged segmentation system.
(Multics' strategy was "all the world's a segment." Files, libraries, programs were all
memory segments.)

6.7.1 Segmentation with Paging

You may already be aware that paging scheme allows internal fragmentation and
segmentation scheme allows external fragmentation. Combing both paging and
segmentation provides a better solution, where every segment differs in size and has
numerous of pages. It is important to note that every page in every segment has same
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size. Paging and segmentation have their respective advantages as well as
disadvantages. Segmentation with paging scheme eradicates external fragmentation.
As with paging, the last page of every segment usually will not be entirely full (internal Notes
fragmentation). The concept of internal and external segmentation is shown in figure
6.18.

Source: http://fourier.eng.hmc.edu/e85_old/lectures/memory/node9.html

Figure 6.18: Segmentation and Paged Segmentation

In fact, of the two most popular microprocessors now being used, the Motorola
68000 line is designed based on a flat address space, whereas the Intel 80x8 family is
based on segmentation. Both are merging memory models towards a mixture of paging
and segmentation. You must understand that it is possible to combine these two
schemes to improve on each. This combination is best illustrated by two different
architectures – the innovative but not widely used MULTICS system and the Intel 386.
The MULTICS system solved problems of external fragmentation and lengthy
search times by paging the segments.
The Intel 386 utilises segmentation with paging for memory management with a
two-level paging scheme

6.8 Summary
Memory consists of a large array of words or bytes, each with its own address. Dynamic
loading is the process in which one can attach a shared library to the address space of
the process during execution. Dynamic linking is accomplished by placing the name of a
sharable library in the executable image. The method assumes dividing a program into
self-contained object code blocks called overlays. A memory management unit (MMU)
is a computer hardware component responsible for handling accesses to memory
requested by the CPU. Swapping is necessary when there are more processes than
available memory. To move a program from fast-access memory to a slow-access
memory is known as "swap out", and the reverse operation is known as "swap in".
Different strategies used to allocate space to processes competing for memory are:
Best fit, Worst fit, and First fit. Paging avoids the considerable problem of fitting the
varying-sized memory chunks onto the backing store, from which most of the previous
memory-management schemes suffered. Segmentation is a memory-management
scheme that supports the user view of memory. Segmentation with paging scheme
removes external fragmentation

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9.9 Check Your Progress

Notes Multiple Choice Questions
1. Thrashing
(a) is a natural consequences of virtual memory system
(b) can always be avoided by swapping
(c) always occurs on large computers
(d) can be caused by poor paging algorithms
2. Memory management is
(a) not used in modern operating system
(b) replaced with virtual memory on current system
(c) not used on multiprogramming systems
(d) critical for even the simplest operating system
3. Which is not true about the memory management?
(a) virtual memory is used in multi-user system
(b) segmentation suffers from external fragmentation
(c) paging suffers from internal fragmentation
(d) segmented memory can be paged
4. In the multiprogramming system, a set of processes is deadlock if each process in
the set is waiting for an event to occur that can be initialized only by another
process in the set. Which of the following is not one of the four conditions that are
necessary for deadlock to occur?
(a) nonpreemption
(b) process suspension
(c) partial assigment of resources
(d) circular wait
5. Block or Buffer caches are used
(a) to improve disk performance
(b) to handle interrupts
(c) to increase the capacity of main memory
(d) to speed up main memory read operation
6. CPU fetches the instruction from memory according to the value of
(a) program counter
(b) status register
(c) instruction register
(d) program status word
7. A memory buffer used to accommodate a speed differential is called
(a) stack pointer
(b) cache
(c) accumulator
(d) disk buffer
8. Which one of the following is the address generated by CPU?
(a) physical address
(b) absolute address

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(c) logical address
(d) none of the mentioned
Notes
9. Run time mapping from virtual to physical address is done by
(a) memory management unit
(b) CPU
(c) PCI
(d) none of the mentioned
10. Memory management technique in which system stores and retrieves data from
secondary storage for use in main memory is called
(a) fragmentation
(b) paging
(c) mapping
(d) none of the mentioned

6.10 Questions and Exercises

1. What is memory management and what are its requirements?
2. Discuss the advantages and disadvantages of segmentation and paging.
3. Describe the process of binding of instructions and data to memory.
4. Explain the concept of memory swapping.
5. Describe the strategies used for Contiguous Memory Allocation.
6. Why are segmentation and paging sometimes combined into one scheme? Explain.
7. Describe a mechanism by which one segment could belong to the address space of
two different processes.
8. Given memory partitions of lOOK, 5OOK, 200K, 300K, and 600K (in order), how
would each of the first-fit, best-fit, and worst-fit algorithms place processes of 212K,
417K, 112K, and 426K (in order)? Which algorithm makes the most efficient use of
memory?

6.11 Key Terms

z Memory: It is the electronic holding place for instructions and data that the
computers microprocessor can reach quickly.
z Memory Manager: The memory manager is a part of operating system which is
responsible for allocating primary memory to processes and for assisting the
programmer in loading and storing the contents of the primary memory.
z Overlaying: It means replacement of a block of stored instructions or data with
another.
z Logical Address: It is an address generated by the CPU is commonly referred to
as a logical address.
z Physical Address: It is an address seen by the memory unit-that is, the one loaded
into the memory-address register of the memory-is commonly referred to as a
physical address.
z Memory Management Unit (MMU): It is a computer hardware component
responsible for handling accesses to memory requested by the CPU.
z Swapping: It is the act of moving processes between memory and a backing store.
z Paging: It is a technique for increasing the memory space available by moving
infrequently-used parts of a programs working memory from RAM to a secondary
storage medium, usually hard disk.
z Page: In paging system the unit of transfer is called a page.

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z Segmentation: It is a memory-management scheme that supports the user view of

memory.
Notes
Check Your Progress: Answers
1. (d)can be caused by poor paging algorithms
2. (b)replaced with virtual memory on current system
3. (a)virtual memory is used in multi-user system
4. (b) process suspension
5. (a) to improve disk performance
6. (a) program counter
7. (b) cache
8. (c) logical address
9. (a) memory management unit
10. (b) paging

6.12 Further Readings

z Sathe, Operating Systems, Macmillan, 2009
z Dr. R.C. Joshi, Operating Systems, Dreamtech Press, 2008
z Er. Vivek Sharma, Er. Manish Varshney, Shantanu Sharma , Design and
Implementation of Operating System, Laxmi Publications, 2010
z Sibsankar Haldar, Operating Systems, Pearson Education India, 2010
z Dp Sharma, Foundation of Operating Systems, Excel Books India, 2008

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Unit 7: Virtual Memory

Notes
Structure
7.1 Introduction
7.2 Virtual Memory
7.3 Demand Paging
7.3.1 Performance of Demand Paging
7.4 Process creation
7.5 Page replacement
7.5.1 Page Replacement Algorithms
7.6 Allocation of frames
7.7 Thrashing
7.8 Demand Segmentation
7.9 Questions and Exercises
7.10 Key Terms
7.11 Further Readings

Objectives
After studying this unit, you should be able to:
z Explain the concept of virtual memory
z Describe the process of demand paging
z Identify the methods for process creation
z Recognise the need for page replacement
z Describe page replacement algorithms
z Explain the standard methods of frame allocation
z Describe the concept of thrashing

7.1 Introduction
In the previous unit, you have studied memory management concepts such as
swapping and contiguous memory allocation. You have also understood the concept of
paging and segmentation.
In this unit, you will study the concept of virtual memory. Today application is getting
bigger and bigger. Therefore, it requires a bigger system memory in order for the
system to hold the application data, instruction, and thread and to load it. The system
needs to copy the application data from the HDD into the system memory in order for it
to process and execute the data. Once the memory gets filled up with data, the system
will stop loading the program. In this case, users need to add more memory onto their
system to support that intense application. However, adding more system memory
costs the money and the normal user only needs to run the intense application that
requires the memory only for one or two days. Therefore, virtual memory is introduced
to solve that type of problem. This lesson will cover the concept of demand paging,
process creation, page replacement, and allocation of frames. You will also learn about
thrashing in this lesson.

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Virtual memory is utilised to improve the RAM capacity and to speed up the
operations of the computer. When RAM is low, data is transferred from virtual memory
Notes to a space named Paging File. The process of transmitting data to paging file frees up
the RAM in order to perform its task.

7.2 Virtual Memory

In this section, you will learn about the background virtual memory. Various memory-
management has the goal – to keep as many processes in memory as possible,
simultaneously to allow multi-programming. However, these strategies tend to require
that the entire process to be in memory before the process can execute. Obviously,
because of the limited size of physical memory available in a system, these schemes
are not very optimal. The largest process (program) that can be executed at one time is
limited by the size of physical memory.
Example: If 16MB RAM (physical memory) is available in the system. Assuming
that the operating system itself occupies 4MB, then no process larger than 12MB can
be executed on this system. The total number of processes that can be executed
simultaneously is also limited to total space of 12MB, in this case.
It is important to note this limitation may be overcome by another memory
management technique – Virtual Memory System.
Virtual memory is a technique that permits the execution of processes that may not
be completely resident in the memory. The main advantage of this scheme is that
programs can be larger than physical memory. Further, it views main memory into an
extremely large, uniform array of storage, separating logical memory as viewed by the
user from physical memory. It, as a matter of fact augments the main memory with
secondary storage devices (like hard disks). This technique frees programmers from
concern over memory storage limitations. Virtual memory is not easy to implement,
however, and may substantially decrease performance if it is used carelessly. In this
lesson, we discuss virtual memory in the form of demand paging, and examine its
complexity and cost.
The memory-management algorithms discussed so far are necessary because of
one basic requirement: the instructions being executed must be in physical memory.
The first approach to meeting this requirement is to place the entire logical address
space in physical memory. Overlays and dynamic loading can help ease this restriction,
but they generally require special precautions and extra effort by the programmer. This
seems both necessary and reasonable, but it is also unfortunate, since it limits the size
of a program to the size of physical memory.
In fact, an examination of real programs shows us that, in many cases, the entire
program is not needed for execution.
For instance, Programs often have code to handle unusual error conditions. Since
these errors rarely, if ever, occur in practice, this code is almost never executed.
The arrays, lists and tables are often allocated more memory than they actually
need. An array may be declared 100 by 100 elements, even though it is seldom larger
than 10 by 10 elements at execution time. An assembler symbol table may have room
for 4000 symbols, although the average program has less than 300 symbols.
It is essential to note that not all sub-routines are executed always. Certain options
and features of a program may be used rarely. Even in those cases where the entire
program may be needed at the same time (such is the case with overlays, for example).
The ability to execute a program that is only partially in memory would have many
benefits:
z A program would no longer be constrained by the amount of physical memory that
is available. Users would be able to write programs for an extremely large virtual

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address space, simplifying the programming task. The users do not have to worry
about the amount of memory available for the programs.
z Because each user program could take less physical memory, more programs
Notes
could be run at the same time, with a corresponding increase in CPU utilisation and
consequently, throughput, but with no increase in response time or turnaround time.
Less I/O would be needed to load or swap each user program into memory, so
each user program would run faster.
Thus, you may be able to understand that running a program that is not entirely in
memory would benefit both the system, and the user. Virtual memory is the separation
of user logical memory from physical memory. This separation allows an extremely
large virtual memory to be provided for programmers when only a smaller physical
memory is available as you can see in Figure 7.1. Virtual memory makes the task of
programming much easier, because the programmer no longer needs to worry about
the amount of physical memory available, or about what code can be placed in
overlays, but can concentrate instead on the problem to be programmed. Therefore you
may say that on systems which support virtual memory, overlays have virtually
disappeared.
Virtual memory is commonly implemented by Demand Paging. It can also be
implemented in a segmentation system. Several systems provide a paged
segmentation scheme, where segments are broken into pages. Thus, the user view is
segmentation, but the operating system can implement this view with demand paging.
Demand segmentation can also be used to provide virtual memory. Burroughs'
computer systems have used demand segmentation. The IBM OS/2 operating system
also uses demand segmentation. However, you must note that the segment-
replacement algorithms are more code and complex than the page-replacement
algorithms because the segments have variable sizes.

Page 0

Page 1

Page 2

memory
map

Page n physical
memory
virtual
memory

Figure 7.1: Virtual Memory Larger than Physical Memory

Now, you will understand the concept of demand paging.

7.3 Demand Paging

In this section, you will learn about the demand paging. A demand-paging system is
similar to a paging system with a little difference that it uses — swapping. Processes
reside on secondary memory (which is usually a disk). When you want to execute a
process, you may swap it into memory. Rather than swapping the entire process into
memory, however, we use a lazy swapper, which swaps a page into memory only when
that page is needed. Since you are now viewing a process as a sequence of pages,
rather than one large contiguous address space, the use of the term swap will not
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technically correct. A swapper manipulates entire processes, whereas a pager is

concerned with the individual pages of a process.
Notes
You shall use the term pager, rather than swapper, in connection with demand
paging.
When a process is to be swapped in, the pager guesses which pages will be used
before the process in swapped out again. Instead of swapping in a whole process, the
pager brings only those necessary pages into memory. Thus, it avoids reading into
memory pages that will not be used anyway, decreasing the swap time and the amount
of physical memory needed.
With this scheme, you need some form of hardware support to distinguish between
those pages that are in memory and those pages that are on the disk. The valid-invalid
bit scheme described earlier can be used for this purpose. This time, however, when
this bit is set to “valid”, this value indicates that the associated page is both legal and in
memory. If the bit is set to “invalid,” this value indicates that the page either is not valid
(that is, not in the logical address space of the process), or is valid but is currently on
the disk not in the memory. The page-table entry for a page that is not currently in
memory is simply marked invalid, or contains the address of the page on disk. This
situation is depicted in Figure 7.2.

swap out 0 1 2 3
program
A 4 5 6 7

8 9 10 11

12 13 14 15

program swap in 16 17 18 19
B
20 21 22 23

main
memory

Figure 7.2: Transfer of a Paged Memory to Contiguous Disk Space

You must notice that marking a page invalid will have no effect if the process never
attempts to access that page. Hence, if you guess right and only those pages that are
actually needed are brought into the memory, the process will run exactly as though you
had brought in all pages. While the process executes and accesses pages that are
memory resident, execution proceeds normally.
But what happens if the process tries to use a page that was not brought into
memory? Access to a page marked invalid causes a page-fault trap. The paging
hardware, in translating the address through the page table, will notice that the invalid
bit is set, causing a trap to the operating system. This trap is the result of the operating
system's failure to bring the desired page into memory (in an attempt to minimise disk-
transfer overhead and memory requirements), rather than an invalid address error as a
result of an attempt to use an illegal memory address (such as an incorrect array
subscript). You must therefore, correct this oversight. Figure 7.3 below depicts the page
table when some pages are not in main memory.

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Virtual Memory 135
0
1
Notes
A 2
0
B valid-invalid 3
1 frame bit

C 0
4 A
2 4 V

D 1 i 5
3 2 6 v
6 C A B
4 E 3 i

F 4 i
7
5 C D E
5 9 v 8
6 G
6 i
9 F F
H i
7 7
logical
page table 10
memory
11
12
13
14
15
physical
memory

Figure 7.3: Page Table when some Pages are not in Main Memory
The procedure for handling this page fault is simple as you can see in Figure 7.4.
1. Check an internal table (usually kept with the process control block) for the process
under consideration, to determine whether the reference was a valid or invalid
memory access.
2. If the reference was invalid, we terminate the process. If it was valid, but we have
not yet brought in that page into memory, we now page in the latter.
3. We find a free frame,
Example: By taking one from the free-frame list.
1. We schedule a disk operation to read the desired page into the newly allocated
frame.
2. When the disk read is complete, we modify the internal table kept with the process
and the page table to indicate that the page is now in memory.
3. We restart the instruction that was interrupted by the illegal address trap. The
process can now access the page as though it had always been in memory.
Operating System
3
Page is in Backing Store

1
Reference
2
Trap

Load M i

Free Frame
Page Table

5 4
Reset page table Bring in missing page

6 Physical Memory
Restart Instruction

Figure 7.4: Steps in Handling a Page Fault

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136 Operating Systems

It is important to realise that, because we save the state (registers, condition code,
instruction counter) of the interrupted process when the page fault occurs, you can
Notes restart the process in exactly the same place and state, except that the desired page is
now in memory and is accessible. In this way, you are able to execute a process, even
though portions of it are not (yet) in memory. When the process tries to access locations
that are not in memory, the hardware traps the operating system which is known as
"page fault". The operating system reads the desired page into memory and restarts the
process as though the page had always been in memory.
In the extreme case, you could start executing a process with no pages in memory.
When the operating system sets the instruction pointer to the first instruction of the
process would immediately fault for the page. After this page was brought into memory
due to recourse taken in response to this page fault, the process would continue to
execute, faulting as necessary until every page that it needed was actually in memory.
At that point, it could execute with no more faults. This scheme is pure demand paging:
never bring a page into memory until it is required.
Theoretically, you must understand that some programs may access several new
pages of memory with each instruction execution (one page for the instruction and
many for data), possibly causing multiple page faults per instruction. This situation
would result in unacceptable system performance because of the overheads involved.
Fortunately, analyses of running processes show that this behaviour is exceedingly
unlikely. Programs tend to have locality of reference, which results in reasonable
performance from demand paging.
The hardware to support demand paging is the same as the hardware for paging
and swapping:
z Page Table: This table has the ability to mark an entry invalid through a valid-
invalid bit or special value of protection bits.
z Secondary Memory: This memory holds those pages that are not present in main
memory. The secondary memory is usually a high-speed disk. It is known as the
swap device, and the section of disk used for this purpose is known as swap space
or backing store.
In addition to this hardware support, considerable software is needed, as we shall
see. Some additional architectural constraints must be imposed. A crucial issue is the
need to be able to restart any instruction after a page fault. In most cases, this
requirement is easy to meet. A page fault could occur at any memory reference. If the
page fault occurs on the instruction fetch, we can restart by fetching the instruction
again.
If a page fault occurs while we are fetching an operand, not an instruction, then we
must re-fetch the instruction, decode it again, and then fetch the operand.
As a worst-case scenario; consider a three-address instruction such as ADD the
content of A to B placing the result in C. The steps to execute this instruction would be
z Fetch and Decode the Instruction (ADD).
z Fetch A.
z Fetch B.
z Add A and B.
z Store the sum in C.
If we faulted when we tried to store in C (because C is in a page not currently in
memory), we would have to get the desired page in it, correct the page table, and
restart the instruction. The restart would require fetching the instruction again, decoding
it again, fetching the two operands again, and then adding again. However, there is
really not much repeated work (less than one complete instruction), and the repetition is
necessary only when a page fault occurs.

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The major difficulty occurs when one instruction may modify several different
locations.
Notes
Example: Consider the IBM System 360/370 MVC (move character) instruction,
which can move up to 256 bytes from one location to another (possible overlapping)
location. If either block (source or destination) straddles a page boundary, a page fault
might occur after the move is partially done. In addition, if the source and destination
blocks overlap, the source block may have been modified, in which case we cannot
simply restart the instruction.
This problem can be solved in two different ways. In one solution, the micro-code
computes attempts to access both ends of both blocks. If a page fault is going to occur,
it will happen at this step, before anything is modified. The move can then take place,
as we know that no page fault can occur, since all the relevant pages are in memory.
The other solution uses temporary registers to hold the values of overwritten locations.
If there is a page fault, all the old values are written back into memory before the trap
occurs. This action restores memory to its state before the instruction was started, so
that the instruction can be repeated.
A similar architectural problem occurs in machines that use special addressing
modes, including auto-decrement and auto-increment modes.
Example: PDP-11 is an example of such machine.
These addressing modes use a register as indicated. Auto-decrement automatically
decrements the register before using its contents as the operand address; auto-
increment automatically increments the register after using its contents as the operand
address. Thus, the instruction:
MOV (R2) +, – (R3)
copies the contents of the location pointed to by register 2 into the location pointed
to by register 3. Register 2 is incremented (by 2 for a word, since the PDP-11 is a byte-
addressable computer) after it is used as a pointer; register 3 is decremented (by 2)
before it is used as pointer. Now consider what will happen if we get a fault when trying
to store into the location pointed to by register 3. To restart the instruction, it is must to
reset the two registers to the values they had before we started the execution of the
instruction.
You must take into consideration that one solution is to create a new special status
register to record the register number and amount modified for any register allows the
operating system to "undo" the effects of a partially executed instruction that causes a
page fault.
These are by no means the only architectural problems resulting from adding
paging to an existing architecture to allow demand paging, but they illustrate some of
the difficulties. Paging is added between the CPU and the memory in a computer
system. It should be entirely transparent to the user process. Thus, people often
assume that paging could be added to any system. Although this assumption is true for
a non-demand paging environment, where a page fault represents a fatal error, it is not
true in the case, where a page fault means only that an additional page must be brought
into memory and the process restarted.

7.3.1 Performance of Demand Paging

Demand paging can have a significant effect on the performance of a computer system.
To see why, let us compute the effective access time for a demand-paged memory. The
memory access time, ma, for most computer systems now ranges from 10 to 200
nanoseconds. As long as you have no page faults, the effective access time is equal to
the memory access time. If however, a page fault occurs, you must first read the
relevant page from disk, and then access the desired word.

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Let p be the probability of a page fault (0 <= p <= 1)). We would expect p to be
close to zero; that is, there will be only a few page faults. The effective access time is
Notes then
effective-access time = (1 – p) * ma + p * page-fault-time.
To compute the effective access time, you must know how much time is needed to
service a page fault.
A page fault causes the following sequence to occur:
1. Cause trap to the operating system.
2. Save the user registers and process state on the memory stack of the process.
3. Determine that the interrupt was a page fault.
4. Check that the page reference was legal and determine location of the page on the
disk.
5. Issue a read from the disk to a free frame:
(a) Wait in a queue for device until the read request is serviced.
(b) Wait for the device seek and/or latency time.
(c) Begin the transfer of the page to a free frame.
6. While waiting, allocate the CPU to some other user (CPU scheduling; optional).
7. Interrupt from the disk (I/O completed).
8. Save the registers and process state for the other user (if step 6 executed).
9. Determine that the interrupt was from the disk.
10. Correct the page table and other tables to show that the desired page is now in
memory.
11. Wait for the CPU to be allocated to this process again.
12. Restore the user registers, process state, and new page table, and then resume the
interrupted instruction.
Not all of these steps may be necessary in every case.
Example: We are assuming that, in step 6, the CPU is allocated to another process
while the I/O occurs. This arrangement allows multi-programming to maintain CPU
utilisation, but requires additional time to resume the page-fault service routine when
the I/O transfer is complete.
In any case, we are faced with three major components of the page-fault service
time:
z Service the page-fault interrupt
z Read in the page
z Restart the process
The first and third tasks may be reduced, with careful coding, to several hundred
instructions. These tasks may take from 1 to 100 microseconds each. The page-switch
time, on the other hand, will probably be close to 24 milliseconds. A typical hard disk
has an average latency of 8 milliseconds, a seek-time of 15 milliseconds, and a transfer
time of 1 millisecond. Thus, the total paging time would be close to 25 milliseconds,
including hardware and software time. Remember also that you are looking at only the
device service time. If a queue of processes is waiting for the device (other processes
that have caused page faults), you have to add device queuing-time as you wait for the
paging device to be free to service our request, increasing the time to swap even more
than the one calculated.

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Virtual Memory 139
Example: If you take an average page-fault service time of 25 milliseconds and a
memory access time of 100 nanoseconds, then the effective access time in
nanoseconds is: Notes
Effective-access-time = (1 – p) * (100) + p * 25 milliseconds
= (1 – p) * 100 + p * 25,000,000
= 100 – 100p + 25000000p
= 100 + 24999900p
We see then that the effective access time is directly proportional to the page-fault
rate (or probability). If one access out of 1000 causes a page fault, the effective access
time is 25 microseconds. The computer would be slowed down by a factor of 250
because of demand paging. If you want less than 10 per cent degradation, then you
need:
110 > 100 + 25,000,000 * p
10 > 25,000,000 * p
p < 0.0000004
That is, to keep the slowdown due to paging to a reasonable level, you can allow
only less than 1 memory access out of 2,500,000 to page fault. That is, to keep the
slowdown due to paging to a reasonable level, you can allow only less than 1 memory
access out of 2,500,000 to page fault.
As is obvious, it is important to keep the page-fault rate low in a demand-paging
system. Otherwise, the effective access time increases, slowing process execution
dramatically.
One additional aspect of demand paging is the handling and overall use of swap
space. Disk I/O to swap space is generally faster than that to the file system. It is faster
because swap space is allocated in much larger blocks, and file lookups and indirect
allocation methods are not used. It is, therefore, possible for the system to gain better
paging throughput, by copying an entire file image into the swap space at process start
up, and then to perform demand paging from the swap space. Systems with limited
swap space can employ a different scheme when binary files are used. Demand pages
for such files are brought directly from the file system. However, when page
replacement is called and read in from the file system again if needed. Yet another
option is initially to demand pages from the file system, but to write the pages to swap
space as they are replaced. This approach will ensure that only needed pages are ever
read from the file system, but all subsequent paging is done from swap space. This
method appears to be a good compromise.
Example: This scheme is used in BSD UNIX.

7.4 Process creation

This section will help you understand about process creation. A process can begin by
demand paging. However, using VM techniques also allows for other efficient methods
for creating processes. First-generation Unix systems implemented process creation in
a rather clumsy way: when a fork ( ) system call was issued, the kernel duplicated the
whole parent address space in the literal sense of the word and assigned the copy to
the child process. This activity was quite time consuming since it requires:
z Allocating page frames for the Page Tables of the child process
z Allocating page frames for the pages of the child process
z Initialising the Page Tables of the child process
z Copying the pages of the parent process into the corresponding pages of the child
process.

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It will be essential to note that this way of creating an address space involved many
memory accesses, used up many CPU cycles, and completely spoiled the cache
Notes contents. Last but not least, it was often pointless because many child processes start
their execution by loading a new program, thus discarding entirely the inherited address
space.
Modern Unix kernels, including Linux, follow a more efficient approach called Copy
On Write (COW). The idea is quite simple: instead of duplicating page frames, they are
shared between the parent and the child process. However, as long as they are shared,
they cannot be modified. Whenever the parent or the child process attempts to write
into a shared page frame, an exception occurs. At this point, the kernel duplicates the
page into a new page frame that it marks as writable. The original page frame remains
write-protected: when the other process tries to write into it, the kernel checks whether
the writing process is the only owner of the page frame; in such a case, it makes the
page frame writable for the process.
Example: Copy-on-write method is shown in Figure 7.5 and Figure 7.6, which
display the physical memory contents before and after process 1 modifies page C.
Figure 7.5 shows the contents before process 1 modifies page C:

Source: http://www.cs.odu.edu/~cs471w/spring11/lectures/virtualmemory.htm

Figure 7.5: Before Process 1 Modifies Page C

Figure 7.6 shows the contents after process 1 modifies page C:

Source: http://www.cs.odu.edu/~cs471w/spring11/lectures/virtualmemory.htm

Figure 7.6: After Process 1 Modifies Page C

Copy-on-write is needed to be marked only on those pages that can be modified.
Pages that cannot be modified can be shared by the parent as well as child.
Example: Copy-on-write is a common method utilised by various operating
systems, including Windows XP, Linux, and Solaris.

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Pages utilised to satisfy copy-on-write duplications are usually allotted by means
of zero-fill-on-demand. This means that their previous contents are zeroed out before
the copy proceeds. Notes
7.5 Page Replacement
In this section, you will understand about the page replacement. The page-fault rate is
not a serious problem because each page is faulted for at most once, when it is first
referenced. This representation is not strictly accurate. Consider that, if a process of 10
pages actually uses only one-half of them, and then demand paging saves the I/O
necessary to load the five pages that are never used. You could also increase the
degree of multi-programming by running twice as many processes. Thus, if you had 40
frames, you could run eight processes, rather than the four that could run if each
required 10 frames (five of which were never used).
If you increase the degree of multi-programming, it means that you are over-
allocating memory. If you run six processes, each of which is 10 pages in size, but
actually uses only five pages, you have higher CPU utilisation and throughput, with 10
frames to spare. It is possible, however, that each of these processes, for a particular
data set, may suddenly try to use all 10 of its pages, resulting in a need for 60 frames,
when only 40 are available. Although this situation may be unlikely, it becomes much
more likely as you increase the multiprogramming level, so that the average memory
usage is close to the available physical memory.
Over-allocating will show up in the following way. While a user process is executing,
a page fault occurs. The hardware traps to the operating system, which checks its
internal tables to see that this is a page fault and not an illegal memory access. The
operating system determines where the desired page is residing on the disk, but then
finds there are no free frames on the free-frame list; all memory is in use (Figure 7.7).
The operating system has several options at this point. It could terminate the user
process. However, demand paging is something that the operating system is doing to
improve the computer system's utilisation and throughput. Users should not be aware
that their processes are running on a paged system. Paging should be logically
transparent to the user. So, this option is not the best choice.

A Page may
be replaced

Pages to be B
swapped into
the memory
C A
Page may
be replaced
D
D
E
Physical Memory
F with page
Secondary Memory Media location [RAM]
[Hard Disk] G

Page Diagram

Figure 7.7: Need for Page Replacement

You could swap out a process, freeing all its frames, and reducing the level of multi-
programming. This option is a good idea at times. Let us discuss one intriguing
possibility: page replacement.
Page replacement takes the following approach. If no frame is free, we find one that
is not currently being used and free it. You can free a frame by writing its contents to
swap space, and changing the page table (and all other tables) to indicate that the page

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is no longer in memory. The freed frame can now be used to hold the page for which
the process faulted. The page-fault service routine is now modified to include
Notes replacement:
z Find the location of the desired page on the disk.
z Find a free frame:
z If there is a free frame, use it.
z Otherwise, use a page-replacement algorithm to select a victim frame.
z Write the victim page to the disk; change the page and frame tables accordingly.
z Read the desired page into the (newly) free frame; change the page and frame
tables.
z Restart the user process.
You must notice that, if no frames are free, two page transfers (one out and one in)
are required. This situation effectively doubles the page-fault service time and will
increase the effective access time accordingly. This overhead can be reduced by the
use of modify (dirty) bit. Each page or frame may have a modify bit associated with it in
the hardware. The modify bit for a page is set by the hardware whenever any word or
byte in the page is written into, indicating that the page has been modified.
When you select a page for replacement, you examine it’s modify bit. If the bit is
set, you know that the page has been modified since it was read in from the disk. In this
case, you must write that page to the disk. If the modify bit is not set, however, the page
has not been modified since it was read into memory. Therefore, if the copy of the page
on the disk has not been overwritten (by some other page, for example), you can avoid
writing the memory page to the disk; it is already there. This technique also applies to
read-only pages (for example, pages of binary code). Such pages cannot be modified;
thus, they may be discarded when desired. This scheme can reduce significantly the
time to service a page fault, since it reduces I/O time by one-half if the page is not
modified.

Frame Valid-invalid bit

Swap out
victim
2 change page
to invalid 1
4 victim
reset page
page table table for 3
new page
Swap out
desired
page in

physical
memory

Figure 7.8: Page Replacement

Page replacement as depicted in Figure 7.8 is basic to demand paging. It
completes the separation between logical memory and physical memory. With this
mechanism, a very large virtual memory can be provided to programmers on a smaller
physical memory. With non-demand paging, user addresses were mapped into physical
addresses, allowing the two sets of addresses to be quite different. All of the pages of a
process still must be in physical memory, however. With demand paging, the size of the
logical address space is no longer constrained by physical memory. If you have a user

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process 20 pages long, you can execute it in 10 frames simply by using demand
paging, and using a replacement algorithm to find a free frame whenever necessary. If
a page that has been modified is to be replaced, its contents are copied to the disk. A Notes
later reference to the pages will cause a page fault. At the time, the page will be brought
back into memory, perhaps replacing some other page in the process.
You must solve two major problems to implement demand paging: You must
develop a page-replacement algorithm and a frame-allocation algorithm. If you have
multiple processes in memory, you must decide how many frames to allocate to each
process. Further, when page replacement is required, you must select the frames that
are to be replaced. Designing appropriate algorithms to solve these problems is an
important task, because disk I/O is so expensive in terms of time. Even slight
improvements in demand-paging methods yield large gains in overall system
performance.

7.5.1 Page Replacement Algorithms

It is essential to understand that many different page replacement algorithms exist.
Probably every operating system has its own unique replacement scheme. How do you
select a particular replacement algorithm? In general, you want the one with the lowest
page-fault rate. You may evaluate an algorithm by running it on a particular string of
memory references and computing the number of page faults. The string of memory
references is called a reference string. You can generate reference strings artificially (by
a random-number generator, for example) or by tracing a given system and recording
the address of each memory reference. The latter choice produces a large number of
data (on the order of 1 million addresses per second). To reduce the number of data,
we note two things.
First, for a given page size (and the page size is generally fixed by the hardware or
system), you need to consider only the page number, not the entire address. Second, if
you have a reference to page p, then any immediately following references to page p
will never cause a page fault. Page p will be in memory after the first reference; the
immediately following references will not fault.
Example: If you trace a particular process, you might record the following address
sequence:
0100, 0432, 0101, 0612, 0102, 0103, 0104, 0101, 0611, 0102, 0103,
0104, 0101, 0610, 0102, 0103, 0104, 0101, 0609, 0102, 0105,
which at 100 bytes per page, is reduced to the following reference string.
1, 4, 1, 6, 1, 6, 1, 6, 1, 6, 1.
To determine the number of page faults for a particular reference string and page-
replacement algorithm, you also need to know the number of page frames available.
Obviously, as the number of frames available increases, the number of page faults will
decrease.
Example: For the reference string considered previously, if you had three or more
frames, you would have only three faults, one frame available, you would have a
replacement with every reference, resulting in 11 faults.
In general, you expect a curve such as that in Figure 7.9. As the number of frames
increases, the number of page faults drops to some minimal level. Of course, adding
physical memory increases the number of frames.

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number of page faults

16
Notes 14
12
10
8
6
4
2
1 2 3 4 5 6
number of frames

Figure 7.9: Graph of Page Faults versus the Number of Frames

To illustrate the page-replacement algorithms, we shall use the reference string:
7, 0, 1, 2, 0, 3, 0, 4, 2, 3, 0, 3, 2, 1, 2, 0, 1, 7, 0, 1
for a memory with three frames.

FIFO Algorithm
It will be important for you to understand that the simplest page-replacement algorithm
is a FIFO algorithm. A FIFO replacement algorithm associates with each page the time
when that page was brought into memory. When a page must be replaced, the oldest
page is selected. You can create a FIFO queue to record the time when a page is
brought into the memory. You can create a FIFO queue to hold all pages in memory.
You replace the page at the head of the queue. When a page is brought into memory,
we insert it at the tail of the queue.
Example: As an example of reference string, three frames are initially empty. The
first three references (7, 0, 1) cause page faults, and are brought into these empty
frames. The next reference (2) replaces page 7, because page 7 was brought in first.
Since 0 is the next reference and 0 is already in memory, we have no fault for this
reference. The first reference to 3 results in page 0 being replaced, since it was the
oldest of the three pages in memory (0, 1, and 2) to be brought in. This replacement
means that the next reference, to 0, will fault. Page 1 is then replaced by page 0. This
process continues as shown in Figure 7.10. Every time a fault occurs, we show which
pages are in our three frames. There are 15 faults altogether.
Reference String
7 0 1 2 0 3 0 4 2 3 0 3 2 1 2 0 1 7 0 1

7 7 7 2 2 2 4 4 4 0 0 0 7 7 7
0 0 0 3 3 3 2 2 2 1 1 1 0 0
1 1 1 0 0 0 3 3 3 2 2 2 1

Page Frames

Figure 7.10: FIFO Page-replacement Algorithm

The FIFO page-replacement algorithm is easy to understand and program.
However, its performance is not always good. The page replaced may be an
initialisation module that was used a long time ago and is no longer needed. On the
other hand, it could contain a heavily used variable that was initialised early and is in
constant use.
Even if you select for replacement a page that is in active use, everything still works
correctly.
After you page out an active page to bring in a new one, a fault occurs almost
immediately to retrieve the active page. Some other page will need to be replaced to

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bring the active page back into memory. Thus, a bad replacement choice increases the
page-fault rate and slows process execution, but does not cause incorrect execution.
Notes
Example: To illustrate the problems that are possible with a FIFO page-
replacement algorithm, let us consider the reference string
1, 2, 3, 4, 1, 5, 1, 2, 3, 4, 5
Figure 7.11 shows the curve of page faults versus the number of available frames.
This is to be noticed that the number of faults for four frames (=10) is greater than the
number of faults for three frames (=9). This result is most unexpected and is known as
Belady's anomaly. Belady's anomaly reflects the fact that, for some page-replacement
algorithms, the page fault rate may increase as the number of allocated frames
increases. We would expect that giving more memory to a process would improve its
performance. In some early research, investigators noticed that this assumption was not
always true. Belady's anomaly was discovered as a result.

16
14

12
10
8
6
4
2

1 2 3 4 5 6 7
number of frames

Figure 7.11: Page-fault Curve for FIFO Replacement on a Reference String

Optimal Algorithm
It is important to note that one result of the discovery of Belady's anomaly was the
search for an optimal page-replacement algorithm. An optimal page-replacement
algorithm has the lowest page-fault rate of all algorithms.
An optimal algorithm will never suffer from Belady's anomaly.
An optimal page-replacement algorithm exists, and has been called OPT or MIN.
Stated simply, it is:
z Replace the page that will not be used for the longest period of time.
z Use of this page-replacement algorithm guarantees the lowest possible page-fault
rate for a fixed number of frames.
Example: On our sample reference string, the optimal page-replacement algorithm
would yield nine page faults, as shown in Figure 7.12. The reference to page 2 replaces
page 7, because 7 will not be used until reference 18, whereas page 0 will be used at 5,
and page 1 at 14. The reference to page 3 replaces page 1, as page 1 will be the last of
the three pages in memory to be referenced again. With only nine page faults, optimal
replacement is much better than a FIFO algorithm, which had 15 faults.

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Notes

Figure 7.12: Optimal Algorithm Illustration

Unfortunately, the optimal page-replacement algorithm is extremely difficult to
implement because it requires prior knowledge of the reference string and therefore, is
often used for comparison purpose alone.

LRU Algorithm
As stated earlier, you must be aware that it is very difficult to implement optimal
algorithm. Yet an approximation to this algorithm may be employed, and that is LRU.
The algorithm associates to each page brought into the memory, the time at which the
page was last used. When a page is needed to be replaced, the page with the longest
period of time when it was not used is selected for replacement.
Example: You can see this in Figure 7.13.

Figure 7.13: Replace the Page that has not been used for the Longest Period of
Time
However, even this algorithm needs a lot of hardware support for its
implementation. This algorithm looks forward in time than the backward scheme of the
optimal algorithm. This algorithm requires extensive hardware support in terms of
counters and stack.
Example: The Figure 7.14 shows the replacement scheme.

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Notes

Figure 7.14: Maintain a “stack” of Recently Used Pages

In the next section, you will understand frame allocation algorithm.

7.6 Allocation of frames

Another important issue to discuss in virtual memory system is allocation of frames.
This section emphasises on this topic. How can the free memory be allocated among
the various processes? Also, you will learn some standard methods of frame allocation
from the free memory.

7.6.1 Equal Allocation

The available frames are equally divided (rounded to nearest next integer) among the
processes. The scheme is simple but not all processes need equal amount of memory,
and hence some frames are wasted if allocated to a process that does not need as
many.
Example: If there are 100 frames and 5 processes, give each process 20 frames.

7.6.2 Proportional Allocation

It is important to understand that the available frames are divided among the processes
proportional to their sizes (rounded to the nearest nest integer). This scheme ensures
that the processes do not waste the frame allocated to them.
Example: If there are 2 processes, 10 and 30 pages long and there are 200 frames
available. Then the allocation will be as follows:
No. of frames for 1st process = 200 * (10/(10 + 30))
= 50
No. of frames for 2nd process = 200 * (30/(10 + 30))
= 150
This algorithm may be modified to include process priority or combination of size
and priority.

7.7 Thrashing
Now let us discuss about the concept of thrashing. A process that is spending more
time paging than executing is known as thrashing. Thrashing happens when a hard
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drive has to move its heads over the swap area many times due to the high number of
page faults. This happens when memory accesses are causing page faults as the
Notes memory is not located in main memory.
The thrashing happens as memory pages are swapped out to disk only to be paged
in again soon afterwards. Instead of memory access happening mainly in main memory,
access is mainly to disk causing the processes to become slow as disk access is
required for many memory pages and thus thrashing.
It is important to note that the operating system monitors CPU utilisation. Early
schemes of process scheduling would control the multiprogramming level based on the
utilisation of CPU, providing more processes when CPU utilisation was low.
The difficulty is that when memory filled up and processes began spending a huge
amount of time waiting for their pages to page in, then the utilisation of CPU would
lower, getting the schedule to add in even more processes and worsening the problem.
Ultimately the system would basically get stuck.
This you can see in the Figure 7.15.

Source: http://www.cs.uic.edu/~jbell/CourseNotes/OperatingSystems/9_VirtualMemory.html

Figure 7.15: Thrashing

With the increase in the degree of multiprogramming, the utilisation of CPU also
increases, even though more slowly, until a maximum is achieved.
The OS can reduce the effects of thrashing and improve performance by choosing
a more suitable replacement strategy for pages.
It must be understood that having a replacement strategy that does not cause
memory areas to be written to disk that have not modified since been retrieved reduces
thrashing. Using replacement strategies that allow little used rarely accessed pages to
remain in memory while the most required pages are swapped in and out.
Now, you will see an example of operating systems which use virtual memory.
Example: Windows Operating System
Windows uses demand paging with clustering, meaning they page in multiple pages
whenever a page fault occurs.
The working set minimum and maximum is normally set at 50 and 345 pages
respectively. (Maximums can be exceeded in rare circumstances.)
Free pages are maintained on a free list, with a minimum threshold indicating when
there are enough free frames available.
If a page fault occurs and the process is below their maximum, then additional
pages are allocated. Otherwise some pages from this process must be replaced, using
a local page replacement algorithm.

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If the amount of free frames falls below the allowable threshold, then working set
trimming occurs, taking frames away from any processes which are above their
minimum, until all are at their minimums. Then additional frames can be allocated to Notes
processes that need them.
The algorithm for selecting victim frames depends on the type of processor:
z On single processor 80x86 systems, a variation of the clock (second chance)
algorithm is used.
z On Alpha and multiprocessor systems, clearing the reference bits may require
invalidating entries in the TLB on other processors, which is an expensive
operation. In this case Windows uses a variation of FIFO.

7.8 Demand Segmentation

Same idea as demand paging applied to segments.
z If a segment is loaded, base and limit are stored in the STE and the valid bit is set
in the PTE.
z The PTE is accessed for each memory reference (not really, TLB).
z If the segment is not loaded, the valid bit is unset. The base and limit as well as the
disk address of the segment is stored in the an OS table.
z A reference to a non-loaded segment generate a segment fault (analogous to page
fault).
z To load a segment, we must solve both the placement question and the
replacement question (for demand paging, there is no placement question).
z I believe demand segmentation was once implemented by Burroughs, but am not
sure. It is not used in modern systems.
The following table compares demand paging with demand segmentation.
Table 7.1: Comparison of demand paging with demand segmentation
Consideration Demand Paging Demand Segmentation
Programmer aware No Yes
How many addr spaces 1 Many
VA size > PA size Yes Yes
Protect individual No Yes
procedures separately
Accommodate No Yes
elements
with changing sizes
Ease user sharing No Yes
Why invented let the VA size exceed the PA size Sharing, Protection, independent
addr spaces
Internal fragmentation Yes No, in principle
External fragmentation No Yes
Placement question No Yes
Replacement question Yes Yes

7.10 Summary
Virtual memory permits the execution of processes that may not be completely resident
in the memory. Virtual memory is commonly implemented by Demand Paging. It can
also be implemented in a segmentation system. In demand paging, rather than
swapping the entire process into memory, a lazy swapper is used, which swaps a page
into memory only when that page is needed. The idea of Copy on Write (COW) is quite
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simple: instead of duplicating page frames, they are shared between the parent and the
child process. Page replacement is basic to demand paging. It completes the
Notes separation between logical memory and physical memory. A FIFO replacement
algorithm associates with each page the time when that page was brought into memory.
An optimal page-replacement algorithm has the lowest page-fault rate of all algorithms.
LRU algorithm associates to each page brought into the memory, the time at which the
page was last used. Standard methods used for frame allocation include Equal
allocation and Proportional allocation. Thrashing happens when a hard drive has to
move its heads over the swap area many times due to the high number of page faults

7.11 Check Your Progress

Multiple Choice Questions
1. ................... is a facility that allows programmers to address memory from a logical
point of view, without regard to the main memory, physically available.
(a) Visual memory
(b) Real memory
(c) Virtual memory
(d) Secondary memory
2. Virtual memory is
(a) an extremely large main memory
(b) an extremely large secondary memory
(c) an illusion of extremely large main memory
(d) a type of memory used in super computers
3. In virtual memory systems, Dynamic address translation
(a) is the hardware necessary to implemented paging
(b) stores pages at a specifies location on disk
(c) is useless when swapping is used.
(d) is part of the operating system paging algorithm
4. Paging ………………
(a) solves the memory fragmentation problem
(b) allows modular programming
(c) allows structured programming
(d) avoids deadlock
5. A page fault occurs
(a) when the page is not in the memory
(b) when the page is in the memory
(c) when the process enters the blocked state
(d) when the process is in the ready state
6. Because of virtual memory, the memory can be shared among
(a) processes
(b) threads
(c) instructions
(d) none of the mentioned

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7. …………… is the concept in which a process is copied into main memory from the
secondary memory according to the requirement.
(a) Paging
Notes
(b) Demand paging
(c) Segmentation
(d) Swapping
8. The pager concerns with the
(a) individual page of a process
(b) entire process
(c) entire thread
(d) first page of a process
9. Swap space exists in
(a) primary memory
(b) secondary memory
(c) CPU
(d) none of the mentioned
10. When a program tries to access a page that is mapped in address space but not
loaded in physical memory, then
(a) segmentation fault occurs
(b) fatal error occurs
(c) page fault occurs
(d) no error occurs

7.12 Questions and Exercises

1. What is virtual memory? Explain the working of Virtual Memory.
2. Explain the performance of demand paging.
3. Describe the methods used for creating processes.
4. How the first generation Unix kernel creates a process? How the same differs from
Modern Unix kernel?
5. Describe the major problems related to demand paging.
6. Explain the concept of optimal algorithm with example.
7. What is the cause of thrashing? How does the system detect thrashing? Once it
detects thrashing, what can the system do to eliminate this problem?
8. Discuss the need of page replacement. Explain the concept of page replacement
with example.

7.13 Key Terms

z Virtual Memory: It is a technique that permits the execution of processes that may
not be completely resident in the memory.
z FIFO (First In First Out): It is the replacement algorithm which associates with
each page the time when that page was brought into memory.
z LRU (Least Recently Used): It replaces the page that has not been used for the
longest period of time.
z Optimal Algorithm: It replaces the page that will not be used for the longest period
of time.
z Thrashing: It is a process that is spends more time paging than executing..

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Check Your Progress: Answers

1. (c) Virtual memory
Notes
2. (c) an illusion of extremely large main memory
3. (a) is the hardware necessary to implemented paging
4. (a) solves the memory fragmentation problem
5. (a) when the page is not in the memory
6. (a) processes
7. (b) Demand paging
8. (a) individual page of a process
9. (b) secondary memory
10. (c) page fault occurs

7.14 Further Readings

z Dr. R.C. Joshi, Operating Systems, Dreamtech Press, 2008
z Er. Vivek Sharma, Er. Manish Varshney, Shantanu Sharma , Design and
Implementation of Operating System, Laxmi Publications, 2010
z Sibsankar Haldar, Operating Systems, Pearson Education India, 2010
z Dp Sharma, Foundation of Operating Systems, Excel Books India, 2008

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