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Lab 0.2 Vivado Simulation

This document provides instructions for using Vivado simulation software to design and test an FPGA project. It describes how to create a new project, add design and testbench sources, run a behavioral simulation, and debug the design by examining waveforms and reordering signals. The tutorial demonstrates basic Vivado functions for simulation and debugging an FPGA project designed on a Basys3 development board.

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龔資尹
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107 views17 pages

Lab 0.2 Vivado Simulation

This document provides instructions for using Vivado simulation software to design and test an FPGA project. It describes how to create a new project, add design and testbench sources, run a behavioral simulation, and debug the design by examining waveforms and reordering signals. The tutorial demonstrates basic Vivado functions for simulation and debugging an FPGA project designed on a Basys3 development board.

Uploaded by

龔資尹
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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EECS 207002

Logic Design Laboratory


邏輯設計實驗

Vivado Simulation
黃元豪
Yuan-Hao Huang

國立清華大學電機工程學系
Department of Electrical Engineering
National Tsing-Hua University

NTHU EECS Logic Design Lab. 1


FPGA Development Kits

Pmod cable
Basys3 development board

PmodAMP2
audio amplifier

Box

USB-to-microUSB cable

NTHU EECS Logic Design Lab. 2


FPGA Development Kits

Only 5V DC

NTHU EECS Logic Design Lab. 3


Basys3 Demo Board

NTHU EECS Logic Design Lab. 4


Create New Project (1/4)

Click this icon

NTHU EECS Logic Design Lab. 5


Create New Project (2/4)

• Fill in project name and location

NTHU EECS Logic Design Lab. 6


Create New Project (3/4)
• Choose project type

NTHU EECS Logic Design Lab. 7


Create New Project (4/4)

Find these information on your box

NTHU EECS Logic Design Lab. 8


Simulation (1/4): Add Source

• Add sources (e.g., design, testbench, …etc)

NTHU EECS Logic Design Lab. 9


Simulation (2/4): Add Source

Your design and corresponding testbench

NTHU EECS Logic Design Lab. 10


Simulation (3/4): Run Simulation
• Run Simulation -> Run behavioral Simulation

NTHU EECS Logic Design Lab. 11


Simulation (4/4): Check Signals

• Show waveform

NTHU EECS Logic Design Lab. 12


Debugging The Design (1/4)

• Zoom fit Unfit waveform

NTHU EECS Logic Design Lab. 13


Debugging The Design (2/4)
• Reorder the signals
Choose the
block that you
want to see

1. clock
2. Inputs
3. output

NTHU EECS Logic Design Lab. 14


Debugging The Design (3/4)
• Right click to open the popup menu again, and
select Radix > Unsigned Decimal

NTHU EECS Logic Design Lab. 15


Debugging The Design (4/4)

• Right click to open the popup menu again, and


select New Divider

NTHU EECS Logic Design Lab. 16


Reference

• You can find the tutorial of Vivado in DocNav


(e.g., ug937-vivado-design-suite-simulation-tutorial.pdf)

NTHU EECS Logic Design Lab. 17

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