CT2 Coa KCS-302

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Roll

No.
KRISHNA ENGINEERING COLLEGE, GHAZIABAD
Department of Computer Science & Engineering
B. Tech. (SEM: III)
CT-2 (Odd Sem-2019-20), Oct. 2019
Subject Name: Computer Organization & Architecture Subject Code: KCS-302
Max. Time: 2 Hrs Max. Marks: 50
Faculty Name: Mr. Ankit Kumar/ Mr. Shashi Bhushan

Study of the basic structure and operation of a digital computer BL1,


CO 1
system. BL2
Analysis of the design of arithmetic & logic unit and understanding BL2,
CO 2 BL4
of the fixed point and floating point arithmetic operations.
Implementation of control unit techniques and the concept of BL3
CO 3
Pipelining
Understanding the hierarchical memory system, cache memories and BL2
CO 4
virtual memory
Understanding the different ways of communicating with I/O BL2,
CO 5
devices and standard I/O interfaces BL4
Note: Attempt all sections.

SECTION - A
Attempt all questions. (2x4=8)
Q. No. Question Marks CO BL
a Illustrate horizontal and Vertical microprogramming. 2 3 BL3
Show the relationship among micro-operation, micro- 2 3 BL3
b
instruction and micro-program.
1.
c Differentiate between SRAM and DRAM? 2 4 BL2
Discuss how many 128X8 RAM chips are needed to provide 2 4 BL2
d
memory capacity of 2048 bytes?

SECTION - B
Attempt all questions. (6x4=24)
Q. No. Question Marks CO BL
2. Model the micro-program sequencer and show the working 6 3 BL3
of micro-program sequencer?
OR
Demonstrate the working of pipelining. How it is essential in
parallel processing. If no of tasks are 6 and segment are 4
then how many clock cycles are there in pipelining.

Examine the working of RISC and CISC in detail?


OR
3. 6 3 BL3
Examine different types of micro-operation? State different
types of micro-operations in detail.
Describe Auxiliary Memory? What is the need of Auxiliary
Memory? Explain different types of Auxiliary Memory in
4. detail? 6 4 BL2
OR
Explain 2D and 2 1/2D Memory Organization in detail
A digital computer has a memory unit of 64K and a cache
memory of 1K words. The cache uses direct mapping with
block size of four words.

(i)Interpret how many bits are there in main memory and


5. cache memory? 6 4 BL2
(ii) Interpret how many bits are there in tag, index, block and
word fields of the address format?

OR
Explain the concept of instruction cycle & subcyles.

SECTION - C
Attempt all questions. (9x2=18)
Q. No. Question Marks CO BL
6. Illustrate Hard-wired Control Unit in detail? Mention its 9 3 BL3
advantages and disadvantages too?
OR
Solve the following arithmetic statement:

X = (A-B) * (((C-D/F)/G)

(i) using a general register computer with three


address instruction.
(ii) using a general register computer with two address
instruction.
(iii) using an accumulator type computer with one
address instruction.
(iv) using a stack organized computer with zero
address instruction.

Explain and compare different cache mapping techniques in


detail?
OR
7. Interpret page fault by applying FIFO and Optimal page 9 4 BL2
replacement algorithm for the following string, free frame
size is 3.
7,0,1,2,0,3,0,4,2,3,0,3,2,1,2

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