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Sequential Circuits

Synchronous Asynchronous

Digital Design Behavior defined at discrete Depends on i/p signals

Intervals of time. at any instant of time
Lecture 35-37 and the order in which
i/ps change.

n input
variables
x1
x2
z1
z2 m output
variables
Asynchronous Sequential Logic
xn zm

y1 Combinational Y1 • Asynchronous sequential circuit – combinational circuit with delay

Circuit
y2 Y2
yk Yk
• Delay elements – providing short term memory for sequential circuit
k secondary k excitation
Variables Variables
(present state) (next state) • Present state variables – Secondary variables
Delay

Delay
• Next state variables – Excitation variables

Delay

Async Sequential ckt - Fundamental mode of Async Seg ckts

• Steady state - System is stable  yi = Yi, for i = 1,2,…,k. • Simultaneous changes of two or more input variable is prohibited.

• Transition state – System is Unstable  yi ≠ Yi • I/p changes one at a time and only when the ckt is in stable state.

• Transition from one stable state to another occurs only in response to change in • Time between two i/p changes is longer than time to reach stable state.
input variables.

 Fundamental mode

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Transition Table Y1 = (x . y1) + (x’ . y2)

Y2 = (x . y1’) + (x’ . y2)

y1
x
Y1

y2
Y2

States = y1y2x
Transition Table 4 stable states and
4 unstable state
State Table
x x x
y1y2 0 1 y1y2 0 1 y1y2 0 1 Next State
Present State
00 0 0 00 0 1 00 00 01
x=0 x=1
1 0 1 1
01 01 01 11 01
0 0 0 0 0 1
1 1 1 0 11 10
11 11 11 0 1 1 1 0 1
0 1
0 0 00 10
10 10 10 1 0 0 0 1 0

Y1 = (x . y1) + (x’ . y2) Y2 = (x . y1’) + (x’ . y2) Transition Table 1 1 1 1 1 0

Procedure for Transition table

Flow Table – Use of “letter symbols”
• Determine the feedback loops in the circuit.
x
• O/p of feedback loop is Yi and i/p is yi. y 0 1
x1 x2
a a b 00 01 11 10
y
• Determine Boolean function of Y in terms of external inputs and y.
a a , 0 a , 0 a , 0 b , 0
b c b
a , 0 a , 0
• Plot each Y function in map, using y as rows and external inputs as columns. b , 1 b , 0
b
c c d

• Combine the maps into one table showing Y = Y1Y2…Yk.

a d More than one stable state in same row.
d

• Circle the values where Y=y. Primitive flow table 

Only one stable state in each row.

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Flow Table – Use of “letter symbols” Flow table to transition table

Y x1 x2
x1 x2
00 01 11 10 00 01 11 10
y y
0 0 0 0 1
a a , 0 a , 0 a , 0 b , 0

a , 0 a , 0 0 0 1 1
b , 1 b , 0 1
b
Output Map
z = x1 x2 y
Transition Table z x1 x2
Y = (x1 . x2’) + (x1 . y) 00 01 11 10
y
0 0 0 0 0

1 0 0 1 0

Logic Diagram

x1
x2 Y

Race conditions Noncritical Races

• In an async circuit, two or more binary state variable may change value in response to x x
a change in an input variable. y1y2 0 1 y1y2 0 1

00 00 11 00 00 11
• For example state variable change can be 00 to 11, where-in unequal delays may lead
to situation like, 01 11 01 01
00  01  11 or
00  10  11 11 11 01
11

11 11
• If the order of change of variable is not important, and irrespective of this order we 10 10
can reach to final steady state, then it is non-critical race condition.
• If depending on order of change of variable, ckt can end up in two or more different 00 → 11 00 → 11 → 01
stable state, then it is critical race condition and should be avoided. 00 → 01 → 11 00 → 01
00 → 10 → 11 00 → 10 → 11 → 01

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Critical Races Cycles

x x x x x
y1y2 0 1 y1y2 0 1 y1y2 0 1 0 1
y1y2 y1y2 0 1
00 00 11 00 00 11 00 00 01 00 00 01 00 00 01

01 01 01 11 01 11 01 11 01 11

11 11 11 10 11
11 11 11 11 10

10 10 10 10
10 10 10 10 01
10

00 → 11 00 → 11
00 → 01 → 11 → 10 00 → 01 → 11 01 → 11 → 10
00 → 01 00 → 01 → 11
00 → 10 00 → 10

Unstable Circuit Unstable Circuit

Y = (x1 . y)’ x2

y = x1’x2+x2y’ y
x1 x1

Y Y
x2 x2
Transition Table Transition Table
Logic Diagram x1 x2 Logic Diagram x1 x2
00 01 11 10 00 01 11 10
y y
0 0 1 1 0 0 0 1 1 0

0 1 0 0 0 1 0 0
1 1

SR Latch with NOR gates

S R Q Q’
R
Q 1 0 1 0

0 0 1 0 Aftter SR = 10

0 1 0 1

S Q’ 0 0 0 1 Aftter SR = 01

1 1 0 0
Cross-coupled Circuit

Truth Table

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SR Latch with NOR gates SR Latch with NAND gate

S R Q Q’

Transition Table S 1 0 0 1
Y=Q SR Q
R 00 01 11 10 1 1 0 1 Aftter SR = 10
y
0 0 0 0 1
S 0 1 1 0
Q’
R
1 1 0 0 1 1 1 1 0 Aftter SR = 01
y
0 0 1 1
Y = SR’ + R’y
Circuit showing feedback Cross-coupled Circuit
Y = S + R’y when SR = 0
Truth Table

SR Latch with NAND gate Analysis Example S1 = x1 y2

R1 = x1’ x2’

S2 = x1 x2
R2 = x2’ y1
Transition Table
S
Y=Q x1 x2
00 01 11 10
Step 1 – Check whether condition
y SR =0 is satisfied.
0 1 1 0 0
R
Step 2 –Build transition table.
1 1 1 1 0 i.e. Specify Y in terms of y and x.
y

Y1 = S1+ R1’y1 = x1y2 + x1y1 + x2y1

Circuit showing feedback
Y = S’ + R y Y2 = S2+ R2’y2 = x1x2+ x2y2+ y1’y2

Analysis Example Analysis Example

Y1Y2 Y1Y2
x1 x2 x1 x2
00 01 11 10 00 01 11 10
y1y2 y1y2
00 00 00 01 00 00 00 00 01 00

01 01 01 11 11 01 01 01 11 11

11 00 11 11 10 11 00 11 11 10

10 00 10 11 10 10 00 10 11 10

Transition Table Transition Table

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Steps for Analysis Latch Excitation table

• Label each latch output with Yi and its external feedback path (if any) with yi.
SR Latch Excitation Table
• Derive the Boolean functions for the Si and Ri inputs in each latch.
y Y S R

• For proper operation of ckt, in NOR latch  SR =0, in NAND latch S’R’=0. 0 0 0 X

0 1 1 0
• Evaluate Y = S+R’y for NOR latch, and Y = S’+Ry for NAND latch.
1 0 0 1
• Construct map for Y, with y as rows and x as columns.
1 1 X 0

• Transition table  circle the stable states Y=y.

SR Latch Excitation Table

x1 x2
00 11 y Y S R
01 10
z y
0 0 0 0 1 0 0 0 X
x1
0 1 1 0
x2 Y 1 0 0 1 1
1 0 0 1
Transition Table
1 1 X 0

x1 x2
00 01 11 10
y x1 x2 x1 x2
0 00 01 11 10 00 01 11 10
0 0 0 1 y y
0 0 0 1 X X X 0
1 0 0 1 1
0 0 X X 1 1 0 0

Transition Table
Y = (x1 . x2’) + (x1 . y) Map Map
S = x1 x2’ R = x1’

SR Latch Excitation Table

x1 x2
00 11 y Y S R
01 10
y x1 R
Y
0 0 0 0 1 0 0 0 X

0 1 1 0
1 0 0 1 1
1 0 0 1 S
x2
Transition Table
1 1 X 0
Circuit with NOR Latch Circuit with NAND Latch
x1 x2 x1 x2
00 01 11 10 x2 S
00 01 11 10 Y
y y
0 0 0 1 X X X 0

0 0 X X 1 1 0 0
x1 R

Map Map
S = x1 x2’ R = x1’

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S R Q Q’
1 0 0 1

Debounce Circuit 1 1 0 1
0 1 1 0
1 1 1 0
0 0 1 1

S
Q

A Q

R Q’
B
Q’

A B A

State model
Design Example - D =1,
G=1
D =0, D =1, 11
a, 0 b, 1 G=1
Design a gated latch circuit with two inputs G (gate) and D (data) and one output Q. 01 G=1 D =0,
G=1
Binary information present at the D input is transferred to the Q output when G is
equal to 1. D =0, D =1,
G=0 D =0, D =1, 10
The Q output will follow the D input as long as G = 1. G=1 G=1
G=0
00 D =1,
When G goes to 0, the information that was present at the D input at the time the c, 0 e, 1
G=1
transition occurred is retained at the Q output.
D =0,
The gated latch is a memory element that accepts the value of D when G = 1 and G=1
D =1,
retains this value after G goes to 0. D =1, D =0, G=0
D =0,
G=0 G=0 G=0 00
Once G = 0, a change in D does not change the value of the output Q.
10
d, 0 f, 1

Gated latch states

Inputs Output
State Comment
D G Q

a 0 1 0 D = Q because G = 1

b 1 1 1 D = Q because G = 1

c 0 0 0 After state a or d

d 1 0 0 After state c

e 1 0 1 After state b or f

f 0 0 1 After state e