MIC4609

600V 3-Phase MOSFET/IGBT Driver

Features General Description
• Gate Drive Supply Voltage up to 20V The MIC4609 is a 600V 3-phase MOSFET/IGBT driver.
• Overcurrent Protection with Programmable The MIC4609 features a 300 ns typical input filtering
Restart Delay time to prevent unwanted pulses and a 550 ns of
• 1A Gate Drivers propagation delay. The MIC4609 has TTL input
thresholds.
• Dual (HI/LI) Inputs per Phase
• Fault Signal Asserts on Overcurrent and The robust operation of the MIC4609 ensures that the
VDD UVLO outputs are not affected by supply glitches, High Side
(HS) ringing below ground, or HS slewing with
• TTL Input Thresholds
high-speed voltage transitions. Undervoltage
• 300 ns Typical Input Filtering Time protection is provided on both the low-side and
• Shoot-Through Protection high-side drivers.
• Low-Power Consumption The MIC4609 is available in a 28-pin wide SOIC
• Supply Undervoltage Protection package. The MIC4609 has an operating junction
• -40°C to +125°C Junction Temperature Range temperature range of -40°C to +125°C.
Package Type
Typical Applications MIC4609
• 3-Phase Motor Drive 28-Pin SOICW
• Field-Oriented Control (FOC)
VDD 1 28 AHB
• White Goods Appliances
• Brushless DC Fans AHI 2 27 AHO
BHI 3 26 AHS
CHI 4 25 NC
ALI 5 24 BHB
BLI 6 23 BHO
CLI 7 22 BHS
FAULT 8 21 NC
ISNS 9 20 CHB
EN 10 19 CHO
RCIN 11 18 CHS
VSS 12 17 NC
COM 13 16 ALO
CLO 14 15 BLO

 2016 Microchip Technology Inc. DS20005531A-page 1

MIC4609
Functional Block Diagram MIC4609 – Top Level Circuit
VDD

VDD AHB
UVLO VDD

UVLO AHO
UVLO
EN Phase A Drive Circuit
AHS
AHI
AHI
Input Filter & ALO
Anti-Shoot-Through ALI
VSS COM
ALI

VSS BHB
VDD

UVLO BHO

EN Phase B Drive Circuit

BHS
BHI BHI
Input Filter & BLO
Anti-Shoot-Through BLI COM
VSS

BLI

VSS CHB
VDD

UVLO CHO

EN Phase C Drive Circuit CHS

CHI
CHI

Input Filter & CLO

Anti-Shoot-Through CLI COM
VSS
CLI

VSS COM COM

UVLO
S Q
ISNS + Input Latch
- Blanking _ FAULT
R Q

VISNS
VSS
IRCIN
RCIN + Input
EN EN
Filter
-

VRCIN+
VSS

VSS

VSS

DS20005531A-page 2  2016 Microchip Technology Inc.

 MIC4609
Functional Block Diagram MIC4609 – Phase x Drive Circuit

xHB

VDD
UVLO
DRIVER xHO
UVLO
EN
LEVEL
SHIFT
xHS

xHI

S Q

R Q
xLI DRIVER xLO

COM
Note: The x in the suffix of a pin name designates any of the three phases, e.g., xHS refers to either AHS,
BHS or CHS.

 2016 Microchip Technology Inc. DS20005531A-page 3

 Typical Application Circuit MIC4609 – 300V, 3-Phase Motor Driver
DS20005531A-page 4

MIC4609
VDD
R3 D3

R2 D2 300V
SUPPLY
R1 D1
VCC

V DD AHB Q2 Q4 Q6
AHO
FAULT
AHS C1
EN
BHB
BHO
AHI C2
BHS
ALI
Controller MIC4609 CHB
CHO
BHI C3
CHS
BLI
ALO
BLO Q1 Q3 Q5
CHI
CLO
CLI
ISNS
RCIN V SS COM
 2016 Microchip Technology Inc.

CDLY
RS
 MIC4609
1.0 ELECTRICAL Operating Ratings (1)
CHARACTERISTICS Supply Voltage (VDD) ....................................... +10V to +20V
Voltage on xHS (continuous) ............................. -1V to +600V
Absolute Maximum Ratings † Voltage on xHS (repetitive transient) ................. -5V to +600V
HS Slew Rate .............................................................. 50V/ns
Supply Voltage (VDD, VXHB - VXHS) .................. -0.3V to +25V Voltage on xHB .............................VXHS + 10V to VXHS + 20V
Input Voltages (VXLI, VXHI, VEN) .......................... -0.3V to VDD and/or ........................................VDD - 1V to VDD + 600V
Voltage on LO (VXLO) .......................................... -0.3V to VDD Junction Temperature (TJ) ........................... -40°C to +125°C
Voltage on HO (VXHO) .................................VHS - 0.3V to VHB Junction Thermal Resistance (JA).............. -40°C to +125°C
Voltage on HS .................................................... -5V to +630V SOIC Wide 28LD ................................................ 53°C/W
Voltage on HB ...............................................................+655V
Storage Temperature ...................................-60°C to +150°C
Note 1: The device is not guaranteed to function
ESD Rating
outside its operating rating.
HBM .......................................................................... 2kV
CDM ...................................................................... 1.5 kV
† Notice: Stresses above those listed under “Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only and functional operation of
the device at those or any other conditions above those
indicated in the operational listings of this specification
is not implied. Exposure to maximum rating conditions
for extended periods may affect device reliability.

AC/DC ELECTRICAL CHARACTERISTICS (Note 1, 2)

Electrical Specifications: Unless otherwise indicated, VDD = VxHB = 20V, VEN = 5V, VSS = VxHS = 0V; No load on
xLO or xHO, TA = +25°C. Bold values indicate -40°C TJ +125°C.
Parameter Sym. Min. Typ. Max. Unit Conditions
Supply Current
VDD Quiescent Current IDD — 150 250 µA xLI = xHI = 0V
VDD Shutdown Current IDDSH — 0.1 10 µA EN = 0V with HS = floating
or ground
VDD Operating Current IDDO — 240 350 µA f = 20 kHz
Total xHB Quiescent Current IxHB — 81 180 µA xLI = xHI = 0V or
xLI = 0V and xHI = 5V
Total xHB Operating Current IxHBO — 600 1500 µA f = 20 kHz
High-Side Leakage Current ILxHB — 1 10 µA VxHB = VxHS = 600V
Input (TTL: xLI, xHI, EN)
Low-Level Input Voltage VIL — — 0.8 V
High-Level Input Voltage VIH 2.2 — — V
Input Voltage Hysteresis VHYS — 0.2 — V
Input Pull-Down Resistance RI 100 370 500 k For xLI and xHI only (Note 3)
Undervoltage Protection
VDD Falling Threshold VDDR 7 8 9 V
VDD Threshold Hysteresis VDDH — 0.5 — V
xHB Falling Threshold VxHBR 7 8 9 V
xHB Threshold Hysteresis VxHBH — 0.5 — V
Note 1: Specification for packaged product only.
2: The x in the suffix of a pin name designates any of the three phases, e.g., xHS refers to either AHS, BHS
or CHS.
3: Enable resistance is typical only and is not production tested.

 2016 Microchip Technology Inc. DS20005531A-page 5

MIC4609
AC/DC ELECTRICAL CHARACTERISTICS (CONTINUED) (Note 1, 2)
Electrical Specifications: Unless otherwise indicated, VDD = VxHB = 20V, VEN = 5V, VSS = VxHS = 0V; No load on
xLO or xHO, TA = +25°C. Bold values indicate -40°C TJ +125°C.
Parameter Sym. Min. Typ. Max. Unit Conditions
Overcurrent Protection
Rising Overcurrent Threshold VISNS+ 420 520 650 mV
ISNS Pin Blanking Time tISNS_BLK 270 370 470 ns
ISNS-to-Gate Propagation Delay tISNS_PROP 400 650 900 ns
Fault Circuit
Fault Pin Output Low Voltage VOLF — — 0.8 V VISNS = 1V, IFAULT = 1 mA
Rising VCIN Pin Threshold VRCIN+ — 5 — V
VCIN Hysteresis VRCIN_HYS — 0.6 — V
RCIN Pin Current Source IRCIN 3 5 7 µA VRCIN = 0V
Fault Clear Time tFCL 0.5 1 2 ms CRCIN = 1nF
LO Gate Driver
Low-Level Output Voltage VxOLL — 0.5 0.9 V IxLO = 50 mA
High-Level Output Voltage VxOHL — 0.6 0.9 V IxLO = -50 mA
VxOHL = VDD - VxLO
Peak Sink Current IxOHL — 1 — A VxLO = 0V
Peak Source Current IxOLL — 1 — A VxLO = 20V
HO Gate Driver
Low-Level Output Voltage VxOLH — 0.5 0.9 V IxHO = 50 mA
High-Level Output Voltage VxOHH — 0.6 0.9 V IxHO = -50 mA
VxOHH = VxHB - VxHO
Peak Sink Current IxOHH — 1 — A VxHO = 0V
Peak Source Current IxOLH — 1 — A VxHO = 20V
Switching Specifications
Turn-On Propagation Delay tON 300 600 700 ns CL = 1 nF
Turn-Off Propagation Delay tOFF 300 550 700 ns CL = 1 nF
Turn-On Rise Time tR — 20 60 ns CL = 1 nF
Turn-Off Fall Time tF — 20 60 ns CL = 1 nF
Input Filtering Time tFLTR 200 300 480 ns xLI, xHI, EN
Dead Time tD 200 300 450 ns CL = 1 nF
Delay Matching tDLYM — 50 — ns CL = 1 nF
EN-to-Gate Shutdown Delay tEN_OFF 450 650 750 ns CL = 1 nF
Output Pulse Width Matching tPWN — 50 — ns tPW > 1 µs
CL = 1 nF
Note 1: Specification for packaged product only.
2: The x in the suffix of a pin name designates any of the three phases, e.g., xHS refers to either AHS, BHS
or CHS.
3: Enable resistance is typical only and is not production tested.

DS20005531A-page 6  2016 Microchip Technology Inc.

 MIC4609
TEMPERATURE CHARACTERISTICS
Electrical Specifications: Unless otherwise indicated, all parameters apply with 10V VDD 20V.
Parameters Sym. Min. Typ. Max. Units Conditions
Temperature Ranges
Specified Temperature Range (Note 1) TA -40 — +125 °C
Operating Temperature Range TA -40 — +125 °C
Storage Temperature Range TS -60 — +150 °C
Thermal Package Resistances
Thermal Resistance, 28LD SOICW JA — 53 — °C/W
Note 1: Operation in this range must not cause TJ to exceed Maximum Junction Temperature (+125°C).

 2016 Microchip Technology Inc. DS20005531A-page 7

MIC4609
2.0 TYPICAL PERFORMANCE CURVES
Note: The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.

Note: Unless otherwise indicated, TA = +25°C with 10V  VDD  20V.

140 50
VHS = GND VHS = GND
VDD Quiescent Current (μA)

EN = VDD EN = VDD

VHB Quiescent Current (μA)

120 125°C
40
100
VHB = 20V VHB = 14V
80 30

60 25°C 20
-40°C
40
10
20
VHB = 10V
0 0
10 11 12 13 14 15 16 17 18 19 20 -50 -25 0 25 50 75 100 125
VDD (V) Temperature (°C)

FIGURE 2-1: VDD Quiescent Current vs. FIGURE 2-4: VHB Quiescent Current vs.
VDD Voltage. Temperature.

140 10
VDD+HB Shutdown Current (μA)

VDD = 20V
VDD Quiescent Current (μA)

120
1 HI = LI = 0V
100 VHS = Floating
EN = 0V 125°C
80 VDD = VHB
0.1
60
VDD = 15V -40°C
40
VDD = 10V 0.01
20
VHS = GND
EN = VDD 25°C
0 0.001
-50 -25 0 25 50 75 100 125 10 11 12 13 14 15 16 17 18 19 20
Temperature (°C) VDD+HB (V)

FIGURE 2-2: VDD Quiescent Current vs. FIGURE 2-5: VDD+HB Shutdown Current
Temperature. vs. Voltage.

50 10
VHS = GND
VDD+HB Shutdown Current (μA)

EN = VDD
VHB Quiescent Current (μA)

40 1
125°C
30 0.1 VDD = 20V
VDD = 15V

20 0.01
25°C HI = LI = 0V
10 -40°C 0.001 VHS = Floating
VDD = 10V EN = 0V
VDD = VHB
0 0.0001
10 12 14 16 18 20 -50 -25 0 25 50 75 100 125
VHB (V) Temperature (°C)

FIGURE 2-3: VHB Quiescent Current vs. FIGURE 2-6: VDD+HB Shutdown Current
VHB Voltage. vs. Temperature.

DS20005531A-page 8  2016 Microchip Technology Inc.

 MIC4609
Note: Unless otherwise indicated, TA = +25°C with 10V  VDD  20V.

120 200
HI = LI = 0V VHB = VDD
VDD+HB Shutdown Current (μA)

VHS= GND 180 VHS = 0V

VHB Operating Current (μA)

100 EN = 0V CL = 0 nF
VDD= VHB 25ºC 160 -40ºC
125ºC
80 140
120 25ºC
60 100
80
40
-40ºC 60
20 40 125ºC
20
0 0
10 11 12 13 14 15 16 17 18 19 20 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
VDD+HB (V) Frequency (kHz)

FIGURE 2-7: VDD+HB Shutdown Current FIGURE 2-10: VHB Operating Current vs.
vs. Voltage. Frequency – One Phase.

120 25
IHO = 50 mA
VDD+HB Shutdown Current (μA)

VHS = GND
VDD = 20V
100 EN = VHB = VDD
VDD = 15V
20 125ºC

RON Sink (Ω)

80 25ºC

60 15

40
HI = LI = 0V 10
20 VDD = 10V
VHS = GND
EN = 0V
VDD = VHB -40ºC
0 5
-50 -25 0 25 50 75 100 125 10 11 12 13 14 15 16 17 18 19 20
Temperature (°C) VDD (V)

FIGURE 2-8: VDD+HB Shutdown Current FIGURE 2-11: HO Output Sink

vs. Temperature. ON-Resistance vs. VDD.

200 25
VHB = VDD IHO = 50 mA
VDD Operating Current (μA)

180 VHS = 0V VHS = GND

CL = 0 nF EN = VHB = VDD
160 125ºC
25ºC 20
VDD = 10V
140
RON Sink (Ω)

120 VDD = 15V

100 15
80
-40ºC
60
10
40
20 VDD = 20V

0 5
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 -50 -25 0 25 50 75 100 125
Frequency (kHz) Temperature (°C)

FIGURE 2-9: VDD Operating Current vs. FIGURE 2-12: HO Output Sink
Frequency. ON-Resistance vs. Temperature.

 2016 Microchip Technology Inc. DS20005531A-page 9

MIC4609
Note: Unless otherwise indicated, TA = +25°C with 10V  VDD  20V.

25 20
ILO = 50 mA IHO = -50 mA
VHS = GND VHS = GND
125ºC EN = VHB = VDD EN = VHB = VDD VDD = 10V
20 15

RON Source (Ω)

RON Sink (Ω)

25ºC
15 10

VDD = 20V
10 5
VDD = 15V
-40ºC

5 0
10 11 12 13 14 15 16 17 18 19 20 -50 -25 0 25 50 75 100 125
VDD (V) Temperature (°C)

FIGURE 2-13: LO Output Sink FIGURE 2-16: HO Output Source

ON-Resistance vs. VDD. ON-Resistance vs. Temperature.

25 25
ILO = 50 mA ILO = -50 mA
VHS = GND VDD = 15V VHS = GND
EN = VHB = VDD 125ºC EN = VHB = VDD
20
VDD = 10V 20
RON Source (Ω)
RON Sink (Ω)

15
15 25ºC
10
VDD = 20V
10
5
-40ºC
0 5
-50 -25 0 25 50 75 100 125 10 11 12 13 14 15 16 17 18 19 20
Temperature (°C) VDD (V)

FIGURE 2-14: LO Output Sink FIGURE 2-17: LO Output Source

ON-Resistance vs. Temperature. ON-Resistance vs. VDD.

25 25
IHO = -50 mA ILO = -50 mA
VHS = GND VHS = GND VDD = 10V
EN = VHB = VDD EN = VHB = VDD
125ºC 20
20 VDD = 15V
RON Source (Ω)
RON Source (Ω)

15
15 25ºC
10
VDD = 20V
10
5
-40ºC
5 0
10 11 12 13 14 15 16 17 18 19 20 -50 -25 0 25 50 75 100 125
VDD (V) Temperature (°C)

FIGURE 2-15: HO Output Source FIGURE 2-18: LO Output Source

ON-Resistance vs. VDD. ON-Resistance vs. Temperature.

DS20005531A-page 10  2016 Microchip Technology Inc.

 MIC4609
Note: Unless otherwise indicated, TA = +25°C with 10V  VDD  20V.

9 70
VxHS = 0V V = 0V
65 CHS= 1 nF
8.8 60
L
VDD rising
55
UVLO Threshold (V)

8.6 125°C
50
8.4 VDD falling 45

tR (ns)
VHB rising 40 25°C
8.2
35
8 30 -40°C
7.8 VHB falling 25
20
7.6 15
7.4 10
-50 -25 0 25 50 75 100 125 10 11 12 13 14 15 16 17 18 19 20
Temperature (°C) VDD (V)

FIGURE 2-19: VDD/VHB ULVO vs. FIGURE 2-22: HO Rise Time vs. VDD
Temperature. Voltage.

700 70
TA = 25°C VHS = 0V
65 CL = 1 nF
680 VHS = 0V 125°C
CL = 1 nF
60
660 LI to LO falling 55 25°C
640 50
Delay (ns)

tF (ns)
620 45
600 40
HI to HO falling
35
580 LI to LO rising 30 -40°C
560 25
540 20
520 HI to HO rising 15
500 10
10 11 12 13 14 15 16 17 18 19 20 10 11 12 13 14 15 16 17 18 19 20
VDD (V) VDD (V)

FIGURE 2-20: Propagation Delay vs. VDD FIGURE 2-23: HO Fall Time vs. VDD
Voltage. Voltage.

70
800 VHS = 0V
VDD = 10V 65 CL = 1 nF
VHS = 0V
60
750 CL = 1 nF
LI to LO rising 55 125°C
50
700
Delay (ns)

LI to LO falling 45
tR (ns)

40
650
35 25°C

600 30
25
20 -40°C
550
15
HI to HO falling HI to HO rising
500 10
-50 -25 0 25 50 75 100 125 10 11 12 13 14 15 16 17 18 19 20
Temperature (°C) VDD (V)

FIGURE 2-21: Propagation Delay vs. FIGURE 2-24: LO Rise Time vs. VDD
Temperature. Voltage.

 2016 Microchip Technology Inc. DS20005531A-page 11

MIC4609
Note: Unless otherwise indicated, TA = +25°C with 10V  VDD  20V.

70 500
VHS = 0V TA = 25°C
65 CL = 1 nF VHS = 0V
60 450 CL = 1 nF
55 125°C HO fall to LO rise

Dead Time (ns)

50 400
45
tF (ns)

40 25°C 350
35
30 300
25 LO fall to HO rise
-40°C
20 250
15
10 200
10 11 12 13 14 15 16 17 18 19 20 10 11 12 13 14 15 16 17 18 19 20
VDD (V) VDD (V)

FIGURE 2-25: LO Fall Time vs. VDD FIGURE 2-28: Dead Time vs. VDD Voltage.
Voltage.

70 500
VDD = 10V VDD = 10V
65 VHS = 0V VHS = 0V
60 CL = 1 nF 450 CL = 1 nF
55 HO fall
HO fall to LO rise
50 Dead Time (ns) 400
tR/tF (ns)

45
40 350
35
30 LO fall LO rise 300
25 LO fall to HO rise
HO rise
20 250
15
10 200
-50 -25 0 25 50 75 100 125 -50 -25 0 25 50 75 100 125
Temperature (°C) Temperature (°C)

FIGURE 2-26: Rise/Fall Time vs. FIGURE 2-29: Dead Time vs. Temperature
Temperature (VDD = 10V). (VDD = 10V).

70 500
VDD = 20V VDD = 20V
65 VHS = 0V VHS = 0V
60 CL = 1 nF 450 CL = 1 nF
55 HO fall to LO rise
Dead Time (ns)

50 HO rise
400
tR/tF (ns)

45 HO fall
40 350
35
30 300
25
20 LO rise 250 LO fall to HO rise
15 LO fall
10 200
-50 -25 0 25 50 75 100 125 -50 -25 0 25 50 75 100 125
Temperature (°C) Temperature (°C)

FIGURE 2-27: Rise/Fall Time vs. FIGURE 2-30: Dead Time vs. Temperature
Temperature (VDD = 20V). (VDD = 20V).

DS20005531A-page 12  2016 Microchip Technology Inc.

 MIC4609
Note: Unless otherwise indicated, TA = +25°C with 10V  VDD  20V.

0.5 700
VHS = 0V VHS = 0V
0.495 CL = 0 nF CL = 0 nF
680

Propagation Delay (ns)

0.49 125°C
OC Threshold (V)

0.485 660
VDD = 20V
0.48 640
0.475 25°C
620
0.47
0.465 600
VDD = 15V
0.46 -40°C
580 VDD = 10V
0.455
0.45 560
10 11 12 13 14 15 16 17 18 19 20 -50 -25 0 25 50 75 100 125
VDD (V) Temperature (°C)

FIGURE 2-31: Overcurrent Threshold vs. FIGURE 2-34: Overcurrent Propagation

VDD Voltage. Delay vs. Temperature.

0.5
0.495
0.49
OC Threshold (V)

0.485 VDD = 20V

0.48
0.475
0.47
VDD = 15V
0.465
0.46
0.455 VDD = 10V VHS = 0V
CL = 0 nF
0.45
-50 -25 0 25 50 75 100 125
Temperature (°C)

FIGURE 2-32: Overcurrent Threshold vs.

Temperature.

700
VHS = 0V
CL = 0 nF
680 125°C
Propagation Delay (ns)

660
-40°C
640

620 25°C

600

580

560
10 11 12 13 14 15 16 17 18 19 20
VDD (V)

FIGURE 2-33: Overcurrent Propagation

Delay vs. VDD Voltage.

 2016 Microchip Technology Inc. DS20005531A-page 13

MIC4609
3.0 PIN DESCRIPTIONS
The descriptions of the pins are listed Table 3-1.

TABLE 3-1: PIN FUNCTION TABLE

SOICW-28LD Symbol I/O Description

1 VDD Power Input Supply for Gate Drivers

Decouple this pin to VSS with a > 2.2 µF capacitor.
Connect anode of bootstrap diodes to this pin.
2 AHI IN A-Phase High-Side Drive Input
3 BHI IN B-Phase High-Side Drive Input
4 CHI IN C-Phase High-Side Drive Input
5 ALI IN A-Phase Low-Side Drive Input
6 BLI IN B-Phase Low-Side Drive Input
7 CLI IN C-Phase Low-Side Drive Input
8 FAULT OUT Fault Output
Open drain asserts low to indicate Overcurrent or VDD Undervoltage condition.
9 ISNS IN Current Sense Input for Overcurrent Shutdown
10 EN IN Enable Input
Logic high on the Enable pin results in normal operation.
Logic low forces the device to enter Shutdown mode.
11 RCIN OUT Overcurrent Fault Clear Delay Pin
Connect to an external capacitor to set the fault clear delay.
12 VSS GND Logic Ground Pin
13 COM — Low-Side Driver Return Pin
14 CLO OUT C-Phase Low-Side Drive Output
Connect to the gate of the external low-side power MOSFET or IGBT.
15 BLO OUT B-Phase Low-Side Drive Output
Connect to the gate of the external low-side power MOSFET or IGBT.
16 ALO OUT A-Phase Low-Side Drive Output
Connect to the gate of the external low-side power MOSFET or IGBT.
17, 21, 25 NC — No Connect
18 CHS — C-Phase High-Side Drive Return Connection
Connect to the emitter or source of the external high-side power device.
Connect the bootstrap capacitor between this pin and the CHB pin.
19 CHO OUT C-Phase High-Side Drive Output
Connect to the gate of the external high-side power MOSFET or IGBT.
20 CHB Power C-Phase High-Side Bootstrap Supply
External bootstrap capacitor is required.
Connect the bootstrap capacitor between this pin and CHS.
Connect to the anode of the external bootstrap diode.
22 BHS — B-Phase High-Side Drive Return Connection
Connect to the emitter or source of the external high-side power device.
Connect the bootstrap capacitor between this pin and the BHB pin.
23 BHO OUT B-Phase High-Side Drive Output
Connect to the gate of the external high-side power MOSFET or IGBT.

DS20005531A-page 14  2016 Microchip Technology Inc.

 MIC4609
TABLE 3-1: PIN FUNCTION TABLE (CONTINUED)
SOICW-28LD Symbol I/O Description

24 BHB Power B-Phase High-Side Bootstrap Supply

External bootstrap capacitor is required.
Connect the bootstrap capacitor between this pin and BHS.
Connect to the anode of the external bootstrap diode.
26 AHS — A-Phase High-Side Drive Return Connection
Connect to the emitter or source of the external high-side power device.
Connect the bootstrap capacitor between this pin and the AHB pin.
27 AHO OUT A-Phase High-Side Drive Output
Connect to the gate of the external high-side power MOSFET or IGBT.
28 AHB Power A-Phase High-Side Bootstrap Supply
External bootstrap capacitor is required.
Connect the bootstrap capacitor between this pin and AHS.
Connect to the anode of the external bootstrap diode.

 2016 Microchip Technology Inc. DS20005531A-page 15

MIC4609
4.0 FUNCTIONAL DESCRIPTION The UVLO circuits are illustrated in the functional block
diagrams. The low-side UVLO circuit, Functional Block
The MIC4609 is a noninverting, 600V three-phase Diagram MIC4609 – Phase x Drive Circuit, monitors
IGBT/MOSFET driver designed to independently drive the voltage between the VDD and VSS pins. The circuit
six IGBTs or MOSFETs in a three-phase bridge. The keeps all the drivers off when VDD is less than the
MIC4609 offers a wide 10V-to-20V VDD operating UVLO threshold voltage.
supply range with six independent inputs (TTL or
The three high-side UVLO circuits, shown in Typical
3.3V CMOS compatible).
Application Circuit MIC4609 – 300V, 3-Phase Motor
The driver is comprised of six input buffers with Driver, monitor the voltage between the xHB and xHS
hysteresis, four independent UVLO circuits (three pins. The circuit keeps its respective high-side output
high-side monitoring the HB voltage and one low-side off when VHB - VHS is less than the UVLO threshold
monitoring the VDD voltage), and six output drivers. voltage.
The high-side output drivers utilize a high-speed
level-shifting circuit that is referenced to the HS pin. An 4.2 Startup and UVLO
overcurrent protection circuit turns off all outputs during
an overcurrent fault. The startup sequence is illustrated in Figure 4-1. As
VDD rises above an unspecified threshold, VT, the
4.1 UVLO Protection internal circuitry becomes active, the FAULT pin
asserts low and the UVLO circuitry begins to monitor
The UVLO circuits force the driver's outputs low until VDD. When the rising VDD reaches the UVLO
the supply voltage exceeds the UVLO threshold.
threshold, a current source begins charging the RCIN
Hysteresis in the UVLO circuits prevents system noise
pin's external capacitor until it reaches the RCIN delay
and finite circuit impedance from causing chatter during
threshold. The output drivers are enabled once the
turn-on.
RCIN threshold is reached and the EN pin is asserted
high.

UVLO Rising Level (VDDR)

UVLO Falling Level
VDD

EN
above VT
VDD rises

RCIN Delay Threshold

above threshold
RCIN rises

above threshold

RCIN
RCIN rises
above VDDR

EN rise enables
down all ckts.

VDD falls below

VDD rises

EN fall shuts

analog ckts.

threshold
UVLO
starts RCIN
UVLO fall

FAULT

UVLO
(Internal)
Normal Operation

FIGURE 4-1: Startup and Fault Timing Diagram.

DS20005531A-page 16  2016 Microchip Technology Inc.

 MIC4609
TABLE 4-1: OPERATIONAL TRUTH TABLE
ULVO (1, 2) Outputs (3, 4)
Condition xHI xLI EN HB ULVO VDD ULVO xHO xLO
Disabled X X L X X L L
VDD ULVO X X X X L L L
VHB ULVO X L or H H L H L L or H
H H H H L L
H H H L L
Switching L H H H H L H
H L H H H H L
L L H H H L L
Note 1: UVLO = H when VDD > UVLO threshold
2: UVLO = L when VDD < UVLO threshold
3: xHO and xLO remain low if both xHI and xLI are low when the VDD rises above the UVLO threshold or
when the EN pin is asserted high. Normal switching operation begins when one of the inputs changes
state from L to H.
4: Anti-shoot-through circuit prevents a high on both outputs simultaneously.

4.3 Enable Inputs

There is one external Enable pin that controls all three
phases. A logic high on the enable pin (EN) allows for
startup of all phases and normal operation. Conversely,
when a logic low is applied on the Enable pin, all
phases turn off and the device enters a low current
Shutdown mode. All outputs (xHO and xLO) are pulled
low when EN is low. The EN pin is internally pulled
down. Leaving the pin open disables the part.

 2016 Microchip Technology Inc. DS20005531A-page 17

MIC4609
4.4 Input Stage An internal pull-down resistor is connected to the
xHI and xLI pins. This pulls the driver output pins low if
The xHI and xLI pins are referenced to the COM pin the inputs are disconnected or left floating. A small
and have a CMOS/TTL compatible input range. The amount of hysteresis is programmed into the input to
input threshold voltage is independent of the prevent false triggering of the output. In addition, each
VDD supply. The input pin voltage must not exceed the input has a minimum pulse-width filter for additional
VDD pin voltage. The voltage state of the input signal(s) noise immunity protection. The input pulse width must
does not change the quiescent current draw of the exceed the tFLTR time before the outputs will change
driver. The input stage block diagram is shown in state. Refer to the Electrical Characteristics table and
Figure 4-2. Figure 4-3 for additional information.

Min PW Filter
xHI/xLI

FIGURE 4-2: Input Stage Block Diagram.

Input and output

tFLTR pulse widths (tPW) are equal

tPW1 tPW

xLI, xHI tPW > tFLTR

tPW1 < tFLTR tOFF

tFLTR

xLO, xHO tON

tPW

tFLTR
tFLTR tPW1
tPW

xLI, xHI tPW > tFLTR

tPW1 < tFLTR

tOFF

xLO, xHO tFLTR

tON

tPW

FIGURE 4-3: Minimum Pulse-Width Diagram.

DS20005531A-page 18  2016 Microchip Technology Inc.

 MIC4609
4.5 Dead Time and
Anti-Shoot-Through Protection
Shoot-through occurs when both the high and low-side
IGBTs/MOSFETs of a particular phase are ON at the
same time. The inputs of each phase use
anti-shoot-through circuitry to prevent this condition
from occurring. If both the HI and LI inputs of a phase
go high, both outputs (HO and LO) of that phase go low.
In addition to anti-shoot-through circuitry, a fixed
"dead-time" delay is added to the input-to-output
propagation delay. This allows the IGBTs/MOSFETs in
a particular phase to fully turn off before the other turns
on.

tR tF
90% 90%

10% 10%
xHI
xLI
tPW
50% 50%
VIL VIH
tOFF
xLO 90% tON

10%

90%
tD

tD
xHO 10%

FIGURE 4-4: Dead Time, Propagation Delay, and Rise/Fall-Time Diagram.

 2016 Microchip Technology Inc. DS20005531A-page 19

MIC4609
4.6 Low-Side Driver Output Stage 4.7 High-Side Driver and Bootstrap
The low-side driver, shown in Figure 4-5, is designed to
Circuit
drive an N-channel MOSFET or IGBT. The driver is The High-Side driver is designed to drive a floating
referenced to the COM pin, which can be floating with N-channel FET or IGBT, whose source/emitter terminal
respect to ground. The COM reference gives the gate is referenced to the HS pin. A simplified diagram of the
drive currents a return path without having to flow high-side driver section is shown in Figure 4-6.
through the current sense resistor.
Low driver impedances allow the external HV
DBST xHB
IGBT/MOSFET to be turned on and off quickly. The VDD
CB
rail-to-rail drive capability of the output ensures a
low VCE or RDSON from the external power device.
When driving the external IGBT on, the driver's internal
P-channel MOSFET is turned on and VDD is applied to
the gate of the external IGBT. To turn off the external Level xHO
IGBT, the driver's N-channel FET is turned on, which Shift
RG
discharges the external IGBT's gate.
xHS

VDD RHS
DCLAMP

xHS Node

FIGURE 4-6: High-Side Driver and

Bootstrap Circuit Block Diagram.
A low-power, high-speed, level-shifting circuit isolates
the low-side (VSS pin) referenced circuitry from the
xLO
high-side (xHS pin) referenced driver. Power to the
high-side driver and UVLO circuit is supplied by the
RG
bootstrap capacitor (CB) while the voltage level of the
xHS pin is shifted high.
The bootstrap circuit consists of an external diode,
DBST, and an external capacitor, CB. In a typical
application, such as the motor driver shown in
Figure 4-7 (Phase A illustrated only), the AHS pin is at
ground potential while the low-side MOSFET is ON.
COM The internal diode charges capacitor CB to VDD - VF
during this time (where VF is the forward voltage drop
FIGURE 4-5: Low-Side Driver Block of the internal diode). After the low-side MOSFET is
Diagram. turned off and the AHO pin turns on, the voltage across
capacitor CB is applied to the gate of the high-side
external MOSFET. As the high-side MOSFET turns on,
voltage on the AHS pin rises with the source of the
high-side MOSFET until it reaches VDD. As the AHS
and AHB pins rise, the internal diode is reverse biased,
preventing capacitor CB from discharging. During this
time, the high-side MOSFET is kept ON by the voltage
across capacitor CB.

DS20005531A-page 20  2016 Microchip Technology Inc.

 MIC4609

VIN
DBST
VIN

CB
AHB
VDD
CVDD

AHO RG Phase B
HI Level
shift
AHS RHS

M
Phase A
DCLAMP

LI
Phase C
ALO
RG

VSS COM

RSNS

FIGURE 4-7: MIC4609 Motor Driver Typical Application – Phase A.

4.8 Overcurrent Protection Circuitry

The MIC4609 provides overcurrent protection for the
3-phase bridge. It consists of:
• a comparator that senses the voltage across a
current-sense resistor
• a latch and timer that keep all gate drivers off
during a fault
• an open-drain FAULT pin that pulls low during the
fault.
Figure 4-8 illustrates the overcurrent protection
sequence. When an overcurrent condition is detected,
the FAULT pin is pulled low and a latch disables the
gate drive outputs for a time determined by the RCIN
pin capacitor. After the delay circuit times out, the latch
is reset, the FAULT pin is deasserted to a high
impedance state and the gate drive outputs are
re-enabled.

 2016 Microchip Technology Inc. DS20005531A-page 21

MIC4609

Blanking
Time

ISNS Threshold

below threshold
ISNS falls
ISNS
RCIN Threshold

RCIN
Normal Normal
OC Fault
Operation Operation

FAULT

FIGURE 4-8: Overcurrent Fault Sequence.

4.8.1 ISNS The delay time can be approximated by applying

Equation 4-1.
The ISNS pin may be used to monitor motor winding
currents. The measurement is referenced to the
VSS pin and can sense the voltage across a low-side EQUATION 4-1:
current sense resistor or it may be connected to a C RCIN  VRCIN+
current sense transformer. The current sense resistor t DLY = -----------------------------------------
I RCIN
is typically connected between the source pins
(MOSFET) or emitter pins (IGBT) of all three low-side
Where:
switches and power ground.
CRCIN = External capacitance on the RCIN pin
If the peak voltage on the ISNS pin exceeds the VISNS
threshold, it will cause all six outputs to latch off. A IRCIN = RCIN pin current source
blanking circuit on the ISNS comparator output (typically 0.44 µA)
prevents noise from falsely tripping the overcurrent VRCIN+ = Internal comparator threshold
circuit. The ISNS pin is internally pulled down to VSS
but may be externally connected to VSS ground for 4.8.3 FAULT
improved noise immunity if the overcurrent feature is
not used. This open-drain output is asserted low for an
overcurrent condition or when the VDD voltage is below
4.8.2 RCIN the UVLO threshold. It will de-assert to a
high-impedance state once the VDD rises above the
A capacitor connected to the RCIN pin determines the
UVLO threshold or when the RCIN pin voltage has
amount of time the gate drive outputs are latched off
reached the VRCIN+ threshold. During normal
before they can be restarted.
operation, the internal pull-down MOSFET of the pin is
During normal operation, the RCIN pin is internally high impedance. A pull-up resistor must be connected
pulled low. Once an overcurrent condition is detected, to this pin.
the RCIN pin capacitor is charged up by an internal
current source until the voltage reaches the
VRCIN+ threshold and the latch is reset. The outputs are
then enabled.

DS20005531A-page 22  2016 Microchip Technology Inc.

 MIC4609
5.0 APPLICATION INFORMATION Typical leakage currents for the bootstrap capacitor
and IGBT/MOSFET are in the 100 nA range. The
MIC4609 HS-pin-to-driver leakage current is generally
5.1 Bootstrap Circuit
higher with typical values in the 1 µA range (or higher
The high-side gate drive cannot be operated at high junction temperature and voltage). The
continuously (100% duty cycle). It must be periodically minimum value of bootstrap capacitor that prevents an
turned off to refresh/recharge the bootstrap capacitor, excessive drop in the gate drive voltage to the
CB. There are two separate requirements to consider high-side switch is calculated as per Equation 5-2.
when choosing the bootstrap capacitor value:
• IGBT or MOSFET gate charge EQUATION 5-2:
• Duration of the high-side switch on-time tON  I discharge
C B  -----------------------------------
The high-side bootstrap circuit for Phase A is illustrated V HB
in Figure 5-1. Where:
tON = Maximum ON-time of the high-side
DBST switch
VIN
VHB = Voltage drop at the HB pin
CVDD *RHB CB
AHB *RCB Idischarge = Total discharge current at the HB pin
VDD
(capacitor, IGBT/MOSFET, and HB
pin)
AHI Level AHO RG
shift Resistors RHB and RCB can be used to reduce the peak
AHS
RHS CB charge current or modify the high-side
IGBT/MOSFET turn-on time. This helps reduce noise
DCLAMP and EMI as well as ripple on the VDD pin.

ALI
The resistor in series with the HB pin, RHB, controls the
ALO
turn-on time of the high-side switch by limiting the
RG
charge current into the gate.
Adding a resistor in series with capacitor CB will reduce
COM
the peak charging current drawn through diode DBST. It
has some effect on slowing down the high-side switch
turn-on time, however, it is not as effective as resistor
* Optional Components RHB since charging current also comes from VDD until
the high-side switch starts to turn on and raise the
FIGURE 5-1: MIC4609 – Bootstrap Circuit. voltage on the HB node.
The bootstrap capacitor voltage drops each time it
delivers charge to turn on the IGBT. The voltage drop 5.2 HS Node Clamp
depends on the gate charge required by the IGBT. Most
A resistor/diode clamp between the switching node and
IGBT and MOSFET specifications contain gate charge
the HS pin is recommended to minimize large negative
versus VGE or VGS voltage information or graphs.
glitches or pulses on the HS pin.
Based on this information and a recommended VHB of
0.1V to 0.5V, the minimum value of bootstrap As shown in Figure 5-2, the high-side and low-side
capacitance is calculated by applying Equation 5-1. IGBTs turn on and off to regulate motor speed. During
the on-time, when the high-side IGBT is conducting,
EQUATION 5-1: current flows into the motor. After the high-side IGBT
turns off, and before the low-side IGBT turns on, there
Q GATE
C B  ----------------- is a brief period of time (dead time) that prevents both
V HB IGBTs from being ON at the same time. During the
Where: dead time, current from the motor flows through the
QGATE = Total gate charge at VHB diode in parallel with the low-side IGBT. Depending on
the diode characteristics (VF and turn-on time), the
VHB = Voltage drop at the HB pin
motor current and circuit parasitics, the initial negative
After the high-side switch has turned on, the bootstrap voltage on the switch node can be several volts or
capacitor will continue to discharge due to leakage more.
currents in the bootstrap capacitor, the IGBT/MOSFET Even though the HS pin is rated for negative voltage, it
gate-to-source and the driver (HS-pin-to-ground is good practice to clamp the HS pin with a resistor and
leakage). diode to prevent excessive negative voltage from
damaging the driver. Depending on the application and

 2016 Microchip Technology Inc. DS20005531A-page 23

MIC4609
amount of negative voltage on the switch node, a 1A
fast recovery diode and a minimum 10 resistor are DBST CB
recommended. A higher current diode and/or larger VIN
values of resistance can be used if necessary. AHB External
VDD
Adding a series resistor in the switch node limits the IGBT

peak high-side driver current, which affects the

CGC
switching speed of the high-side driver. The resistor, in RON

series with the HO pin, may be reduced to help

compensate for the extra HS pin resistance. AHO

RG RG_INT
DBST
VIN ROFF CGE
CB
VDD AHB
CVDD AHS RHS
DCLAMP
AHI Level AHO RG
shift
AHS RHS VNEG

10W
DCLAMP FIGURE 5-3: MIC4609 High-Side Driving
ALI an External IGBT.
ALO R M
G

5.3.2 DISSIPATION DURING THE

COM
EXTERNAL IGBT/MOSFET
TURN-ON
Energy from capacitor CB is used to charge up the input
FIGURE 5-2: Negative HS Pin Voltage.
capacitance of the IGBT (CGE and CGC). The energy
delivered to the gate is dissipated in the three resistive
5.3 Power Dissipation Considerations components, RON, RG and RG_INT. RG is the series
Power dissipation in the driver can be separated into resistor between the driver output and the IGBT. RG_INT
two areas: is the gate resistance of the IGBT. RG_INT is usually
• Gate driver dissipation listed in the IGBT or MOSFET specifications. The ESR
• Quiescent current dissipation used to supply the of capacitor CB and the resistance of the connecting
internal logic and control functions etch can be ignored since they are much less than RON
and RG_INT.
5.3.1 GATE DRIVER POWER The effective capacitances of CGE and CGC are difficult
DISSIPATION to calculate because they vary nonlinearly with IC, VGE,
Power dissipation in the output driver stage is mainly and VCE. Most power IGBT and MOSFET
caused by charging and discharging the specifications include a graph of total gate charge
gate-to-emitter and gate-to-collector capacitance of the versus VGE. Figure 5-4 shows a typical gate charge
external IGBT. Figure 5-3 shows a simplified equivalent curve for an arbitrary IGBT. The chart shows that for a
circuit of the MIC4609 driving an external
gate voltage of 12V, the IGBT requires 12 nC of charge.
high-side IGBT.

20
VGE, Gate-to-Emitter Voltage

16

12
(V)

0
0 4 8 12 16
QG, Total Gate Charge (nC)

FIGURE 5-4: Typical Gate Charge vs. VGE.

DS20005531A-page 24  2016 Microchip Technology Inc.

 MIC4609
The power dissipated by the resistive components of Letting RON = ROFF, the power dissipated in the
the gate drive circuit during turn-on is calculated as individual driver output in the IC is calculated as shown
shown in Equation 5-3. in Equation 5-4:

EQUATION 5-3: EQUATION 5-4:

PDRIVER = Q G  V GE  f S  D R ON
P DISS = P DRIVER  -------------------------------------------------
Where: RON + RG + RG_INT

PDRIVER (1) = Average drive circuit power due to

The total power dissipated in the MIC4609, due to
switching
switching, is equal to the sum of all six driver
QG = Total gate charge at VGE dissipations.
VGE = Gate-to-emitter voltage on the
IGBT 5.3.3 SUPPLY CURRENT POWER
fS = Switching frequency of the gate DISSIPATION
drive circuit Power is dissipated in the MIC4609 even if nothing is
D (2)
= Operating duty cycle of the driver being driven. The supply current is drawn by the bias
output for the internal circuitry, the level shifting circuitry, and
shoot-through current in the output drivers. The supply
Note 1: PDRIVER is the power dissipated by the
current is proportional to the operating frequency and
individual driver for one of the six gate
the VDD and VHB voltages. Figures 2-9 and 2-10 show
drive outputs.
how supply current varies with switching frequency and
2: Operating duty cycle is the percentage of supply voltage.
time that particular driver output is
switching during one rotation of the The power dissipated by the MIC4609 due to supply
motor. current is calculated by applying Equation 5-5.

The power dissipated by each of the internal gate EQUATION 5-5:

drivers (high-side or low-side) is equal to the ratio of PDISS_SUPPLY = V DD  I DD  VHB  I HB
RON and ROFF to the external resistive losses in RG
and RG_INT.
5.3.4 TOTAL POWER DISSIPATION AND
THERMAL CONSIDERATIONS
Total power dissipation in the MIC4609 is equal to the
power dissipation caused by driving the external IGBTs
and the supply current. Equation 5-6 shows this
relation.

EQUATION 5-6:
P DISS_TOTAL = P DISS_SUPPLY +  PDISS_DRIVERS

The die temperature can be calculated after the total

power dissipation is determined as shown in
Equation 5-7.

EQUATION 5-7:
T J = T A + P DISS_TOTAL   JA
Where:
TA = Maximum ambient temperature (°C)
TJ = Junction temperature (°C)
PDISS_TOTAL = MIC4609 power dissipation (W)
JA = Thermal resistance from
junction-to-ambient air (°C/W)

 2016 Microchip Technology Inc. DS20005531A-page 25

MIC4609
5.3.5 OTHER TIMING CONSIDERATIONS 5.5 Grounding, Component
Make sure the input signal pulse width is greater than Placement and Circuit Layout
the minimum specified pulse width. An input signal that
Nanosecond switching speeds and high-peak currents
is less than the minimum pulse width may result in no
in and around the MIC4609 driver requires proper
output pulse or an output pulse whose width is
placement and trace routing of all components.
significantly less than the input.
Improper placement may cause degraded noise
The maximum duty cycle (ratio of high-side on-time to immunity, false switching, excessive ringing, or circuit
switching period) is controlled by the minimum pulse latch-up.
width of the low side and by the time required for the CB
Figure 5-5 shows the critical current paths when the
capacitors to charge during the off-time. Adequate time
driver outputs go high and turn on the external IGBTs.
must be allowed for the CB capacitor to charge up
It also helps demonstrate the need for a low impedance
before the high-side driver is turned on.
ground plane. Charge needed to turn on the IGBT
gates comes from the decoupling capacitors CVDD and
5.4 Decoupling Capacitor Selection CB. Current in the low-side gate driver flows from CVDD
Decoupling capacitors are required on the VDD pin to through the internal driver, into the IGBT gate, and out
supply the charge necessary to drive the external the emitter. The return connection back to the
IGBTs or MOSFETs and also to minimize the voltage decoupling capacitor is made through the ground
ripple on these pins. The VDD pin decoupling capacitor plane. Any inductance or resistance in the ground
supplies the transient current for all six drivers return path causes a voltage spike or ringing to appear
(three high-side and three low-side). The minimum on the emitter of the IGBT. This voltage works against
recommended VDD capacitance should be greater than the gate drive voltage and can either slow down or turn
the sum of all three CB capacitors with a minimum 1 µF off the IGBT during the period when it should be turned
ceramic capacitor regardless of CB value. on.

Ceramic capacitors are recommended because of their Current in the high-side driver is sourced from
low impedance and small size. Z5U-type ceramic capacitor CB and flows into the HB pin and out the HO
capacitor dielectrics should not be used due to the pin, into the gate of the high-side IGBT. The return path
large change in capacitance over temperature and for the current is from the emitter of the IGBT and back
voltage. Larger IGBTs/MOSFETs and low-switching to capacitor CB. The high-side circuit return path
frequencies may require larger capacitance values for usually does not have a low-impedance ground plane
proper operation. The voltage rating of the capacitors so the etch connections in this critical path should be
depends on the supply voltage, ambient temperature short and wide to minimize parasitic inductance. As
and the voltage derating used for reliability. with the low-side circuit, impedance between the
25V-rated X5R or X7R ceramic capacitors are IGBT emitter and the decoupling capacitor causes
recommended for most applications. The minimum negative voltage feedback that fights the turn-on of the
capacitance value should be increased if low voltage IGBT.
capacitors are used because even good quality It is important to note that capacitor CB must be placed
dielectric capacitors, such as X5R, will lose 40% to close to the HB and HS pins. This capacitor not only
70% of their capacitance value at the rated voltage. provides the current for turn-on but it must also keep
Placement of the decoupling capacitors is critical. The HB pin noise and ripple low for proper operation of the
bypass capacitor for VDD should be placed as close as high-side drive circuitry.
possible between the VDD pin and the ground plane.
The bypass capacitor (CB) for the HB supply pin must LOW-SIDE DRIVE TURN-ON HS Node
CURRENT PATH
be located as close as possible between the HB and
HS pins. The etch connections must be short, wide, VDD xLO

and direct. The use of a ground plane to minimize CVDD

GND
connection impedance is recommended. VIN
plane
xHB
VSS

GND
xHO plane
xLI

CB Level
xHS shift
HS Node xHI

HIGH-SIDE DRIVE TURN-ON

CURRENT PATH

FIGURE 5-5: Turn-On Current Paths.

DS20005531A-page 26  2016 Microchip Technology Inc.

 MIC4609
Figure 5-5 shows the critical current paths when the
driver outputs go low and turn off the external IGBTs.
Short, low-impedance connections are important
during turn-off for the same reasons given in the
turn-on explanation. Current flowing through the
internal diode replenishes charge in the bootstrap
capacitor, CB.

LOW-SIDE DRIVE TURN-OFF HS Node

CURRENT PATH

VDD xLO

CVDD
GND
xHB
plane
VIN
VSS
GND
xHO plane
xLI

CB Level
HS Node xHS shift
xHI

HIGH-SIDE DRIVE TURN-OFF

CURRENT PATH

FIGURE 5-6: Turn-Off Current Paths.

It is highly recommended to use a ground plane to
minimize parasitic inductance and impedance of the
return paths. The MIC4609 is capable of greater than
1A peak currents and any impedance between the
MIC4609, the decoupling capacitors, and the external
IGBTs/MOSFETs will degrade the performance of the
driver.

 2016 Microchip Technology Inc. DS20005531A-page 27

MIC4609
6.0 PACKAGING INFORMATION

DS20005531A-page 28  2016 Microchip Technology Inc.

 MIC4609
APPENDIX A: REVISION HISTORY

Revision A (March 2016)

• Original release of this document.

 2016 Microchip Technology Inc. DS20005531A-page 29

MIC4609
NOTES:

DS20005531A-page 30  2016 Microchip Technology Inc.

 MIC4609
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.

PART NO. X XX –X (1) Examples:

a) MIC4609YWM-TR: 600V 3-Phase MOSFET/IGBT Driver,
Device Lead Finish Package Code Tape and Reel 7.52 mm body,
Option 28LD SOIC Wide package,
Tape and Reel
Device: MIC4609: 600V 3-Phase MOSFET/IGBT Driver

Lead Finish: Y = Pb-Free with Industrial Temperature

Grade Note 1: Tape and Reel identifier only appears in the catalog
part number description. This identifier is used for
ordering purposes and is not printed on the device
Package Code: WM = Plastic Small Outline, 7.52 mm Body, package. Check with your Microchip Sales Office for
28-Lead SOIC Wide Package package availability with the Tape and Reel option.

 2016 Microchip Technology Inc. DS20005531A-page 31

MIC4609
NOTES:

DS20005531A-page 32  2016 Microchip Technology Inc.

Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device Trademarks

applications and the like is provided only for your convenience The Microchip name and logo, the Microchip logo, AnyRate,
and may be superseded by updates. It is your responsibility to
dsPIC, FlashFlex, flexPWR, Heldo, JukeBlox, KeeLoq,
ensure that your application meets with your specifications.
KeeLoq logo, Kleer, LANCheck, LINK MD, MediaLB, MOST,
MICROCHIP MAKES NO REPRESENTATIONS OR
MOST logo, MPLAB, OptoLyzer, PIC, PICSTART, PIC32 logo,
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
RightTouch, SpyNIC, SST, SST Logo, SuperFlash and UNI/O
IMPLIED, WRITTEN OR ORAL, STATUTORY OR are registered trademarks of Microchip Technology
OTHERWISE, RELATED TO THE INFORMATION, Incorporated in the U.S.A. and other countries.
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR ClockWorks, The Embedded Control Solutions Company,
FITNESS FOR PURPOSE. Microchip disclaims all liability ETHERSYNCH, Hyper Speed Control, HyperLight Load,
arising from this information and its use. Use of Microchip IntelliMOS, mTouch, Precision Edge, and QUIET-WIRE are
devices in life support and/or safety applications is entirely at registered trademarks of Microchip Technology Incorporated
the buyer’s risk, and the buyer agrees to defend, indemnify and in the U.S.A.
hold harmless Microchip from any and all damages, claims, Analog-for-the-Digital Age, Any Capacitor, AnyIn, AnyOut,
suits, or expenses resulting from such use. No licenses are BodyCom, chipKIT, chipKIT logo, CodeGuard, dsPICDEM,
conveyed, implicitly or otherwise, under any Microchip dsPICDEM.net, Dynamic Average Matching, DAM, ECAN,
intellectual property rights unless otherwise stated. EtherGREEN, In-Circuit Serial Programming, ICSP, Inter-Chip
Connectivity, JitterBlocker, KleerNet, KleerNet logo, MiWi,
motorBench, MPASM, MPF, MPLAB Certified logo, MPLIB,
MPLINK, MultiTRAK, NetDetach, Omniscient Code
Generation, PICDEM, PICDEM.net, PICkit, PICtail,
PureSilicon, RightTouch logo, REAL ICE, Ripple Blocker,
Serial Quad I/O, SQI, SuperSwitcher, SuperSwitcher II, Total
Endurance, TSHARC, USBCheck, VariSense, ViewSpan,
WiperLock, Wireless DNA, and ZENA are trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and Silicon Storage Technology is a registered trademark of
Tempe, Arizona; Gresham, Oregon and design centers in California Microchip Technology Inc. in other countries.
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping GestIC is a registered trademarks of Microchip Technology
devices, Serial EEPROMs, microperipherals, nonvolatile memory and Germany II GmbH & Co. KG, a subsidiary of Microchip
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified. Technology Inc., in other countries.
All other trademarks mentioned herein are property of their
respective companies.
QUALITY MANAGEMENT SYSTEM © 2016, Microchip Technology Incorporated, Printed in the
CERTIFIED BY DNV U.S.A., All Rights Reserved.
ISBN: 978-1-5224-0438-5
== ISO/TS 16949 ==

 2016 Microchip Technology Inc. DS20005531A-page 33

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07/14/15

DS20000000A-page 34  2016 Microchip Technology Inc.