Introduction of Sequential Circuits

Sequential circuit is a combinational logic circuit that consists of inputs variable

(X), logic gates (Computational circuit), and output variable (Z).

A combinational circuit produces an output based on input variables only, but

a sequential circuit produces an output based on current input and previous
output variables. That means sequential circuits include memory elements that are
capable of storing binary information. That binary information defines the state of
the sequential circuit at that time. A latch capable of storing one bit of information.

As shown in the figure, there are two types of input to the combinational logic :
1. External inputs which are not controlled by the circuit.
2. Internal inputs, which are a function of a previous output state.
Secondary inputs are state variables produced by the storage elements, whereas
secondary outputs are excitations for the storage elements.
Types of Sequential Circuits:
There are two types of sequential circuits:
Type 1: Asynchronous sequential circuit: These circuits do not use a clock
signal but uses the pulses of the inputs. These circuits are faster than synchronous
sequential circuits because there is clock pulse and change their state immediately
when there is a change in the input signal. We use asynchronous sequential circuits
when speed of operation is important and independent of internal clock pulse.

But these circuits are more difficult to design and their output is uncertain.

Type2: Synchronous sequential circuit: These circuits uses clock signal and level
inputs (or pulsed) (with restrictions on pulse width and circuit propagation). The
output pulse is the same duration as the clock pulse for the clocked sequential
circuits. Since they wait for the next clock pulse to arrive to perform the next
operation, so these circuits are bit slower compared to asynchronous. Level output
changes state at the start of an input pulse and remains in that until the next input
or clock pulse.

We use synchronous sequential circuit in synchronous counters, flip flops, and in

the design of MOORE-MEALY state management machines. We use sequential
circuits to design Counters, Registers, RAM, MOORE/MEALY Machine and other
state retaining machines.

Flip Flop
Flip flop is a sequential circuit which generally samples its inputs and changes its
outputs only at particular instants of time and not continuously. Flip flop is said to be
edge sensitive or edge triggered rather than being level triggered like latches.
S-R Flip Flop
It is basically S-R latch using NAND gates with an additional enable input. It is also
called as level triggered SR-FF. For this, circuit in output will take place if and only if the
enable input (E) is made active. In short this circuit will operate as an S-R latch if E = 1
but there is no change in the output if E = 0.

Block Diagram

Circuit Diagram

Truth Table
Operation
S.N. Condition Operation

1 S = R = 0 : No change
If S = R = 0 then output of NAND gates 3 and 4 are
forced to become 1.
Hence R' and S' both will be equal to 1. Since S' and R'
are the input of the basic S-R latch using NAND gates,
there will be no change in the state of outputs.

2 S = 0, R = 1, E = 1
Since S = 0, output of NAND-3 i.e. R' = 1 and E = 1 the
output of NAND-4 i.e. S' = 0.
Hence Qn+1 = 0 and Qn+1 bar = 1. This is reset condition.

3 S = 1, R = 0, E = 1
Output of NAND-3 i.e. R' = 0 and output of NAND-4 i.e.
S' = 1.
Hence output of S-R NAND latch is Qn+1 = 1 and Qn+1 bar
= 0. This is the reset condition.

4 S = 1, R = 1, E = 1
As S = 1, R = 1 and E = 1, the output of NAND gates 3
and 4 both are 0 i.e. S' = R' = 0.
Hence the Race condition will occur in the basic NAND
latch.

Master Slave JK Flip Flop

Master slave JK FF is a cascade of two S-R FF with feedback from the output of second
to input of first. Master is a positive level triggered. But due to the presence of the
inverter in the clock line, the slave will respond to the negative level. Hence when the
clock = 1 (positive level) the master is active and the slave is inactive. Whereas when
clock = 0 (low level) the slave is active and master is inactive.
Circuit Diagram

Truth Table

Operation
S.N. Condition Operation

1 J = K = 0 (No change)
When clock = 0, the slave becomes active and master is
inactive. But since the S and R inputs have not changed,
the slave outputs will also remain unchanged. Therefore
outputs will not change if J = K =0.

2 J = 0 and K = 1 (Reset)
Clock = 1 − Master active, slave inactive. Therefore
outputs of the master become Q1 = 0 and Q1 bar = 1.
That means S = 0 and R =1.
Clock = 0 − Slave active, master inactive. Therefore
outputs of the slave become Q = 0 and Q bar = 1.
 Again clock = 1 − Master active, slave inactive. Therefore
even with the changed outputs Q = 0 and Q bar = 1 fed
back to master, its output will be Q1 = 0 and Q1 bar = 1.
That means S = 0 and R = 1.
Hence with clock = 0 and slave becoming active the
outputs of slave will remain Q = 0 and Q bar = 1. Thus
we get a stable output from the Master slave.

3 J = 1 and K = 0 (Set)
Clock = 1 − Master active, slave inactive. Therefore
outputs of the master become Q1 = 1 and Q1 bar = 0.
That means S = 1 and R =0.
Clock = 0 − Slave active, master inactive. Therefore
outputs of the slave become Q = 1 and Q bar = 0.
Again clock = 1 − then it can be shown that the outputs
of the slave are stabilized to Q = 1 and Q bar = 0.

4 J = K = 1 (Toggle)
Clock = 1 − Master active, slave inactive. Outputs of
master will toggle. So S and R also will be inverted.
Clock = 0 − Slave active, master inactive. Outputs of
slave will toggle.
These changed output are returned back to the master
inputs. But since clock = 0, the master is still inactive. So
it does not respond to these changed outputs. This
avoids the multiple toggling which leads to the race
around condition. The master slave flip flop will avoid
the race around condition.

Delay Flip Flop / D Flip Flop

Delay Flip Flop or D Flip Flop is the simple gated S-R latch with a NAND inverter
connected between S and R inputs. It has only one input. The input data is appearing at
the output after some time. Due to this data delay between i/p and o/p, it is called delay
flip flop. S and R will be the complements of each other due to NAND inverter. Hence S
= R = 0 or S = R = 1, these input condition will never appear. This problem is avoid by
SR = 00 and SR = 1 conditions.
Block Diagram

Circuit Diagram

Truth Table

Operation
S.N. Condition Operation

1 E=0
Latch is disabled. Hence no change in output.

2 E = 1 and D = 0
If E = 1 and D = 0 then S = 0 and R = 1. Hence irrespective of
the present state, the next state is Qn+1 = 0 and Qn+1 bar = 1. This
is the reset condition.
 3 E = 1 and D = 1
If E = 1 and D = 1, then S = 1 and R = 0. This will set the latch
and Qn+1 = 1 and Qn+1 bar = 0 irrespective of the present state.

Toggle Flip Flop / T Flip Flop

Toggle flip flop is basically a JK flip flop with J and K terminals permanently connected
together. It has only input denoted by T as shown in the Symbol Diagram. The symbol
for positive edge triggered T flip flop is shown in the Block Diagram.

Symbol Diagram

Block Diagram

Truth Table

Operation
S.N. Condition Operation
 1 T = 0, J = K = 0 The output Q and Q bar won't change

2 T = 1, J = K = 1 Output will toggle corresponding to every leading edge of clock

signal.

Different Classes of CPU Registers

In Computer Architecture, the Registers are very fast computer memory which
are used to execute programs and operations efficiently. This does by giving
access to commonly used values, i.e., the values which are in the point of
operation/execution at that time. So, for this purpose, there are several different
classes of CPU registers which works in coordination with the computer
memory to run operations efficiently.
The sole purpose of having register is fast retrieval of data for processing by
CPU. Though accessing instructions from RAM is comparatively faster with
hard drive, it still isn’t enough for CPU. For even better processing, there are
memories in CPU which can get data from RAM which are about to be executed
beforehand. After registers we have cache memory, which are faster but less
faster than registers.
These are classified as given below.

 Accumulator:
This is the most frequently used register used to store data taken from
memory. It is in different numbers in different microprocessors.

 Memory Address Registers (MAR):

It holds the address of the location to be accessed from memory. MAR
and MDR (Memory Data Register) together facilitate the
communication of the CPU and the main memory.

 Memory Data Registers (MDR):

It contains data to be written into or to be read out from the addressed
location.

 General Purpose Registers:

These are numbered as R0, R1, R2….Rn-1, and used to store
temporary data during any ongoing operation. Its content can be
accessed by assembly programming. Modern CPU architectures tends
to use more GPR so that register-to-register addressing can be used
more, which is comparatively faster than other addressing modes.

 Program Counter (PC):

Program Counter (PC) is used to keep the track of execution of the
program. It contains the memory address of the next instruction to be
fetched. PC points to the address of the next instruction to be fetched
from the main memory when the previous instruction has been
successfully completed. Program Counter (PC) also functions to count
the number of instructions. The incrementation of PC depends on the
type of architecture being used. If we are using 32-bit architecture, the
PC gets incremented by 4 every time to fetch the next instruction.

 Instruction Register (IR):

The IR holds the instruction which is just about to be executed. The
instruction from PC is fetched and stored in IR. As soon as the
instruction in placed in IR, the CPU starts executing the instruction and
the PC points to the next instruction to be executed.

So, these are the different registers which are operating for a specific purpose.
System Bus in Computer Architecture
Computer Organization and Architecture

System Bus in Computer Architecture-

What Is A System Bus?

 A bus is a set of electrical wires (lines) that connects the various hardware components
of a computer system.
 It works as a communication pathway through which information flows from one
hardware component to the other hardware component.

A bus that connects major components (CPU, memory and I/O devices) of a computer system is called as
a System Bus.

Why Do We Need Bus?

 A computer system is made of different components such as memory, ALU, registers

etc.
 Each component should be able to communicate with other for proper execution of
instructions and information flow.
 If we try to implement a mesh topology among different components, it would be really
expensive.
 So, we use a common component to connect each necessary component i.e. BUS.
Components Of A System Bus-

The system bus consists of three major components-

1. Data Bus
2. Address Bus
3. Control Bus

Let us learn about each component one by one.

1) Data Bus-
  As the name suggests, data bus is used for transmitting the data / instruction from CPU
to memory/IO and vice-versa.
 It is bi-directional.

Data Bus Width

 The width of a data bus refers to the number of bits (electrical wires) that the bus can carry at a
time.
 Each line carries 1 bit at a time. So, the number of lines in data bus determine how many bits can be
transferred parallely.
 The width of data bus is an important parameter because it determines how much data can be
transmitted at one time.
 The wider the bus width, faster would be the data flow on the data bus and thus better would be
the system performance.

Examples-
 A 32-bit bus has thirty two (32) wires and thus can transmit 32 bits of data at a time.
 A 64-bit bus has sixty four (64) wires and thus can transmit 64 bits of data at a time.

2) Control Bus-

 As the name suggests, control bus is used to transfer the control and timing signals from
one component to the other component.
 The CPU uses control bus to communicate with the devices that are connected to the
computer system.
 The CPU transmits different types of control signals to the system components.
 It is bi-directional.

What Are Control & Timing Signals?

Control signals are generated in the control unit of CPU.

Timing signals are used to synchronize the memory and I/O operations with a CPU
clock.

Typical control signals hold by control bus-

  Memory read – Data from memory address location to be placed on data bus.
 Memory write – Data from data bus to be placed on memory address location.
 I/O Read – Data from I/O address location to be placed on data bus.
 I/O Write – Data from data bus to be placed on I/O address location.

Other control signals hold by control bus are interrupt, interrupt acknowledge, bus
request, bus grant and several others.
The type of action taking place on the system bus is indicated by these control signals.

Example-

When CPU wants to read or write data, it sends the memory read or memory write
control signal on the control bus to perform the memory read or write operation from the
main memory. Similarly, when the processor wants to read from an I/O device, it
generates the I/O read signal.

3) Address Bus-

 As the name suggests, address bus is used to carry address from CPU to memory/IO
devices.
 It is used to identify the particular location in memory.
 It carries the source or destination address of data i.e. where to store or from where to
retrieve the data.
 It is uni-directional.

Example-

When CPU wants to read or write data, it sends the memory read or memory write
control signal on the control bus to perform the memory read or write operation from the
main memory and the address of the memory location is sent on the address bus.
If CPU wants to read data stored at the memory location (address) 4, the CPU send the
value 4 in binary on the address bus.
 Address Bus Width

 The width of address bus determines the amount of physical memory addressable by the processor.
 In other words, it determines the size of the memory that the computer can use.
 The wider is the address bus, the more memory a computer will be able to use.
 The addressing capacity of the system can be increased by adding more address lines.

Examples-
 An address bus that consists of 16 wires can convey 2 16 (= 64K) different addresses.
 An address bus that consists of 32 wires can convey 2 32 (= 4G) different addresses.

Difference between Single Bus Structure

and Double Bus Structure
1. Single Bus Structure: In a single bus structure, one common bus is used to
communicate between peripherals and microprocessors. It has disadvantages due
to the use of one common bus.

2. Double Bus Structure: In a double bus structure, one bus is used to fetch
instructions while other is used to fetch data, required for execution. It is to
overcome the bottleneck of a single bus structure.
Differences between Single Bus and Double Bus Structure :
S.
No. Single Bus Structure Double Bus Structure

The same bus is shared by three

units (Memory, Processor, and The two independent buses link various units
1. I/O units). together.

One common bus is used for Two buses are used, one for communication
communication between from peripherals and the other for the
2. peripherals and processors. processor.

Here, the I/O bus is used to connect I/O units

The same memory address space and processor and other one, memory bus is
3. is utilized by I/O units. used to connect memory and processor.

Instructions and data both are Instructions and data both are transferred in
4. transferred in same bus. different buses.
 S.
No. Single Bus Structure Double Bus Structure

5. Its performance is low. Its performance is high.

The cost of a single bus structure

6. is low. The cost of a double bus structure is high.

Number of cycles for execution is

7. more. Number of cycles for execution is less.

8. Execution of the process is slow. Execution of the process is fast.

Number of registers associated

9. are less. Number of registers associated are more.

At a time single operand can be

10. read from the bus. At a time two operands can be read.

Advantages- Advantages-
 Less expensive  Better performance
11.  Simplicity  Improves Efficiency

What are Instruction Formats?

Instruction : A statement that tells a computer to do something.

Instruction Format:The way an instruction is written.
An instruction in a computer comprises of groups called fields.The most common fields are:
1. Operation Field

 Opcode
 Specifies the operation to be performed by the instruction
Eg:ADD,SUB,MOV,etc.
  It can be a value or register number on which the operation is performed.
 Mandatory part of every instruction.
2. Address Field
 Adress of operand/Operand Reference
 Refers to a location (address) where the operand is stored.
 The address may be a memory address or a register address.

The format of an instruction is usually depicted in a rectangular box symbolizing the bits of the
instruction as they appear in memory words or in a control register. The bits of the instruction are
divided into groups called fields.
The most common fields found in instruction formats are:
1 An operation code field that specifies the operation to be performed.
2. An address field that designates a memory address or a processor registers.
3. A mode field that specifies the way the operand or the effective address is determined. Other special
fields are sometimes employed under certain circumstances, as for example a field that gives the
number of shifts in a shift-type instruction.

OPCODE Address Mode

A computer performs a task based on the instruction provided. Instruction

in computers comprises groups called fields. These fields contain different
information as for computers everything is in 0 and 1 so each field has different
significance based on which a CPU decides what to perform. The most
common fields are:
 Operation field specifies the operation to be performed like addition.
 Address field which contains the location of the operand, i.e., register
or memory location.
 Mode field which specifies how operand is to be founded.
Instruction is of variable length depending upon the number of addresses it
contains. Generally, CPU organization is of three types based on the number of
address fields:
1. Single Accumulator organization
2. General register organization
 3. Stack organization
In the first organization, the operation is done involving a special register called
the accumulator. In second on multiple registers are used for the computation
purpose. In the third organization the work on stack basis operation due to
which it does not contain any address field. Only a single organization doesn’t
need to be applied, a blend of various organizations is mostly what we see
generally.
Based on the number of address, instructions are classified as:
Note that we will use X = (A+B)*(C+D) expression to showcase the procedure.

1. Zero Address Instructions –

A stack-based computer does not use the address field in the instruction. To
evaluate an expression first it is converted to reverse Polish Notation i.e. Postfix
Notation.
Expression: X = (A+B)*(C+D)
Postfixed : X = AB+CD+*
TOP means top of stack
M[X] is any memory location
 PUSH A TOP = A

PUSH B TOP = B

ADD TOP = A+B

PUSH C TOP = C

PUSH D TOP = D

ADD TOP = C+D

MUL TOP = (C+D)*(A+B)

POP X M[X] = TOP

2 .One Address Instructions –

This uses an implied ACCUMULATOR register for data manipulation. One
operand is in the accumulator and the other is in the register or memory
location. Implied means that the CPU already knows that one operand is in the
accumulator so there is no need to specify it.

Expression: X = (A+B)*(C+D)
AC is accumulator
M[] is any memory location
M[T] is temporary location

LOAD A AC = M[A]

ADD B AC = AC + M[B]
 STORE T M[T] = AC

LOAD C AC = M[C]

ADD D AC = AC + M[D]

MUL T AC = AC * M[T]

STORE X M[X] = AC

3.Two Address Instructions –

This is common in commercial computers. Here two addresses can be specified
in the instruction. Unlike earlier in one address instruction, the result was stored
in the accumulator, here the result can be stored at different locations rather
than just accumulators, but require more number of bit to represent address.

Here destination address can also contain operand.

Expression: X = (A+B)*(C+D)
R1, R2 are registers
M[] is any memory location

MOV R1, A R1 = M[A]

ADD R1, B R1 = R1 + M[B]

MOV R2, C R2 = C

ADD R2, D R2 = R2 + D

MUL R1, R2 R1 = R1 * R2
 MOV X, R1 M[X] = R1

4.Three Address Instructions –

This has three address field to specify a register or a memory location. Program
created are much short in size but number of bits per instruction increase.
These instructions make creation of program much easier but it does not mean
that program will run much faster because now instruction only contain more
information but each micro operation (changing content of register, loading
address in address bus etc.) will be performed in one cycle only.

Expression: X = (A+B)*(C+D)
R1, R2 are registers
M[] is any memory location

ADD R1, A, B R1 = M[A] + M[B]

ADD R2, C, D R2 = M[C] + M[D]

MUL X, R1, R2 M[X] = R1 * R2

Instruction Cycle in Computer Architecture?

A program consisting of the memory unit of the computer includes a series of

instructions. The program is implemented on the computer by going through a cycle for
each instruction.
In the basic computer, each instruction cycle includes the following procedures −

 It can fetch instruction from memory.

 It is used to decode the instruction.
  It can read the effective address from memory if the instruction has an
indirect address.
 It can execute the instruction.
After the following four procedures are done, the control switches back to the first step
and repeats the similar process for the next instruction. Therefore, the cycle continues
until a Halt condition is met. The figure shows the phases contained in the instruction
cycle.

As display in the figure, the halt condition appears when the device receive turned off,
on the circumstance of unrecoverable errors, etc.

Fetch Cycle
The address instruction to be implemented is held at the program counter. The
processor fetches the instruction from the memory that is pointed by the PC.
Next, the PC is incremented to display the address of the next instruction. This
instruction is loaded onto the instruction register. The processor reads the instruction
and executes the important procedures.

Execute Cycle
The data transfer for implementation takes place in two methods are as follows −

 Processor-memory − The data sent from the processor to memory or from

memory to processor.
 Processor-Input/Output − The data can be transferred to or from a
peripheral device by the transfer between a processor and an I/O device.
In the execute cycle, the processor implements the important operations on the
information, and consistently the control calls for the modification in the sequence of
data implementation. These two methods associate and complete the execute cycle.

State Diagram for Instruction Cycle

The figure provides a large aspect of the instruction cycle of a basic computer, which is
in the design of a state diagram. For an instruction cycle, various states can be null,
while others can be visited more than once.

 Instruction Address Calculation − The address of the next instruction is

computed. A permanent number is inserted to the address of the earlier
instruction.
 Instruction Fetch − The instruction is read from its specific memory location
to the processor.
 Instruction Operation Decoding − The instruction is interpreted and the type
of operation to be implemented and the operand(s) to be used are decided.
 Operand Address Calculation − The address of the operand is evaluated if it
has a reference to an operand in memory or is applicable through the
Input/Output.
 Operand Fetch − The operand is read from the memory or the I/O.
 Data Operation − The actual operation that the instruction contains is
executed.
  Store Operands − It can store the result acquired in the memory or transfer it
to the I/O.

What is Addressing Modes:

The operation field of an instruction specifies the operation to be performed.And

this operation must be performed on some data.So each instruction need to specify
data on which the operation is to be performed.But the operand(data) may be in
accumulator, general purpose register or at some specified memory location.So,
appropriate location (address) of data is need to be specified, and in computer,
there are various ways of specifying the address of data.These various ways of
specifying the address of data are known as “Addressing Modes”

So Addressing Modes can be defined as-

“The technique for specifying the address of the operands “

And in computer the address of operand i.e., the address where operand is actually
found is known as
“Effective Address”.

Now, in addition to this, the two most prominent reason of why addressing modes
are so important are:
1. First, the way the operand data are chosen during program execution is
dependent on the addressing mode of the instruction.
2. Second, the address field(or fields) in a typical instruction format are
relatively small and sometimes we would like to be able to reference a large
range of locations, so here to achieve this objective i.e., to fit this large range
of location in address field, a variety of addressing techniques has been
employed. As they reduce the number of field in the addressing field of the
instruction.
Thus, Addressing Modes are very vital in Instruction Set Architecture(ISA).
Now, before discussing various addressing modes, I will give here some notations
that will use in throughout of this section.These are:

A= Contents of an address field in the instruction

R= Contents of an address field in the instruction that refers to a register
EA= Effective Address(Actual address) of location containing the referenced
operand.
(X)= Contents of memory location x or register X.

Types Of Addressing Modes:

Various types of addressing modes are:

1. Implied and Immediate Addressing Modes
2. Direct or Indirect Addressing Modes
3. Register Addressing Modes
4. Register Indirect Addressing Mode
5. Auto-Increment and Auto-Decrement Addressing Modes
6. Displacement Based Addressing Modes
Now, we will explore to each one by one.

1.Implied and Immediate Addressing Modes:

Although most Addressing modes need the address field of the instruction, but
implied and immediate addressing modes are the only addressing modes
that need no address field at all.Now we will discuss each of them in detail one
by one.

Implied Addressing Mode:

 Implied Addressing Mode also known as "Implicit" or "Inherent" addressing mode
is the addressing mode in which, no operand(register or memory location or
data) is specified in the instruction. As in this mode the operand are specified
implicit in the definition of instruction.
As an example: The instruction :
“Complement Accumulator” is an Implied Mode instruction because the operand
in the accumulator register is implied in the definition of
instruction.In assembly language it is written as:
CMA: Take complement of content of AC
Similarly, the instruction,
RLC: Rotate the content of Accumulator is an implied mode instruction.
In addition to this, all Register-Reference instruction that use an accumulator and
Zero-Address instruction in a Stack Organised Computer are implied mode
instructions, because in Register reference operand implied in accumulator
and in Zero-Address instruction, the operand implied on the Top of Stack.
Immediate Addressing Mode:

In Immediate Addressing Mode operand is specified in the instruction itself.In

other words, an immediate mode instruction has an operand field rather
than an address field, which contain actual operand to be used in conjunction
with the operand specified in the instruction.That is, in this mode, the format of
instruction is:

As an example: The Instruction:

MVI 06 Move 06 to the accumulator
 ADD 05 ADD 05 to the content of accumulator
In addition to this , this mode is very useful for initialising the register to a
constant value.
2.Direct and Indirect Addressing Modes:

The instruction format for direct and indirect addressing mode is shown below:

It consists of 3-bit opcode, 12-bit address and a mode bit designated as( I).The
mode bit (I) is zero for Direct Address and 1 for Indirect Address. Now we will
discuss about each in detail one by one.
Direct Addressing Mode:

Direct Addressing Mode is also known as “Absolute Addressing Mode”.In this

mode the address of data(operand) is specified in the instruction itself.That is,
in this type of mode, the operand resides in memory and its address is given
directly by the address field of the instruction.
Means, in other words, in this mode, the address field contain the Effective
Address of operand
i.e., EA=A
As an example: Consider the instruction:
ADD A Means add contents of cell A to accumulator .

It Would look like as shown below:

 Here, we see that in it Memory Address=Operand.
Indirect Addressing Mode:

In this mode, the address field of instruction gives the memory address where on,
the operand is stored in memory.That is, in this mode, the address field of the
instruction gives the address where the “Effective Address” is stored in
memory. i.e., EA=(A)
Means, here, Control fetches the instruction from memory and then uses its
address part to access memory again to read Effective Address.
As an example: Consider the instruction:
ADD (A) Means adds the content of cell pointed to contents of A to
Accumulator.

It look like as shown in figure below:

 Thus in it, AC <-- M[M[A]] [M=Memory]
i.e., (A)=1350=EA

3.Register Addressing Mode:

In Register Addressing Mode, the operands are in registers that reside within the
CPU.That is, in this mode, instruction specifies a register in CPU, which contain
the operand.It is like Direct Addressing Mode, the only difference is that
the address field refers to a register instead of memory location.
i.e., EA=R

It look like as:

 Example of such instructions are:
MOV AX, BX Move contents of Register BX to AX
ADD AX, BX Add the contents of register BX to AX
Here, AX, BX are used as register names which is of 16-bit register.
Thus, for a Register Addressing Mode, there is no need to compute the actual
address as the operand is in a register and to get operand there is no
memory access involved.
4.Register Indirect Addressing Mode:

In Register Indirect Addressing Mode, the instruction specifies a register in CPU

whose contents give the operand in memory.In other words, the selected
register contain the address of operand rather than the operand itself.That is,
i.e., EA=(R)
Means, control fetches instruction from memory and then uses its address to
access Register and looks in Register(R) for effective address of operand in
memory.
It look like as:
 Here, the parentheses are to be interpreted as meaning contents of.

Example of such instructions are:

MOV AL, [BX]

Code example in Register:
MOV BX, 1000H
MOV 1000H, operand

From above example, it is clear that, the instruction(MOV AL, [BX]) specifies a
register[BX], and in coding of register, we see that, when we move
register [BX], the register contain the address of operand(1000H) rather
than address itself.
5.Auto-increment and Auto-decrement Addressing Modes :

These are similar to Register indirect Addressing Mode except that the register is
incremented or decremented after(or before) its value is used to access
memory.
These modes are required because when the address stored in register refers to a
table of data in memory, then it is necessary to increment or decrement the
register after every access to table so that next value is accessed from
memory.Thus, these addressing modes are common requirements in computer.
Now, we will discuss each separately in detail.
 Auto-increment Addressing Mode:

Auto-increment Addressing Mode are similar to Register Indirect Addressing

Mode except that the register is incremented after its value is loaded (or
accessed) at another location like accumulator(AC).
That is, in this case also, the Effective Address is equal to
EA=(R)
But, after accessing operand, register is incremented by 1.
As an example:
It look like as shown below:

Here, we see that effective address is (R )=400 and operand in AC is 7.

And after loading R1 is incremented by 1.It becomes 401.
Means, here we see that, in the Auto-increment mode, the R1 register is increment
to 401 after execution of instruction.
Auto-decrement Addressing Mode:

Auto-decrement Addressing Mode is reverse of auto-increment , as in it the

register is decrement before the execution of the instruction.That is, in this
case, effective address is equal to
 EA=(R) - 1
As an example:
It look like as shown below:

Here, we see that, in the Auto-decrement mode, the register R1 is decremented to

399 prior to execution of the instruction, means the operand is loaded to
accumulator, is of address 1099H in memory, instead of 1088H.Thus, in this
case effective address is 1099H and contents loaded into accumulator is 700.

6.Displacement Based Addressing Modes:

Displacement Based Addressing Modes is a powerful addressing mode as it is a

combination of direct addressing or register indirect addressing mode.
i.e., EA=A+(R)
Means, Displacement Addressing Modes requires that the instruction have two
address fields, at least one of which is explicit means, one is address field indicate
direct address and other indicate indirect address.That is, value contained in one
addressing field is A, which is used directly and the value in other address field is
R, which refers to a register whose contents are to be added to produce
effective address.
It look like as shown in figure below:
 There are three areas where Displacement Addressing modes are used.In other
words, Displacement Based Addressing Modes are of three types.These are:
1. Relative Addressing Mode
2. Base Register Addressing Mode
3. Indexing Addressing Mode
Now we will explore to each one by one.

1. Relative Addressing Mode:

In Relative Addressing Mode , the contents of program counter is added to the

address part of instruction to obtain the Effective Address.
That is, in Relative Addressing Mode, the address field of the instruction is
added to implicitly reference register Program Counter to obtain effective
address.
i.e., EA=A+PC
It becomes clear with an example:
Assume that PC contains the no.- 825 and the address part of instruction
contain the no.- 24, then the instruction at location 825 is read from memory
during fetch phase and the Program Counter is then incremented by one to
826.
The effective address computation for relative address mode is 826+24=850
 It is depicted in fig. below:

Thus, Effective Address is displacement relative to the address of

instruction.Relative Addressing is often used with branch type instruction.

2. Index Register Addressing Mode:

In indexed addressing mode, the content of Index Register is added to direct

address part(or field) of instruction to obtain the effective address.Means,
in it, the register indirect addressing field of instruction point to Index
Register, which is a special CPU register that contain an Indexed value, and
direct addressing field contain base address.
As, indexed type instruction make sense that data array is in memory and each
operand in the array is stored in memory relative to base address.And the
distance between the beginning address and the address of operand is the
indexed value stored in indexed register.
Any operand in the array can be accessed with the same instruction, which
provided that the index register contains the correct index value i.e., the
index register can be incremented to facilitate access to consecutive
operands.
Thus, in index addressing mode
EA=A+Index
It looks like as shown in fig. below:
 3. Base Register Addressing Mode:

In this mode, the content of the Base Register is added to the direct address
part of the instruction to obtain the effective address.Means, in it the register
indirect address field point to the Base Register and to obtain EA, the
contents of Instruction Register, is added to direct address part of the
instruction.This is similar to indexed addressing mode except that the register is
now called as Base Register instead of Index Register.
That is, the EA=A+Base
It looks like as shown in fig. below:

Thus, the difference between Base and Index mode is in the way they are used
rather than the way they are computed.An Index Register is assumed to hold
an index number that is relative to the address part of the instruction.And a
Base Register is assumed to hold a base address and the direct address field
of instruction gives a displacement relative to this base address.
Thus, the Base register addressing mode is used in computer to facilitate the
relocation of programs in memory.
Means, when programs and data are moved from one segment of memory to
another, then Base address is changed, the displacement value of instruction
do not change.So, only the value of Base Register requires updation to
reflect the beginning of new memory segment.