Ambo University, Institute of Technology, Department of Computer Science

Digital Electronics Chapter 4 Handout

Chapter Four

Function of Combinational Logic

Digital systems obtain binary-coded data and information that are continuously being operated
on in some manner.
Among many functions of Combinational logic are
1. Decoding and encoding-changing the data from one type of code to another,
2. Multiplexing-selecting one out of several groups of data,
3. Demultiplexing- distributing data to one of several destinations,
4. Comparing the magnitudes of two binary numbers,
5. Parity checking- to detect data errors and, performing arithmetic operation.
DECODER
A decoder is a logic circuit that accepts a set of inputs that represents a binary number and
activates only the output that corresponds to that input number.
In other words, a decoder circuit looks at its inputs, determines which binary number is
present there, and activates the one output that corresponds to that number; all other outputs
remain inactive.

 Many decoders are designed to produce active –LOW outputs, where only the
selected output is LOW while all others are HIGH.
 This would be indicated by the presence of small circles on the output lines in the
decoder diagram.
 Some decoders do not utilize all of the 2N possible input codes but only certain
ones.
 For example, a BCD-to-decimal decoder has a 4-bit input code and ten output lines
that correspond to the ten BCD code groups 0000 through 1001.
 Decoders of this type are often designed so that if any of the unused codes are
applied to the input, none of the outputs will be activated.
 Figure below shows the circuitry for a decoder with three inputs and 23=8 outputs.
It uses all AND gates, and so the outputs are active-HIGH.
The diagram and table below show 3-line-to-8-line Decoder and it verification
respectively

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Ambo University, Institute of Technology, Department of Computer Science
Digital Electronics Chapter 4 Handout

Enable Inputs
 Some decoders have one or more ENABLE inputs that are used to control the operation

of the decoder .
 The Decoder fig below have a common ENABLE line connected to a fourth input of each
gate. With this ENABLE line held HIGH the decoder will function normally and the A,
B, C input code will determine which output is HIGH.
 With ENABLE held LOW, however, all the outputs will be forced to the LOW state
regardless of the levels at the A, B, C input.
 Thus, the decoder is ENABLED only if ENABLE is HIGH

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Ambo University, Institute of Technology, Department of Computer Science
Digital Electronics Chapter 4 Handout

BCD-to-Decimal Decoder

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Ambo University, Institute of Technology, Department of Computer Science
Digital Electronics Chapter 4 Handout

BCD-TO-7-SEGMENT DECODER/DRIVERS
 Most digital equipment has some means for displaying information in a form that can
be understood readily by the user or operator.
 This information is often numerical data, but can also be alphanumeric (numbers and
letters).
 One of the simplest and most popular methods for displaying numerical digits uses a
7-segnent configuration to form the decimal characters 0 through 9 and sometimes the
hex characters A through F.

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Ambo University, Institute of Technology, Department of Computer Science
Digital Electronics Chapter 4 Handout

Example

Encoder
 Most decoders accept an input code and produce a HIGH (or LOW) at one and only one
output line.
 In other words, we can say that a decoder identifies, recognizes, or
detects a particular code.
 The opposite of this decoding process is called encoding and is performed by a logic
circuit called an encoder.
 An encoder has a number of input lines, only one of which is activated at
a given time, and produces an N-bit output code, depending on which
input is activated.
The given Fig is general diagram for and encoder with M inputs and N outputs. Here the inputs
are active- HIGH, which means they are normally LOW.

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Ambo University, Institute of Technology, Department of Computer Science
Digital Electronics Chapter 4 Handout

Truth table for 8-line-to-3-line Encoder

MULTIPLEXERS (DATA SELECTORS)

A modern home stereo system may have a switch that selects music from one of four sources.
 a cassette tape,
 a compact disc (CD),
 a turntable, or
 a radio
The switch selects one of the electronic signals from one of these four sources and sends it to the
power amplifier and speakers.
In simple terms, this is what a multiplexer does; it selects one of several input signals and passes
it onto the output.

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Ambo University, Institute of Technology, Department of Computer Science
Digital Electronics Chapter 4 Handout
A digital multiplexer or data selector is logic circuit that accepts several digital data inputs and
selects one of them at any given time to pass on to the output.
The routing of the desired data input to the output is controlled by SELECT inputs (often
referred to as ADDRESS inputs).

The multiplexer acts like a digitally controlled multi-position switch where the digital code
applied to the SELECT inputs controls which data inputs will be switched to the output.
For example, output Z will equal data input I 0 for some particular SELECT input code. Z will
equal for another particular SELECT input code; and so on.
Stated another way, a multiplexer selects 1 out of N input data sources and transmits the selected
data to a single output channel. This is called Multiplexing.
Basic Two-Input Multiplexer

An example of where a two- input MUX could be used is in a computer system that uses two
different MASTER CLOCK signals.
 A high-speed clock( say 10 MHz ) for some programs, and
 A slow-speed clock (say 4.77 MHz) for others

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Ambo University, Institute of Technology, Department of Computer Science
Digital Electronics Chapter 4 Handout

Here there are four inputs, which are selectively transmitted to the output according to the four
possible combinations of the s0 s1 select inputs.
Each data input is gated with different combination of select input level.
I 0 Gated with s0 s1 so that I 0 will pass through its AND gate to output Z only when s1=1 and
s0 =0.

Eight in-put Multiplexer

Application of Multiplexer
Parallel-to-Serial Conversion

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Ambo University, Institute of Technology, Department of Computer Science
Digital Electronics Chapter 4 Handout
A 3-bit (MOD-8) counter is used to provide the select code bits s2 s 1 s0 so that they cycle through
from 000 to 111 as clock pulse are applied.

In this way the output of the multiplexer will be X 0 during the first clock period, X 1
during the second clock period, and so on.The output Z is the waveform which is a serial
representation of the parallel input data.
 The waveform in fig (b) are for the case where X 7 x 6 x 5 x 4 x 3 x 2 x 1 x 0=10110101.This
conversion process takes total eight clock cycles. Note that x 0 (LSB) is transmitted first
and the X 7 (MSB) is transmitted the last.

Demultiplexer (DEMUX)
Perform reverse process of Multiplexer. The Select input code input code determines to which
output the DATA input is will be transmitted. In other words, the Demultiplexer takes one input
data source and Selectively distributes it to 1 of N output channel.

1-Line-to-4-Line Demultiplexer

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Ambo University, Institute of Technology, Department of Computer Science
Digital Electronics Chapter 4 Handout

1-to-8 Demultiplexer

The Half-Adder

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Ambo University, Institute of Technology, Department of Computer Science
Digital Electronics Chapter 4 Handout
Arithmetic circuits are the circuits that perform arithmetic operations. A half adder arithmetic

circuit adds two binary digits, giving a sum bit and a carry bit. The sum (S) bit and carry (C) bit,
according to the rules of binary addition, are given by:
The sum (S) is the X-OR of A and B.
Therefore

The carry (C) is the AND of A and B.

Therefore

Half-adder can also be realized in universal logic by using either only NAND gates or only NOR
gates as explained below.
NAND Logic Gates

The Full-Adder
A full-adder is an arithmetic circuit that adds two bits and a carry and outputs a sum bit and a

carry bit. When we want to add two binary numbers, each having two or more bits , the LSBs
can be added by using a half-adder.

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Compiled by Gudisa Tesema(MSc)
Ambo University, Institute of Technology, Department of Computer Science
Digital Electronics Chapter 4 Handout
The carry resulted from the addition of the LSBs is carried over to the next significant column
and added to the two bits in that column.
So, in the second and higher columns, the two data bits of that column and the carry bit
generated from the addition in the previous column need to be added. The full-adder adds the
bits A and B and the carry from the previous column called the carry-in c ¿ and outputs the sum
bit S and the carry bit called the carry-out c out .
There are no sources in the current document.

From the truth table , a circuit that will produce the correct sum and carry bits in response to
every possible combination of A,B, and c ¿ is described by

The sum term of the full-adder is the XOR of A, B, and Cin , i.e. the sum bit is the modulo sum
of the data bits in that column and the carry from the previous column.

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