Microprocessor and Microcontroller

UNIT I – 8085 MICROPROCESSOR

Introduction
Microprocessor: A silicon chip that contains a CPU. A microprocessor is a
computer processor where the data processing logic and control is included on a
single integrated circuit, or a small number of integrated circuits. The
microprocessor contains the arithmetic, logic, and control circuitry required to
perform the functions of a computer's central processingunit. 

8085 Microprocessor Introduction

The Intel 8085 is an 8-bit microprocessor introduced by Intel in 1977. It
was binary compatible with the more-famous Intel 8080 but required less
supporting hardware, thus allowing simpler and less expensive microcomputer
systems to be built. The "5" in the model number came from the fact that the
8085 requires only a +5-Volt (V) power supply rather than the +5 V, −5 V and
+12 V supplies the 8080 needed. The main features of 8085 μP are:
 It is an 8-bit microprocessor.
 It is manufactured with N-MOS technology.
 It has 16-bit address bus and hence can address up to 216= 65536
bytes (64KB) memory locations through A0–A15.
 The first 8 lines of address bus and 8 lines of data bus are
multiplexed AD0–AD7
 Data bus is a group of 8 lines D0–D7.
 It supports external interrupt request.
 A 16-bit program counter (PC)
 A 16-bit stack pointer (SP)
 Six 8-bit general purpose register arranged in pairs: BC, DE, HL.
 It requires a signal +5V power supply and operates at 3.2 MHZ
single phase clock.
 It is enclosed with 40 pins DIP (Dual in line package).
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8085 Architecture

8085 consists of various units as shown in and each unit performs its own
functions. The various units of a microprocessor are listed below
 Accumulator
 Arithmetic and logic Unit
 General purpose register
 Program counter
 Stack pointer
 Temporary register
 Flags
 Instruction register and Decoder
 Timing and Control unit
 Interrupt control
 Address buffer and Address-Data buffer
 Address bus and Data bus

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Accumulator
Accumulator is nothing but a register which can hold 8-bit data.
Accumulator aids in storing two quantities. The data to be processed by
arithmetic and logic unit is stored in accumulator. It also stores the result of the
operation carried out by the Arithmetic and Logic unit. The accumulator is also
called an 8-bit register. The accumulator is connected to Internal Data bus and
ALU (arithmetic and logic unit). The accumulator can be used to send or receive
data from the Internal Data bus.

Arithmetic and Logic Unit

There is always a need to perform arithmetic operations like +, -, *, / and to
perform logical operations like AND, OR, NOT etc. So, there is a necessity for
creating a separate unit which can perform such types of operations. These
operations are performed by the Arithmetic and Logic Unit (ALU). ALU
performs these operations on 8-bit data. But these operations cannot be
performed unless we have an input (or) data on which the desired operation is
to be performed. So, from where do these inputs reach the ALU? For this
purpose, accumulator is used. ALU gets its Input from accumulator and
temporary register. After processing the necessary operations, the result is
stored back in accumulator.

General Purpose Registers

Apart from accumulator 8085 consists of six special types of registers called
General Purpose Registers. These general-purpose registers are used to hold
data like any other registers. The general-purpose registers in 8085 processors
are B, C, D, E, H and L. Each register can hold 8-bit data. Apart from the above
function these registers can also be used to work in pairs to hold 16-bit data.
They can work in pairs such as B-C, D-E and H-L to store 16-bit data. The H-L
pair works as a memory pointer. A memory pointer holds the address of a
particular memory location. They can store 16-bit address as they work in pair.

Program Counter and Stack Pointer

Program counter is a special purpose register.
Consider that an instruction is being executed by processor. As soon as the
ALU finished executing the instruction, the processor looks for the next
instruction to be executed. So, there is a necessity for holding the address of the
next instruction to be executed in order to save time. This is taken care by the

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program counter. A program counter stores the address of the next instruction
to be executed. In other words, the program counter keeps track of the memory
address of the instructions that are being executed by the microprocessor and
the memory address of the next instruction that is going to be executed.
Microprocessor increments the program whenever an instruction is being
executed, so that the program counter points to the memory address of the next
instruction that is going to be executed. Program counter is a 16-bit register.
Stack pointer is also a 16-bit register which is used as a memory pointer. A
stack is nothing but the portion of RAM (Random access memory).
So, does that mean the stack pointer points to portion of RAM?
Yes. Stack pointer maintains the address of the last byte that is entered into
stack.
Each time when the data is loaded into stack, Stack pointer gets
decremented. Conversely it is incremented when data is retrieved from stack.
Temporary Register
As the name suggests this register acts as a temporary memory during the
arithmetic and logical operations. Unlike other registers, this temporary
register can only be accessed by the microprocessor and it is completely
inaccessible to programmers. Temporary register is an 8-bit register.

Flags
Flags are nothing but a group of individual Flip-flops. The flags are mainly
associated with arithmetic and logic operations. The flags will show either a
logical (0 or 1) (i.e.) a set or reset depending on the data conditions in
accumulator or various other registers. A flag is actually a latch which can hold
some bits of information. It alerts the processor that some event has taken
place.
D7 D6 D5 D4 D3 D2 D1 D0
S Z AC P CY
Fig. 1.2 Flag Register
Intel processors have a set of 5 flags.
1. Carry flag
2. Parity flag
3. Auxiliary carry flag
4. Zero flag
5. Sign flag
Consider two binary numbers.
For example
1100 0000

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1000 0000
When we add the above two numbers, a carry is generated in the most
significant bit. The number in the extreme right is least significant bit, while the
number in extreme left is most significant bit. So, a ninth bit is generated due to
the carry. So how to accommodate 9th bit in an 8-bit register?
For this purpose, the Carry flag is used. The carry flag is set whenever a
carry is generated and reset whenever there is no carry. But there is an

auxiliary carry flag? What is the difference between the carry flag and auxiliary
carry flag?
Let’s discuss with an example. Consider the two numbers given below
0000 1100
0000 1001
When we add both the numbers a carry is generated in the fourth bit from
the least significant bit. This sets the auxiliary carry flag. When there is no
carry, the auxiliary carry flag is reset. So, whenever there is a carry in the most
significant bit Carry flag is set. While an auxiliary carry flag is set only when a
carry is generated in bits other than the most significant bit.
Parity checks whether it’s even or add parity. This flag returns a 0 if it is
odd parity and returns a 1 if it is an even parity. Sometimes they are also called
as parity bit which is used to check errors while data transmission is carried
out.
Zero flag shows whether the output of the operation is 0 or not. If the value
of Zero flag is 0 then the result of operation is not zero. If it is zero the flag
returns value 1.
Sign flag shows whether the output of operation has positive sign or
negative sign. A value 0 is returned for positive sign and 1 is returned for
negative sign.

Instruction Register and Decoder

Instruction register is 8-bit register just like every other register of
microprocessor. Consider an instruction. The instruction may be anything like
adding two data's, moving a data, copying a data etc. When such an instruction
is fetched from memory, it is directed to Instruction register. So, the instruction
registers are specifically to store the instructions that are fetched from
memory. There is an Instruction decoder which decodes the information
present in the Instruction register for further processing.

Timing and Control Unit

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Timing and control unit is a very important unit as it synchronizes the
registers and flow of data through various registers and other units. This unit
consists of an oscillator and controller sequencer which sends control signals
needed for internal and external control of data and other units. The oscillator
generates two-phase clock signals which aids in synchronizing all the registers
of 8085 microprocessor.
Signals that are associated with Timing and control unit are:
Control Signals: RD’, WR’, ALE
 ALE is used for provide control signal to synchronize the
components of microprocessor and timing for instruction to
perform the operation.
 RD (Active low) and WR (Active low) are used to indicate whether
the operation is reading the data from memory or writing the data
into memory respectively.

Status Signals: S0, S1, IO/M’

 IO/M (Active low) is used to indicate whether the operation belongs
to the memory or peripherals.

Table 1.1 Status signals and the status of data bus

IO/M’ (Active Low) S1 S2 Data Bus Status (Output)
0 0 0 Halt
0 0 1 Memory WRITE
0 1 0 Memory READ
1 0 1 IO WRITE
1 1 0 IO READ
0 1 1 Op code fetch
1 1 1 Interrupt acknowledge

DMA Signals: HOLD, HLDA, READY

 HOLD: Indicates that another master is requesting the use of the
address and data buses. The CPU, upon receiving the hold request,
will relinquish the use of the bus as soon as the completion of the
current bus transfer. Internal processing can continue. The
processor can regain the bus only after the HOLD is removed. When
the HOLD is acknowledged, the Address, Data RD, WR and IO/M’
lines are tri-stated.
 HLDA: Hold Acknowledge: Indicates that the CPU has received the
HOLD request and that it will relinquish the bus in the next clock

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cycle HLDA goes low after the Hold request is removed. The CPU
takes the bus one half-clock cycle after HLDA goes low.
 READY: This signal synchronizes the fast CPU and the slow memory,
peripherals. If READY is high during a read or write cycle, it
indicates that the memory or peripheral is ready to send or receive

data. If READY is low, the CPU will wait an integral number of clock cycle for
READY to go high before completing the read or write cycle. READY must
conform to specified setup and hold times.

Reset Signals: Reset in, Reset Out

RESET IN: A low on this pin;
 Sets the program counter to zero (0000H)
 Resets the interrupt enables and HLDA flip-flops.
 Tri-states the data bus, address bus and control bus.
 Affects the content of processors internal registers randomly.
On Reset, The Program counter sets to 0000h which causes the 8085 to
execute; the first instruction from address 0000H.
 RESET OUT: This active high signal indicates that the processor; is
being reset. This signal is synchronized to the processor clock and it
can be used to reset other devices connected in the system.

Interrupt control
As the name suggests this control interrupts a process. Consider that a
microprocessor is executing the main program. Now whenever the interrupt
signal is enabled or requested the microprocessor shifts the control from main
program to process the incoming request and after the completion of request,
the control goes back to the main program. For example, an Input/output
device may send an interrupt signal to notify that the data is ready for input.
The microprocessor temporarily stops the execution of main program and
transfers control to I/O device. After collecting the input data, the control is
transferred back to main program. Interrupt signals present in 8085 are:
 INTR
 RST 7.5
 RST 6.5
 RST 5.5
 TRAP
INTR is maskable 8080A compatible interrupt. When the interrupt occurs
the processor fetches from the bus one instruction, usually one of these
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instructions: One of the 8 RST instructions (RST0 - RST7). The processor saves
current program counter into stack and branches to memory location N * 8
(where N is a 3 - bit number from 0 to 7 supplied with the RST instruction).

CALL instruction (3-byte instruction). The processor calls the subroutine,

address of which is specified in the second and third bytes of the instruction.
RST5.5 is a maskable interrupt. When this interrupt is received the
processor saves the contents of the PC register into stack and branches to 2CH
(hexadecimal) address.
RST6.5 is a maskable interrupt. When this interrupt is received the
processor saves the contents of the PC register into stack and branches to 34H
(hexadecimal) address.
RST7.5 is a maskable interrupt. When this interrupt is received the
processor saves the contents of the PC register into stack and branches to 3CH
(hexadecimal) address.
TRAP is a non-maskable interrupt. When this interrupt is received the
processor saves the contents of the PC register into stack and branches to 24H
(hexadecimal) address.
All maskable interrupts can be enabled or disabled using EI and DI
instructions. RST5.5, RST6.5 and RST7.5 interrupts can be enabled or disabled
individually using SIM instruction.

Serial Input/output control

The input and output of serial data can be carried out using 2 instructions
in 8085.
 SID-Serial Input Data
 SOD-Serial Output Data
Two more instructions are used to perform serial-parallel conversion
needed for serial I/O devices.
 SIM
 RIM

Address buffer and Address-Data buffer

The contents of the stack pointer and program counter are loaded into the
address buffer and address-data buffer. These buffers are then used to drive the
external address bus and address-data bus. As the memory and I/O chips are
connected to these buses, the CPU can exchange desired data to the memory
and I/O chips.
The address-data buffer is not only connected to the external data bus but

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also to the internal data bus which consists of 8-bits. The address data buffer
can both send and receive data from internal data bus.

Address bus and Data bus

We know that 8085 is an 8-bit microprocessor. So, the data bus present in
the microprocessor is also 8-bits wide. So, 8-bits of data can be transmitted
from or to the microprocessor. But 8085 processor requires 16-bit address bus
as the memory addresses are 16-bit wide. The 8 most significant bits of the
address are transmitted with the help of address bus and the 8 least significant
bits are transmitted with the help of multiplexed address/data bus. The eight-
bit data bus is multiplexed with the eight least significant bits of address bus.
The address/data bus is time multiplexed. This means for few microseconds,
the 8 least significant bits of address are generated, while for next few seconds
the same pin generates the data. This is called Time multiplexing. But there are
situations where there is a need to transmit both data and address
simultaneously. For this purpose, a signal called ALE (address latch enables) is
used. ALE signal holds the obtained address in its latch for a long time until the
data is obtained and so when the microprocessor sends the data next time the
address is also available at the output latch. This technique is called
Address/Data demultiplexing.

Pin Diagram of 8085

The signals can be grouped as follows

1. Power supply and clock signals
2. Address bus
3. Data bus
4. Control and status signals
5. Interrupts and externally initiated signals
6. Serial I/O ports

Power supply and Clock frequency signals

 Vcc + 5-volt power supply
 Vss Ground
 X1, X2: Crystal or R/C network or LC network connections to set the

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frequency of internal clock generator. The frequency is internally
divided by two. Since the basic operating timing frequency is 3 MHz,
a 6 MHz crystal is connected externally.
 CLK (output) – Clock Output is used as the system clock for
peripheral and devices interfaced with the microprocessor.

Data Bus and Address Bus

AD0-AD7:-These are multiplexed address and data bus. So, it can be used to
carry the lower order 8-bit address as well as the data. Generally, these lines
are demultiplexed using the Latch. During the opcode fetch operation, in the
first clock cycle the lines deliver the lower order address bus A0-A7. In the
subsequent IO/M read or write it is used as data bus D0-D7. CPU can read or
write data through these lines. A8-A15:- These are address bus used to address
the memory location.

Pin Diagram of 8085

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A8 - A15 (Output 3 State)

Address Bus:The most significant 8 bits of the memory address or the 8 bits
of the I/0 address,3 stated during Hold and Halt modes.

AD0 - AD7 (Input/Output 3state)

Multiplexed Address/Data Bus; Lower 8 bits of the memory address (or I/0
address) appear on the bus during the first clock cycle of a machine state. It
then becomes the data bus during the second and third clock cycles. 3
stated during Hold and Halt modes.

ALE (OUTPUT) ADDRESS LATCH ENABLE

It occurs during the first clock cycle of a machine state and enables the
address to get latched into the on chip latch of peripherals. The falling edge
of ALE is set to guarantee setup and hold times for the address information.
ALE can also be used to strobe the status information. ALE is never 3stated.

SO, S1 (OUTPUT)

S0 S1 Encoded status of the bus cycle

0 0 HALT
0 1 WRITE
1 0 READ
1 1 FETCH

RD (Output 3state)
READ: indicates the selected memory or 1/0 device is to be read and that
the Data Bus is available for the data transfer.

WR (Output 3state)
WRITE: Indicates the data on the Data Bus is to be written into the selected
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memory or 1/0 location. Data is set up at the trailing edge of WR. 3 stated
1
during Hold and Halt modes.

READY (Input)
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If Ready is high during a read or write cycle, it indicates that the memory or
peripheral is ready to send or receive data. If Ready is low, the CPU will
wait for Ready to go high before completing the read or write cycle.

HOLD (Input)
It indicates that another Master is requesting the use of the Address and
Data Buses. The CPU, upon receiving the Hold request will relinquish the
use of buses as soon as the completion of the current machine cycle.
Internal processing can continue.

SIGNAL CLASSIFICATION OF 8085

The signal Classification of 8085 is as shown in fig3.

ADDRESS BUS

 Unidirectional
 Identifying peripheral or memory location

DATA BUS

 Bidirectional
 Transferring data

CONTROL BUS
 Synchronization signals
 Timing signals
 Control signal

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