Volume 7, Issue 12, December – 2022 International Journal of Innovative Science and Research Technology

ISSN No:-2456-2165

VIP Development of SPI Controller for Open-Power

Processor based Fabless SoC
D. Anupriya
M. Tech Scholar, VLSI-SD, ECE Department, JNTUA College of Engineering (AUTONOMOUS)Ananthapuramu,
Andhra Pradesh, India.

Abstract:- Since integrated circuit designs continuously data transmission method on the SPI bus. SPI devices operate
expanding, which makes the verification process more in full duplex mode by transmitting and receiving in this way.
difficult and time-consuming, effective verification of such The lines on the SPI bus are entirely one-way. Master generates
circuit designs is essential. As a result, a strong testbench the clock signal, which generally used to synchronize data
structure is required, one that includes major generic transfer. Data is transmitted from the master to the slave on the
verification components that are highly reusable and are master-output slave-input (MOSI) line and from the slave to the
simple to adapt to new designs. The UVM hierarchy is one master on the master-input slave-output(MISO) line. The
such design capable of realizing testbench architectures master selects each slave device using a separate select line.
with coverage-driven verification environments with CRT Over the SPI bus, data transfer rates range from almost 0 bits
(constrained Random Test). According to the verification per second to 1 MB per second. Typically, data is transferred
plan devised following a thorough review of the SPI in blocks of eight or sixteen bits. The serial clock synchronises
protocol requirements, the current effort is appropriately all data transport (SCLK). Each clock cycle transfers one bit of
concentrated on SPI One Master and Multi Slave protocol data. The values of the clock phase and polarity bits dictate four
verification using UVM. The UVM Testbench different clock modes for the SPI bus. When new data is to be
concentrates on generating random vectors that are sent to transferred onto the bus, the clock phase determines which
the SPI module or the DUT (Design Under Test). This clock edge to use, and the clock polarities establishes the
method aids in verifying the functionality of SPI by intensity of the clock idle state. Any hardware component with
making comparisons with the captured response received multiple operating modes will have a mechanism for choosing
via scoreboard. By using acceptable or appropriate test the value of these bits.
cases, Testbench also validates the functionality and
distinguishing characteristics of SPI, and at the conclusion Four logic signals are listed for the SPI bus:
of the test, it delivers a cumulative coverage report of the  Serial Peripheral Interface Clock (SCLK)
design.  Master-Output Slave-Input (MOSI).
 Master-Input Slave-Output (MISO).
Keywords:- UVM, System Verilog, SPI Protocol, Questsim,  Active low Slave Select (SS).
and EDA-playground mentor.

I. INTRODUCTION

For applications that need to transport data at 8 or 16-bits

per second, the SPI acts as a "3-wire plus chip select" serial
bus.Information is transmitted between bus-connected devices
through the three wires. Every gadget on the bus serves as both
a sender and a recipient simultaneously. Two out of the three
lines, one in every direction, are used to transfer data; the third
line acts as a serial clock. Some devices may only be senders, Fig1.Serial Peripheral Interface Architecture
while others may only be receivers. The transmitting gadget
typically has the ability to receive data as well. A receive-only II. RESEARCH GOALS
device is an example of an SPI display, whereas a receiver and
send device is an EEPROM. SPI bus-connected devices can be Building an usable test bench to validate the SPI slave
categorised as Master/Slave devices. A master device creates model-based SPI master controller and the AXI bus function
clock and control signals and starts an information transfer on model is the goal of this research project. The upcoming goals
the bus. Through a slave choose (chip enable) line, a slave aid in achieving the desired outcome:
device is managed by the master and is only operational when  One must comprehend the SPI protocol architecture and the
selected. For each slave device, a separate select line is particular requirements of the AXI platform in order to link
typically needed. In a multi-master mode arrangement, the the test bench components to the core controller.
same device can act as both a master and a slave, but only one  Employing state-of-the-art verification techniques, such as
master can ever control the bus at any given moment. Any non- Coverage Driven Functional Verification and Universal
selected slave device has to withdraw (make the slave output Verification Methodology.
line high impedance). Data is timed into and out of the active  To provide a AXI-compliant SPI master component with
devices before being transferred using a standard shift register reusable Verification IP.

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Volume 7, Issue 12, December – 2022 International Journal of Innovative Science and Research Technology
ISSN No:-2456-2165
oriented programming is one of the most promising methods
The following are the main contributions of this paper:: for top - level functional verification for modern complex SOC
1. Become familiar with SPI sub-system architecture, UVM, systems. System Verilog provides a complete verification
and System Verilog. environment that includes metrics based on coverage, direct
2. Developing an AXI bus function model to enable closed- and limited random generation, and assertion-based
loop verification testing by serving as a connection between verification. Base class libraries created in System Verilog are
both the test bench and the SPI master device under test used by the Universal Verification Methodology (UVM), the
(DUT) and SPI slave model. most recent functional verification approach.The AVM from
3. Use UVM libraries, assertions, coverage, limited random Mentor, the OVM from Mentor & Cadence, the eRM from
stimuli, and System Verilog structures to create hierarchical Verisity, and the VMM-RAL from Synopsys are some of the
testbench components. older technique libraries on which UVM is built.Thanks to this
4. Verify data transmission by experimenting with different standardization, users can now create highly compatible,
character widths and data types. portable verification modules. The term "verification
components" refers to these modules. For whole systems,
One of the most often utilized serial protocols in a SoC is SPI modules, or protocols, they are encased and transformed into
since it operates at better bandwidth and throughput than other useable, flexible verification environments. These apps are
protocols like UART and I2C. Microcontrollers on the host built upon the extensive base class library. It offers hardware
side and slave devices are frequently made to interact more acceleration, emulation, assertion-based verification, coverage-
easily through the SPI Protocol. It is well-liked since it driven restricted random verification, and restricted random
operates with less control signals. The specific SPI core that verification. It emphasizes simulation.
was the focus of this study serves as a slave AXI compliant
device on the host side. Serial Shift Interface (SSI), Clock III. DESIGN OF SPI
Generator (CG), and AXI Connection (AXI) are the three
fundamental components of the SPI Master Core Controller. Combining a single Master with a single Slave is the simplest
The AXI interface that allows for changes to be made to the configuration for the Serial Peripheral Interface (SPI) [2].
five 32-bit registers of the SPI core controller. However, interaction between a single Master unit or module
and several Slave devices is possible i.e., with more than one
The serial Peripheral interface consists of serial clock signal Slave device. Any microcontroller device and accompanying
and slave select signal. Implementing a high-speed SPI peripherals can exchange information utilizes the SPI
Master/Slave between 900 and 1000 MHz is possible. When technology's high-speed, full-duplex, and synchronous
two slaves are present, for instance, the core can be built with communication bus protocol. But when it comes to verification,
more flexible SPI-bus control handling. the core's control System Verilog, which is regarded as a hardware description
register, which determines whether the SPI module runs in language(HDL), is used to implement the oops programming
master or slave mode, which is a key component, can be altered. language and provide a test environment for the SPI protocol.
The SPI status register provides information about running data Advanced SystemVerilog features aid in creating a prospective
transfer operations, including their state and whether they have verification environment, yet UVM implementation still
finished or not. One more crucial factor is the adaptability of enables a standardised verification technique (Universal
SPI Interface IPs built with a parameterization technique for VerificationMethodology).
different devices. Time Sharing Multiplex (TSM), an advanced
design method, in multi-master systems, is utilized to
automatically detect the master/slave devices. TSM is used to
fix communication issues between many devices. Verification
has been harder as a result of the current SoC's increased
complexity. The truth is that difficult SoC verification
consumes 70% of the time needed for product development.

Reduced verification work is the answer to the issue of time to

market. This increasing complexity is managed using
contemporary verification techniques. For IP verification, Fig2. Single master- single slave configuration
extensive functional coverage employing constraint random
simulation technique is required.Several tools are used for this, As a multi-point interface, the SPI protocol connects the
including scoreboards and coverage monitors. It is crucial to devices in a Master-Slave relationship. At this kind of interface,
verify that a communication protocol, such as the SPI a single device typically a microcontroller plays the role of the
communication protocol, complies with the design Master, while other linked devices.
specifications. By adopting a restricted random technique for
better functional coverage, effective verification can be Single Slave Configuration:
accomplished. More recent verification methods and languages A serial peripheral interface device has multiple slave devices
have long been advocated by EDA businesses. For a system and only one master device. There are 4 signalling pins in the
level verification technique or language to be effective, it must SPI bus protocol . These are them:
be scalable and reusable of the produced verification  Master-Output Slave-Input (MOSI)
components. The combination of System Verilog and object-  Master-Input Slave-Output(MISO)

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Volume 7, Issue 12, December – 2022 International Journal of Innovative Science and Research Technology
ISSN No:-2456-2165
 Serial Clock or master Clock (SCLK, SCK, or MK)
 Slave Select pin (SS)/chip select pin(CS)

Here, each signal pin's operational functionality is listed:

 Serial clock or master clock, often known as SCK or MK:
One or more slaves can receive clock signals from this pin, but
only the master can modify those signals. But this pin continues
to be inactive. When there is no operation, the device is inactive
(tri-state).
 Slave Select (SS): This pin is used by the Master module to
select the Slave it wants to connect with or send data to.
 Master-Output Slave-Input (MOSI): The Master output pin
and the Slave input pin are shared by this. This pin is utilized
for data transfer as from Master module to the Slave module. A
single direction is present in the pin.
 Master-Input Slave-Output (MISO): Both the Master input
and Slave output pins are referred to as this pin. From the Slave
unit to the Master unit, data is transmitted using this port. Fig3. Single Master Multi Slave Configuration
Additionally, it has a single direction.
Multi-Slave Configuration: IV. UVM METHODOLOGY
A single SPI Master can implement numerous Slaves. The
Slaves may be connected as separate components or in a daisy- Verification involves a test plan, which functions as a roadmap
chain arrangement. Every Slave module that is under the and gives instructions on how to complete the necessary task
direction of the Master module has its own individual Chip for verifying the design. The verification plan offers a road map
Select (CS) pin in an individual configuration. When the that details the introduction, working hypotheses, test cases to
Master activates the Slave Select (SS) port, the selected Slave execute, various aspects that can be tested, and the strategy to
has access to the information on the MOSI and MISO lines as be used. All of these requirements allow the validation engineer
well as the clock produced by the Master module. However, to observe and understand how the testing procedure should be
since the Master cannot tell which Slave is sending or receiving carried out. The verification test plan may be delivered in a
the information, data corruption on the MISO line results when variety of formats, including a document, plain text file, or
multiple Slave Select (SS) signal ports are active. Figure spreadsheet. A Testbench's design and every module's
3 shows that when the number of Slaves rises, the Master's functionality must be described in order to be verified.
Chip Select (CS) pin count also gradually rises.
In addition to using Assertion-Based Testing (ABT), Coverage
Features of SPI: Driven Validation (CDV), and Constraint Randomized
 Has full duplex communication capabilities. Generation (CRG), System Verilog, an efficient and promising
 I2C has higher and greater throughput than TWI (integrated hardware description language (HDL), also offers a good
Interface circuit). verification environment. These System Verilog-provided
 For bit transferring, there is no restriction on a particular bit features steadily improve the verification process. System
size. Verilog's feature is its improved hardware modelling, which
 With more superior and straightforward hardware streamlines the test procedure for the given DUT and gradually
interfaces than UART and I2C. and efficiently increases RTL design productivity.
 The power need is very little. Programming Direct Interface is the name of a System Verilog
 Slaves don't require precise oscillators because they use the module that is a programming interface that can be used to
master's clock. interact with other language families. System Verilog may
 Less circuitry than I2C results in lower power consumption. handle a variety of foreign languages, including C, C++,
Different strategies can be used, such as employing a System C, and others.
multiplexer module to regulate a Slave Select (SS) signal, to
progressively increase the number of Slaves in each The Universal Verification Methodology (UVM), a
configuration. replacement for System Verilog, is created to meet the
requirement for automated DUT testing. UVM is a powerful
set of System Verilog APIs that also includes a set of tried-and-
true verification standards that can assist verification engineers
in creating a productive and effective atmosphere for testing.
Accellera keeps up an approachable open platform. Engineers
began developing validation components that were mostly
generic and could be applied to other projects as a result of the
implementation of UVM approach, which boosted interaction
and method and technology sharing across different
verification users. The growth of validation components

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Volume 7, Issue 12, December – 2022 International Journal of Innovative Science and Research Technology
ISSN No:-2456-2165
without altering the source code was also highly encouraged
and advocated.

UVM COMPONENTS

Sequence-item: The group consists of the elements or stimuli

necessary to provide the intended stimulus. The sequence-
items must be randomized in some way in order for the
stimulus to be generated. The data variables produced by
sequence-items must therefore be explicitly defined using the
rand prefix and may also include limitations. The UVM
sequence item is extended to create the sequence-item in UVM.
Sequence: A sequence grows or produces a collection of
sequence items and sends them through a sequencer to the Fig4. UVM ARCHITECTURE
driver. Extending UVM sequence is how the sequence process
is carried out. V. VERIFICATION OF SPI

Sequencer: The UVM sequencer is changed into a class called A sequence item is the first component of the UVM
a sequencer, which manages the response exchange between environment's architecture. Typically, uvm transaction or uvm
the sequence and the driver. Driver and Sequencer both use sequence item classes are expanded to create sequence item
TLM Interface to establish transaction communication. class objects. It is composed of all required information
exchange which can be either randomised or constrained to a
Driver: By extending the UVM driver, a driver is created. In specific boundary by using UVM structures. Sequences are
order for the sequencer and driver to communicate, the TLM created by extending uvm sequences to produce additional
port (seq_item_port) needs to be addressed. Driver sends data sequence components. To drive DUT pins, the driver receives
to DUT via interface connection. the created sequences. There are duties in the SPI master core
driver. The following sequence item must be obtained as the
Monitor: A passive type component, by modifying the UVM driver's initial action. Second, we control data transmission.
monitor class, the monitor class is produced. At the virtual Third, the sequence item is finished once the packet is written
interface level, it samples DUT signals and transforms signal- to the UVM analysis port. A fork...join call is used to run the
level actions into transaction-level operations. Monitor class, jobs concurrently. The design of the testbench entails the
drives DUT signals, but does not. creation of a monitor that keeps track of how the DUT interacts
with the testbench. When the protocols are broken, an error is
Agent: The UVM agent class is extended to create the Agent. reported after watching the pin level transaction at the DUT's
Driver, monitor, collector, and sequencer are some examples of outputs. These UVM components are all connected by the
the verification components that the agent incorporates or agent. On the scoreboard, the DUT's actual reaction is
groups. It is used to establish TLM connections between the contrasted with the expected response after predicting the
aforementioned components. The agent has an operational expected output of the DUT in the monitor. The env class
mode that can be either active or passive, and occasionally both. handles the creation and connection of the agent and
Scoreboard: This class accepts data from the monitor and scoreboard.
compares the numbers to what is expected. The reference
model generates the expected values; however, the driver class
can also be used to retrieve a copy.

Environment: The uvm_env class is extended to create the

environment class. Other classes like agents, scoreboards, and
top-level monitors are grouped under this class.

Test: By expanding the uvm_test, the Test is created. It belongs

to the very top class. The Test class, which is the top-level class,
is in responsibility of creating the Testbench, configuring it,
and starting the many components that go into it.

Interface: Interface serves as a link between the verification

environment and the design-under-test, as depicted in Figure
4. All pin-level connections to the DUT are contained within
the interface. A collection of nets or variables make up an Fig5. VIP Development of SPI Architecture
interface.
As listed here, each UVM class includes a variety of simulation
stages.

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Volume 7, Issue 12, December – 2022 International Journal of Innovative Science and Research Technology
ISSN No:-2456-2165
BUILD PHASE: The UVM testbench simulation starts with the
construction phase, which creates instances of each UVM
component.

CONNECT PHASE: Connections are made between the

subcomponents during this phase. Using TLM ports, testbench
connections are established.

ELABORATION PHASE: The elaboration phase involves

checking connections and setting up address ranges, values,
and pointers.

SIMULATION PHASE: Phase one of simulation involves

setting up initial runtime configurations and validating UVM
testbench topology.

RUN PHASE: Run phase is a task-based simulation because of

this it takes more time than other phases. Time 0 begins this
phase.

EXTRACT PHASE: In this stage, to build final statistics, Fig7. Transcript Results
information is gathered from the DUT and the scoreboard.
Waveform results:
CHECK PHASE: It is used to verify that the DUT functioned The AXI bus function model is used by the SPI master and AXI
as expected and to spot any mistakes that may have happened bus function model to communicate. In terms of the AXI
while the test bench was being run. protocol, the read, write, and reset features of the architecture
are its key functions. The sclk signal, which is used to
REPORT PHASE: In the Report phase, simulation results are synchronize communications between the master and slave.
provided for the verification engineer to review. The control registers of the master and slave are both set up
ahead of the transfer. The send and receive signals' sampling
FINAL PHASE: It is used to perform any additional unfinished edges are specified by flags in the control register like tx
tasks that have not yet been handled by the test bench. negedge/rx posedge. These two flags ought to have distinct
values to one another because SPI write output and read input
both happen at the identical single buffer when using a shift
register approach. once each and every SPI register has been
set, the go flag of the control loop must be asserted in order for
the transfer to begin.The testbench makes use of the current
flag transfer to synchronize the watch each element of the
endless loop. Finally, the transaction in progress signal is
emitted, as seen in Figure, after 32 clock cycles, indicating that
the AXI interface can now collect the data.

Fig8. SPI Master to Slave Communication

Fig6. UVM PHASES

VI. RESULTS

Transcript results

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Volume 7, Issue 12, December – 2022 International Journal of Innovative Science and Research Technology
ISSN No:-2456-2165
[2]. S. Sutherland, S. Davidmann, and P. Flake, System
Verilog for Design: A Guide to Using System Verilog for
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[3]. IEEE Standard for Universal Verification Methodology
Language Reference Manual, 2017.
[4]. Design and Verification of Serial Peripheral Interface, by
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[5]. IP Design of Universal Multiple Devices SPI Interface ,
by Tianxiang Liu , Yunfeng Wang.
VII. CONCLUSION AND FUTURESCOPE [6]. S. Simon, SPI Master Core Specification, pp 1-13,
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environment. System Verilog was employed in the project to [8]. K. Fathy and K. Salah, “An Efficient Scenario Based
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