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Simulations Imp Questions

This document contains 50 questions related to simulation for integrated circuit design and testing. Some of the key topics covered include: 1. The basic steps of simulation and its uses for design for test (DFT). 2. The differences between serial and parallel simulation and their uses for debugging mismatches. 3. Types of patterns like chain, basic, clock sequential, and ram sequential patterns. 4. Commands and files used for simulation like read_patterns, testbenches, testvectors, and SDF files. 5. Debugging techniques for patterns, scan chains, and timing issues. 6. Factors that can cause timing violations like setup/hold times and clock skew.

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Mayur Mestry
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1K views1 page

Simulations Imp Questions

This document contains 50 questions related to simulation for integrated circuit design and testing. Some of the key topics covered include: 1. The basic steps of simulation and its uses for design for test (DFT). 2. The differences between serial and parallel simulation and their uses for debugging mismatches. 3. Types of patterns like chain, basic, clock sequential, and ram sequential patterns. 4. Commands and files used for simulation like read_patterns, testbenches, testvectors, and SDF files. 5. Debugging techniques for patterns, scan chains, and timing issues. 6. Factors that can cause timing violations like setup/hold times and clock skew.

Uploaded by

Mayur Mestry
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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Simulations IMP Questions

Created by: Er. Manjeet Singh

1. What is simulation. 30. How can you tell if the patterns were
2. Explain 3 steps of simulation. generated for an EDT design or fastscan
3. What we do in simulation, what is the design.
use of simulation in DFT. 31. What commands should you look for in
4. Difference between serial & Parallel the logfile to see, if there are any
simulation. internal defined clock or pin.
5. Which simulation we use for debugging 32. Explain (i).po.name (ii).chain.name
the mismatch. (iii).v.0.vec (iv).v.cfg (v).v (vi)-
6. What are chain patterns. voptargs (vii)-novoptargs
7. What are basic patterns. 33. Difference between two dft libraries.
8. What are clock sequential patterns. 34. What values we are comparing during
9. What is psd flow. simulation debug.
10. Explain debugDB switch 35. Difference between simulation &
11. Which patterns we are going to deliver Emulation.
to tester (ATE) 36. What are ram sequential patterns.
12. Explain the steps for chain pattern 37. Whether debugging process for
debug. compressed & Bypassed pattern is same.
13. Explain the steps for scan pattern debug. 38. What is setup time & hold time.
14. What is the use of flattened design 39. What violation will occur if setup &
during simulation debug. hold not maintain properly.
15. What are the files we save after atpg. 40. If clock skew is more than half clock
16. Difference between testbench & cycle then how you will avoid the hold
Testvector. violation.
17. Can you write debug_atpg script. 41. If scan chain is broken how you debug.
18. What patterns we load in atpg view 42. What is setup slack equation.
during pattern mismatch debug. 43. What are main causes of simulation
19. What are the two main commands used mismatch.
for simulation debug. 44. Can you write simulation run script used
20. Difference between timing & No timing in questasim.
simulation. 45. How do you design a clock gating
21. What is sdf file. circuit which is glitch free.
22. What is c6 drc violation mismatch. 46. What is critical path , false path & multi
23. What is T24 drc violation mismatch. cycle path.
24. Input/output files for simulation. 47. In your design if you have both setup &
25. How to handle BB during simulations. hold time violation, which one you
26. What pattern buffer does read_patterns resolve first & why.
place the patterns into internal or 48. Adding lockup latch, is it helps to avoid
external. hold time violation.
27. What is preshift & postshift 49. What is difference between RTL & Gate
28. What are the issues you faced during level simulation
notiming simulation. 50. What is the difference between zero
29. What are the issues you faced during delay & unit delay simulation.
timing simulation.

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