Advanced verification of Single precision floating

point ALU
Varunkumar J [1], Anusha R [2], Shreenidhi S [3], Vishwas S [4]
Department of Electrical & Electronics Engineering
PES Institute of Technology and Management, NH-206, Sagar Road, Shivamogga District-577204, Karnataka
Email: [email protected], [email protected], [email protected], [email protected]

ABSTRACT-- Arithmetic is the basic operation in II. FLOATING POINT NUMBERS

everyday life which includes operations such as addition,
subtraction and multiplication. To keep a check on the The IEEE Standard for 32-bit Single precision
proper working on these arithmetic operations, Floating Point Arithmetic will be used throughout the
Arithmetic logical unit (ALU) is used, and it is the most work. The single precision format is shown in Figure-1.
important element of a system. In this paper it is discussed
about the Verification of DUT of Single precision Floating-
point Arithmetic logical unit (ALU) in System Verilog
language using Questa Sim software and the goal is to
achieve maximum Functional Coverage.

KEYWORDS: ALU, IEEE standard 754, DUT, System

Verilog, Implicit bit, sign bit, Exponent, Mantissa.

I. INTRODUCTION
Figure-1
Arithmetic is a basic operation in everyday life
Numbers in this format are composed of the following
which include operations such as addition, subtraction
three elements:
and multiplication. To keep a check on proper working
1. Sign bit(S)
on these arithmetic operations, ALU is the most
It is the first bit of the binary representation, where “0”
important element of the system.
represents a Positive number and “1” represents a
But for most of the applications we need floating Negative number.
point numbers in order to provide high precision and Example: 1 10000010 10101000000000000000000 this
represent very small or very large numbers. Hence is a Negative number.
“Floating Point ALU (FPU)” was designed. 0 10000011 10100000000000000000000 this
An Arithmetic logic unit (ALU) is a digital is a Positive number.
electronic that performs arithmetic and bitwise logical
operations on integer binary numbers. This is contrast 2. Exponent(E)
to a floating-point unit (FPU), which operates on The next 8 bits represent the Exponent. In 32-bit
floating point numbers. Multiple ALUs are incorporated floating-point representation a unique number i.e., 127
in a single CPU. is used. It is known as “Bias”. This Bias number is
determined by 2k-1 -1, where ‘k’ is the number of bits in
Floating-point numbers are widely used in many the exponent field (for 32-bit FPU k is 8).
applications. ALU is a block in a microprocessor that Bias =127 for 32-bit FPU. (28-1 -1 = 128-1 = 127)
handles arithmetic operations and FPU is a coprocessor Example: 0 10000011 10100000000000000000000
which handles the floating-point operations. Some 10000011 – the decimal value of exponent part is 131.
CPUs have more than one floating-point unit (FPU) that By doing Bias operation on exponent i.e., 131-127 = 4.
handles floating-point operations.
This is designed by one person or more using a 3. Mantissa(M)
particular logic, but while using we come across plenty The mantissa will be of 24 bits and one bit will be an
of test cases in which it may fail to perform. Therefore, “Implicit bit” which is ‘1’ and the other 23 bits will be
verification of the design has to be done for the given the real mantissa which has to determined.
design specifications in which maximum testcases Example: 0 10000011 10100000000000000000000
should be passed to obtain maximum Coverage. The mantissa is calculated as (without Implicit bit),
Compared to the process of developing a Design unit, 1*(1/2) +0*(1/4) +1*(1/8) +0*(1/16) +…. = 0.625
the process of verifying the Design unit will require Thus, the mantissa will be (with implicit bit)
more time and resources. The verification process can 1+0.625 = 1.625.
be started as soon as the design specification is The decimal number is:
developed. The verification process can be done (Sign) (Exponent)*(Mantissa)
parallelly with the design process. i.e., (+) (24) *(1.625) = 26.

978-1-7281-0418-8/19/$31.00©2019 IEEE 365

Authorized licensed use limited to: College of Engineering - THIRUVANANTHAPURAM. Downloaded on December 18,2022 at 08:42:41 UTC from IEEE Xplore. Restrictions apply.
 III. METHODOLOGY This is a “Golden model” that replicates the DUV.
Building a Verification Environment: It generates the reference results which is used for
comparison. It receives the inputs from the driver
through a mailbox and sends the outputs to the
scoreboard through another mailbox.

9. Scoreboard
It receives the golden values from reference model
through a mailbox and also the outputs (actual
results) from monitor through a mailbox. It
compares both the values and generates a report.

IV. OPERATIONS

1. Addition operation/ Subtraction operation

Addition or Subtraction operation will have
The figure shows the block diagram of general form of two operands. The sign bit of both operands can be
Testbench. ‘0’ or ‘1’. To perform addition operation, firstly
the exponents of operands are biased (i.e., subtract
Verification environment consists of the following the exponent with 127), the exponent value of both
blocks. operands should be checked, whether they are
1. Top or program equal or not. If the exponents are equal then
This is the top most module of the SV testbench, perform bitwise addition/subtraction on the
clocks and reset are generated here. Interface block mantissa of both the operands depending upon the
will be inside top. operation to be performed.
If the exponents are not equal, then the bigger
2. Test
value exponent is kept as it is and then take the
Test cases are written in this module. In here the
difference of both the exponents and perform right
Environment is instantiated and built.
shift operation (with the value of difference number
of times) on the mantissa of smaller exponent
3. Environment including the implicit bit. Now that the exponents
In this module the generator, driver, monitor, are equal, perform bitwise addition/subtraction on
reference model and scoreboard are instantiated. the mantissa of both the operands. After the
operation resultant is checked for overflow.
4. Packet or Transaction
All the inputs to Design Under Verification (DUV) Now the final value will be represented as, the
are written inside the transaction class, excluding sign bit will be either ‘0’ or ‘1’ depending on the
the clock and reset signals that are generated in the given inputs. The exponent part will be biased (i.e.,
top module. add 127 to the exponent) and the mantissa obtained
Constraints to the inputs are given as per after bitwise addition will be the resultant value of
requirement. Constraints are given such that it mantissa.
would also cover the special cases as well, which in
turn will be helpful for achieving 100% coverage. 2. Multiplication operation

5. Generator In Multiplication operation, there will be two

This is written inside a Class, it generates the operands. To perform multiplication, firstly the
constrained random inputs. sign bit of both operands can be ‘0’ or ‘1’. The sign
bits of both operands should be “XORed”.
6. Driver Assuming there are two operands ‘a and b’, the
It receives the generated values from generator biasing of the exponents can be done by using the
through a mailbox drives it to the DUV through a equation “Er=Ea+Eb-127”, where “Er” is the
Virtual interface. It sends the received values from exponent of resultant, “Ea” is the exponent of ‘a’
generator to the reference model through another operand and “Eb” is the exponent of ‘b’ operand.
mailbox. Now the mantissa of both the operands should be
multiplied. After multiplication the resultant (Er)
7. Monitor will be of 46 bits (i.e., 45:0), to obtain the final
Monitor receives the outputs of DUV through a value of mantissa, the higher 23 bits of “Er” is
virtual interface and sends it to the scoreboard taken (i.e., 45:23). The final value will be
through a mailbox. represented as, the XOR of two sign bits, the
exponent as per the equation and then the mantissa.
8. Reference model
366

Authorized licensed use limited to: College of Engineering - THIRUVANANTHAPURAM. Downloaded on December 18,2022 at 08:42:41 UTC from IEEE Xplore. Restrictions apply.
 After the operation resultant is checked for Functional coverage is a feature from which the
overflow. measurement can be made as how much of the design
specification has been exercised in verification.
3. Special cases in Floating point operations.
The special cases include “zero, normal, 2. VERIFICATION PROCESS
subnormal, NaN (Not a Number) and infinity”. The verification process includes, collection of
Before performing the normal operations DUT (Device Under Test), building a SystemVerilog
(addition or subtraction or division), the operands Environment for verification. The Environment
are checked for special cases. If there exists a includes blocks shown in block diagram. The process of
special case the normal operation will not be verification starts by providing the number of testcases
performed, rather a special output will be displayed required. Then the random data generated will be sent
as per the special case. to driver block as per the number of testcases. The
driver will drive these data to the DUT and also to the
V. VERIFICATION METHODOLOGY reference model block.
1. TEST BENCH COMPONENTS The DUT will perform its operations as per its
The key elements in the System Verilog Test bench program, and will send its response through its output.
used here are: The Reference model will be programmed as
i. Classes per the DUT’s specifications. Therefore, the Reference
ii. Scoreboard block will perform its operations with the given inputs
iii. Generators and will send the response through its output (the input
iv. Interface and output can be saved if required in some cases). The
v. Mailbox output or response from Reference model is known as
vi. Functional coverage “Golden values”.
The Monitor block is connected to DUT’s
Classes output and hence the Monitor will get the output.
Classes are written in SystemVerilog and utilize the
same software techniques as would be present in a C++ The Scoreboard is connected to both Reference
style environment. Classes with the help of object model and Monitor. Therefore, the scoreboard will get
handles allow objects to be dynamically created, the outputs from monitor and reference block. The
deleted, assigned and accessed. Scoreboard will compare the monitor’s output with the
Golden values. After comparing, it verifies if the
Scoreboard response from DUT is matching with our Golden
Scoreboard has two mailboxes, the data from these two values. If they are same, then it can be said that the
mailboxes are compared and if they don’t match, then DUT is working as per the given specifications.
the errors will be dealt with.
The coverages will show the testcases that
Generators have been met. It will show the scenarios where the
Here the Random pattern data are generated and they testcases are not met. It will help to see whether the
are sent as inputs to two main blocks i.e., Design under corner cases are covered or not.
test (DUT) and Golden value generator. In some cases,
the data is constrained so as to limit the amount of non- CONCLUSION
useful data generated. The Verification environment has been built in
SystemVerilog (SV) language for the verification of the
Interface DUT (Design program) of the Single Precision (32 bit)
Interface is used to communicate between blocks. floating-point ALU for addition, subtraction and
multiplication operations using QuestaSim software.
Mailbox IEEE-754 standard based floating-point representation
Mailbox is a communication medium which transfers has been used. We developed the test cases to achieve
data between the two blocks. Mailboxes can be created 100% functional coverage. From this, it can be seen that
having either a bounded or unbounded queue size. by performing Verification on the DUT, the operations
of the DUT is verified for all the test cases as per the
Functional coverage specifications.

367

Authorized licensed use limited to: College of Engineering - THIRUVANANTHAPURAM. Downloaded on December 18,2022 at 08:42:41 UTC from IEEE Xplore. Restrictions apply.
 OUTPUT WAVEFORMS
ADDITION

SUBTRACTION

MULTIPLICATION

REFERENCES
[1] IEEE–754[2008]: This standard specifies interchange and [7] Design and Simulation of Floating point Pipelined ALU using
arithmetic formats and methods for binary and decimal floating- HDL and IP core generator- Itagi Mahi,S.S.Kerur, Department
point in arithmetic. of Electronics and communication Engineering, SDMCET,
Dharwad, India.
[2] IRJET research paper engineering students of Abha Gaikwad
college of Engineering, Nagpur, maharashtra. [8] Single precision Floating point ALU- Pradnya A. Shengale,
vidya Dahake, Mithilesh Mahendra, EC, Abha Gaikwad patil
[3] The Development of Advanced Verification Environment using college of Engineering and technology, Nagpur, Maharashtra,
System Verilog – Martin Keaveney, Anthohny McMahon, Nial India.
o’keeffe, kevin keane, James O’Reilly, Department of
Electronic Engineering, GMIT, Dublin road, Galway. [9] Simulation and synthesis model for addition of single precision
floating point numbers using Verilog – Ravi payal, school of
[4] Floating Point Arithmetic Unit Using Verilog Lalita Gangwar1 electronics, CDAC, Noida.
and Rajan Chaudhary Department of Electronics and
Communication, Future Institute of Engineering and [10] Questa Sim user’s manual.
Technology Bareilly, India.
[11] SystemVerilog for verification – Springer.
[5] Floating point Arithmetic unit using Verilog- Lalitha Ganagwari
and Rajan Chaudhary, Department of Electronics and
communication, Future Institute of Engineering and technology,
India.

[6] Implementation of 32-bit Binary Floating-point Adder using

IEEE-754 single precision format- Rupali Dhobale, Soni
Chaturvedi, ECE, PIET, Nagpur, India.

368

Authorized licensed use limited to: College of Engineering - THIRUVANANTHAPURAM. Downloaded on December 18,2022 at 08:42:41 UTC from IEEE Xplore. Restrictions apply.