Techno College of Engineering Agartala

Study Notes
Subject: Embedded Systems
Code: PC MI 405
Arm7 Architecture

The ARM Architecture

 Arithmetic Logic Unit

This article covers the below mentioned components.

The ARM processor conjointly has other components like the Program status register, which contains the processor
flags (Z, S, V and C). The modes bits conjointly exist within the program standing register, in addition to the
interrupt and quick interrupt disable bits; some special registers: Some registers are used like the instruction,
memory data read and write registers and memory address register.

Priority encoder: The encoder is used in the multiple load and store instruction to point which register within the
register file to be loaded or kept.

Multiplexers: several multiplexers are accustomed to the management operation of the processor buses. Because of
the restricted project time, we tend to implement these components in a very behavioral model. Each component is
described with an entity. Every entity has its own architecture, which can be optimized for certain necessities
depending on its application. This creates the design easier to construct and maintain.

Arithmetic Logic Unit (ALU)

The ALU has two 32-bits inputs. The primary comes from the register file, whereas the other comes from the shifter.
Status registers flags modified by the ALU outputs. The V-bit output goes to the V flag as well as the Count goes to
the C flag. Whereas the foremost significant bit really represents the S flag, the ALU output operation is done
by NOR ed to get the Z flag. The ALU has a 4-bit function bus that permits up to 16 opcode to be implemented.

Booth Multiplier Factor

The multiplier factor has 3× 32-bit inputs and the inputs return from the register file. The multiplier output is
barely 32-Least Significant Bits of the merchandise. The entity representation of the multiplier factor is shown in the
above block diagram. The multiplication starts whenever the beginning 04 input goes active. Fin of the output goes
high when finishing.

Booth Algorithm

Booth algorithm is a noteworthy multiplication algorithmic rule for 2’s complement numbers. This treats positive
and negative numbers uniformly. Moreover, the runs of 0’s or 1’s within the multiplier factor are skipped over
without any addition or subtraction being performed, thereby creating possible quicker multiplication. The figure
shows the simulation results for the multiplier test bench. It’s clear that the multiplication finishes only in16
clock cycle.

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 Techno College of Engineering Agartala
Study Notes
Subject: Embedded Systems
Code: PC MI 405
Barrel Shifter

The barrel shifter features a 32-bit input to be shifted. This input is coming back from the register file or it might be
immediate data. The shifter has different control inputs coming back from the instruction register. The Shift field
within the instruction controls the operation of the barrel shifter. This field indicates the kind of shift to be
performed (logical left or right, arithmetic right or rotate right). The quantity by which the register ought to be
shifted is contained in an immediate field within the instruction or it might be the lower 6 bits of a register within the
register file.

The shift_val input bus is 6-bits, permitting up to 32 bit shift. The shift type indicates the needed shift sort of 00, 01,
10, 11 are corresponding to shift left, shift right, an arithmetic shift right and rotate right, respectively. The barrel
shifter is especially created with multiplexers.

Control Unit

For any microprocessor, control unit is the heart of the whole process and it is responsible for the system operation,
so the control unit design is the most important part within the whole design. The control unit is sometimes a pure
combinational circuit design. Here, the control unit is implemented by easy state machine. The processor timing is
additionally included within the control unit. Signals from the control unit are connected to each component within
the processor to supervise its operation.

ARM7 Functional Diagram

The final thing that must be explained is how the ARM will be used and the way in which the chip appear. The
various signals that interface with the processor are input, output or supervisory signals which will be used to control
the ARM operation.

ARM Functional Diagram

ARM Microcontroller Register Modes

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 Techno College of Engineering Agartala
Study Notes
Subject: Embedded Systems
Code: PC MI 405
the memory by an address. The ARM cortex-M3 consists of 37 register sets wherein 31 are general purpose
registers and 6 are status registers. The ARM uses seven processing modes to run the user task.

 USER Mode
 FIQ Mode
 IRQ Mode
 SVC Mode
 UNDEFINED Mode
 ABORT Mode
 Monitor Mode

USER Mode: The user mode is a normal mode, which has the least number of registers. It doesn’t have SPSR and
has limited access to the CPSR.

FIQ and IRQ: The FIQ and IRQ are the two interrupt caused modes of the CPU. The FIQ is processing interrupt
and IRQ is standard interrupt. The FIQ mode has additional five banked registers to provide more flexibility and
high performance when critical interrupts are handled.

SVC Mode: The Supervisor mode is the software interrupt mode of the processor to start up or reset.

Undefined Mode: The Undefined mode traps when illegal instructions are executed. The ARM core consists of 32-
bit data bus and faster data flow.

THUMB Mode: In THUMB mode 32-bit data is divided into 16-bits and increases the processing speed.

THUMB-2 Mode: In THUMB-2 mode the instructions can be either 16-bit or 32-bit and it increases the
performance of the ARM cortex –M3 microcontroller. The ARM cortex-m3 microcontroller uses only THUMB-2
instructions.

Some of the registers are reserved in each mode for the specific use of the core. The reserved registers are

 Stack Pointer (SP).

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 Techno College of Engineering Agartala
Study Notes
Subject: Embedded Systems
Code: PC MI 405
The reserved registers are used for specific functions. The SPSR and CPSR contain the status control bits which are
used to store the temporary data. The SPSR and CPSR register have some properties that are defined operating
modes, Interrupt enable or disable flags and ALU status flag. The ARM core operates in two states 32-bit state or
THUMBS state.