Table of Content

1 INTRODUCTION

2 INTERCONNECTION STRUCTURES
The bus and Various Multiple-Bus Structures
Classification of Bus Lines
Bus Operation
Bus architecture
Elements of Bus Design
Bus types
Method of Arbitration
Timing

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INTRODUCTION

Introduction
The internal structure of the computer consists four main structural
components:
Central processing unit (CPU): Controls the operation of the
computer and performs its data processing functions; often simply
referred to as processor.
Main memory: Stores data.
I/O: Moves data between the computer and its external
environment.
System interconnection: mechanism that provides communication
among CPU, main memory, and I/O.
Thus, there must be paths for connecting the modules.
The collection of paths connecting the various modules is called the
interconnection structure.

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INTERCONNECTION STRUCTURES

Interconnection Structures
1 The bus and various multiple-bus structures.
2 Point-to-point interconnection structures with packetized data
transfer.

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The bus and Various Multiple-Bus Structures

A bus is a communication pathway connecting two or more devices.

A key characteristic of a bus is that it is a shared transmission
medium. Multiple devices connect to the bus, and a signal
transmitted by any one device is available for reception by all other
devices attached to the bus.
If two devices transmit during the same time period, their signals will
overlap and become garbled. Thus, only one device at a time can
successfully transmit.
Typically, a bus consists of multiple communication pathways, or
lines. Each line is capable of transmitting signals representing binary
1 and binary 0.
A bus that connects major computer components (processor, memory,
I/O) is called a system bus.

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Computer System

Figure: Computer System

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CLASSIFICATION OF BUS LINES

Classification of Bus Lines

The Bus lines can be classified into three functional groups
1 Data lines
2 Address lines
3 Control lines

Figure: Bus Interconnection Scheme

In addition, there may be power distribution lines that supply power to the
attached modules.

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CLASSIFICATION OF BUS LINES

1 Data lines provide a path for moving data among system modules.
These lines, collectively, are called the data bus.
The data bus may consist of 32, 64, 128, or even more separate lines.
The number of lines are being referred to as the width of the data bus.
Each line can carry only 1 bit at a time.
The number of lines determines how many bits can be transferred at a
time.
2 Address lines
3 Control lines

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CLASSIFICATION OF BUS LINES

1 Data lines
2 Address lines Are used to designate the source or destination of the
data on the data bus.
The width of the address bus determines the maximum possible
memory capacity of the system. Furthermore, the address lines are
generally also used to address I/O ports.
3 Control lines

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CLASSIFICATION OF BUS LINES

1 Data lines
2 Address lines
3 Control lines are used to control the access to and the use of the
data and address lines.
Because the data and address lines are shared by all components,
there must be a means of controlling their use.
Control signals transmit both command and timing information
among system modules

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CLASSIFICATION OF BUS LINES(Control line)

The control lines include the following lines for:

Memory write Bus grant

Memory read Interrupt request
I/O write
Interrupt ACK
I/O read
Transfer ACK Clock
Bus request Reset

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Bus Operation

Bus Operation
The following are Operations of the bus :
If a module wishes to send data , the following are two steps to be
followed:
1 Obtain the use of the bus.
2 Transfer data via bus.
If one module wishes to request data from another module , the
following steps are followed:
1 Obtain the use of the bus.
2 Send a request over the appropriate control and address lines and wait
the response.

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Bus architecture

Multiple-Bus Hierarchies
If too many devices are connected to the same bus, the performance will
suffer
Here are two main causes:
Generally, the more devices attached to the bus, the more the length
of the bus increases, therefore an increase in the propagation delay.
If data transfer demand approaches the bus capacity , the bus may
become a bottleneck.
Consequently most of computer system bus-based use multiple buses
generally laid out in a hierarchy , to overcome the above problems

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Bus architecture

An expansion bus interface buffers data transfers between the system bus
and the I/O controllers on the expansion bus.
This arrangement allows the system :
To support a wide variety of I/O devices.
At the same time insulate memory-to-processor traffic from I/O traffic

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Traditional Bus Architecture

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Mezzanine Approach

The traditional bus architecture is reasonably efficient but begins to break

down as higher and higher performance is seen in the I/O devices. To
overcome these growing demand industries taken a common approach to
build high-speed bus
Closely integrated with the rest of the system
Need only a bridge between the processor’s bus and the high-speed
bus
This arrangement is sometimes known as a mezzanine architecture
Advantage is that high-speed devices are brought closer to processor
and at the same time is independent of the processor
Therefore:
differences in processor and high-speed bus and signal line definitions
are tolerated.
Changes in processor architecture do not affect the high-speed bus, and
vice versa.

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Mezzanine Approach

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Elements of Bus Design

Elements of Bus Design

There are few basic parameters that serve to classify and differentiate
buses even if a variety of different bus implementations exist.
Bus types : Bus lines can be separated into two generic types
1 Dedicated
* A functional dedication is the use of separate dedicated address and
data lines, which is common on many buses
2 Multiplexed
* Using the same lines for multiple purposes
* Address valid or data valid control line
* Advantages
-Use of fewer lines, which saves space and, usually, cost
* Disadvantages
-More complex circuitry is needed within each module.
-Potential reduction in performance

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Elements of Bus Design (Physical dedication)

Refers to the use of multiple buses, each of which connects only a

subset of modules
- Physically separating buses and controlling them with a ”channel
changer”
Advantages
- There is high throughput, because there is less bus
contention.(Faster)
Disadvantages
-There is the increased size and cost of the system.

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Method of Arbitration

More than one module may need control of the bus, however only one
module can transmit over a bus at time, to manage this there is a need of
some Arbitration Methods , classified as follows:
centralized arbitration
1 Single hardware device controlling bus access.
2 The device may be a separate module or May be part of CPU
distributed arbitration
1 No central control.
2 Access control logic to all modules.
3 Modules act together to share the bus.
The purpose behind both methods of arbitration is to designate one device
either the CPU or an I/O module , as master. This one may initiate a data
transfer with some other device.

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Timing(Synchronous Timing)

Timing
Timing mention the coordination way of the event on the bus. buses apply
one of the following timing:
Synchronous Timing

- Events occurrence on the bus is - All event start at the beginning of

determined by a clock. a clock cycle.
- Control Bus includes clock line
- Usually sync on leading/rising
- A single 1-0 cycle is a bus cycle
edge.
- All device on the bus can read the
clock line. - Usually a single cycle for an event

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Synchronous Bus Timing

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Asynchronous Timing
Asynchronous Timing
Asynchronous Timing Here the occurrence of the event on a bus follows
and depends on the occurrence of a previous event, and an asynchronous
bus has no system clock. In the simple read example we have that :

- The CPU places address and acknowledged line signal the

status signals on the bus. availability of the data to the
- Once signals are stabilized ,The CPU.
CPU issue a read command to - The read signal is canceled, once
indicate that a valid address and the master has read the data
control signals are present. from the data line.
- The concerned memory decode - The memory module drop the
the address and respond by data and acknowledge lines.
placing the data on the data line. - The master removes the address
- After stabilizing the data line , information after the
the memory module assert the acknowledge line is dropped.
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Asynchronous Timing - System bus read cycle

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Asynchronous Timing - System bus write cycle

In a simple asynchronous write operation we have :

- Simultaneously the master places the data on data line and puts
signals on the status and address lines
- The Memory modules copy the data from the data line and assert the
acknowledge line as his response.
- The master drops the write signal and the memory module drops the
acknowledge signal.

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Asynchronous Timing - System bus write cycle

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Timing Conclusion

Timing Conclusion
Synchronous timing is simpler to implement and test.
Synchronous timing is less flexible than asynchronous timing.
In Synchronous timing All devices can read clock line
With asynchronous timing, a mixture of slow and fast devices, using
older and newer technology, can share a bus.

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Thank you

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References

William Stallings, Computer Organization and Architecture Designing

for Performance Ninth Edition. Pearson, 2006.
Lizy Kurian John. Bus Architectures. Paper

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