Experiment: 1

Aim: (a) Introduction to basic logic gates using discrete components.

(b) Study various digital ICs & verify the truth tables. (AND, OR, NOT, NAND,
NOR, EX-OR gates)

Apparatus: IC 7408, 7432, 7404, 7400, 7402, 7486, Trainer kit, connecting wires

Theory: Logic gates are the fundamental building blocks of digital systems. The name
logic gate is derived from the ability of such a device to make decisions, in the
sense that it produces one output level when some combination of input levels
are present, and a different output level when other combination of input levels
are present. There are three basic types of logic gates AND, OR and NOT.
Inputs and outputs of logic gates can occur only in two levels. These two levels
are termed HIGH and LOW or TRUE and FALSE or ON and OFF or simply 1 and 0.
A table, which lists all the possible combination of input variables and the
corresponding outputs is called a truth table, logic 1 corresponds to +5V and
logic 0 presents 0V.
The AND Gate:
The AND gate has two or more inputs but only one output. The output assumes
the logic 1 state when each one of its input is at logic 1 state. The output assumes
the logic 0 state even if one of its inputs is at logic 0 state. The AND gate may,
therefore, be defined as a device whose output is 1, if and only if all its input are
1.
The logic symbol and truth table of two input AND gates is shown in fig. Note that
the output is 1 only when all the inputs are 1. The symbol for the AND operation
is “.”.
Truth Table
A A B X
X 0 0 0
0 1 0
B 1 0 0
1 1 1

A O/p

Discrete AND gate may be realized using diodes as shown in fig. The two inputs
A and B to the gates may be either 0 or 1.
In the diode AND gate, when A = +5V and B = +5V, both the diodes D1 and D2 are
off. So current flows through R and therefore No voltage drop occur across
resistor R. Hence the output X =5V. When A=0V or B=0V, the corresponding diode
D1 and D2 is ON or both diodes are on and act as a short circuit, therefore the
output X = 0V.
The OR gate: -
Like an AND gate, OR gate have two or more inputs but only one output. The
output assumes the logic 1 state, if one of its inputs is in logic 1 state. Its output
assumes the logic 0 state, only when each one of its inputs is in logic 0 state.
The logic symbol and truth table of two input OR gate is shown in fig. The symbol
for the OR operation is “+”
Truth Table
A A B X
X 0 0 0
0 1 1
B 1 0 1
1 1 1

1k D1
o/p
A o/p

1k D2
B
1kR

In the Diode OR gate, when A = 0V and B = 0V, both diodes D1 and D2 are OFF,
No current flows through and so no voltage drop across R. Hence the output
voltage X = 0V. When A = +5V and B = +5V, the corresponding diode D1 and D2
are ON and act as a short circuit therefore output X = +5V.

The NOT gate: -

A NOT gate also called as Inverter, has only one input and one output. It is a device
whose output is always the complement of its input. The output of the NOT gate
is assuming 0 when its input is 1 and vice versa. The logic symbol and truth table
of the NOT gate is shown into the figure.
Truth Table
A X
A X 0 1
1 0

The logic symbol for the NOT gate is “−” (Bar). The discrete NOT gate can be
realized by using the transistor is as shown in fig. When input A = 0V, transistor
T is reverse biased and remain OFF. Hence the output voltage X = 5V. When the
input A = +5V, T is ON and therefore X = 0V.

The NAND gate:

NAND means NOT AND, i.e. the AND output is inverted. So a NAND gate is a
combination of AND gate and a NOT gate. The expression for the NAND gate is
X = (A.B)’ The logic symbol and truth table for two inputs NAND gate is shown in
fig.
 A Truth Table
X A B X
0 0 1
B
0 1 1
1 0 1
The NOR gate: 1 1 0
NOR means NOT OR, i.e. the OR operation is inverted. So a NOR gate is a
combination of OR gate and NOT gate. The expression for the output of the NOR
gate is a X = (A + B)’
The logic symbol and truth table for two input NOR gate is shown in fig.
Truth Table
A B X
A 0 0 1
X
0 1 1
B 1 0 1
1 1 0
The NAND and NOR gate are said to be universal gates because any Boolean
function or Digital system can be implemented with it. To show that any Boolean
function can be implemented with NAND and NOR gates, we need only show that
the logic operations AND, OR and NOT can be implemented with NAND and NOR
gates. The figure below shows the implementation.

The EX-OR gate:

Like an AND gate, OR gate, EX-OR (exclusive OR) gate have two or more inputs
but only one output. The output assumes the logic 1 state, if and only if one of its
inputs is in logic 1 state. Its output assumes the logic 0 state, when both the inputs
assume the logic 0 state or the logic 1 state.
The logic symbol and truth table of two input X-OR gate is shown in fig. The
symbol for the Ex-OR operation is “ + “
Truth Table
A B X
0 0 0
0 1 1
1 0 1
1 1 0

The NAND and NOR gate are said to be universal gates because any Boolean
function or Digital system can be implemented with it. To show that any Boolean
function can be implemented with NAND and NOR gates, we need only show that
the logic operations AND, OR and NOT can be implemented with NAND and NOR
gates.
 Logic gates IC Pin diagrams:

Conclusion
 Review Questions

1. What are the two voltage levels normally used to represent binary digits 0 & 1?
2. What do you mean by a logic gate? name the basic gates.
3. What do you mean by a positive logic system & negative logic system?
4. Give IC number of the following TTL gates: - AND, OR, NOT, XOR, NOR & NAND
5. Justify the sentence, “A positive logic AND gate is negative logic OR gate and vice versa.
6. What is truth table?
7. Which logic gate is called (a) any or all gate (b) all or nothing gate (c) inverter?
8. Name the Universal gates? Define the functions performed by them.
9. Which gates can be used as inverter in addition to NOT gate and how?
10. Draw the two equivalent symbols for the two input NAND gate & NOR gate.
11. How can we convert the Ex- OR gate into the NOT gate?
12. Design Ex – OR gate by using the NAND & NOR gate.
 Experiment: 2

Aim : Implement the following Boolean expression using NAND gates only.
[1] F1=ABC+A’B’C+A’BC+ABC’+A’B’C’
[2] F2=(A+C+D)(A+C+D’)(A+C’+D)(A+B’)
[3] F3=(BC’+A’D)(AB’+CD’)
[4] F4=(AB)(A+B)’+(CD)’
[5] F5=ABC+AB’(A’C’)’
[6] F6=AC+ABC+A’C+A’B’C+BC
[7] F7=AB’(A+C)+AC(A’+C’)
[8] F8=(A(AB)’)’(B(AB)’)’

Apparatus: IC 7400, 7410 NAND gates, Trainer kit, connecting wires.

Theory : Boolean algebra is a system of mathematical logic, which uses capital or small
letters of English alphabet to represent variables or a function of the variables.
In Boolean algebra, there is no subtraction and division. Only logical addition
and logical Multiplication are performed. There are no fractions or negative
numbers in Boolean algebra.
ASSOCIATIVE LOW : A + (B+C) = ( A + B ) + C ;
(A.B) C = A (B.C)

DISTRIBUTIVE LAW : A ( B + C ) = AB + AC ;
A + BC = (A + B) ( A + C)
IDEMPOTNCE LAW : A.A = A ; A + A = A

NEGATION LAW : A.A’ = 0 ; A + A’ = 1

DOUBLE NEGATION LAW : (A’)’ = A

IDENTITY LAW : A. 1 = A ; A + 1 = 1

NULL LAWS : A. 0 = 0 ; A + 0 = A

ABSORPTION LAWS : A + AB = A ; A (A + B) = A

CONSENSUS LAW : AB + A’C + BC = AB + A’C

TRANSPOSITION THEOROM : AB + A’C = ( A + C ) ( A’ + B)

De MORGON’s THEOROM : ( A + B )’ = A’ B’ ; ( A.B )’ = A’ + B’

[1] F1=ABC+A’B’C+A’BC+ABC’+A’B’C’
=BC (A+A’) +A’B’ (C+C’) +ABC’
=BC + A’B’ + ABC’
=A’B’ + B (C+AC’)
=A’B’ + B (A+C)
=A’B’+AB+BC
 U1A
Key = A

74LS00N
Key = B
U4A

U2A
Key = A 74LS10N
74LS00N
Key = B
U3A
Key = B

74LS00N
Key = C

[2] F2= (A+C+D) (A+C+D’) (A+C’+D) (A+B’)

= (A’C’D’+A’C’D+A’CD’+A’B)’
= (A’C’ (D’+D) +A’CD’+A’B)’
= (A’ (C’+CD’) +A’B)’
= (A’ (C’+D’) +A’B)’
= (A’C’+A’D’+A’B)’
= (A’ (C’+D’+B))’
= A+CDB’
U1A

Key = A U2A
74LS00N
U4A
Key = B 74LS00N

Key = C 74LS10N

Key = D

[3] F3= (BC’+A’D) (AB’+CD’)

= BC’AB’+BC’CD+A’DAB’+A’DCD’
=0

[4] F4= (AB) (A+B)’+ (CD)’

= AB (A’B’) + C’+D’
= C’+D’
U1A
U3A
Key = C
74LS00N
U2A
74LS00N

Key = D
74LS00N

[5] F5=ABC+AB’ (A’C’)’

=ABC+AB’ (A+C)
=ABC+AB’A+AB’C
=ABC+AB’ (1+C)
=A (BC+B’)
=A (B’+C)
=AB’+AC
 Key = A
U1A
U3A
Key = C 74LS00N
U2A
74LS00N
Key = A

74LS00N
Key = B

[6] F6=AC+ABC+A’C+A’B’C+BC
=AC (1+B) +A’C (1+B’) +BC
=C (A+A’) +BC
=C (1+B)
=C

[7] F7=AB’ (A+C) +AC (A’+C’)

=AB’+AB’C
=AB’ (1+C)
=AB’

Key = A

74LS00D 74LS00D
Key = B

[8] F8= (A (AB)’)’ (B (AB)’)’

= (A’+AB) (B’+AB)
= (A’+B) (A+B’)
= AB+A’B’
Key = A
U1A
U3A
Key = B 74LS00N
U2A
74LS00N
Key = A

74LS00N
Key = B

Conclusion
 Review Questions

1. Simplify each of the following function and implement them with NAND gate.

(a) A + B [AC + (B + C’) D]

(b) A [B + C’ (AB + AC’)’]

2. Implement the following functions with NOR gates.

(a) AB’C + B + BD’ + ABD’ +A’C

(b) AB + AB’C + BC’
 Experiment: 3

Aim: Simplifying the given Boolean function using K-map & implement it using NAND
gate only.
i. F(A,B,C,D)=∑(1,3,5,6,7,8,9,10,11,13,14,15)
ii. F(A,B,C,D)=∑(1,2,8,9,10,12,13,14)
iii. F(A,B,C,D)=∑(1,7,10,11,13) + ∑ 𝑑(5,8,15)

Apparatus: IC 7400, 7410 NAND gates, Trainer kit, connecting wires

Simplifying the given Boolean function using K-map & implement it using NAND gate only
(i) F(A, B, C, D)=∑(1,3,5,6,7,8,9,10,11,13,14,15)

CD
AB 00 01 11 10
00 1 1
01 1 1 1
11 1 1 1
10 1 1 1 1

F=D+AB’+BC

Key = A

74LS00D
Key = B

U4A
Key = B

74LS00D 74LS10N
Key = C

Key = D
74LS00D

(ii) F(A,B,C,D)=∑(1,2,8,9,10,12,13,14)

CD
AB 00 01 11 10
00 1 1
01
11 1 1 1
10 1 1 1

F=AC’+AD’+B’C’D+B’CD’
 (iii) F(A,B,C,D)=∑(1,7,10,11,13) + ∑ 𝑑(5,8,15)

CD
AB 00 01 11 10
00 1
01 X 1
11 1 X
10 X 1 1

F=BD+A’C’D+AB’C
Key = B

74LS00D
Key = D

Key = A

Key = C
74LS10N 74LS10N
Key = D

Key = A

Key = B
74LS10N
Key = C

IC 7410 Pin Diagram:

 Review Questions

1. What do you mean by a K – map? Name its advantages and disadvantages.

2. What do you mean by don’t care condition?
3. What do you mean by min-terms & max-terms of Boolean expressions?
4. Convert to min-terms:

a) A + B’C’
b) ABC + AB + DC + D’
c) A’ + B + CA

5. Convert to maxterms:

a) A (B’+ C)
b) (A’ + B’) (A + D)

6. Simplify the Boolean function using the K-map method

a) xy + x’y’z’ + x’yz’
b) A’B + BC’ + B’C’
c) a’b’ + bc + a’bc’
d) xy’z + xyz’ + x’yz + xyz

7. Simplify the Boolean function using the K-map method

a) D(A’+B) + B’(C + AD)

b) ABD + A’C’D’ + A’B + A’CD’ + AB’D’
c) k’lm’ + k’m’n + klm’n’ + lmn’
d) A’B’C’D’ + AC’D’ + B’CD’ + A’BCD + BC’D
 Experiment: 4

Aim: (a) Implement half adder and full adder using digital ICs.
(b)Study 4-bit full adder and implement 8-bit adder using two 4-bit full adders.

Apparatus: IC 7486, 7408, 7432,7483 Analog and Digital Trainer kit, connecting wires.

Theory:

Half Adder: This circuit needs two binary inputs and two binary outputs. The input variables
designate the augend and addend bits; the output variables produce the sum and carry. It is
necessary to specify two output variables because the result may consist of two binary digits. We
arbitrarily assign symbols X and Y to the two inputs and S (for sum) and C (for carry) to the
outputs.
X Y C S
0 0 0 0
0 1 0 1
1 0 0 1
1 1 1 0

S=X’Y + XY’
C=XY
Logic Diagram:

Full Adder: A full-adder is a combinational circuit that forms the arithmetic sum of three input
bits. It consists of three inputs and two outputs. Two of the input variables, denoted by X and Y,
represent the two significant bits to be added. The third input Z represents the carry from the
previous lower significant position. The carry from the previous lower significant position. Two
outputs are necessary because the Arithmetic sum of three binary digits ranges in value from 0 to
3, and binary 2 or 3 needs two digits. The two outputs are designated by the symbols S for sum
and C for carry.

X Y Z C S
0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1
 S = X’Y’Z + X’YZ’ + XY’Z’ +XYZ
= Z (X’Y’ + XY) + Z’ (X’Y + XY’)
= Z (X ⊕ Y)’ + Z’ (X ⊕ Y)
S = Z ⊕ (X ⊕ Y)

The carry output is:

C = X’YZ + XY’Z + XYZ’ + XYZ
= Z (X’Y + XY’) + XY (Z’ +Z)
= Z (X ⊕ Y) + XY

Logic Diagram:

(B) 8-bit adder using two 4-bit Full Adders: IC 7483

Conclusion:
 Review Questions

1. Describe the operation performed by following circuits.

a) Half adder
b) Full adder
c) Half subtractor
d) Full Subtractor

2. Implement a full – subtractor with two half- subtractor and an OR gate.

 Experiment: 5

Aim: (a) Implement the following functions using a Decoder.

i) F1(A, B, C) = ∑(1,2,4,7)
ii) F2(A, B, C) = ∑(3,5,6,7)

(b) Design a 2 to 4 line Decoder with enable input using NAND gate only.

Apparatus: Analog and Digital Trainer Kit, IC 74LS138, 7408, 7410, 7400, Connecting wires.

Theory: A decoder is a combinational circuit that converts binary information from n input
lines to a maximum of 2n unique output lines. If the n-bit decoded information has unused or don’t
care combinations, the decoder output will have less than 2n outputs.
The decoders presented here are called n-to-m line decoders where m≤ 2n. Their
purpose is to generate the 2n (or less) min-terms of n inputs variables. The three inputs are
decoded into eight outputs, each output representing one of the min-terms of 3 input variables.
The three inverters provide the complement of the inputs, and each one of the eight AND gates
generates one of the min-terms. A particular application of this decoder would be a binary-to-
octal conversion.
Truth table of a 3-to-8 line decoder
Inputs Outputs
x y z D0 D1 D2 D3 D4 D5 D6 D7
0 0 0 1 0 0 0 0 0 0 0
0 0 1 0 1 0 0 0 0 0 0
0 1 0 0 0 1 0 0 0 0 0
0 1 1 0 0 0 1 0 0 0 0
1 0 0 0 0 0 0 1 0 0 0
1 0 1 0 0 0 0 0 1 0 0
1 1 0 0 0 0 0 0 0 1 0
1 1 1 0 0 0 0 0 0 0 1

a) F1(A,B,C) = ∑(1,2,4,7)
F2(A,B,C) = ∑(3,5,6,7)

Logic Diagram:
 b) 2 to 4 line Decoder with enable input using NAND gate

E A B D0 D1 D2 D3
1 X X 1 1 1 1
0 0 0 0 1 1 1
0 0 1 1 0 1 1
0 1 0 1 1 0 1
0 1 1 1 1 1 0

D0 = A’B’E’
D1 = A’BE’
D2 = AB’E’
D3 = ABE’
Logic Diagram:

Conclusion:

Review Questions

1. What is the use of the enable input in a decoder?

2. Describe the operations performed decoder?
3. A combinational circuit is defined by the following three functions:

F1 = x’y’z’ + xz
F2 = xy’z’ + x’y
F3 = x’y’z + xy
Design a circuit with decoder and external gates.

4. Construct a 4*16 decoder using two 3*8 decoders.

 Experiment: 6

Aim: (a) Implement priority encoder using digital ICs and verify its truth table.
(b)Design a 4-input priority encoder using basic gates & verify its performance.

Apparatus: Analog and Digital Trainer Kit, IC 74LS148, 7408, 7432, 7404, Connecting wires.

Theory: (A)
An encoder is a digital function that produces a reverse operation from that of a decoder.
An Encoder has 2n (or less) input lines and n out lines. the output lines generate the binary codes
for the 2n input variables. The type of encoder available in IC form is called a priority encoder.
These encoders establish an input priority to ensure that only the highest-priority input line is
encoded. if priority is given to an input with a higher subscript number over one with a lower
subscript number, then if both D2 and D5 are logic-1 simultaneously, the output will be 101
because D5 has a higher priority over D2.

Priority Encoder: IC 74LS148

 (B) a 4-input priority encoder using basic gates

Inputs Output
EN D3 D2 D1 D0 A1 A0 V
0 1 X X X 1 1 1
0 0 1 X X 1 0 1
0 0 0 1 X 0 1 1
0 0 0 0 1 0 0 1
1 X X X X X X 0
A1

D1 D0 00 01 11 10
D3 D2
00 0 0 0 0
01 1 1 1 1
11 1 1 1 1
10 1 1 1 1

A1=D3+D2
A0
D1 D0 00 01 11 10
D3 D2
00 0 0 1 1

01 0 0 0 0

11 1 1 1 1

10 1 1 1 1

A0=D3+ D2’D1
V= D3+D2+D1+D0
Logic Diagram:

Conclusion:
 Review Questions

1. Describe the operations performed by Encoder?

2. How does a priority encoder differ from an ordinary encoder?
3. Which of the following statements refer to a decoder and which to an encoder?
(a) Has more inputs than outputs.
(b) Is used to convert key actuations to a binary code.
(c) Only one output can be activated at one time.
(d) Can be used to interface a BCD input to an LED display.
4. Design an 8421-to-2421 BCD code converter and draw its logic diagram.
 Experiment: 7

Aim: (a) Design a 2-to-1 line multiplexer using basic logic gates.
(b) Verify the truth table of IC 74153.
(C)Implement the following function using 4×1 MUX:
F (A, B, C) = ∑ (0, 3, 6, 7)

Apparatus: Analog and Digital Trainer kit, IC 74153, 7404, 7408, 7432, Connecting Wires.
Theory:
To multiplex means combining many into
one. We have seen multiplex cinemas
which have many auditoriums in the same
building. Likewise, multiplexer is a device
has many inputs but a single output. It is a
kind of rotary switch which connects
several inputs to the same output line. A
key idea is that only one of the many
inputs can be connected to the output at
any point of time. The selection of any
input is controlled by a set of selection
lines i.e. depending on state of selection
lines; different inputs can drive the
output. The block diagram of multiplexer
(often abbreviated as MUX) is shown in the figure. It should be noted that n selection lines are
capable of distinguishing 2n input channels. Such type of MUX is known as 2n×1 MUX. Depending
on various values of n, we can have 2×1 MUX, 4×1 MUX, 8×1 MUX and so on.

(a) 2×1 MUX

This type of MUX has two input lines and one selection. However, in practical situations,
multiplexers are designed with one additional control signal known as enable signal as shown in
the figure. It is important to understand the function of enable signal ( E ). If E = 0, then
multiplexer functions normally and output Y is same as either I0 or I1 depending on status of
selection line S. When E =1, both the and gates get disabled and the circuit will not function. From
this, it is clear that the output Y = E S I 0 + E S I1 .

Function Table of 2×1 MUX

Enable Selection Inputs Output
Input Line (Y)
I0 I1
(S)
1 X X X 0
0 0 0 X 0
0 0 1 X 1
0 1 X 0 0
0 1 X 1 1
Logic diagram:

Logic diagram of 2×1 MUX Symbol of 2×1 MUX

(b) IC 74153
IC 74153 is a dual 4 line-to-1 line multiplexer. Thus, it contains two on-chip multiplexers which
act independently from each other. However, they both share the same select lines.

Pin diagram: Function Table:

Enable Select Data Inputs Output

Inputs
E S1 S0 I0 I1 I2 I3 Y
H X X X X X X L
L L L L X X X L
L L L H X X X H
L L H X L X X L
L L H X H X X H
L H L X X L X L
L H L X X H X H
L H H X X X L L
L H H X X X H H

(c) Implementation of a Boolean function

One important application of a multiplexer is that it can be used to implement specified Boolean
function. Advantages of using multiplexer are simplicity of the design and flexibility.
The truth table for given Boolean function is shown below:

S1 S0
A B C F
0 0 0 1
C
0 0 1 0
0 1 0 0
C
0 1 1 1
1 0 0 0
0
1 0 1 0
1 1 0 1
1
1 1 1 1
As shown, variables A and B are used as selection lines which can take four combinations. We can
confer following points after observing the truth table:
1. When AB = 00, C can take value of either 0 or 1. But for these two instances output F is
complement of C. Hence I0 must be connected to C .
2. When AB = 01, function F takes the same value as variable C. Hence, I1 must be connected
to C.
3. When AB = 10, function F maintains logic 0 independent of values of variable C. Hence I2
must be connected to logic 0.
4. When AB = 11, function F maintains logic 1 independent of values of variable C. Hence I3
must be connected to logic 1.
Based on above points, we can implement the specified Boolean function using 4×1 MUX as shown
in logic diagram below:

Conclusion:

Review Questions
1. A multiplexer with 128 input lines requires ___________ selection lines.
2. A multiplexer with three selection lines is known as _____________.
3. Design an 8×1 multiplexer using 4×1 multiplexers.
4. Implement following Boolean function using 8×1 MUX and 4×1 MUX:
F =  m ( 0,1, 2, 7,9,12,14,15 )
 Experiment: 8

Aim: Design following Code Converters.

i. Binary to Gray
ii. Gray to Binary
Apparatus: Analog and Digital Trainer kit, IC 7486, Connecting Wires.

Theory:

Gray Code system is a binary number system in which every successive pair of numbers differs in
only one bit.

i. Converting Binary to Gray Code –

Let b0, b1, b2, b3 be the bits representing the binary numbers, where b0 is the LSB and b3 is the MSB,
and Let g0, g1, g2, g3 be the bits representing the gray code of the binary numbers, where g0 is the
LSB and g3 is the MSB.
The truth table for the conversion is-
Corresponding minimized boolean expressions for gray code bits –

The corresponding digital circuit –

ii. Converting Gray Code to Binary –

Converting gray code back to binary can be done in a similar manner.

Truth table-
Using K-map to get back the binary bits from the gray code –
K-map for b0 – K-map for b1 –

K-map for b2 – K-map for b3 –

Corresponding Boolean expressions –

Corresponding digital circuit –

Conclusion:

Review Questions

1. Design BCD to Excess 3 code converter circuit.

2. Design Binary to BCD code converter circuit.
3. Design a circuit for subtraction using adder.
 Experiment: 9

Aim: (a) Perform various flip-flops operation using DICs. (7474)

(b)Design three bit ripple up/down counter using negative trigged JK flip flop

Apparatus: Analog and Digital Trainer kit, IC7474,7432,7408,7404,7486,7473, Connecting

wires.
Theory: (a) Various flip-flops
Sequential switching circuits are those whose output levels at any instant of time are
dependent not only one the levels present at the inputs at that time, but also on the prior input
level conditions. It means that sequential switching have memory. Sequential circuits are thus
made of combinational circuits and memory elements.
The most important memory element is the flip-flop, which is made up of an assembly
of logic gates. Even through a logic gate by itself has no storage capability, several logic gates can
be connected together in ways that permit information to be stored. There are several different
gate arrangements that are used to construct flip-flops in a wide variety of ways. Each type of flip-
flop has special features or characteristics necessary for particular applications.
A flip-flop, known more formally as a bistable multivibrator, has two stable states. It can
remain in either of the states indefinitely. Its state can be changed by applying the proper
triggering signal.
Design of JK Flip Flop using D Flip Flop (7474) is shown in figure1.
Its Characteristics table is shown in Table 1.
Logic Diagram:

Fig 1: Design of JK FF
Characteristics equation: D = JQ’ + K’Q

Table 1: Characteristics Table

J K Q D Q (t+1)
0 0 0 0 0
0 0 1 1 1
0 1 0 0 0
0 1 1 0 0
1 0 0 1 1
1 0 1 1 1
1 1 0 1 1
1 1 1 0 0
• Design of RS Flip Flop using D Flip Flop (7474) is shown in figure2.
Its Characteristics table is shown in Table 2.
Characteristics equation: D = R’Q + S
Table 2: Characteristics Table
R S Q D Q (t+1)
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 1 1
1 0 0 0 0
1 0 1 0 0
1 1 0
1 1 1
Logic Diagram:

Fig 2 : design of RS FF
• Design of T Flip Flop using D Flip Flop (7473) is shown in figure3.
Its Characteristics table is shown in Table 3.
Characteristics equation: D = T’Q + TQ’

Table 3: Characteristics Table

T Q D Q= T’Q + TQ’
0 0 0 0
0 1 1 1
1 0 1 1
1 1 0 0

Logic Diagram:

Fig 3: design of T FF
(b) 3- bit ripple up down counter using negative triggered JK Flip-flop.(7473)

Ripple Counter

A synchronous counters are also called ripple counters. The ripple counter is the simplest
type of counter, the easiest to design and requires the least amount of hardware. In ripple
counters the FFs within the counter are not made to change the states at exactly the same time.
This is because the FFs are not triggered simultaneously. The clock does not directly control the
time at which every stage changes state. An asynchronous counter uses T FFs to perform a
counting function. The actual hardware used is usually J-K FFs connected in toggle mode,i.e. with
Js and Ks connected to logic 1. Even D FFs may be used here.
 The asynchronous counter has a disadvantage, insofar as the unwanted spikes are
concerned. This limitation is overcome in parallel, counters. The asynchronous counter is called
ripple counter because when the counter, for example, goes from 1111 to 0000, the first stage
causes the second to flip, the second causes the third to flip, and the third cause the fourth to flip,
and so on. In other words, the transition of the first stage ripples through to the last stage. In doing
so, many intermediate stages are briefly entered. If there is a gate that will AND during any state,
a brief spike will be seen at the gate output every time the counter goes from 1111 to 0000. Ripple
counters are also called serial or series counters. Synchronous counters are clocked such that
each FF in the counter is triggered at the same time. This is accomplished by connecting the clock
line to each stage of the counter. Synchronous counters are faster than asynchronous counters,
because the propagation delay involved is less.

A counter may be an up-counter or a down-counter. An up-counter is a counter which

counts in the upward direction. i.e. 0, 1, 2, 3,…, N. A down counter is a counter which counts in the
downward direction, i.e. N,N -1,N-2,N-3,…, 1,0. Each of the counts off the counter is called the state
of the counter. The number of states through which the counter passes before returning to the
starting state is called the modulus of the counter. Hence, the modulus of a counter is equal to the
total number of distinct states (counts) including zero that a counter can store. In other words the
number of input pulses that causes the counter to reset to its initial count is called the modulus of
the counter. Since a 2-bit counter has 4 states, it is called a mod-4 counter. It divides the input
clock signal frequency by 4; therefore, it is also called a divide-by-4 counter. It requires two FFs.
Similarly a 3-bit counter uses 3 FFs and has 23 = 8 states. It divides the input clock frequency by
23 , i.e. 8. In general, an n-bit counter will have n FFs and 2n states, and divides the input frequency
by 2n.Hence; it is a divide-by-2n counter.

Logic Diagram:
3-bit ripple up/down counter

Conclusion:
 Review Questions

1. Distinguish between combinational and sequential switching circuits.

2. What is meant by stable state?
3. What do you mean by (a) a latch, and (b) a gated latch?
4. How do you build a latch using universal gates?
5. How does a J-K flip-flop differ from an S-R flip-flop in its basic operation? What is its
advantage over an S-R flip-flop?
6. Describe the main difference between a gated S-R latch and an edge-triggered S-R flip-flop?
7. What J, K condition will always set Q upon the occurrence of the active CLK transition?
8. Explain why the S and R inputs of an edge-triggered S-R flip-flop affect Q only during the
active transition of CLK.
9. Suppose that the D input of a flip-flop changes from LOW to HIGH in the middle of a clock
pulse. Describe what would happen if the flip-flop is a positive edge-triggered type, a pulse-
triggered type.
̅̅̅̅̅̅ = 1?
10. Can a D flip-flop respond to its D and CLK inputs while 𝑃𝑅𝐸
11. What do you mean by toggling?
12. Which is the most versatile flip-flop? Which flip-flop is preferred for data transfer?
 Experiment: 10

Aim: (a) Design a 3-bit Synchronous up/down counter using negative edge Trigged JK Flip Flop.
(b) Design a 3-bit counter which counts as 0, 1, 3, 5, 7, 0,…. Continue Negative edge trigged
JK flip flop.
Apparatus: Analog and Digital Trainer kit, IC 7408, 7486, 7473, 7432, connecting Wires.

Theory:
Synchronous Counter
A Synchronous counters are serial counters. They are slow because each FF can change
state only if all the preceding FFs have changed their state. The propagation delay thus gates
accumulated, and so causes problems. If the clock frequency is very high, the asynchronous
counter may skip some of the states and, therefore, malfunction. This problem is overcome in
synchronous or parallel counters. Synchronous counters are counters in which all the FFs are
triggered simultaneously (in parallel) by the clock input pulses. Whether a FF toggles or not
depends on the FFs inputs (J, K or T, or S, R).
Since all the FFs change state simultaneously in synchronization with the clock pulse, the
propagation delays of FFs do not add together (as in ripple counters) to produce the overall delay.
In fact, the propagation delay of a synchronous counter is equal to the propagation delay of just
one FF plus the propagation delay of the gates involved. So, the synchronous counters can operate
at much higher frequencies than those that can be used in asynchronous counters.
Synchronous counters have the advantages of high speed and less severe decoding
problems, but the disadvantages of having more circuitry than that of asynchronous counters.
Many synchronous (parallel) counters that are available as ICs are designed to be presettable, i.e.
they can be preset to any desired starting count either asynchronously or synchronously. This
presetting operation is also referred to us loading the counter.
(a) Design a 3-bit Synchronous up/down counter using negative edge Trigged JK Flip- Flop is
shown figure 1. Its Excitation Table is shown in table 1.

Up counter Excitation Table

Q2 Q1 Q0 T2 T1 T0
0 0 0 0 0 1
0 0 1 0 1 1
0 1 0 0 0 1
0 1 1 1 1 1
1 0 0 0 0 1
1 0 1 0 1 1
1 1 0 0 0 1
1 1 1 1 1 1
So, T2 = Q1. Q0
T1 = Q0
T0 = 1

Down counter Excitation Table

Q2 Q1 Q0 T2 T1 T0
1 1 1 0 0 1
1 1 0 0 1 1
1 0 1 0 0 1
1 0 0 1 1 1
0 1 1 0 0 1
0 1 0 0 1 1
0 0 1 0 0 1
0 0 0 1 1 1
 So,
T2 = Q’1.Q’0
T1 = Q0 ’
T0 = 1

Logic Diagram:

3-bit up/down counter

(b) Design a 3-bit counter which counts as 0, 1, 3, 5, 7, 0,…. Continue
Negative edge trigged JK flip flop(7473).
Excitation Table
Q2 Q1 Q0 T2 T1 T0
0 0 0 0 0 1
0 0 1 0 1 0
0 1 0 x x x
0 1 1 1 1 0
1 0 0 x x x
1 0 1 0 1 0
1 1 0 x x x
1 1 1 1 1 1
So,
T2 = Q1
T1 = Q0
T0 = Q’0 + Q1Q2
Logic Diagram:

Conclusion:

.
 Review Questions

1. What is a master-slave flip-flop? Discuss its working.

2. What do you mean by (a)clock skew, and (b)time race?
3. What do you mean by a flip-flop with data lock-out? How does it differ from a normal
master-slave flip-flop?
4. How must a J-K flip-flop be connected to function as a divide-by-two element? How many
flip-flops are required to produce a divide-by-64 device?
5. State true or false.
a) The CLK input will affect the flip-flop output only when the active transition of the
control input occurs.
b) The SET input can never be used to make Q a 0.
c) A J-K flip-flop can be used as an S-C flip-flop, but an S-C flip-flop cannot be used as a J-
K flip-flop.
d) The Q output of a D flip-flop will equal the level at the D input at all times.
e) A D latch is in its transparent mode when EN is a 0.
f) Synchronous data transfer requires less circuitry than that required by asynchronous
transfer.
g) Why are MOS inverters preferred over TTL inverters in making astable Multivibrators.