ECE3210 Microprocessor Engineering

Homework 8

1. (Chapter 10.1) What types of connections are common to all memory devices?
Address, data, and control connections

2. (Chapter 10.2.d) List the number of words found in each memory device for the following
numbers of address connections: 16K x 1
213 = 8K

3. (Chapter 10.17) Why are memory address decoders important?

Memory rarely fills the entire memory, which requires some form of decoder to select the
memory device for a specific range of memory addresses.

4. (Chapter 10.18) Modify the NAND gate decoder of Figure 10–13 to select the memory for
address range DF800H–DFFFFH.
DF800H – 1101 1111 1000 0000 0000
DFFFFH – 1101 1111 1111 1111 1111

5. (Chapter 10.19) Modify the NAND gate decoder in Figure 10–13 to select the memory
for address range 40000H–407FFH.
40000H – 0100 0000 0000 0000 0000
407FFH – 0100 0000 0111 1111 1111

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 A0--A10 D0--D7

U1 NMC27C16B

8 9
7 A0 O0 10
6 A1 O1 11
___ 5 A2 O2 13
RD 4 A3 O3 14
3 4 3 A4 O4 15
U2 74ALS133 2 A5 O5 16
A19 1 1 A6 O6 17
A18 2 23 A7 O7
A17 3 22 A8
A16 4 19 A9
A15 5 6 5 A10
A14 6 20
A13 7 9 18 OE
A12 10 CE
A11 11 21
VCC VPP
9 8 12
13
14
15

11 10

13 12

U3D 74ALS04
1 2 __
IO/M
9 8

3 4

5 6

6. (Chapter 10.20) When the G1 input is high and both and are low, what happens to the
outputs of the 74HCT138 3-to-8 line decoder?
One of the eight outputs becomes a logic zero as dictated by the address inputs.

7. (Chapter 10.21) Modify the circuit of Figure 10–15 to address memory range 70000H–
7FFFFH.
70000H – 0111 0000 0000 0000 0000
7FFFFH – 0111 1111 1111 1111 1111
U1

A13 1 15
A14 2 A Y0 14
A15 3 B Y1 13
C Y2 12
A16 6 Y3 11
A19 4 G1 Y4 10
5 G2A Y5 9
G2B Y6 7
Y7
U2A
74HCT138
A17 1
3
A18 2

74HCT00

8. (Chapter 10.22) Modify the circuit of Figure 10–15 to address memory range 40000H–
4FFFFH.

40000H – 0100 0000 0000 0000 0000

4FFFFH – 0100 1111 1111 1111 1111

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 9. (Chapter 10.27) Modify the circuit of Figure 10–19 by rewriting the PLD program to
address memory at locations A0000H–BFFFFH for the ROM.
A0000H – 1010 0000 0000 0000 0000
BFFFFH– 1011 1111 1111 1111 1111

begin

ROM <= A19 or (not A18) or A17 or MIO;

RAM <= A18 and A17 and (not MIO);

AX19 <= not A19;

end V1;

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 10. (Chapter 10.29) Modify the circuit of Figure 10–20 to select memory at location 60000H–
77FFFH.
60000H – 0110 0000 0000 0000 0000
77FFFH – 0111 0111 1111 1111 1111

A19 is 0, A18 is 1, so they can be directly connected G2A and G1 of decoder ‘138

In Fig. 10-20, A17A16A15 are connected to C/B/A input pins of ‘138.

A17A16A15 Y4 Y5 Y6
1 0 0 0
1 0 1 0
1 1 1 0

So, Y4  U1 CE, Y5  U2 CE, Y6  U1 CE

D0 -- D7

A0 -- A14

U1 AT27256 U2 AT27256 U3 AT27256

10 11 10 11 10 11
9 A0 O0 12 9 A0 O0 12 9 A0 O0 12
8 A1 O1 13 8 A1 O1 13 8 A1 O1 13
7 A2 O2 15 7 A2 O2 15 7 A2 O2 15
6 A3 O3 16 6 A3 O3 16 6 A3 O3 16
5 A4 O4 17 5 A4 O4 17 5 A4 O4 17
4 A5 O5 18 4 A5 O5 18 4 A5 O5 18
3 A6 O6 19 3 A6 O6 19 3 A6 O6 19
25 A7 O7 25 A7 O7 25 A7 O7
24 A8 24 A8 24 A8
21 A9 21 A9 21 A9
23 A10 23 A10 23 A10
2 A11 2 A11 2 A11
26 A12 26 A12 26 A12
27 A13 27 A13 27 A13
A14 A14 A14
#RD 22 22 22
20 OE 20 OE 20 OE
U4 74HCT138 CE CE CE
28 28 28
A15 1 15 1 VCC 1 VCC 1 VCC
A16 2 A Y0 14 VPP VPP VPP
A17 3 B Y1 13
C Y2 12
A18 6 Y3 11
A19 4 G1 Y4 10
IO/#M 5 G2A Y5 9
G2B Y6 7
Y7

VCC

11. (Chapter 10.30) Modify the circuit of Figure 10–20 to select eight 27256 32K × 8 EPROMs
at memory locations 40000H–7FFFFH.

27256 32K x 8 EPROM has 15 address pins (32K = 215), 8088 address pins A0 – A14 go to
EPROM. Remaining A19-A15 need to be connected to decoder ‘138

40000H – 0100 0000 0000 0000 0000

7FFFFH – 0111 1111 1111 1111 1111

A19 is 0, A18 is 1, so they can be directly connected G2A and G1 of decoder ‘138
A17A16A15 can be connected to C/B/A input pins of ‘138, and output pins Y0 – Y7 connect
to the chip select pin (CE) of the eight 27256 units U1 to U8.

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 12. (Chapter 10.35) Outline the major difference between the buses of the 8086 and 8088
microprocessors.
The main differences are the data bus size and the I/O, memory control signal.

13. (Chapter 10.36) What is the purpose of the BHE and A0 pins on the 8086 microprocessor?
BHE selects the upper memory bank and A0 selects the lower memory bank.

14. (Chapter 10.37) What is the purpose of the BLE and A0 pins on the 8086 microprocessor?
Bank low enable has replaced the A0 pin.

15. (Chapter 10.39) If BHE is a logic 0, then the ________ memory bank is selected.
Upper memory bank

16. (Chapter 10.40) If A0 is a logic 0, then the ________ memory bank is selected.
Lower memory bank

17. (Chapter 10.41) Why don’t separate bank read (RD) strobes need to be developed when
interfacing memory to the 8086?
It does not matter if 16-bit or 8-bit are read because the microprocessor just ignores any
data bus bits that are not needed.

18. (Chapter 10.43) Develop a 16-bit-wide memory interface that contains SRAM memory at
locations 200000H–21FFFFH for the 80386SX microprocessor. Modify the circuit of
Figure 10–32.

200000H – 0010 0000 0000 0000 0000 0000

21FFFFH– 0010 0001 1111 1111 1111 1111

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 D0 - D7

D8 - D15

A1 - A15

HM62256 HM62256
10 11 10 11
9 A0 D0 12 9 A0 D0 12
8 A1 D1 13 8 A1 D1 13
7 A2 D2 15 7 A2 D2 15
6 A3 D3 16 6 A3 D3 16
5 A4 D4 17 5 A4 D4 17
4 A5 D5 18 4 A5 D5 18
3 A6 D6 19 3 A6 D6 19
25 A7 D7 25 A7 D7
24 A8 24 A8
21 A9 21 A9
23 A10 23 A10
2 A11 2 A11
26 A12 26 A12
1 A13 1 A13
A14 A14
22 22
27 OE 27 OE
20 WE 20 WE
CE CE
28 28
VCC VCC

#RD

U18
10 11 10 11
#WR 3 17 9 A0 D0 12 9 A0 D0 12
#BHE 4 I I/O 18 8 A1 D1 13 8 A1 D1 13
A0 5 I I/O 19 7 A2 D2 15 7 A2 D2 15
A23 6 I I/O 20 6 A3 D3 16 6 A3 D3 16
A22 7 I I/O 21 5 A4 D4 17 5 A4 D4 17
A21 9 I I/O 23 4 A5 D5 18 4 A5 D5 18
A20 10 I I/O 24 3 A6 D6 19 3 A6 D6 19
A19 11 I I/O 25 25 A7 D7 25 A7 D7
A18 12 I I/O 26 24 A8 24 A8
A17 13 I I/O 27 21 A9 21 A9
A16 16 I I/O 23 A10 23 A10
I 2 A11 2 A11
2 26 A12 26 A12
I/CLK 1 A13 1 A13
28 A14 A14
VCC 22 22
27 OE 27 OE
GAL22LV10C/LCC 20 WE 20 WE
CE CE
28 28
VCC VCC VCC

HM62256 HM62256

----------------End----------------

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