Received 4 June 2021; revised 20 August 2021; accepted 30 August 2021.

Date of publication 6 September 2021; date of current version 22 September 2021.

Digital Object Identifier 10.1109/OJSSCS.2021.3109854

Harmonic Oscillators in CMOS—A Tutorial Overview

PIETRO ANDREANI 1 (Fellow, IEEE), AND ANDREA BEVILACQUA 2 (Senior Member, IEEE)
(Invited Paper)
1 Department of Electrical and Information Technology, Lund University, 221 00 Lund, Sweden

2 Department of Information Engineering, University of Padova, 35131 Padova, Italy

CORRESPONDING AUTHOR: P. ANDREANI (e-mail: [email protected])

ABSTRACT The harmonic oscillator is a truly irreplaceable as well as ubiquitous analog integrated
circuit. Starting from the basics of its CMOS implementation, we will discuss the phase noise of the
harmonic oscillator in some detail, where the intrinsic large-signal operation mandates a time-variant
analysis. This will be followed by a survey of the most popular design techniques enabling a low phase
noise and a wide range of oscillation frequencies.

INDEX TERMS Oscillator, harmonic, phase noise, tuning range, CMOS.

I. INTRODUCTION In communication systems, phase noise is also responsible

S ONE of the very few areas of analog electronics for the so-called reciprocal mixing in the receiver: if an
A still withstanding the irresistible onslaught of its digital
nemesis, frequency generation keeps attracting the interest of
undesired signal (referred to as an interferer) is located
at a frequency offset ω from the desired signal, phase
beginners and specialists alike, oscillators being especially noise at ω from the carrier translates the interferer to the
fascinating for their ability to create time-varying periodic frequency of the desired signal, again causing an SNR dete-
signals out of a constant power supply; and while it is not rioration. If transmitter and receiver are active at the same
difficult to generate an oscillation, at least at low enough time, the receiver SNR is also affected by the phase noise
frequencies, ensuring its high quality in the presence of sev- in the transmitter oscillator mixing with the transmitted sig-
eral conflicting constraints (low power supply, limited power nal. In sampled data systems, such as data converters and
consumption, frequency tunable over a wide range, compli- discrete-time filters, phase noise on the sampling clock (more
ance with digital CMOS processes, etc.) is a never-ending commonly referred to as jitter) is critical, as it introduces
challenge, which, despite valiant attempts to enlist digital- a sampling error that increases with the bandwidth of the
friendly ring oscillators in the struggle [1], [2], is made sampled signal.
somewhat less daunting only by turning to harmonic oscil- It is therefore clear that oscillator design quickly becomes
lators − i.e., oscillators based on inductor(s) and capacitor(s) a quest for a sufficiently low phase noise.
− whenever a good frequency purity at a reasonable power The literature on harmonic oscillators is vast, which forces
consumption is desired. us to limit the scope of this survey to implementations in
Of paramount importance in this context is the oscillator CMOS − their bipolar counterparts would be very similar,
phase noise, which modulates the phase of the oscillation with however two major differences: bipolar transistors can-
(the carrier in radio communication parlance) through the not be allowed to enter saturation, and the lack of a natural
action of various thermal and possibly 1/f noise sources. switch in purely bipolar processes severely complicates
Phase noise easily becomes the performance bottleneck in frequency tuning (Section V). Furthermore, we will not take
any application making use of an oscillator. In a communica- up the specific problems encountered in the design of mm-
tion system, phase noise is transferred onto the information wave oscillators, where the resonator is made of distributed
signal during frequency modulation/demodulation, deterio- rather than lumped components. Likewise, we will not treat
rating the signal-to-noise ratio (SNR). Similarly, phase noise oscillators delivering more than one signal or two differen-
impairs the received signal in a carrier-based radar system. tial signals, and we will deal only with the most popular

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2 VOLUME 1, 2021
FIGURE 1. Lossy LC resonator and its equivalent shunt model.

oscillator architectures, fascinating as more exotic architec- FIGURE 2. Simplified schematic view of a Colpitts oscillator.

tures may be. Finally, we will mainly consider applications

to wireless systems, although most of the discussion applies
in general.

II. FUNDAMENTALS
The simplest harmonic oscillator is built around a resonator
made of one inductor (L) in parallel with one capacitor (C),
as in Fig. 1: a combination often referred to as an LC tank,
as it acts as a reservoir of energy. The resonance√ of the LC
tank occurs at an angular frequency ω0 = 1/ LC, where
FIGURE 3. Small-signal equivalent circuit for the Colpitts oscillator in Fig. 2.
the two impedances cancel each other.
In general, both L and C have losses, exemplified by the
series resistances in Fig. 1; if these are not large compared
to the impedance of L (or C, equivalently) at resonance, ω0
is largely unaffected by them. In the vicinity of ω0 , all losses
are conveniently compacted into a single equivalent parallel
resistance R, as in Fig. 1 (it should be noted though that
this is not correct if the parallel coupling of L and C is not
maintained across the whole oscillation period T0 = 2π/ω0 ,
as in, e.g., class-D oscillators [3]). Thus, at resonance the
impedance of the lossy LC tank is simply R, which tends
to infinity as the tank becomes more ideal. A measure of
the quality of the tank is its quality factor Q, defined as
R/(ω0 L) or Rω0 C.
To create a harmonic oscillator, we need a transconduc-
tor acting as an active negative resistance replenishing the FIGURE 4. Voltage and current waveforms for the Colpitts oscillator in Fig. 2.
losses caused by R. Since it is placed in parallel to R, this
negative resistance must have an absolute value lower than the nMOS source, and applying standard circuit analysis to
R, or equivalently a conductance higher than 1/R to make the linearized small-signal circuit, as shown in Fig. 3, where
the circuit unstable. An elegant implementation of a negative the loop output must be loaded with the impedance seen
resistance was invented by E. Colpitts in 1918 [4]–[6]: Fig. 2 looking into the loop input, i.e., 1/gm (very suitably, we
shows a simplified view of a singled-ended common-gate have assumed an infinitely high output resistance for the
Colpitts oscillator, where only one active device is needed, nMOS transistor). Barkhausen’s criterion for the onset of
as the current source may be a simple resistor (as a mat- instability is that the loop gain be equal to 1ej 0 , a condition
ter of fact, R. Hartley had already invented the eponymous yielding the minimum value gm,min of gm as
oscillator in 1915 [7], where C and L swap places compared
1 1
to its Colpitts counterpart). gm,min = (1)
The positive feedback from nMOS drain to source, which R n(1 − n)
yields the sought negative resistance, is implemented with where n = C1 /(C1 + C2 ) is the feedback factor.
the tapped capacitor C1 -C2 . Once the values of the pas- The steady-state regime of a Colpitts (or any other) oscil-
sive components are given, we can determine the minimum lator is, however, very much non-linear, as we can appreciate
values of the nMOS transconductance gm needed to start from Fig. 4, which shows that the current delivered by the
the oscillation by breaking the loop at a suitable node, e.g., transistor is made of tall and narrow pulses. Assuming though

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ANDREANI AND BEVILACQUA: HARMONIC OSCILLATORS IN CMOS—TUTORIAL OVERVIEW

FIGURE 6. Voltage and current waveforms for the class-B oscillator in Fig. 5.

FIGURE 5. Simplified schematic view of the class-B oscillator with single

cross-coupled differential pair.

that the tank Q is not too low, all higher current harmon-
ics are filtered out by the tank, and only the fundamental
current harmonic contributes significantly to the oscillation
amplitude, which is therefore almost sinusoidal.
While deriving the oscillation amplitude in such a non-
linear system may appear overwhelmingly difficult, it is in
fact surprisingly straightforward by means of the describing-
function technique [5], which posits that the amplitude of the
fundamental current harmonic is largely independent of the
oscillation amplitude. This may seem too drastic a simplifi-
cation, but it does indeed lead to very accurate predictions.
Thus, if the current pulses of Fig. 4 are narrow enough, FIGURE 7. Simplified schematic view of the class-B oscillator with double
cross-coupled differential pair.
they can be represented as Dirac deltas, and then the ampli-
tude of the fundamental current harmonic is easily found
to be twice the bias current IB , a value that changes very
little with the actual shape of the current pulses, as long as period (swapping the power supply VDD and ground, flip-
they are narrow compared to T0 . This allows us to substitute ping the direction of IB , and substituting the nMOS pair
the nMOS transistor in Fig. 2 with an independent current with a pMOS pair, we obtain a pMOS class-B oscillator,
source of value and frequency equal to the fundamental cur- with an otherwise identical operation). The current wave-
rent harmonic, immediately finding the amplitude Apk of the forms are therefore square waves alternating between 0 and
sinusoidal voltage oscillation as [5] IB (Fig. 6), with a first harmonic of amplitude 2IB /π . Notice
that the inductor has a center tap connecting to VDD , whereby
Apk ≈ 2IB R(1 − n) (2) the oscillation swings symmetrically above and below VDD ,
reaching close to twice VDD at maximum oscillation ampli-
The deleterious factor (1 − n) < 1 is caused by the feedback tude. The fact that VDD is fed through the center tap of the
network effectively loading the tank. inductor has the consequence that each current wave sees
Beautiful as the Colpitts oscillator is, the real star in only half of the tank impedance at resonance, i.e., R/2. The
the world of integrated electronics is the cross-coupled oscillation amplitude across the differential tank is therefore
differential-pair oscillator (Fig. 5), as differential phases 2 (2IB /π ) R/2 = 2IB R/π .
are needed anyway in almost all modern applications. This A very popular variant of the class-B oscillator is that in
allows us to implement the negative resistance by simply Fig. 7, where two cross-coupled pairs are used, one nMOS
cross-coupling the differential tank outputs to the differen- and one pMOS, which, if their gain factors are identical,
tial nMOS pair inputs (gates), obtaining a value of −2/gm , double the overall transconductance. The single-ended volt-
where gm is the transconductance of a single transistor at DC. age oscillations are now those in Fig. 8: they resemble half
This oscillator works in class B (and we will refer to it sinusoids, since during half of the oscillation period each
as the class-B oscillator in the following), or at least very output is stuck at VDD when the respective pMOS is on;
close to it, since in steady state each nMOS injects the differentially, though, the tank voltage is again (almost) sinu-
whole IB into the tank for (almost) half of the oscillation soidal with amplitude 4π IB R, i.e., double that in the class-B

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 FIGURE 11. Oscillator circuit model for LTI phase noise analysis.

FIGURE 8. Voltage and current waveforms for the class-B oscillator in Fig. 7.

FIGURE 12. Asymptotic plot of the phase noise sideband in log-log scale.

FIGURE 9. Oscillations affected by a (strong) white noise source. resistance exactly cancel each other out. If we now want
to analyze the impact of the thermal noise introduced by
R (which, obviously, is not canceled by the uncorrelated
noise generated by the negative resistance), the relevant cir-
cuit reduces to that in Fig. 11, where i2n /f = 4kB T/R, kB
being Boltzmann’s constant and T the absolute temperature.
It is straightforward to show that the power spectral density
(PSD) of the noise voltage generated by i2n /f at a frequency
ω from ω0 , with ω  ω0 , is
 
FIGURE 10. Frequency spectrum of a noisy oscillator. v2n 1 ω0 2
≈ 4kB TR (3)
f 2 Q ω
This expression, though, does not discriminate between
oscillator with a single cross-coupled pair. This is because
amplitude noise and phase noise, while we have already
now the square wave current, commutating between IB and
stated that only phase noise survives close to the carrier.
−IB , flows across the whole tank, not just half of it. Notice
The correct phase noise expression is therefore half of (3),
though that the oscillation is contained between VDD and
divided by the power of the sinusoidal carrier, yielding
ground, and not between 2VDD and ground as in Figs. 5–6.    
2kB TR 1 ω0 2
L(ω) = 10 log10 (4)
III. PHASE NOISE A2pk /2 2Q ω
The uncertainty on the phase of the oscillation in a real oscil-
lator grows without bound with time because of the action This is the absolute minimum phase noise we can expect,
of various noise sources. In the time domain, this uncertainty since all noise sources but the tank have been neglected. It
is referred to as jitter: as shown by the simulations of Fig. 9, is worth remarking explicitly that ω at the denominator
where the impact of (white) noise has been highly exagger- of (4) makes phase noise fall by 20 dB/dec with ω.
ated, the uncertainty on the zero crossings grows in time Equation (4) lies at the core of the famous phase noise
in a random-walk fashion. The same phenomenon is called equation by Leeson [8],
phase noise in the frequency domain, a terminology derived     
2kB TR 1 ω0 2
from the fact that noise affects only the phase of the oscil- L(ω) = 10 log10 F · 2 1+
lation for frequencies close to ω0 , the amplitude noise being Apk /2 2Q ω
 
rejected by the oscillator itself. Phase noise is expressed in ω1/f 3
dB with respect to the carrier and over a bandwidth of 1 Hz, · 1+ (5)
ω
i.e., in dBc/Hz (Fig. 10).
The simplest way to approach phase noise is via a stan- plotted in Fig. 12. The additional factor F captures the impact
dard linear time-invariant (LTI) analysis, starting with the of all white noise sources besides the tank, and primarily
assumption that active negative resistance and parallel tank the negative resistance; moreover, the region closest to ω0 is

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ANDREANI AND BEVILACQUA: HARMONIC OSCILLATORS IN CMOS—TUTORIAL OVERVIEW

FIGURE 14. Ideal LC oscillation when a noise impulse is injected at the waveform
peak (left) or at the zero crossing (right).

its contribution to phase noise can be assessed correctly,

yielding an effective current noise

FIGURE 13. Example of phase noise measurement, from [10]. in,eff (φ) = in (φ)in (φ) (6)
where φ = ω0 t is the phase of the oscillation (the same
approach applies to voltage noise sources, see, e.g., [3]).
typically dominated by low-frequency 1/f noise upconverted Traditionally, the ISF is normalized to be dimensionless,
to frequencies close to the carrier. In this region, extending frequency and amplitude independent, and with period 2π .
up to a corner frequency of ω1/f 3 , phase noise falls by If in is a cyclo-stationary noise source, it is convenient (and
30 dB/dec with increasing ω. Finally, phase noise may hit indeed very often possible) to express it as the product of a
a floor, where it becomes white. This region is not, however, wide-sense stationary (WSS) noise source and a modulating
intrinsic to the oscillator itself, but originates from the addi- function capturing the time variance of the noise process.
tive noise introduced by circuits using or distributing the Hence,
oscillation, such as buffers. Obviously, such a noise floor in,eff (φ) = in,wss (φ)in ,eff (φ) (7)
does not have to start at an offset frequency of ω0 /(2 Q);
rather, it is in the neighborhood of this offset frequency where now all time variance is contained in an effective
where amplitude noise starts adding up to phase noise in ,eff (φ). If in is a white current noise source, either station-
in a well-designed oscillator [9]. Fig. 13 shows an actual ary or cyclo-stationary, it can be shown that its contribution
phase noise measurement, with superimposed 1/f 2 and 1/f 3 to phase noise is [11], [14]
asymptotes.  
While fairly successful as a phenomenological description, i2n,wss /f i2n ,eff,rms
L(ω) = 10 log10 (8)
it is obvious that the Leeson equation leaves much to be 2C2 A2pk ω2
desired: a factor of two was removed from (4) by hand,
ω1/f 3 is a fitting parameter, and it is difficult to see how where i2n,wss /f is the PSD of in,wss and in ,eff,rms is the
the equation could be extended to, e.g., the treatment of root-mean-square value of in ,eff .
noise generated by the negative-resistance transistors, whose An equation similar to (8) applies when in is a 1/f
operation varies wildly across T0 . noise current source (as we will discuss in more detail in
A turning point for the comprehension of phase noise in Section IV-A, there is no upconversion of 1/f noise into
the SSCS community has been Ali Hajimiri and Thomas H. 1/f 3 phase noise in ideal Colpitts or class-B oscillators in
Lee’s linear time-variant analysis [11]–[14]: the lightness and CMOS).
yet rigor of the approach have earned it a just and enduring Another way to understand the role of the ISF is to turn
fame (although, it goes without saying, many advances have to the frequency domain: as shown in Fig. 15, the various
intervened in the 20+ years since its appearance). harmonics of in ,eff convolve with the relevant noise side-
The need for a time variant analysis becomes inescapable bands of in,wss , causing phase modulation of the carrier, and
when we realize that the conversion of noise into phase ultimately phase noise.
noise depends on when it occurs across T0 , even when a Very conveniently, the ISF in a harmonic oscillator is (to
time invariant noise source (e.g., R) is considered. In fact, if the first order) a sinusoid of unit amplitude in quadrature to
we inject a noise pulse at the top of the oscillation sinusoid the voltage across the (single) tank, i.e., with arbitrary initial
(Fig. 14), no disturbance is caused to the phase of the sinu- phase for the oscillation,
soid, i.e., no phase noise is generated. On the other hand, if in = sin(φ) (9)
we inject it at a zero crossing, the phase disturbance is at a
maximum. If, on the other hand, the oscillator employs two independent
Leaving the mathematical details aside, the lesson tanks, the value of the ISF is halved [15]. Be as it may, such
from [11] is that any current noise source in must be weighed simple ISF expressions readily enable a symbolic analysis
by an associated impulse sensitivity function (ISF) in before of phase noise. As an example, we can calculate (again)

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 Notably, the two transistors appear only through the factor
γn , and, assuming γn = 1 for simplicity (its long-channel
value being 2/3), the tank and the nMOS pair contribute
equally to phase noise. Equation (10) is in fact remarkable,
as it states that, no matter the gain factor of the transistors,
their phase noise contribution is always proportional to the
tank’s. This unexpected and nevertheless correct prediction
can be traced back to the following mechanism: the effective
current noise generated by the transistors is proportional to
FIGURE 15. Noise folding due to the time-variant conversion of noise current into
the current commutation time (Fig. 16), which is inversely
phase noise. proportional to the amplitude of the oscillation, which is
proportional to the tank resistance, whose current noise is
inversely proportional to its value. Of course, this does not
mean that transistors do not matter, but rather that it is suf-
ficient that their strength be large enough to ensure a quick
current commutation, which yields the highest possible oscil-
lation amplitude; transistors, on the other hand, should not be
larger than this, in order to limit their parasitic capacitances,
whose impact will be discussed in Section IV.
It is important to realize that a naive LTI analysis would
have predicted, very wrongly, that the phase noise induced by
the transistors increases with their small-signal transconduc-
tance. That this is not the case can be qualitatively understood
from the following argument: if we increase the transcon-
ductance by, e.g., making the transistors larger, current noise
FIGURE 16. Current waveforms, ISF and effective noise current in the class-B
is increased but commutation time is reduced, the two effects
oscillator of Fig. 5. canceling each other exactly.
Turning to the class-B oscillator of Fig. 7, it can be
shown [16] that its phase noise is
the phase noise induced by tank losses using (6)-(9), where ⎛   ⎞
γn + γp
i2n /f ·i2n ,eff,rms = 2 kB T/R, since i2n ,eff,rms = 1/2. Thus, (8) 2kB TR 1 +  2
⎜ 2 1 ω0 ⎟
allows us to recover (4), without the necessity, however, of L(ω) = 10 log10 ⎜ ⎝
⎟
invoking the empirical disappearance of the amplitude noise, A /2
2
pk
2 Q ω ⎠
which is instead accounted for in a natural way by i2n ,eff,rms
being equal to 1/2 instead of 1. (11)
Even more interesting is that we can now do something where γp is the channel noise factor for the pMOS transistor.
new, namely, find the phase noise contribution from the Assuming γp = γn , the only difference between (10) and (11)
cross-coupled nMOS pair in the class-B oscillator of Fig. 5. is the oscillation amplitude, which, we recall, is twice as
Here, the PSD of the noise current generated by each large in the class-B oscillator with complementary switch
transistor is given by 4 kB Tγn gm (φ), where γn is the chan- pairs, meaning that it enjoys a 6 dB phase-noise advantage
nel noise factor for the nMOS transistor. Each transistor over the class-B oscillator with a single switch pair. That it
contributes noise only during the short time when IB com- should be so is not wholly obvious, as the former contains
mutates from one branch to the other, for a total of two four noise-generating transistors instead of only two in the
commutations for each transistor over T0 (transistor noise latter. The difficulty is resolved when we consider that a
is otherwise rejected by the infinite impedance of the tail doubled oscillation amplitude halves the commutation time
current source). Fig. 16 shows the effective noise from one for the switch pairs, which means that the four transistors
transistor: since the associated ISF is almost constant and in Fig. 7 generate together as much phase noise as the two
equal to 1 across the commutation, the whole of the nMOS transistors in Fig. 5 together.
noise is turned into phase noise, not just half of it. We have already mentioned that the transistor ISF in the
Calculations are lengthy, but the final expression for the class-B oscillators is very nearly unity when it matters, which
phase noise induced by both tank losses and MOS pair is means that we would have had the theory (almost) right even
very simple [15]: bypassing the ISF theory altogether [17]. However, while
    this is true for a class-B oscillator, it would definitely not
2kB TR(1 + γn ) 1 ω0 2
Lclass−B (ω) = 10 log10 be the case in, e.g., a Colpitts oscillator, where ignoring
A2pk /2 2Q ω the ISF results in a badly wrong phase noise prediction.
(10) The reason for this is obvious from Fig. 17: far from being

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FIGURE 18. Simplified schematic view of a class-C oscillator.

FIGURE 17. Noise current, ISF and effective noise current for the Colpitts oscillator
of Fig. 2.
transistor pair downwards, as done in Fig. 18 by means of
an RC filter that should load the tank as little as possible.
unity, the transistor ISF is in this case small, even vanishing Another possibility is to replace the tank inductance with
when transistor noise is at a maximum. Thus, the effective a transformer and use the center-tapped secondary coil for
transistor noise is here much smaller than the native transistor feedback and DC bias [18]. The DC bias voltage is gener-
noise. ated by a low-frequency feedback loop for optimal oscillation
The phase noise equation for a Colpitts oscillator is [15] amplitude [19]–[21].
   Still, the demand that the transistor pair should stay safely
kB T 1−n in the active region entails that we can obtain a higher
L(ω) = 10 log10 1 + γn
4IB2 R3 (1 − n)2 C2 ω2 n maximum oscillation amplitude in the ideal class-B CMOS
(12) oscillator (ideal being the keyword here), since the MOS
devices there are mostly working as switches deeply in
where the oscillation amplitude has been written in terms the linear region. When we deal with real implementations,
of IB , R and n to emphasize the dependence of (12) on though, the class-C oscillator may have an edge, albeit not
n, showing that there is an optimal value of n minimizing a large one [21]. Finally, since BJT transistors cannot be
phase noise (close to 0.3 for reasonable values of γn ). In allowed to enter saturation, the class-C topology is definitely
absolute terms, Colpitts phase noise is (marginally) higher very attractive for BJT oscillators [22].
than in a class-B oscillator, assuming identical R and IB . It is noteworthy that, in all phase noise expressions derived
In fact, while it is true that the Colpitts class-C current so far, transistors contribute in proportion to the tank through
waveform yields a superior conversion of IB into the first γn (γp ), where the proportionality factor depends on the spe-
current harmonic, the feedback n from MOS drain to source, cific oscillator topology. In fact, this is not a coincidence, but
essential to generate the negative resistance, increases phase rather a general result for harmonic oscillators [9], [18], [23]:
noise, as it decreases the oscillation amplitude [denominator if 1) the ISF is sinusoidal and in quadrature with the
of (12)] and boosts the transistor contribution [last term tank voltage (which is typically the case); 2) all negative-
in (12), where the fraction is equal to 2 when n = 1/3]. resistance devices are either off, or working as transistors
These drawbacks can be avoided, while retaining a class-C in the active region (this is effectively the case in a class-B
operation, by moving to a differential architecture, since there oscillator as well, even though transistors there work in the
the negative resistance is immediately synthesized, as we linear region for most of the time, since they do work in
have already seen, by cross-coupling the feedback signals the active region when they generate their contribution to
from the differential tank to the gates of the transistor pair. phase noise [15]); and 3) the current noise PSD of these
This means that we can set n to 0, i.e., we can remove C1 transistors is proportional to their transconductance, then
altogether, keeping C2 to shape the class-C current, as in it is possible to show that the phase noise caused by the
Fig. 18 [18]. transistors depends only on tank losses and oscillator topol-
Ideally, the class-C oscillator yields a 20 log 10 (π/2) ≈ ogy, and nothing else. Actually, the first condition above
4 dB lower phase noise than the class-B oscillator with can be removed by adopting a more powerful (and much
the same IB . The class-C oscillator comes, however, with less intuitive) phase noise analysis, where no assumptions
a number of issues, and primarily that the differential pair are required on the nature of the resonator, which may be
must not be allowed to enter the linear region of opera- much more complex than a simple LC tank [24]. As a final
tion, which would thwart class-C operation by shorting tank word on this theme, we remark that compacting all tank
and C2 together, bringing about a large phase noise penalty. losses into an equivalent parallel tank resistance may not
This means that we must shift the DC gate voltage of the be correct in some (uncommon) cases, due to the fact that

8 VOLUME 1, 2021
high-frequency noise from the resistance in series with C
acts almost unimpeded on the transistor pair, since C itself
offers a negligible impedance at frequencies much higher
than ω0 (opposite to L, whose impedance blocks all high
frequency noise). If the transconductance of the transistor
pair is inordinately large, as it may be in particular topolo-
gies, the high frequency noise from such a resistance can mix
with the relevant transconductance harmonic to be folded in
the vicinity of ω0 , increasing phase noise [25]. Even in this
case though, tank and transistors contribute in the same fixed
proportion to phase noise.
FIGURE 19. Possible implementations of the tail current source.
A. A REMARK ON THE ISF
If we consider an oscillator where the negative-resistance
transistors act as transconductors with an ideally infinite in modern CMOS processes, which means that the oscillator
output impedance, as in all cases above, then it is correct behavior may depart significantly from the ideal situation we
to take the fist-order expression of the ISF as a pure sinu- have assumed so far. In particular, the upconversion of 1/f
soid proportional to the derivative of the voltage across the MOS noise may become significant, from being negligible in
resonator − which coincides with the voltage across the the ideal case (see Section IV-A). The bias resistance may be
transistors − when the resonator is a simple LC tank with a dispensed with altogether, making the current consumption
reasonable Q [24]. Things are different when the negative- of the oscillator wholly dependent on VDD (which is such an
resistance transistors are pushed into the linear region of important feature that these are referred to as voltage-mode
operation over a fraction T  of T0 , where they come to work oscillators) and transistor strength, and usually exacerbating
as (small) resistors. When this happens, the voltage across 1/f noise upconversion. Clever countermeasures to the latter
the transistors becomes almost constant, which would seem have been devised, e.g., resistors in series with the drains
to imply that the ISF is negligible across T  − in fact, it of the transistors [27], [28] or a commom-mode resonance
is often assumed that in this situation the noise from the at twice the oscillation frequency [29], [30] (about which
transistors, or from the tank, or both, is not converted into more presently). In general, one would wish that the 1/f 3
phase noise thanks to a supposedly close-to-zero ISF. performance of voltage-mode oscillators were more robust
This is a wrong conclusion, stemming from the belief with respect to unavoidable voltage, process, and temperature
that the ISF can always be calculated by injecting a current (PVT) variations.
pulse in parallel to the LC tank [11], and that such a pulse A popular alternative is an active current source (Fig. 19),
is completely drained by the small resistance presented by which benefits from a high output impedance and a more
the transistors without affecting the LC tank. In reality, the ideal oscillator operation with it; the drawback is that it
notion of equivalent parallel tank resistance breaks down if itself generates a possibly large amount of 1/f noise, which
the transistors work as small resistors [3], when the most con- is actually much more prone to upconversion that the one
venient way to derive the ISF is by modeling a linear-region from the MOS pair.
transistor as a voltage noise source rather than a current noise A certain amount of parasitic capacitance at the common
source [3] (by virtue of Norton’s theorem, voltage-mode source of the MOS pair is unavoidable, and simulations show
and current-mode models are mathematically equivalent, but that this may result in a deterioration of phase noise, even
the former lends itself most naturally when the impedance by a large amount, if the transistors are allowed to enter the
presented by the transistor is low). This approach applies linear region of operation as is typical in class-B designs.
to the LC tank losses as well, and makes it clear that the Again, it is the upconversion of 1/f noise that is of particular
ISF is far from negligible even when the large-signal voltage concern.
across the transistors hardly moves [3], and may in fact be A popular and effective solution to this problem is the
quantitatively identical to (9) [26]. noise filter [31] of Fig. 20. The parasitic capacitance Cpar
is made to resonate with Ltail at 2ω0 , i.e., at the natural
IV. BIAS frequency of the common source, boosting its impedance
So far, we have assumed an ideal bias current IB in all and recovering close-to-ideal current waveforms. Ctail filters
oscillators, but this is hardly the case in practice, and in fact the high frequency noise from the tail, besides giving an AC
the way we implement the real bias current may become a ground to Ltail . At the same time, the parasitic capacitance
major limitation for the phase noise performance. in the tail nMOS current source can be absorbed into Ctail ,
As shown in Fig. 19, we can use a resistance, perhaps which means that the dimension of this nMOS can be large;
tunable in steps: this is very simple and has the advantage in particular, a long device generates a lower 1/f noise, while
that the resistance does not generate any 1/f noise. This a large aspect ratio minimizes the DC drop across the chan-
resistance is typically not large however, due to the low VDD nel. A (minor) drawback is that an extra inductor is needed,

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ANDREANI AND BEVILACQUA: HARMONIC OSCILLATORS IN CMOS—TUTORIAL OVERVIEW

FIGURE 22. Transformer-based oscillators implementing differential-mode

resonance at ω0 and common-mode resonance at 2ω0 , as proposed in [29], [33].
FIGURE 20. The tail noise filter.

both (voltage) oscillation and ISF are pure sine waves in

quadrature with each other [11] (which is usually enough
for a satisfactory treatment of the conversion of white
noise into phase noise, as we have seen). The situation
is actually even more complex than that: the upconver-
sion vanishes in both class-B and class-C oscillators if they
employ ideal, square-law MOS transistors with no parasitic
capacitances, independently of the shape of the oscillation
waveforms, provided the PSD of the 1/f noise is proportional
to the transistor current, i.e., to the square of the transistor
transconductance [10], [34].
Thus, unlike, e.g., CMOS ring oscillators, where the
1/f noise upconversion is a first-order effect [35]–[37],
harmonic oscillators force us to consider a number of second-
order effects (transistor non-idealities, parasitic capacitances,
the exact dependence of 1/f noise on device parameters,
etc.) that make the analysis repulsively intricate. To date,
FIGURE 21. Class-B oscillator with noise filters as proposed in [32]. only one such analysis has been carried out [10], and this
under strongly simplifying hypotheses and addressing a sin-
gle transistor non-ideality (velocity saturation of the charge
but the technique has proved so effective that it has spawned carriers in the MOS channel). Even so, it is anything but
a large number of variations and has become a staple of trivial.
class-B oscillator design. As an example, Fig. 21 shows a Despite the above, simulations and measurements alike
class-B oscillator with complementary switch pairs, where have consistently shown that a strong common-mode reso-
Ltail has been substituted with a transformer to increase the nance at 2ω0 (and a fortiori at all even harmonics) in class-B
impedance at the common source of both pairs. The overall oscillators is effective in limiting the 1/f noise upconver-
performance of this oscillator is excellent [32]. sion to a low level, the main concern of the technique being
Alternatives to the noise filter have been proposed simulta- its robustness to PVT variations, as well as to intentional
neously by two research groups [29], [33]. The idea (Fig. 22) variations of ω0 (discussed in Section V). A simple qual-
is to design a transformer-based tank having two distinct itative explanation of this is that the current waveforms in
resonances: at ω0 for differential signals, as usual, and at the class-B oscillator get closer to the ideal ones when even
2ω0 for common-mode signals. It can be shown that this is current harmonics are suppressed by the common-mode res-
equivalent to a noise filter, at least in principle [30]. onance at 2ω0 , and we have already seen that no 1/f noise
upconversion occurs in an ideal class-B operation.
A. 1/f NOISE A different route to the containment of 1/f noise upconver-
The analysis of the upconversion of 1/f noise into phase sion is via the class-C oscillator, which, to repeat, is ideally
noise in harmonic oscillators is particularly difficult, since immune to it [10], [34]. Notice that this is true even though
such an upconversion vanishes if we stop the analysis at class-C current waveforms do contain even harmonics: the
the first order of approximation, i.e., if we assume that apparent contradiction is resolved by recalling that the core

10 VOLUME 1, 2021
transistors in a class-B oscillator are allowed to enter the
linear region of operation, becoming switches, while those
in a class-C oscillator are not (if, on the other hand, the
class-B transistors are kept out of the linear region, no noise
filter is needed to prevent 1/f noise upconversion, the oscil-
lator effectively working somewhere between ideal class-B
and ideal class-C depending on the amount of Cpar [10]). In
a class-C oscillator, too, the MOS current generator can be FIGURE 23. Cross section of an AMOS varactor.
made long and wide, as was the case in the class-B oscil-
lator with noise filter, since its parasitic capacitances can
be absorbed into Ctail (up to a limit, though, as the exotic
squegging behavior must be avoided [18]). Despite encour-
aging results [10], the effectiveness of the class-C oscillator
in rejecting 1/f noise has yet to be probed in earnest.

B. FIGURE OF MERIT
To assess the performance of an oscillator in terms of phase FIGURE 24. C-V curve of an AMOS varactor (in red) as compared to a pMOS device.
noise, and possibly compare it to that of other oscillators,
phase noise is normalized vs oscillation frequency, off-
set frequency, and power consumption (P, traditionally V. FREQUENCY TUNING
normalized to 1 mW). The resulting figure of merit, FoM, is An oscillator where the oscillation frequency cannot be var-
ω   
FoM(ω) = −L(ω) + 20 log10
0
− 10 log10 103 P ied at least to some extent is useless in practice, as this is
ω needed to counteract uncertainties in component values as
(13) well as PVT variations. Since the oscillation frequency is
It is easy to show that the FoM can be written as typically adjusted through a control voltage, real oscillators
 2  are voltage-controlled oscillators (VCOs, or, if the control
2Q η
FoM(ω) = 10 log10 − 30 dB (14) voltage is a purely digital signal, DCOs).
kB T F The easiest way of tuning the oscillation frequency is
where the maximum FoMmax is obtained for an oscillator by replacing part of the tank capacitance with a compo-
power efficiency η of 1 (when all power is consumed in the nent whose capacitance is dependent on the DC voltage
resonator) and a noise factor F of 1 (when only the tank across the component itself, realizing a variable reac-
generates phase noise). The strong FoM dependence on the tor (varactor). Two such components are readily available
resonator Q is obvious. in any CMOS process: the (parasitic) pn diode and the
The FoM is an important instrument for the oscillator MOS device itself. Particularly attractive is the two-terminal
designer, who can gauge the oscillator quality across var- accumulation-mode nMOS device in an N-well (AMOS),
ious design stages, provided this information is combined shown in Fig. 23 [41]–[43], replacing the standard four-
with a knowledge of the discrepancy that can be reasonably terminal nMOS device in a P-well. This maximizes the
expected between FoM and FoMmax . capacitance variation vs DC voltage between gate and
The FoM is also useful in comparing different oscillator substrate, as the AMOS works between accumulation (max-
topologies, for instance the class-B oscillator with a sin- imum capacitance) and depletion (minimum capacitance)
gle switch pair vs two complementary switch pairs. Perhaps while avoiding inversion (where the capacitance would
surprisingly, these two topologies are ideally capable of the climb back to its maximum value), as depicted in Fig. 24.
same FoMmax , which however is attained at different lev- Moreover, compared to a pMOS device in a P-well, losses
els of phase noise and power consumption. This opens up are minimized by the higher electron mobility.
for a reconfigurable architecture where one or the other An efficient frequency tuning is thus obtained by connect-
configuration is selected, based on specific phase noise ing two back-to-back AMOS devices to the oscillator tank,
requirements [38]. each gate to the respective differential tank node, while the
The importance of a high FoM in boosting the perceived common AMOS substrate is acted upon by the control volt-
importance of a work cannot be overstated. This is not age. Compared to the reverse-biased diode, which may carry
entirely positive, as the FoM is not well suited to cap- a large DC current if it becomes forward biased by too large
ture vital oscillator features in real-life applications, such an oscillation amplitude, which would destroy the tank Q,
as robustness to PVT variations and EM disturbances. As the AMOS varactor allows for a more robust design, as it
an example, we can mention that using an 8-shaped induc- is a natural DC blocker.
tor can dramatically improve the oscillation insensitivity to In principle we can increase the frequency tuning range
external magnetic fields, but also (slightly) decreases tank (TR) of the oscillator by means of a larger varactor. This
Q and FoM with it [39], [40]. is not a popular choice though, as the noise present on

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ANDREANI AND BEVILACQUA: HARMONIC OSCILLATORS IN CMOS—TUTORIAL OVERVIEW

FIGURE 25. Typical circuit for a switchable differential capacitance CSC .

FIGURE 26. Switchable capacitor bank for discrete frequency tuning.

the control voltage is also going to affect the oscillation

frequency, contributing a surplus of phase noise: if the var-
latter. By the same argument, the product of Ron and CSB
actor is very large, the control voltage would have to be
is a (first-order) technology constant, and should be as low
extremely clean to avoid a significant phase noise deterio-
as possible in a harmonic-oscillator-friendly CMOS process
ration. Furthermore, the various 1/f current noise sources
[e.g., a fully-depleted silicon-on-insulator (FD-SOI) CMOS
in the oscillator may determine a change in the oscilla-
process].
tion amplitude across the varactor, inducing a change in the
Finally, the value of the decoupling resistance Rdcp should
effective capacitance presented by the varactor itself: this is
be so high as to leave the tank Q unaffected in the off-state;
invariably a major mechanism of 1/f noise upconversion if
yet, the desired value of Rdcp may be limited by the follow-
the varactor is large [44], [45].
ing interesting mechanism: the low-frequency noise voltage
The varactor is therefore not larger than what is needed
from Rdcp modulates the MOS source voltage, which mod-
to ensure phase lock when the oscillator is used in a
ulates the value of the non-linear CSB , which modulates the
phase-locked loop (PLL), possibly accommodating phase
frequency of oscillation, which is tantamount to generating
modulation as well, while the rest of the TR is covered
phase noise. An FD-SOI CMOS technology may be of great
in discrete steps by switching a number of linear capacitors
help also in this respect.
in and out of the oscillator tank [46].
We conclude this section by mentioning that phase noise
and tuning range are often baked together in an augmented
A. DISCRETE TUNING
figure of merit, FoMT . Unlike the FoM of (13), FoMT does
A typical arrangement for switching one such differential
not rest on a firm theoretical ground, making its widespread
capacitor is shown in Fig. 25. When Vctr is high (e.g.,
use questionable.
equal to VDD ), the (minimum-length) MOS device becomes
a small resistance Ron in series with the two capacitors CSC ,
each connecting to one side of the differential tank. In this B. VERY WIDE FREQUENCY TUNING RANGE
way, the overall tank capacitance is increased, decreasing f0 . The ongoing band proliferation in wireless communication
Obviously, Ron must be low to avoid a degradation of the favors VCOs with a very wide TR, where a TR larger than
overall tank Q [47], which means that Vctr,S should be low one octave is especially attractive, as all lower frequencies
(e.g., 0 V) to maximize the MOS overdrive voltage. When can be generated by repeated frequency division by two,
Vctr is low, on the other hand, ideally no extra capacitance which is easy enough to implement.
loads the tank, leaving f0 unaffected; in reality, the para- The simplest way of obtaining a very wide TR is to design
sitic MOS capacitances between gate and drain/source and the LC tank with a relatively small inductance and a suf-
between drain/source and bulk (since no DC current flows ficiently large array of switchable capacitances (Fig. 26),
in the device, drain and source swap place together with the which must vary by at least a factor of four from minimum
direction of the AC MOS current), i.e., CGS and CSB , make to maximum to cover one octave of TR. The corresponding
the off-state capacitance approximately equal to CGS + CSB , large number of MOS switches introduces a large parasitic
forcing a deleterious drop in f0 . It is therefore advantageous non-linear capacitance as well. In this solution, power is
to set Vctr,S as high as possible in the off-state, which min- likely to be wasted at the lowest oscillation frequencies, com-
imizes the value of the reversed-biased diode capacitance pared to reasonable phase noise specifications: as soon as we
CSB . Care must be taken though that the peak value of the are able to establish an oscillation, phase noise is already
oscillating voltage, added to Vctr,S , does not exceed the max- unnecessarily low, as can be appreciated from, e.g., (10)
imum rating for the MOS device; the availability of two (or when R is very low (which is a consequence of the relation
more) supply voltages eases the task considerably [39]. Q = Rω0 C, assuming a very large C and a reasonable Q).
It is immediate to see that there is a hard trade-off between One might think of reducing power by scaling down Apk
Ron and CSB , as a larger MOS device decreases Ron and in (10) by a sizeable amount, but this is not without compli-
increases CSB by the same amount. The same trade-off acts cations, as it needs a dedicated and precise controller of the
between tank Q and TR, since a large CSB impairs the oscillation amplitude and, moreover, the circuitry driven by

12 VOLUME 1, 2021
 FIGURE 29. Examples of varactor coupling using a magnetic transformer:
(a) pn-varactor; (b) MOS varactor.

FIGURE 27. Switched inductor, as proposed in [48].

FIGURE 30. Dual-mode oscillator proposed in [57].

both resonances are used to expand the TR, it is still possible

to achieve a comparable Q at both. As an aside, it must be
noted that the increase in Q due to the mutual inductance
between the transformer primary and secondary windings is
FIGURE 28. Transformer-based dual-mode oscillator. enjoyed by a standard inductor as well, as its turns are also
mutually coupled. As a consequence, there is no intrinsic Q
improvement from the sheer use of a transformer [54], [55].
the oscillator (distribution buffers, frequency dividers, etc.) A transformer is useful for frequency tuning from a dif-
typically expects an input close to rail-to-rail. ferent perspective, too: it provides a means to AC-couple the
It is also possible to switch inductors [48] instead of capac- varactor to the tank and, simultaneously, a convenient bias
itors, as shown in Fig. 27. Two problems may affect this point for the varactor via the center tap of the secondary
approach: the MOS switch turning the inductor on and off winding, as shown in Fig. 29. This is especially effective
may have to carry a (large) DC current, and the parasitic at mm-wave frequencies (and higher), where capacitor Q
capacitances introduced by the switch may shunt at least is lower than inductor Q. AC-coupling the varactor is typi-
part of the inductor. To date, switched inductors are not cally required to explore the entire TR without the need of
behind the best VCOs, although very wide TRs have been a separate DC voltage, or, when a pn diode is used, as in
demonstrated. Fig. 29(a), to avoid the junction turn-on during part of the
A more attractive choice is a magnetic transformer [49] oscillation cycle, which would heavily deteriorate the tank
(hereafter simply referred to as a transformer), with which Q [52], [56], as already mentioned.
two distinct resonances can be realized [50], [51]; a very An elegant development of the dual-mode oscillator is
large overall TR can then be obtained by joining two over- shown in Fig. 30 [57], yielding excellent phase noise and
lapping TRs, each tuning one of the resonances. While two FoM with a TR wider than one octave; a mm-wave example
active oscillator cores are needed (Fig. 28), the great advan- is presented in [58], with oscillation frequency spanning from
tage here is that it is the cores that are turned on/off (one 25 to 38 GHz.
at a time, depending on which of the resonances should be A different take in the same spirit is the mode-switching
active) by turning on/off their bias current, so that no switch VCO in [59], with four inductors and, again, two oscillation
is placed in series with any inductor, with great benefit for modes. Here, MOS switches are used to hop between the
the resonator Q. two oscillation modes, but in such a way that they do not
The mutual inductance between the coupled coils of the carry any signal, thereby avoiding again any Q deterioration.
transformer increases the energy stored in the resonator at The mode-switching VCO achieves a very wide TR, a very
the lower resonance while decreasing it at the higher res- low phase noise and an excellent FoM at the same time, the
onance [52], [53]. If only one resonance is used, then this (partial) downside being the large area needed by the four
must be the lower one, as the resonator Q is thus maximized. coils. A further desirable feature of this architecture is its
Nevertheless, the resonator Q increases with frequency, as rejection of external magnetic fields (the same property of
long as it is limited by the transformer itself. Hence, when the aforementioned 8-shaped inductor).

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ANDREANI AND BEVILACQUA: HARMONIC OSCILLATORS IN CMOS—TUTORIAL OVERVIEW

The success of these works has attracted a great deal sufficiently strong third harmonic from an oscillator work-
of interest in transformer-based/mode-switching techniques, ing at ω0 , realizing an implicit frequency multiplication by
which are currently a very active research area [60]–[64]. three [67], [68], which is especially useful at mm-waves.
Finally, since low power consumption and design sim- Multiple coupled inductors potentially allow all node volt-
plicity and robustness are priorities in portable wireless ages in the oscillator to swing below ground and/or well
applications, we note that commercial designs often obtain above the power supply [61], [69], increasing the maximum
a very large effective TR in the most straightforward way, amplitude of oscillation, with obvious benefits for phase
i.e., by optimizing two (or more) VCOs with much narrower noise. This is particularly welcome when very low supply
TRs and letting the TRs overlap one another, trading silicon voltages are used. It also results in an improved DC-to-RF
area for power efficiency. power efficiency, and hence a higher FoM. The downside is
that the higher voltage excursions may exceed the voltage
VI. IMPROVING PHASE NOISE ratings of the transistors, raising reliability concerns.
In the evolution of systems for communication, radar, and
data conversion, the requirement of ever higher spectral
purity is relentless. At the same time, the constantly dropping A. MULTI-CORE OSCILLATORS
power supply voltage in modern ultra-scaled CMOS tech- To further improve phase noise, N identical oscillators can
nologies thwarts this very goal, as a lower supply voltage be coupled and operated in a synchronous fashion [70]–[75],
translates to a lower maximum attainable oscillation ampli- thereby lowering the phase noise power by a factor N. In
tude, yielding a higher minimum phase noise, as is clear this way, a higher power consumption is traded for a lower
from (5). Since the resonator Q is set by technology and phase noise, ideally keeping a constant FoM and accepting
frequency of operation, (5) points out that the only possibil- the drawback of a larger silicon area.
ity to reach a lower phase noise is to reduce the resonator The implementation of large arrays of coupled oscillators
parallel resistance R (which entails a reduction of L), thereby and the achievement of the related phase noise benefit is
trading a higher power consumption for a lower phase noise. not trivial. Ideally, the coupling network should not affect
This approach cannot be pursued indefinitely, however, as the operation of the synchronized oscillators, nor degrade
there is a lower bound to the minimum practical value of R. the phase noise performance. However, if the oscillator
The use of a transformer-based resonator can help obtain- coupling is weak (i.e., the coupling impedance is high)
ing a lower value of R: it can be shown that the equivalent the mentioned phase noise improvement may be experi-
resistance of such a resonator is similar to what would be enced only at small frequency offsets from the carrier.
achieved by shunting the coupled coils in the transformer Additionally, mismatches between the resonance frequencies
(while adjusting the capacitance to keep a constant resonance of the individual resonators induce a phase noise degra-
frequency). dation that increases with the impedance of the coupling
A transformer brings about an additional advantage: it may network [73]. Thus as N increases, the coupling network
provide a passive voltage gain. This is leveraged to introduce becomes correspondingly more difficult to design; a star con-
a gain Av between the output (drain) and the input (gate) of nection, where each oscillator is globally coupled to all the
the negative-resistance transistors, resulting in a reduction of others, becomes impractical, and one has to resort to nearest-
the transistor contribution to phase noise [18], [52], with a neighbor bilateral coupling. This sets some challenges, as it
lower factor F in (5), which becomes is more susceptible to mismatch-induced phase noise degra-
dation [73], [76]. Moreover, the coupling network of a large
γ
F =1+ (15) array of oscillators tends to introduce more parasitics, due to
Av its larger footprint, potentially creating unwanted systematic
It must be noted that this approach is viable as long as mismatches between the oscillators and shifts in the oscilla-
the voltage swing at the input of the transistors does not tion frequency. Another issue related to oscillator coupling
compromise their reliability. is that undesired modes of oscillation might emerge, which
Yet another option offered by a transformer-based res- must be suppressed by a judicious design of the coupling
onator is to introduce an additional differential-mode res- network [71], [72]. As the lowest achievable phase noise
onance located at 3ω0 , often together with the already may not always be needed by the system where the oscilla-
discussed common-mode resonance at 2ω0 , as in the class-F tor operates, reconfigurability of the coupled-oscillator array
oscillator in [65]. The rationale behind this is that a steeper is a welcome feature [73], where the goal is to be able to
slope is obtained in the waveform of the oscillation, which switch off some oscillators to save power when the attending
shortens the time interval when the negative-resistance tran- phase noise deterioration is acceptable. Such reconfigurabil-
sistor generates noise, lowering phase noise; now, however, ity requires the possibility to individually turn on/off and
noise at 3ω0 ± ω also contributes to phase noise, which disconnect the oscillators from the array (Fig. 31); the lat-
may even increase overall if the resonator Q at 3ω0 is not ter operation is non-trivial, as it requires additional switches
sufficiently high [24], [66]. Nevertheless, an additional res- in the coupling networks, which may increase the coupling
onance at 3ω0 may still be used with advantage to extract a impedance and phase noise with it.

14 VOLUME 1, 2021
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[74] A. Moroni, R. Genesi, and D. Manstretta, “Analysis and design of ANDREA BEVILACQUA (Senior Member, IEEE)
a 54 GHz distributed ‘hybrid’ wave oscillator array with quadrature received the Laurea and Ph.D. degrees in elec-
outputs,” IEEE J. Solid-State Circuits, vol. 49, no. 5, pp. 1158–1172, tronics engineering from the University of Padova,
May 2014. Padova, Italy, in 2000, and 2004, respectively.
[75] Y. Peng, J. Yin, P.-I. Mak, and R. P. Martins, “Low-phase-noise From 2005 to 2015, he was an Assistant
wideband mode-switching quad-core-coupled mm-Wave VCO using a Professor with the Department of Information
single-center-tapped switched inductor,” IEEE J. Solid-State Circuits, Engineering, University of Padova, where he
vol. 53, no. 11, pp. 3232–3242, Nov. 2018. is now an Associate Professor. His current
[76] H.-C. Chang, X. Cao, U. K. Mishra, and R. A. York, “Phase noise research interests include the design of analog and
in coupled oscillators: Theory and experiment,” IEEE Trans. Microw. RF/microwave integrated circuits and the analysis
Theory Techn., vol. 45, no. 5, pp. 604–615, May 1997. of wireless communication systems, radars, and
dcdc converters. He is author or coauthor of more than 100 technical
papers, and he holds 6 patents. Prof. Bevilacqua was a member of the
ITPC of IEEE ISSCC from 2017 to 2021. He served in the TPC of IEEE
ESSCIRC from 2007 to 2019, and was TPC Co-Chair of IEEE ESSCIRC
PIETRO ANDREANI (Fellow, IEEE) received the 2014. He was a member of the TPC of IEEE ICUWB from 2008 to 2010.
M.S.E.E. degree from the University of Pisa, He was an Associate Editor of the IEEE TRANSACTIONS OF CIRCUITS
Italy, in 1988, and the Ph.D. degree from Lund AND S YSTEMS II from 2011 to 2013 and was nominated Best Associate
University, Sweden, in 1999. Editor for the IEEE TRANSACTIONS OF CIRCUITS AND SYSTEMS II for
From 2001 to 2007, he was a Chair Professor 2012 to 2013. He served as a Guest Editor for the special issue of the
with the Center for Physical Electronics, Technical IEEE JOURNAL OF SOLID-STATE CIRCUITS dedicated to ESSCIRC 2017.
University of Denmark. He was a part-time He currently serves in the Distinguished Lecturer program of the IEEE
IC Designer with Ericsson AB, Lund, Sweden, Solid-State Circuits Society.
from 2005 to 2014. Since 2007, he has been
an Associate Professor in IC design with
the Department of Electrical and Information
Technology, Lund University. He has been a TPC member of ISSCC from
2007 to 2012, and a Distinguished Lecturer of the IEEE Solid-state Circuits
Society from 2017 to 2019. He is a TPC Member of ESSCIRC (Chair of
the Frequency Generation Subcommittee; TPC Chair in 2014) and RFIC,
and an Associate Editor of the IEEE JOURNAL OF SOLID-STATE CIRCUITS.

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