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Jaimin Brahmbhatt COSC 6351 Advanced Computer Architecture Assignment

The document contains solutions to 4 problems related to cache memory systems: 1) The average access time of a computer system for read and write requests is calculated as 6.08 ns. 2) The pertinent information for a two-way set associative cache is described, and the cache size is determined to be 4096 * 80 bits. 3) The miss rates for first and second level caches are calculated from given data, and the average memory access time is determined to be 4 clock cycles. 4) To obtain a 65% improvement in average memory access time by adding a second level cache, the required hit ratio for the second level cache is calculated to be 75.03%.

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68 views3 pages

Jaimin Brahmbhatt COSC 6351 Advanced Computer Architecture Assignment

The document contains solutions to 4 problems related to cache memory systems: 1) The average access time of a computer system for read and write requests is calculated as 6.08 ns. 2) The pertinent information for a two-way set associative cache is described, and the cache size is determined to be 4096 * 80 bits. 3) The miss rates for first and second level caches are calculated from given data, and the average memory access time is determined to be 4 clock cycles. 4) To obtain a 65% improvement in average memory access time by adding a second level cache, the required hit ratio for the second level cache is calculated to be 75.03%.

Uploaded by

ibrahim
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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Jaimin Brahmbhatt COSC 6351 Advanced Computer Architecture Assignment #2

1. Find the average access time of a computer system for read and write requests. A write-through
procedure is used in the system, where 20 percent are memory write requests, access time for cache
memory is 5ns and that of main memory is 8ns, and the hit ratio for read accesses is reported to be 0.8.

Solution:

Access time for cache memory is 5ns Access time for main memory is 8ns Hit ratio for read access is 0.8
20 % - Memory write requests i.e. 80% - Memory read requests Average access time for memory read =
hit ratio * cache access time + (1 – hit ratio) * Main Memory access time = 0.8 * 5 + 0.2 * 8 = 5.6 ns To
find the average access time of the system for both requests. As Memory read request takes 80% and
write requests takes 20% Therefore, Average access time for memory write = 20% of Main memory
access time = 0.2 * 8 = 1.6 ns So average access time for computer system for read and write requests =
0.8 * 5.6 + 0.2 * 8 = 6.08 ns

Jaimin Brahmbhatt COSC 6351 Advanced Computer Architecture Assignment #2

2. A two-way set associative cache memory uses blocks of four words. The cache can accommodate a
total of 8192 words from main memory. The main memory is 1M X 32. a) Formulate all pertinent
information (tag, index, block, and word sizes) required to construct the cache memory. b) What is the
size of the cache memory?

Solution:

Each word of cache set contains two data words. If cache can accommodate a total of 8192 words from
main memory = cache size is 8192 / 2 = 4096 words Here Block size = 4 words 4096 / 4 = 1024 blocks (2

10

) 10 bits needed to access all blocks. To access 4 words inside a block we need 2 bits (2

) i.e. Index = 10 + 2 = 12 bits Here memory size is 1M = 1024 K = 2

10

 * 2

10
 = 2

20

i.e. 20 bits Tag size = 20 – 12 = 8 bits Cache size = 4096 * 2 (tag size + main memory) = 4096 * 2 (8 + 32) =
4096 * 80 bits

Jaimin Brahmbhatt COSC 6351 Advanced Computer Architecture Assignment #2

3. Suppose that in 1000 memory references there are 100 misses in the first level cache and 10 misses in
the second level cache. a) What is miss rate (local or global) for the first level (L1)? b) What is the miss
rate (local) for the second level (L2)? c) Assume miss penalty from L2 cache to memory is 200 clock
cycles, the hit time of the L2 cache is 10 clock cycles, and the hit time of L1 is 1 clock cycle. What is the
average memory access time? Ignore impact of writes.

Solution:

a)

For the first level (L1) miss rate = 100 / 1000 = 0.1 or 10% b)

For the second level (L2) miss rate = 10 / 100 = 0.1 or 10% c)

L2 cache miss penalty = 200 clock cycles L2 cache hit time = 10 clock cycles L1 cache hit time = 1 clock
cycle Average memory access time = Hit time (L1) + miss rate (L1) * (Hit time (L2) + miss rate (L2) * Miss
penalty L2) = 1 + 0.1 (10 + 0.1 * 200) = 1 + 3 = 4 clock cycles

4. The average memory access time for a microprocessor with 1 level of cache is 2.4 clock cycles. If data
is present and valid in the cache, it can be found in 1 clock cycle. If data is not found in the cache, 80
clock cycles are needed to get it from off-chip memory. Designers are trying to improve the average
memory access time to obtain a 65% improvement in average memory access time (i.e., speedup =
1.65), and are considering adding a 2nd level of cache on-chip. This second level of cache could be
accessed in 6 clock cycles. To obtain the desired speedup, how often must data be found in the 2nd level
cache (hit ratio for 2nd level cache)?
Solution:

Memory access time of processor with L1 cache is 2.4 clock cycles. L1 cache hits take 1 clock cycle L1
cache miss takes 80 clock cycles Effective memory access time = L1 cache hit * L1 cache access time + L1
cache miss * (L1 cache access time + main memory access time) 2.4 = h1 * 1 + (1 – h1) * (1 + 80) 2.4 = h1
+ 81 – 81h1 h1 = 0.9825 In L2 cache memory access has new speedup = 1.65 Therefore, old time / new
time = 1.65, 2.4 / new time = 1.65 New time = 1.4545 We are considering adding a 2

nd

 level of cache on chip. Access time for 2

nd

 level cache = 6 clock cycle We must find hit ratio for 2

nd

 level cache h2. 1.4545 = h1 * 1 + (1 – h1) * h2 (L2 cache access clock cycles + Main memory access
clocks) + (1-h1) (1-h2) * (L1 cache access clock cycles + L2 cache access clock cycles + Main memory
access clocks) 1.4545 = 0.9825 + 0.0175 * h2 (6 + 1 + 0.0175(1 – h2) * (80 + 6 + 1) 0.472 = 0.1225h2 +
1.5225 – 1.5225h2 h2 = 1.0505 / 1.4 = 0.7503 or 75.03%

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