Experiment 10 - Lab Report
Experiment 10 - Lab Report
EXPERIMENT NO 10
Lab Title:
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Student Name: ______________________________________ Reg. No:
_________________
Objective: ___________________________________________________________________
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LAB ASSESSMENT:
Data presentation
Experimental results
Conclusion
Objective:
Familiarizing students with ADC in PIC18F452 and writing codes in MikroC to convert analog
values to digital values
Equipment:
Hardware:
1. PIC18F452 microcontroller
2. 16x2 LCD
3. RIMS Trainer
4. DMM
Software:
1. mikroC Pro
2. SmartPRO 5000U
3. Proteus
Introduction:
The Analog-to-Digital (A/D) converter module has five inputs for the PIC18F2X2 devices and eight for
the PIC18F4X2 devices. This module has the ADCON0 and ADCON1 register definitions that are
compatible with the mid-range A/D module. The A/D allows conversion of an analog input signal to a
corresponding 10-bit digital number.
The ADCON0 register controls the operation of the A/D module. The ADCON1 register configures the
functions of the port pins.
ADCON0 Register:
The ADCON0 register with detail explanation of function of each bit is given below:
ADCON1 Register:
The ADCON1 register with detail explanation of function of each bit is given below:
where:
The analog reference voltage is software selectable to either the device’s positive or negative supply
voltage (VDD and VSS), or the voltage level on the RA3/AN3/VREF+ pin and RA2/AN2/VREF- pin.
The A/D converter has a unique feature of being able to operate while the device is in SLEEP mode. To
operate in SLEEP, the A/D conversion clock must be derived from the A/D’s internal RC oscillator. A
device RESET forces all registers to their RESET state. This forces the A/D module to be turned off and
any conversion is aborted.
Each port pin associated with the A/D converter can be configured as an analog input (RA3 can also be a
voltage reference) or as a digital I/O. The ADRESH and ADRESL registers contain the result of the A/D
conversion. When the A/D conversion is complete, the result is loaded into the ADRESH/ADRESL
registers, the GO/DONE bit (ADCON0<2>) is cleared, and A/D interrupt flag bit, ADIF is set.
After the A/D module has been configured as desired, the selected channel must be acquired before the
conversion is started. The analog input channels must have their corresponding TRIS bits selected as an
input. The following steps should be followed for doing an A/D conversion:
The A/D conversion time per bit is defined as TAD. The A/D conversion requires 12 TAD per 10-bit
conversion. The source of the A/D conversion clock is software selectable.
The ADCON1, TRISA and TRISE registers control the operation of the A/D port pins. The port pins that
are desired as analog inputs, must have their corresponding TRIS bits set (input). If the TRIS bit is
cleared (output), the digital output level (VOH or VOL) will be converted. The A/D operation is
independent of the state of the CHS2:CHS0 bits and the TRIS bits.
Note that:
When reading the port register, all pins configured as analog input channels will read as cleared
(a low level). Pins configured as digital inputs will convert an analog input. Analog levels on a
digitally configured input will not affect the conversion accuracy.
Analog levels on any pin that is defined as a digital input (including the AN4:AN0 pins) may
cause the input buffer to consume current that is out of the device’s specification.
Clearing the GO/DONE bit during a conversion will abort the current conversion. The A/D result register
pair will NOT be updated with the partially completed A/D conversion sample. That is, the
ADRESH:ADRESL registers will continue to contain the value of the last completed conversion (or the
last value written to the ADRESH:ADRESL registers). After the A/D conversion is aborted, a 2 TAD
wait is required before the next acquisition is started. After this 2 TAD wait, acquisition on the selected
channel is automatically started. The GO/DONE bit can then be set to start the conversion.
The ADRESH : ADRESL register pair is the location where the 10-bit A/D result is loaded at the
completion of the A/D conversion. This register pair is 16-bits wide. The A/D module gives the flexibility
to left or right justify the 10-bit result in the 16-bit result register. The A/D Format Select bit (ADFM)
controls this justification. Figure below shows the operation of the A/D result justification. The extra bits
are loaded with ’0’s. When an A/D result will not overwrite these locations (A/D disable), these registers
may be used as two general purpose 8-bit registers.
Clock Selection:
Temperature Message
Below 10 degrees Celsius Bit Chilly!
Between 10 – 30 degrees Celsius Nice Weather!
Greater than 30 degrees Celsius Im Boiling!