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32 DLD Lec 32 Combinational Circuit Implementation Using Decoder, Encoder, Priority Encoder 30 Nov 2022 Lecture Slides

This document summarizes a lecture on encoders, priority encoders, multiplexers, demultiplexers, and tri-state buffers. It discusses how encoders perform the inverse function of decoders by mapping n input lines to 2n output lines. An example is given of an octal-to-binary encoder implemented with OR gates. Priority encoders include a priority function such that the highest priority input is encoded if multiple inputs are 1. Implementation of combinational logic using decoders with OR gates is also covered.

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Zuha Fatima
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46 views

32 DLD Lec 32 Combinational Circuit Implementation Using Decoder, Encoder, Priority Encoder 30 Nov 2022 Lecture Slides

This document summarizes a lecture on encoders, priority encoders, multiplexers, demultiplexers, and tri-state buffers. It discusses how encoders perform the inverse function of decoders by mapping n input lines to 2n output lines. An example is given of an octal-to-binary encoder implemented with OR gates. Priority encoders include a priority function such that the highest priority input is encoded if multiple inputs are 1. Implementation of combinational logic using decoders with OR gates is also covered.

Uploaded by

Zuha Fatima
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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Digital Logic and Design

Lecture 32 : Encoder, Priority Encoder, Multiplexer,


Demultiplexer, Tri-State buffer

BEE-13AB
Dated 30 November 2022

By Nasir Mahmood
[email protected]
[email protected]

◦ Application of Decoder
◦ Encoder
◦ Priority Encoder

Combination Logic Implementation


● A decoder provides the 2n minterms of n input variables.
● Any function is can be expressed in sum of minterms.
● Use a decoder to make the minterms and an external OR gate to make the
logical sum.
● In this way any combinational circuit with n inputs and m outputs can be
implemented with an n-to-2n line decoder and m OR gates. Such
implementation needs that the Boolean function is expressed in sum of
minterms
● For example: consider a full adder.
◦ S(x,y,z) = Σ(1,2,4,7)
◦ C(x,y,z) = Σ (3,5,6,7) x y z c s
0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1
3

Implementation of Full Adder with a Decoder

◦ S(x,y,z) = Σ(1,2,4,7)
◦ C(x,y,z) = Σ (3,5,6,7)
● There are three inputs and eight outputs so we need 3-to-8-
line decoder
● Two OR gates are required for logical sum of the desired
minterms

Implementation of Function with a Decoder Contd..


● A function with long list of minterms requires an OR gate with large number of
inputs
● A function having a list of K minterms can be expressed in its complemented
form F’ with 2n-K minterms
● If the number of minterms in a function is greater than 2n/2 then F’ can be
expressed with fewer minterms
● In such case it is advantageous to use a NOR gate to sum the minterms of F’.
The output of the NOR gate complements this sum and generates the normal
output F

◦ F1’(x,y,z) = Σ(2,4)
◦ F1(x,y,z) = Σ(0,1,3,5,6,7)
◦ F2’(x,y,z) = Σ(0,5,6)
◦ F2(x,y,z) = Σ(1,2,3,4,7)

Practice Problems
P1 : Consider the following circuit with an active
high output decoder. Draw a truth table for X and Y
in terms of a, b and c

Practice Problems Contd..

P2

7
Encoders
● An encoder is a digital circuit that performs the
inverse operation of a decoder.
● An encoder has 2n (or fewer) input lines and n
output lines.
● The output lines generate the binary code
corresponding to the input value

Truth Table: Octal to Binary Encoder

z=D1+D3+D5+D7 y=D2+D3+D6+D7 x=D4+D5+D6+D7

9
Encoder: Example
● An example of encoder is octal-to-binary encoder
● It has eight inputs (one for each octal digits) and
three outputs that generate the corresponding
binary number
● It is assumed that only one input has a value of 1
at any given time
● The encoder can be implemented with OR gates
whose inputs are determined directly from the
truth table
● Output z is equal to 1 when the input octal digit is
1,3,5 or 7. Output y is 1 for octal digits 2,3,6 or 7
and output x is 1 for digits 4,5,6 or 7. These
conditions can be expressed as by the Boolean
functions as shown in the previous slide
10

Octal to Binary Encoder


Implementation

z=D1+D3+D5+D7 y=D2+D3+D6+D7 x=D4+D5+D6+D7

11
Priority Encoder
● A priority encoder is an encoder circuit that includes
the priority function.
● The operation of the priority encoder is such that if
two or more inputs are equal to 1 at the same time,
the input having the highest priority will take
precedence
◦ D3 has the highest priority
◦ D0 has the lowest priority

● Valid bit indicator (V) is set to 1 when one or more


inputs are equal to 1. If all inputs are 0, there is no
valid inputs and V is equal to 0. The other two
outputs are not inspected when V equals 0 and are
specified as don’t care conditions

Priority Encoder: Expanded Truth


Table
Priority Encoder: Truth Table
Input Output
D0 D 1 D2 D3 x y v
0 0 0 0 X X 0
1 0 0 0 0 0 1
X 1 0 0 0 1 1
X X 1 0 1 0 1
X X X 1 1 1 1

–X: don't-care conditions in the output, used in the inputs to condense


truth table, replaced by both 0 and then 1
–V: valid output indication, implemented by OR function
Maps for Priority Encoder
Priority Encoder: Logic circuit
Practice Problem

● Designa Priority Encoder with Priority


to Lower Subscript

17
End of Lecture

18

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