Company Confidential

BROADCAST 1500 SPECIFICATION

IP BC1500
Major Rev A
Version 0
Minor Rev

Owner Nehal Patel

Last Modification Owner
Date June 25, 2015
Document Rev 1228

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Table of Contents
BROADCAST 1500 SPECIFICATION....................................................................................................1
INTRODUCTION.................................................................................................................................4
SCOPE..............................................................................................................................................7
REFERENCES.................................................................................................................................7
INTERFACES.......................................................................................................................................8
INSTRUCTION REGISTER..............................................................................................................10
ACCESS MODES...............................................................................................................................11
BROADCAST MODE........................................................................................................................11
DAISY MODE....................................................................................................................................13
BROADCASTEN TDR......................................................................................................................14
BYPASSEN TDR................................................................................................................................15
BYPASS TDR.....................................................................................................................................17
DELAYCHAIN INSTRUCTION.......................................................................................................18
SECURITY.........................................................................................................................................18
RESET.................................................................................................................................................19
Special Tile BC1500 Resets................................................................................................................21

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Index of Tables
Table 1: Port List........................................................................................................................................8
Table 2: WDR (1500_INSTRUCTIONS)................................................................................................11
Table 3: BROADCASTEN Register Definition......................................................................................15
Table 4: BYPASSEN Register Definition...............................................................................................17

Illustration Index
Illustration 1: TDR access path from MTAP.............................................................................................4
Illustration 2: TDR access path from MTAP->1500.................................................................................5
Illustration 3: TDR access path from MTAP->STAC->1500....................................................................6
Illustration 4: BC1500 Broadcast Mode..................................................................................................13
Illustration 5: BC1500 Daisy Mode.........................................................................................................14
Illustration 6: BroadcastEN......................................................................................................................15
Illustration 7: BypassEN..........................................................................................................................17
Illustration 8: BC1500 Resets..................................................................................................................21
Illustration 9: USB BC1500 Resets.........................................................................................................22

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INTRODUCTION

Any test/debug feature of the chip is accessible through the test controller logic. The test controller uses
the JTAG interface to access the test/debug features. Here is the typical diagram of the test controller
interface.

Illustration 1: TDR access path from MTAP

The tap controller is located in dft_t tile. The physical location of the TDRs can be anywhere in the
chip. If all TDRs are in near the tap controller (in dft_t tile), the output of TDRs which control the test
mode need to be routed from dft_t tile to wherever test intercept is needed. The test mode controls (like
TEST_CLK_DIS) needs separate signal per tile. Adding those control registers in dft_t tile create lot of
point to point connection from dft_t to other tiles. This creates congestion near dft_t tile. This causes

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routing issues for PD. The top level congestion is getting bigger issue as chip size grows.

To tackle the top level congestion issue from dft to other tiles, local test controller (1500 clients) is
added in all tiles. All test control needed in target tiles should be through tile local 1500 instead of
directly coming from the dft tile.

Illustration 2: TDR access path from MTAP->1500

Motivation for 1500

1. Reduce top level congestion.
2. Any test/debug mode control registers can be directly added inside the tile without touching top
level.
3. Standardize the dfx interface across all tiles.

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For SOC15, the DFX interfaces are standardize across all IP containers. The STC (STAC Controller)
and STR (STAC Routers) are introduced to achieve this. The STR is inside SCF (Scalable control
Fabric) The STR provide expansion point for each IP for DFX access. The TDRs are access through
JTAG → MTAP → STR → STC → 1500 → TDRs path. Below diagram shows the access path. More
details about STAC can be found from STAC

Illustration 3: TDR access path from MTAP->STAC->1500

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SCOPE
This document describes the micro architecture of the Broadcast 1500. The Broadcast 1500 is different
than IEEE standard 1500 as it provide the broadcast programming feature which is not present for
IEEE 1500.

REFERENCES
IEEE specs:
http://sharedbook/twiki/bin/view/DFTest/IEEEDocuments

STAC spec:
http://twiki.amd.com/twiki/pub/SOCArch/SOC15DFX/STAC_Architecture_Specification_v0.73.pdf

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INTERFACES

Table 1: Port List

Name Port Clock Description
Interface to the STC
BC1500_Wrck Input 1500 clock
Scanned_Tck Output Buffer version of BC1500_Wrck.
Use this clock for scanable logic in TCK
domain (Like SMSGs)
BC1500_Wsi Input Broadcast WSI. Program IR. Program TDR
in broadcast mode
BC1500_Sel_Wir Input IR select
BC1500_Shift Input Shift Enable
BC1500_Capture Output Capture Enable
BC1500_Update Output Update Enable
BC1500_Tlr Input Test Logic Reset.
Reset for IR, BypassEn, BroadcastEn
Registers
BC1500_Trstb Input TDR reset.
BC1500_Daisy_Wsi Input Daisy WSI. Program TDR in daisy mode.
Shift in TDR content in daisy mode
BC1500_Daisy_Wso Output Daisy WSO. Program Shift out TDR
content in daisy mode
Interface for TDR Security
BC1500_Inst_<\d+>_Dec_En Input This is used for instruction base security.
1 – TDR access is enabled.
0 – TDR access is disabled.

If Instruction base security is required, then

these ports should be driven by AEB.
If Instruction base security is not required,
tied these ports to 1'b1 to access the TDR.
For the unused instructions, tie these ports to
1'b0 of that tile bc1500.

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Name Port Clock Description

Point to Point Interface to
TDR
BC1500_Inst_<\d+>_En Output TDR Enable.
BC1500_Inst_<\d+>_Tdo Input Serial Data from TDR

Broadcast Interface to all

TDRs
Tdr_Tck Output TDR clock
Tdr_Trstb Output TDR reset for Always ON (AON ) TDRs.
Tdr_Tdi Output TDR Serial Data In
Tdr_Shift Output TDR Shift
Tdr_Capture Output TDR Capture
Tdr_Update Output TDR Update

Tdr_P0_Trstb Output TDR reset for P0 Domain (ONO) TDRs.

Tdr_P1_Trstb Output TDR reset for P1 Domain (ONO) TDRs.
Tdr_P2_Trstb Output TDR reset for P2 Domain (ONO) TDRs.
Tdr_P3_Trstb Output TDR reset for P3 Domain (ONO) TDRs.
Tdr_P4_Trstb Output TDR reset for P4 Domain (ONO) TDRs.
Tdr_P5_Trstb Output TDR reset for P5 Domain (ONO) TDRs.
Tdr_P6_Trstb Output TDR reset for P6 Domain (ONO) TDRs.
Tdr_P7_Trstb Output TDR reset for P7 Domain (ONO) TDRs.

Interface to the TDR-Broadcast

Tdr_Broadcast_En Output Enable TDR broadcast Mode.
Interface to the PGFSM/BPM
PGFSM_P0_resetb Input Toggle 1->0->1 when P0 power domain
Turn ON->OFF->ON
PGFSM_P1_resetb Input Toggle 1->0->1 when P1 power domain
Turn ON->OFF->ON

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Name Port Clock Description

PGFSM_P2_resetb Input Toggle 1->0->1 when P2 power domain
Turn ON->OFF->ON
PGFSM_P3_resetb Input Toggle 1->0->1 when P3 power domain
Turn ON->OFF->ON
PGFSM_P4_resetb Input Toggle 1->0->1 when P4 power domain
Turn ON->OFF->ON
PGFSM_P5_resetb Input Toggle 1->0->1 when P5 power domain
Turn ON->OFF->ON
PGFSM_P6_resetb Input Toggle 1->0->1 when P6 power domain
Turn ON->OFF->ON
PGFSM_P7_resetb Input Toggle 1->0->1 when P7 power domain
Turn ON->OFF->ON

Misc Interfaces
Tdr_Bypass_Tdo Output Output from the Bypass TDR

INSTRUCTION REGISTER

The instruction is used to

– select the test to be performed or
– test data register to be programmed or
– status registers to be read

The instruction registers consists of the shift register + parallel update registers. The instruction register
width depends of total number of instruction needed in 1500. In our design, the IR width is controlled
by the feature BC1500_IR_WIDTH. This feature is set to 8. Hence total 2^8 = 256 instructions are
available.

When WRSTN is active (logic 0), all IR bits is asynchronously reset to logic 1. This would select the
bypass register between WSI and WSO.

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The IR shift registers are shifting the WSI data when both Sel_Wir and ShiftWR are enabled (1'b1).
The IR shift registers are clocked on the positive edge of the WRCK. The ShiftWR signal coming from
STAC is generated on the negedge of WRCK.

The IR shift register value is latched in the parallel IR registers when Sel_Wir and UpdateWR is
enabled (1'b1). The IR update registers are clocked in negedge ot WRCK. The UpdateWR signal
coming from STAC is generated on the posedge of WRCK. The parallel IR register are used to decode
the instruction.

The instruction register is connected to the broadcast WSI. IR can only be programmed in broadcast
mode. Hence, all 1500 tiles IR are loaded with same instruction.

WIR(INSTRUCTION REGISTER) Register Definition

Bits Mnemonic Type Reset Description
8:0 WIR R/W 'h1FF

Table 2: WDR (1500_INSTRUCTIONS)

Condition Registers
WIR == 9'h01 BROADCASTEN
WIR == 9'h02 BYPASSEN
WIR == 9'h1FF || BYPASSEN == 1'b1 BYPASS
WIR == 9'h00 WBYPASS
WIR == 9'h03 DELAYCHAIN

ACCESS MODES
There are 2 different access modes for 1500 registers.

BROADCAST MODE

In this mode, all 1500 client TDRs are programmed in parallel. The broadcast WSI signal is
used to program the registers.

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Since all different 1500 registers are programmed using the same data coming from the WSI,
it is required to that TDR which is getting programmed in this mode must have to be same
length and same functionality.

This mode is the efficient way to program the common TDRs in all or some tiles. With single
dr_shift, all the common TDRs are programmed which save quite a bit of cycles as compare
of programming it in one tile at a time.

The IR registers are always programmed in the broadcast mode.

The DR registers by default program in daisy mode. To program or access TDRs in

broadcast mode, first the "broadcasten" instruction needs to be programmed and set the
BroradcastEn 1 bit TDR to 1. That would connect Broadcast WSI to TDRs.

The 1500 in different IP container tiles can also be programmed through broadcast mode
using STR->STC network. The STAC document should have mode details about this mode.

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Illustration 4: BC1500 Broadcast Mode.

DAISY MODE

In this mode, all 1500 client registers are accessed in daisy chain manner. The Daisy_WSI serial data is
used to access the registers.

This mode is efficient way to shift out status registers in all or some tiles. Using daisy chain mode, all
tiles or selected tiles status registers can be shifted using single dr_shift.

The IR registers are always programmed in the broadcast mode. There is no way to program IR in
daisy chain mode.

The DR registers by default program in daisy WSI mode.

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Illustration 5: BC1500 Daisy Mode.

BROADCASTEN TDR
This is one bit TDR which control the selection of Daisy or Broadcast mode. The default value
of this TDR is 0. This TDR is reset using TLR coming from STAC.

This TDR serial data in is connected to Broadcast WSI. Hence, this TDR always
programmed in Broadcast mode and always have same value in all tiles 1500.

To program BroadcastEn, load the BroadcastEn instruction in the IR register. Then do 1 bit

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dr_shfit to change the BroadcastEN TDR value.

Illustration 6: BroadcastEN.

Table 3: BROADCASTEN Register Definition

Bits Mnemonic Type Reset Description
0 BROADCASTEN R/W 1'h0 Broadcast vs Daisy Mode selection
1 – Broadcast Mode
0 – Daisy Mode

BYPASSEN TDR
This is one bit TDR which can be used to put 1500 client in bypass mode. The default value
of this TDR is 0. This TDR is reset using TLR coming from STAC.

When BYPASSEN TDR program to 1, one bit BYPASS register is connected between WSI to
WSO. This is done by connecting 'h1..1 to the IR decoder which select bypass TDR.

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The 1500 bypass mode is useful when there are same TDRs connected to different tiles
1500, but user want to access only some 1500s TDRs, but not all 1500s TDRs. In this case,
those 1500s BYPASSEN bit can be programmed to 1.

The BYPASSEN TDR is directly connected to Daisy_WSI. Hence, this TDR always
programmed in daisy mode and never programmed in Broadcast mode.

After BYPASSEN TDR program to 1, the only instructions IR decoder logic will respond are
BYPASSEN and BROADCASTEN. The BYPASSEN instruction is used to set the BYPASSEN
TDR bit and also clear that bit (to enable back 1500.) The BROADCASTEN instruction is
allowed in 1500 byapss mode to configure the BROADCASTEN TDR bit to keep in sync with
rest of the 1500s. This is required when user exit the 1500 bypass mode, that 1500 should
also be in the same mode (broadcast or daisy) where rest of the 1500s are.

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Illustration 7: BypassEN

Table 4: BYPASSEN Register Definition

Bits Mnemonic Type Reset Description
0 BYPASSEN R/W 1'h0 Control Bypass of 1500.
1 – 1500 IR only decode BROADCASTEN and BYPASSEN
instructions. Any other instructions programmed in IR is not
decoded.
BYPASS TDR is connected between WSI and WSO.
0 – All instructions programmed in IR is decoded.

BYPASS TDR
This is one bit TDR. Any unused instructions connect Byapss TDR between WSI
to WSO. The default value of this TDR is 0. This TDR is reset using TRSTb
coming from STAC.

The BYPASS TDR is directly connected to Daisy_WSI. This TDR is always

capturing 1'b0.

The bypass register provides a minimum length serial path from WSI_daisy to
WSO for rapid data movement. Also, it works as a pipeline flop when passing
the data from targeted p1500 to the TDO.

The bypass register is selected between WSI_daisy and WSO when

- All bits of IR are programmed to 1 (reset value.)
– Any unused instruction is programmed. This is done by tieing
BC1500_Inst_\d+_Dec_En bits at 1'b0 for unused instructions.

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BYPASS Register Definition

Bits Mnemonic Type Reset Description
0 BYPASS R/W 'h0 Enabled when BYPASSEN instruction or any unused instruction is loaded.
The unused instructions are the one which corresponding
BC1500_Inst_\d+_Dec_EN signals are tied to 1'b0.

WBYPASS Register Definition

Bits Mnemonic Type Reset Description
0 WBYPASS R/W 'h0

DELAYCHAIN INSTRUCTION
When this instruction is loaded, the WSI_Daisy is connected to WSO directly
without any bypass flop. When all tiles 1500 is loaded with this instruction, the
long metal chain is created from TDI to TDO. The pulse send from TDI and
captured on TDO to check the total metal delay. This delay can be compared
against different chips to screen the metal speed at ATE.

Since stimgen doesn't support the zero length TDR Instuction, theTDR table is
added below, Just to support StimGen, but in RTL, a register doesn't exist.
DELAYCHAIN
Bits Mnemonic Type Reset Description
0 DELAYCHAIN R/W 'h0

SECURITY

The BC1500 Instruction base security info is captured in project csv file.

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RESET

The bc1500 block get

2 active low reset input from STAC
– BC1500_Tlr
– BC1500_Trstb

and 8 active low reset from PGFSM block.

– PGFSM_P[7:0]_resetb

The BC1500_Tlr is active when JTAG_Trstb pin is 0 or when STAC FSM enter
in TestLogicResetB state (by holding TMS high for 5 TCK cycles.) This reset is
used for 2 TDRS in bc1500 – BypassEn & BroadcastEN. These TDRs are
controlling the TDI ->TDO network inside BC1500 and must be rest by JTAG
soft reset (TMS asserted for 5 TCK cycles) to put the network in default state.

The BC1500_Trstb is active when JTAG_Trstb is 0. This reset is used for all
bc1500 space TDRs other than bypassEn and broadcasten This reset won't be
active when MTAP/STAC FSM enter in TestLogicResetb state and preserve
TDR values during jtag soft reset event.

The PGFSM_P*_resetb is generated from PGFSM block. In mission mode, this

reset is generated from FSM inside PGFSM block. The FSM assert this reset
before the respective power domain goes down and de-assert the reset after the
respective power domain is up. This would put the TDR in reset mode after
power down->up even happens.

The STAC and BC1500 needs to be grouped in Always ON (AON) power

domain.

From above inputs resets, bc1500 generates below reset outputs:

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– Tdr_Trstb
– Tdr_P[7:0]_Trstb

The Tdr_Trstb is directly sourced from BC1500_Trstb. This reset is used by

Tdrs in the Always ON (AON) domain.

The Tdr_P*_Trstb is generated by ANDing BC1500_Trstb with

PGFSM_P*_Trstb and synchronizing it in TCK domain. This reset is used by
Tdrs in ON-OFF-ON (ONO) domain. The PGFSM/BC1500 support up-to 8
power domain. The rtl can be scaled to support more power domains, if needed.

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Illustration 8: BC1500 Resets

Special Tile BC1500 Resets

For ZP, USB tile has both S0 and S5 voltage rail. The STAC and BC1500 are in
S5 voltage rail. However, There are few tdrs like dft_clk_cntl and SMSG are in
S0 power rail. When S0 power rail goes down and comes back up, STAC won't
provide the reset 1->0->1 event as STAC is in S5 domain and don't see the S0
power down event. In this case, the S0 PWROK signal is used to reset the
TDRs in the S0 power domain. The USB BC1500 PGFSM_P0_resetb is
connected to PWROK to reset the S0 domain TDRs in USB tile.

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Illustration 9: USB BC1500 Resets

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