CMOS Inverter

A Y VDD
0 1
1 0 OFF
ON
0
1
A Y
ON
OFF

A Y
GND
0: Introduction CMOS VLSI Design 4th Ed. 1
 CMOS NAND Gate
A B Y
0 0 1 ON
OFF
OFF
ON OFF
ON
0 1 1
1
Y
0
1 0 1 ON
A OFF
1 1 0 0
1
1
0 OFF
ON
B ON
OFF

0: Introduction CMOS VLSI Design 4th Ed. 2

 CMOS NOR Gate
A B Y
0 0 1 A
0 1 0
1 0 0 B
1 1 0 Y

0: Introduction CMOS VLSI Design 4th Ed. 3

 3-input NAND Gate
❑ Y pulls low if ALL inputs are 1
❑ Y pulls high if ANY input is 0

Y
A
B
C

0: Introduction CMOS VLSI Design 4th Ed. 4

 CMOS Fabrication
❑ CMOS transistors are fabricated on silicon wafer
❑ Lithography process similar to printing press
❑ On each step, different materials are deposited or
etched
❑ Easiest to understand by viewing both top and
cross-section of wafer in a simplified manufacturing
process

0: Introduction CMOS VLSI Design 4th Ed. 5

 Inverter Cross-section
❑ Typically use p-type substrate for nMOS transistors
❑ Requires n-well for body of pMOS transistors
A
GND VDD
Y SiO2

n+ diffusion

p+ diffusion
n+ n+ p+ p+
polysilicon
n well
p substrate
metal1

nMOS transistor pMOS transistor

0: Introduction CMOS VLSI Design 4th Ed. 6

Well and Substrate Taps
❑ Substrate must be tied to GND and n-well to VDD
❑ Metal to lightly-doped semiconductor forms poor
connection called Shottky Diode
❑ Use heavily doped well and substrate contacts / taps
A
GND VDD
Y

p+ n+ n+ p+ p+ n+

n well
p substrate

well
substrate tap
tap

0: Introduction CMOS VLSI Design 4th Ed. 7

 Inverter Mask Set
❑ Transistors and wires are defined by masks
❑ Cross-section taken along dashed line

GND VDD

nMOS transistor pMOS transistor

substrate tap well tap

0: Introduction CMOS VLSI Design 4th Ed. 8

 Detailed Mask Views
❑ Six masks n well

– n-well
– Polysilicon
Polysilicon

– n+ diffusion
– p+ diffusion n+ Diffusion

– Contact p+ Diffusion

– Metal Contact

Metal

0: Introduction CMOS VLSI Design 4th Ed. 9

 Fabrication
❑ Chips are built in huge factories called fabs
❑ Contain clean rooms as large as football fields

Courtesy of International
Business Machines Corporation.
Unauthorized use not permitted.

0: Introduction CMOS VLSI Design 4th Ed. 10

 Fabrication Steps
❑ Start with blank wafer
❑ Build inverter from the bottom up
❑ First step will be to form the n-well
– Cover wafer with protective layer of SiO2 (oxide)
– Remove layer where n-well should be built
– Implant or diffuse n dopants into exposed wafer
– Strip off SiO2

p substrate

0: Introduction CMOS VLSI Design 4th Ed. 11

 Oxidation
❑ Grow SiO2 on top of Si wafer
– 900 – 1200 C with H2O or O2 in oxidation furnace

SiO2

p substrate

0: Introduction CMOS VLSI Design 4th Ed. 12

 Photoresist
❑ Spin on photoresist
– Photoresist is a light-sensitive organic polymer
– Softens where exposed to light

Photoresist
SiO2

p substrate

0: Introduction CMOS VLSI Design 4th Ed. 13

 Lithography
❑ Expose photoresist through n-well mask
❑ Strip off exposed photoresist

Photoresist
SiO2

p substrate

0: Introduction CMOS VLSI Design 4th Ed. 14

 Etch
❑ Etch oxide with hydrofluoric acid (HF)
– Seeps through skin and eats bone; nasty stuff!!!
❑ Only attacks oxide where resist has been exposed

Photoresist
SiO2

p substrate

0: Introduction CMOS VLSI Design 4th Ed. 15

 Strip Photoresist
❑ Strip off remaining photoresist
– Use mixture of acids called piranah etch
❑ Necessary so resist doesn’t melt in next step

SiO2

p substrate

0: Introduction CMOS VLSI Design 4th Ed. 16

 n-well
❑ n-well is formed with diffusion or ion implantation
❑ Diffusion
– Place wafer in furnace with arsenic gas
– Heat until As atoms diffuse into exposed Si
❑ Ion Implanatation
– Blast wafer with beam of As ions
– Ions blocked by SiO2, only enter exposed Si
SiO2

n well

0: Introduction CMOS VLSI Design 4th Ed. 17

 Strip Oxide
❑ Strip off the remaining oxide using HF
❑ Back to bare wafer with n-well
❑ Subsequent steps involve similar series of steps

n well
p substrate

0: Introduction CMOS VLSI Design 4th Ed. 18

 Polysilicon
❑ Deposit very thin layer of gate oxide
– < 20 Å (6-7 atomic layers)
❑ Chemical Vapor Deposition (CVD) of silicon layer
– Place wafer in furnace with Silane gas (SiH4)
– Forms many small crystals called polysilicon
– Heavily doped to be good conductor

Polysilicon
Thin gate oxide

n well
p substrate

0: Introduction CMOS VLSI Design 4th Ed. 19

 Polysilicon Patterning
❑ Use same lithography process to pattern polysilicon

Polysilicon

Polysilicon
Thin gate oxide

n well
p substrate

0: Introduction CMOS VLSI Design 4th Ed. 20

 Self-Aligned Process
❑ Use oxide and masking to expose where n+ dopants
should be diffused or implanted
❑ N-diffusion forms nMOS source, drain, and n-well
contact

n well
p substrate

0: Introduction CMOS VLSI Design 4th Ed. 21

 N-diffusion
❑ Pattern oxide and form n+ regions
❑ Self-aligned process where gate blocks diffusion
❑ Polysilicon is better than metal for self-aligned gates
because it doesn’t melt during later processing

n+ Diffusion

n well
p substrate

0: Introduction CMOS VLSI Design 4th Ed. 22

 N-diffusion cont.
❑ Historically dopants were diffused
❑ Usually ion implantation today
❑ But regions are still called diffusion

n+ n+ n+

n well
p substrate

0: Introduction CMOS VLSI Design 4th Ed. 23

 N-diffusion cont.
❑ Strip off oxide to complete patterning step

n+ n+ n+

n well
p substrate

0: Introduction CMOS VLSI Design 4th Ed. 24

 P-Diffusion
❑ Similar set of steps form p+ diffusion regions for
pMOS source and drain and substrate contact

p+ Diffusion

p+ n+ n+ p+ p+ n+

n well
p substrate

0: Introduction CMOS VLSI Design 4th Ed. 25

 Contacts
❑ Now we need to wire together the devices
❑ Cover chip with thick field oxide
❑ Etch oxide where contact cuts are needed

Contact

Thick field oxide

p+ n+ n+ p+ p+ n+

n well
p substrate

0: Introduction CMOS VLSI Design 4th Ed. 26

 Metalization
❑ Sputter on aluminum over whole wafer
❑ Pattern to remove excess metal, leaving wires

Metal

Metal
Thick field oxide
p+ n+ n+ p+ p+ n+

n well
p substrate

0: Introduction CMOS VLSI Design 4th Ed. 27

 Layout
❑ Chips are specified with set of masks
❑ Minimum dimensions of masks determine transistor
size (and hence speed, cost, and power)
❑ Feature size f = distance between source and drain
– Set by minimum width of polysilicon
❑ Feature size improves 30% every 3 years or so
❑ Normalize for feature size when describing design
rules
❑ Express rules in terms of l = f/2
– E.g. l = 0.3 mm in 0.6 mm process

0: Introduction CMOS VLSI Design 4th Ed. 28

 Simplified Design Rules
❑ Conservative rules to get you started

0: Introduction CMOS VLSI Design 4th Ed. 29

 Inverter Layout
❑ Transistor dimensions specified as Width / Length
– Minimum size is 4l / 2l, sometimes called 1 unit
– In f = 0.6 mm process, this is 1.2 mm wide, 0.6 mm
long

0: Introduction CMOS VLSI Design 4th Ed. 30

 Summary
❑ MOS transistors are stacks of gate, oxide, silicon
❑ Act as electrically controlled switches
❑ Build logic gates out of switches
❑ Draw masks to specify layout of transistors

❑ Now you know everything necessary to start

designing schematics and layout for a simple chip!

0: Introduction CMOS VLSI Design 4th Ed. 31