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COA Assignments

1) The document contains 11 questions related to computer organization and architecture. The questions cover topics like memory interfacing, cache memory, pipelining, parallelization, and instruction timing. 2) Questions ask the reader to calculate things like check bits, average access time, processor utilization, execution times, and effective CPI. 3) Solutions require applying concepts like memory hierarchies, cache hit ratios, interrupt processing overhead, parallel decomposition, and instruction timing.

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57 views3 pages

COA Assignments

1) The document contains 11 questions related to computer organization and architecture. The questions cover topics like memory interfacing, cache memory, pipelining, parallelization, and instruction timing. 2) Questions ask the reader to calculate things like check bits, average access time, processor utilization, execution times, and effective CPI. 3) Solutions require applying concepts like memory hierarchies, cache hit ratios, interrupt processing overhead, parallel decomposition, and instruction timing.

Uploaded by

magi9999
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as DOCX, PDF, TXT or read online on Scribd
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Computer Organization and Architecture Assignment Questions

1) The 256K X 12 DRAM is interfaced to a 32 bit processor. Assume at a memory location


3FEFEH a 12 bit data word 3FEh is stored. Determine the check bits that would be stored in
that memory location to prevent the misread of data the processor due to soft errors .

2) A processor employs a three level memory hierarchy system. If a referenced word is in


cache, 10 ns are required to access , while if it is in Dram, but not in cache, 100ns are required
to access it, and for disk access of the word, it takes 10ms, followed by 100ns to copy the word
into the cache and then reference is started again. If the cache hit ratio is 0.95and main
memory hit ratio is 0.6, compute the average access time to access a referenced word.

3) An Intel 80386 processor employs a interrupt driven i/o mechanism to access a


slow FDD i/o device which transmits data at a fixed rate of 10KB/sec continuously.
If the interrupt processing takes 50µs ( that is the latency involved in branching to the ISR,
execute the isr and return to main program) , determine what fraction of processor time is
consumed by this i/o device if it interrupts for every byte.
b) Now assume that the device has two 16 byte buffers and interrupts the processor when one
of the buffers becomes full. Naturally interrupt processing will be longer, because ISR needs to
transmit 16 bytes. For the transfer of each byte while executing the ISR, the processor takes
10µs for the transfer of each byte. Determine what fraction of processor time is consumed by
this i/o device in this case.
c) Now assume that the processor is equipped with a block transfer I/O instruction . This
permits the ISR to transfer each byte of a block in only 5 µs . Determine what fraction of
processor time is consumed by this i/o device in this case.
Comment on the results obtained.

4) A 4 way set Associative cache memory in MERS X486 computer system has 4 words in each
set. A replacement procedure based on the LRU algorithm is implemented by means of 2 bit
counters associated with each word in the set. A value in the range 0 to 3 is thus recorded for
each word. When a hit occurs , the counter is associated with the referenced word is set to 0.,
those counters with values originally lower than referenced one are incremented by 1 , and all
others remain unchanged. If a miss occurs , the word with counter value 3 is replaced with the
new word resetting the counter to 0, and other three counters are incremented by 1.
Show that this procedure works for the following sequence of word reference
A,B,C,D,B,E,D,A,C,E,C,E ( Start with A ,B,C,D as the initial four words with A being the least
recently used.
5) Array Processors Pipeline design: In certain scientific computation it is necessary to perform
the arithmetic operation (Pi +Qi)(Xi+Yi) with a stream of numbers. Design a pipeline
configuration to carry out this task for i=1 to 6. Show clearly all the intermediate registers
used for the design.

6) An 8-bit computer has a 16bit address bus. The first 15 lines of address are used to select a
bank of 32K bytes of memory. The higher order bit of address is used to select a register which
receives the contents of the data bus? Explain how this configuration can be used to extend the
memory capacity of system to eight banks of 32 K bytes each, for a total of 256K bytes of
memory.

7) Consider having a program that runs in 50 s on machine - A, which has a 500 MHz clock. We
would like to run the same program on another machine-B, in 20 s. If machine B requires 2.5
times as many clock cycles as machine A for the same program, what clock rate must machine B
have in MHz?

A [B+C + D]
8) Write the program to evaluate the expression X ¿ using zero, one and two address
E [F−G]
instructions. The instructions available to use as follows.

0 - Address 1 - Address 2 - Address


PUSH M LOAD M MOV X,Y
POP M STORE M ADD X,Y
ADD ADD M SUB X,Y
SUB SUB M MUL X,Y
MUL MUL M DIV X,Y
DIV DIV M

9) The following C program is to be executed on a ARM7 computer system , and a parallel


version is to be executed on a 16 computer ARM cluster.

L1. For( i=1 ,i<=512,i++) {


L2 sum(i)=0;
L3 for (j=1,j<=I,j++)
L4 sum(i)=sum(I)+j;
L5 }
assume lines 2 and 4 each take 2 machine cycles including all processor and memory access
operations, and ignore the overhead of the other statements of the loop, and all other resource
conflicts.
1) What is the total execution time when this program runs on a single computer.

131840 clocks
2)Divide the I loop iterations among the 16 cluster as follows.Computer1 executes the first 32
iterations , processor 2 executes the next 32 and so on.What is the total execution time and
speed up factor as compared to 1. Is this a balanced design.

15392+528=15920 x2=31840 clocks

3)explain how to modify the parallelizing to facilitate the balanced parallel execution of all the
16 processors. Find the execution time and speed up over a single computer.
8240= 16480 clocks

10) Analytical Perform Binary division for the following operands.


Dividend : -29, Divisor -11 ( shown are the decimal equivalents of the numbers).
Explain clearly the partial result of each iteration .

11. A benchmark program is run on a 40 MHz processor.The executed program consists of


100,000 instruction executions, with the following instruction mix and clock cycle count.
Determine the effective CPI, MIPS rate, and execution time for this program

Instruction Instruction Cycles per Instruction


Type Count
Integer arithmetic 45000 1
Data transfer 32000 2
Floating point 15000 2
Control transfer 8000 2

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