Department of Electrical and Computer Engineering

Flash ADCs

Vishal Saxena, Boise State University

([email protected])

© Vishal Saxena -1-

Flash ADC Architecture

Vi • Reference ladder
VFS consists of 2N equal
7
7Δ
size resistors
6 • Input is compared
6Δ to 2N-1 reference
5
voltages

Encoder
5Δ
• Massive parallelism
2Δ • Very fast ADC
1
architecture
Δ
0 • Latency = 1 Ts =
Do 0 1/fs
• Throughput = fs
• Complexity = 2N

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Thermometer Code

VFS Vi Strobe Thermometer code

fs
0

2N-1
comparators

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Thermometer Code

VFS Vi Strobe Thermometer code b2 b1 b0

fs
0 1
111

1 0
110

1 1
010

1 1
001

000
N
2 -1 1-of-n code
comparators
ROM encoder

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Flash ADC Challenges

• VDD = 1.8 V
• 10-bit → 1023 comparators
• VFS = 1 V → 1 LSB = 1 mV
• DNL < 0.5 LSB → Vos < 0.5 LSB
• 0.5 mV = 3-5 σ → σ = 0.1-0.2 mV

• 2N-1 very large comparators

• Large area, large power consumption
• Very sensitive design
• Limited to resolutions of 4-8 bits

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Flash ADC Challenges

• DNL < 0.5 LSB

• Large VFS relaxes
offset tolerance
os, max

• Small VFS benefits

conversion speed
(settling, linearity of
building blocks)

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ADC Input Capacitance

A Vth2
σ  Vth  
2
Cg  10 fF / μm2
WL

• N = 6 bits → 63 comparators
N (bits) # of comp. Cin (pF)
• VFS = 1 V → 1 LSB = 16 mV
6 63 3.9
• σ = LSB/4 → σ = 4 mV
8 255 250
• AVT0 = 10 mV·μm → L = 0.24 μm,
10 1023 ??!
W = 26 μm

• Small Vos leads to large device sizes, hence large area and power
• Large comparator leads to large input capacitance, difficult to drive and difficult to
maintain tracking bandwidth

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Fully-Differential Architecture

• VFS doubled
• 3-dB gain in SNR
• Better CMRR
• Noise immunity
• Input feedthrough

Encoder
cancelled
• Cin nonlinearity
partially removed
• Effect of Vcmi diff.
mitigated

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Flash ADC Design Considerations

• Use a dedicated S/H (or T/H) for better dynamic performance

– Can be avoided when using the A/D inside a ΔΣ loop
• Large input range for the quantizer has several benefits
– Increased step-size (VLSB) relaxes offset requirements on the comparators
– Reduced matching requirements result in small input cap to the S/H, easier to
drive
– Reduced input cap results in smaller clock routing parasitics – power savings in
clock drivers
• Comparator Design
– See comparator design slides

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Flash ADC: Reference Ladder

• Differential reference ladder

• Decaps on the reference taps
– large RC time-constant will not allow
reference restoration after kickback noise
– Small R will lead to power dissipation
– Optimize RC

• Subtract references from the input in

a differential manner
– Several topologies

• Several architectures for the digital

backend
– May need to pipeline digital logic at high
sampling rates >500 MS/s

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Reference Generator (for Vrefp and Vrefm)

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Flash ADC: Reference Subtraction

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Reference Subtraction: Scheme I

• Employ reference ladder for subtraction

• Choose current (I) such that differential
voltage drop across R = 1 VLSB
• Ladder is part of the signal path
– Comparator input cap load the resistor taps
– Excess delay

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Reference Subtraction: Scheme II

• Source followers to buffer vin

– reduced swing, varies with PVT

• Ladder is part of the signal path

– Comparator input cap load the resistor taps
– Excess delay

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Reference Subtraction: Scheme III
• Differential difference amplifier for
subtracting the reference
– followed by a zero crossing detector

• Relaxes the impedance requirements on

the ladder
• Mismatch in differential pairs and tail
current sources results in comparator
offset
– current trimming (see the reference below)

• Finite BW of the amplifier causes excess

delay

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Reference Subtraction: Scheme IV

• Switched-capacitor reference
subtraction
– Pay attention to charge injection

• ADC can handle large input swing

• Slow when auto-zeroing preamp is
used
– Large settling time constant
– Reference subtraction in background

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Example: Fully-Differential Comparator

• Double-balanced, fully-differential preamp

• Switches (M7, M8) added to stop input propagation during regeneration
• Active pull-up PMOS added to the latch

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Flash ADC: Errors

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Flash ADC Errors

• SHA-less
• Signal and
clock propa-
gation delay
• 2N-1 PAs +

Encoder
latches must
be matched
• Synchronized
strobe signal
is critical

Going parallel is fast, but also gives rise to inherent problems…

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Preamp Input Common Mode

PA 1 PA j PA j+1

S1 Sj

Vi

VR1 VRj
1 j
VR  VR

Input CM difference creates systematic mismatch (offset, gain, Cin, tracking BW,
and CMRR) among preamps

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Sampling Aperture Error

M3 M4 M5 M6

Cgd1 Cgd2 Φ
Φ Mode
M1 M2 VR
Vin Vo+ Vo- “high” Track
RS M9
Cgs1 Cgs2
“low” Regen

CS M7 M8

• Preamp delay and Vth of sampling switch (M9) are both signal-dependent → signal-
dependent sampling point (aperture error)
• A major challenge of distributing clock signals across 2N-1 comparators in flash ADC
with minimum clock skew (routing, Vth mismatch of M9, etc.)

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Nonlinear Input Capacitance

in
S
out
out

in
in out

Signal-dependent input bandwidth (1/RSCin) introduces distortion

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Input Signal Feedthrough

Vi
M3 M4

M1 M2 VRj
Vin RS
Cgs1 Cgs2

Feedthrough of Vin to the reference ladder through the serial connection of Cgs1 and
Cgs2 disturbs the reference voltages

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Comparator Metastability

Assuming that the input is uniformly

distributed over VFS, then

Δ
BER 
1LSB

Vo t   Vi 0   A V1A V2  expt  gm /CL 

• Cascade preamp stages (typical flash comparator has 2-3 PA stages)

• Use pipelined multi-stage latches; PA can be pipelined too
• Avoid branching off comparator logic outputs

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Comparator Metastability

Logic levels can be misinterpreted by digital gates (branching off, diff. outputs)

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Bubbles (Sparkles) in Thermometer Code

Vi 1 1 0

1 0
100

0 1
011

1 0
010

Static/dynamic comparator errors cause bubbles in thermometer code

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Bubbles (Sparkles)

Comparator offset Timing error

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Bubble-Tolerant Boundary Detector

• 3-input NAND
• Detect “011” instead
of “01” only
• “Single” bubble
correction
• Biased correction

Ref: J. G. Peterson, “A monolithic video A/D converter,” IEEE Journal of Solid-State

Circuits, vol. 14, pp. 932-937, issue 6, 1979.

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Built-In Bias

A B C D
0 0 0 0
0 0 0 0 “011” “001”
Case
0 0 1 0 Det. Det.
0 0 0 1 A  
1
1 0 0 1
2 B Fail 
0 1 1 0
3 1 1 1 0 C  Fail
1 0 1 1
1 1 1 1 D Fail Fail
1 1 1 1

Inspecting more neighboring comparator outputs improves performance

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Majority Voting Logic
*
C j  C j1C j  C jC j1  C j1C j1

A B C D
0 0 0 0
0 0 0 0 “011” Majority
Case
0 0 1 0 Det. voting
0 0 0 1 A  
1
1 0 0 1
2 B Fail 
0 1 1 0
3 1 1 1 0 C  
1 0 1 1
1 1 1 1 D Fail Fail
1 1 1 1

Ref: C. W. Mangelsdorf, “A 400-MHz input flash converter with error correction,” IEEE
Journal of Solid-State Circuits, vol. 25, pp. 184-191, issue 1, 1990.

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Gray Encoding

G1  T1 T3  T5 T7
G2  T2 T6
G3  T4

Only one transition

b/t adjacent codes

• One comparator output is ONLY used once → No branching!

• Gray encoding fails benignly in the presence of bubbles
• Codes are also robust over metastability errors

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Gray Encoding

G1  T1 T3  T5 T7
Conversion of Gray code to binary code is quite time-
G2  T2 T6 consuming → “quasi” Gray code
G3  T4

Ref: Y. Akazawa, et al., “A 400MSPS 8b flash AD conversion LSI,” in IEEE

International Solid-State Circuits Conference, Dig. Tech. Papers, 1987, pp. 98-99.

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Flash ADC: Binary Decoders

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Gray Encoded ROM Decoder

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Wallace Tree Adder (1s Adder)

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Folded Wallace Tree Decoder

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MUX-based Decoder

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Comparison of Decoder Schemes

• Mostly custom design at higher speeds

• Pipeline the digital backend at high-sampling rates to meet clock timing
• Tpd<TCK-(tpcq+tsetup)
• Tcd>thold-tccq

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Flash ADC: Other Techniques

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Offset Averaging (1)

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Offset Averaging (2)

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Flash ADC with Averaging

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Offset Calibration

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Comparator with Offset Correcting DAC

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High-Performance Flash with Calibration (1)

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Comparator Redundancy (1)

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Comparator Redundancy (2)

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Stochastic Flash ADC

• Fully synthesized ADC using ‘digital’ comparator

cells (large offsets)
• Use more than 1 comparator for a reference
threshold
– Use ‘detection theory’ to make accurate decisions
around a threshold, by using more than one
observation
• Low speed designs (<20 MS/s)

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Flash ADC: Case Study

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Case Study: Distortion Compensating Flash ADC

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T/H Distortion

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Pre-distorted References

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ADC Architecture

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T/H Circuit

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Comparator

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Non-linear Reference Generator

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ADC Testing

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Test Results

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Title

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References
1. Rudy van de Plassche, “CMOS Integrated Analog-to-Digital and Digital-to-Analog
Converters,” 2nd Ed., Springer, 2005.
2. M. Gustavsson, J. Wikner, N. Tan, CMOS Data Converters for
Communications, Kluwer Academic Publishers, 2000.

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