QUAN-Digital BSCIT Descriptive

Digital Electronics : Notes By Debanjan Patra
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Long Answer Questions
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NUMBER SYSTEM
Q. If x = 1101.110 and y = 1001.101 (both in binary), find x + y and x - y (by 2’s complement method).
Ans:
x = 1101.110
y = 1001.101
 (x + y) =
1101.110 (13.75)
1001.101 (9.625)
10111.011 (23.375)
 Answer = (10111.011) 2 OR (010111.011) 2 (with sign bit)
Again (x – y) (by 2’s complement)
1101.110 (13.75)
(9.625)
01001.101 10110.010
1’s complement
2’s complement
include sign
10110 010
+1 +1
10111 011
10111 011
So,
01101 0.110
+10111 +0.011
100100 1.001
discard discard

Answer = (100.001) 2
(4.125)
OR (0100.001) 2
Q. Convert Hex CF 8.7 to binary, octal and decimal system.

Ans: HEX to BINARY
(CF8.7)16  ( ? )2
C F 8 . 7
12 15 8 . 7
1100 1111 1000 . 111
(110011111000.111)2
1

Answer = (110011111000.111) 2
HEX to OCTAL
(CF8.7)16  ( ? )8
C F 8 . 7
12 15 8 . 7
1100 1111 1000 . 111
(110011111000.111)2
110 011 111 000 . 111
6 3 7 0 . 7
Answer = (6370.7)8

HEX to DECIMAL
(CF8.7)16  ( ? )10
C F 8 . 7
12 15 8 . 7
12 x 162 + 15 x 161 + 8 x 160 + 7 x 16-1
= 12 x 256 + 15 x 16 + 8 + 7/16
= 3072 + 240 + 8 + 0.4375
= 3320.4375
 Answer = (3320.4375)10
Q. If A = 1001 and B = 1100 (Both in binary) find A+B and A-B.

( by 2’s complement method)
Ans:
A = 1001 (A+B) = 1001 (9)
2
B = 1100 +1100 (12)
sign bit 10101 (21)
Answer = (010101)2

OR (00001 0101)BCD
sign bit
and (A – B) :
1001
01100 10011
 1’s comp.
include sign 2’s comp.
10011
+ 1
10100
 1001 01001
+10100
11101
Again 1’s comp. (As here minuend is greater)
This is sign
00010
This will be + 1 (For 2’s comp.)
here 00011
+1 0 0 1 1
 The result is (10011)2.
sign bit
Answer = (1 0011) 2

BOOLEAN ALGEBRA & LOGIC GATES
Q. Simplify the following functions by K-map:

(a) F(A, B, C) = (0, 2, 3, 4, 6)
(b) xy + yz + xz
Ans:
(a) F(A, B, C) = (0, 2, 3, 4, 6)
The K-map of the given expression is given below:
AB
C 00 01 11 10
000 010 110 100
0 0 1 2 1 6 1 4 1
1 001 011 111 101

1 3 1 7 5
_
AB
_ _
3
 y = (AB + C) (Answer)
_
(b) F = xy + yz + xz
_ _ _ _ _
= xy(z + z ) + yz(x + x) + xz(y + y) [As (A + A) = 01
_ _ _ _
= xyz + xyz + xyz + xyz + xyz + xyz
_ _ _
= xyz + xyz + xyz + xyz [Since, (A + A) = A]
 K – map of the expression is :-
xy __ _ _
Z xy xy xy xy
_ ___ _ _ _ __
Z xyz xyz xyz xyz
1 xy
__ _ _
Z xyz xyz xyz xyz
1 1 1
yz xz
 y = (xy + yz + xz) (Answer)
Q. Simplify the following expression and then express in (a) S-O-P and (b) P-O-S:
x'z' + y'z' + yz' + xy
Ans: y = x'z' + y'z' + yz' + xy
= x'z'(y + y') + y'z' (x + x') + yz'(x + x') + xy(z + z')
= x'yz' + x'y'z' + xy'z' + x'y'z' + xyz' + x'yz' + xyz + xyz'
= (x'y'z' + x'yz' + xy'z' + xyz' + xyz)
 The K-map representation is:

xy _ _ _ _
Z xy xy xy xy
Z ___ _ _ _ __
xyz xyz xyz xyz Z
1 1 1 1
Z __ _ _
xyz xyz xyz xyz
1
xy
_
 y = ( xy + z ). This is the simplified form. (Answer)
Now the SOP & POS form: -

_
4
a) Here the simplified POS form is y = (xy + z).
b) Now for SOP form: -
xy __ _ _
Z xy xy xy xy
___ _ _ _ __ _
Z xyz xyz xyz xyz
1 1 1 1
Z __ _ _
xyz xyz xyz xyz
Z 0 0 1 0
_ _
(x+Z) (y+Z)
_ _
 The SOP form is y = ( x + Z )( y + Z ) (Answer)
Q. Simplify the Boolean equation (A + AB).

Ans: Given, y = (A + AB)
= A(1 + B)
= A . 1 [since, (1 + B) = 1]
=A
OR, Another (K-map) method :-
A _
A A
B
_ __ _
B AB AB
1
B _
AB AB
1
y = A + AB
_ _
= A(B + B) + AB [since, B + B = 1]
_
= AB + AB
y=A
Q. Realize function F = Z(0,1,4,5,8,9,11,13,15) using NOR gates only.

Ans: The given function is y = m (0,1,4,5,8,9,11,13,15).
The K-map representation is :-
5
__ __
 y = ( AC + AD + BC ) (Answer)
Q. For function F (A, B, C, D) = Σ (0,1,7,8,9,14,15), find the expression for F in POS form.
Ans: F (A, B, C, D) = Σm (0,1,7,8,9,14,15)
The K-map representation is :-
__
 y = ( BC + BCD + ABC )
Q. Express the Boolean function F = xy + x′z in a product of maxterm form.

Ans: _
F = xy + x z = Y (let)
_ _ _ _
 Y = xy (z + z) + xz (y + y) [Since, A + A = 1]
_ _ __
= xyz + xyz + xyz + xyz …. (1)
6
Now as this is in SOP form,
 xyz corresponds to 111

_
Similarly, x y z  110
_
x y z  011
__
x y z  001
Q. Given the following Boolean function: F = A′C + A′B + AB′ C + BC. Express it in product of maxterms.
Ans:
7
Q. Simplify the following Boolean function F together with the don’t care conditions d; then express the
simplified function in sum of minterms.
f(x, y, z) =  (0, 1, 2, 4, 5) ; d(x, y, z) =  (3, 6, 7)
Ans: The given expression is:
f(x, y, z) = m (0, 1, 2, 4, 5) + d (3, 6, 7) [Since, f(x, y, z) = (0,1,2,4,5) ; d(x, y, z) = (3,6, 7)]
 The K-map representation of the above expression is:
8
f(xyz) = 0. (Answer)
Q. Minimize the following Using K-Map and Realize it with NAND 9 gates?
F(A,B,C,D) = m (2,3,4,5,13,15) + d (8,9,10,11)
Ans:
Given F(A,B,C,D) = m (2,3,4,5,13,15) + d (8,9,10,11)
 The K-map representation of the above expression is:
_ _ _
 F = (AD + BC + ABC). (Answer).
Q. Simply the following logic function using k-map and find the minterms & maxterms.
F(X,Y,Z)= XZ+ XYZ + YZ
Ans:
9
 F(xyz) = (yz + xz). (Answer).
Q. Realize the expression AB + AC + ABC using minimum NOR gates only.

Ans: The given expression is,
y = AB + AC + ABC
_ _
= AB(C + C) + AC(B + B) + ABC
_ _
= ABC + ABC + ABC + ABC + ABC
_ _
= ABC + ABC + ABC [since, a + a = a]
_ _
 y = (ABC + ABC + ABC) ; putting this expression in K-map:
AB _ _ _ _
C AB AB AB AB
_ _ _ _ _ _ _ __
C AB C AB C AB C A B C
1
__ _ _
C AB C AB C ABC ABC
1 1
AB AC
After solving K-map, the expression becomes as y = (AB + AC) = A(B + C)
Hence, the implementation of the above expression by NOR gate is:
10
_ _____
 y = A + (B + C)
_________
= A . (B + C) [ by De Morgan’s law]
= A . (B + C)
Q. Obtain the truth table of the following & implement it by using NAND Gates?
F(A,B,C) = (AB+BC)(AC+BC)
Ans: The given expression is:
y = F(A,B,C) = (AB+BC)(AC+BC)
= ABC + ABC + ABC + BC [Since, a.a = a ]
= ABC + BC [Since, a + a = a]
_ _
= ABC + BC (A + A) [Since, A + A = 0]
_
= ABC + ABC + ABC
_
= ABC + ABC
_
= BC (A + A) _
= BC [ Since, A + A = 1]
 The implementation of the expression y = BC, by NAND gate is:
ARITHMETIC CIRCUITS
Q. What is a multiplexer? Construct a 64-to-1 multiplexer using 4* 1 MUX.

Ans: A Multiplexer or MUX is a device that performs multiplexing. It selects one of many analog to digital input signals
and forward the selected input into a single line.
A multiplexer of 2n inputs has n selected bits which are used to select which input have to send to output.
Diagram of 64-to-1 multiplexer using 4 to 1 MUX :-
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Q. What is the role of a half adder and half subtractor?

Ans: Role of Half adder : Half adder is a simple combinational circuit which performs the arithmetic addition of two
binary digits, is called half-adder. This circuit has two 1 bit input and two output, called – Sum and Carry.
Role of Half subtractor : Half subtractor is a circuit which is used to perform the arithmetic subtraction. This circuit
also has two input and one output for difference of the two inputs and one output for borrow.
Q. Write the truth table of a Full Adder and then from it derive the circuit in terms of half adders.
Ans: Truth table of a Full Adder:
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Full Adder in terms of Half Adder :-
Q. Draw the circuit of a 2 to 4 decoder and explain its function.

Ans: Circuit diagram of a 2 to 4 decoder :-
This is 2-input 4-output combinational circuit. Now, from the diagram, it is clear that, for a particular input
combination only one output will become active and the others will remain inactive.
For example, when S1 & S2 = 0, then only D0 will become active. Similarly, for S1 = 0 & S2 = 1, D1 will become
active, and so on….
-- By this process, from select input, S1 = 0 & S2 = 0 to S1 = 1 & S2 = 1 - can be decodal.

-- This is the function of decoder.
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Q. Explain how 3 to 8 decoder function can be obtained from a demultiplexer (1 to 8).
Ans: Demultiplexer is a circuit (combinational circuit), that is used to distribute data which comes through a single
data line, into one of its various output line. The output line will be selected by the combination of select lines.
So, a demultiplexer have select lines and a data line as input.
But decoder is a circuit, that is used to decode any number to another form. Decoder have similar design as
demultiplexer but with one difference that decoder don’t have data line.
For example, the design of 1 to 8 demultiplexer is: -
Now the (3 to 8) decoder: -

If we just remove the data line from the 1 to 8 demultiplexer, then, the circuit will be the circuit of (3 to 8) decoder.
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For example, the logical diagram of 3 to 8 decoder is :-
-- So by removing the data line of demux, the circuit will function as demux.
Q. Design BCD to gray converter for digital circuits.
Ans: To design BCD to gray code converter, first we have to consider their respective conversion table: -
15
16
Q. Draw the block diagram of Full adder using half adders.

Ans: Block diagram of Full adder using half adder :-
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Q. Draw the circuit diagram of 8:1 MUX using 2:1 MUXs.

Ans:
Circuit diagram of 8:1 MUX using 2:1 MUX :-
2:1
MUX S
2:1
S MUX
2:1
MUX
S
2:1
MUX
S Output = Y
2:1
MUX
S
2:1
MUX
S
2:1
MUX
Q. Implement BCD to Excess-3 Code converter.

Ans: To implement BCD to Excess-3 Code converter, first we’ve to consider their respective conversion table:-
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 The K-map representation is as follows :-
19
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FLIP FLOP
Q. Draw an S-R flip-flop using NOR gates and develop its truth table.
Ans:
(a) Logic diagram of basic S-R flip-flop circuit with NOR gates
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(b) Truth table of basic S-R flip-flop circuit with NOR gates
When a 1 is applied to both the set and reset inputs of the flip-flop in the Figure below, both Q and Q' outputs go to 0.
This condition violates the fact that both outputs are complement of each other. In normal operation this condition
must be avoided by making sure that 1's are not applied to both inputs simultaneously.
Q. What are the various types of Flip Flop?

Ans: All flip-flops can be divided into four basic types: SR, JK, D and T. They differ in the number of inputs and in
the response invoked by different value of input signals. The four types of flip-flops are defined in Table 1.
Table 1. Flip-flop Types

FLIP-
FLIP-FLOP CHARACTERISTIC
FLOP CHARACTERISTIC TABLE EXCITATION TABLE
SYMBOL EQUATION
NAME
S R Q(next) Q Q(next) S R
0 0 Q 0 0 0 X
Q(next) = S + R'Q
SR 0 1 0 0 1 1 0
SR = 0
1 0 1 1 0 0 1
1 1 ? 1 1 X 0
J K Q(next) Q Q(next) J K
0 0 Q 0 0 0 X
JK 0 1 0 Q(next) = JQ'+ K'Q 0 1 1 X
1 0 1 1 0 X 1
1 1 Q' 1 1 X 0
Q Q(next) D
D Q(next) 0 0 0
D 0 0 Q(next) = D 0 1 1
1 1 1 0 0
1 1 1
Q Q(next) T
T Q(next) 0 0 0
T 0 Q Q(next) = TQ'+T'Q 0 1 1
1 Q' 1 0 1
1 1 0
Each of these flip-flops can be uniquely described by its graphical symbol, its characteristic table, its characteristic
equation or excitation table. All flip-flops have output signals Q and Q'.
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Q. Discuss the Master Slave J-K flip flop with the help of suitable block diagram.
Ans: A master-slave flip-flop is constructed from two separate flip-flops. One circuit serves as a master and the other
as a slave. The logic diagram of an SR flip-flop is shown in the Figure given below. The master flip-flop is enabled on
the positive edge of the clock pulse CP and the slave flip-flop is disabled by the inverter. The information at the
external R and S inputs is transmitted to the master flip-flop. When the pulse returns to 0, the master flip-flop is
disabled and the slave flip-flop is enabled. The slave flip-flop then goes to the same state as the master flip-flop.
Figure: Logic diagram of a master-slave flip-flop
The timing relationship is shown in Figure herewith and is assumed that the flip-flop is in the clear state prior to the
occurrence of the clock pulse. The output state of the master-slave flip-flop occurs on the negative transition of the
clock pulse. Some master-slave flip-flops change output state on the positive transition of the clock pulse by having an
additional inverter between the CP terminal and the input of the master.
Figure. Timing relationship in a master slave flip-flop
Q. Draw the circuit of an S-R Flip Flop using NAND gates only. From it derive the circuit of a D-Flip Flop
and explain its truth table.
Ans:
(a) Logic diagram of basic flip-flop circuit with NAND gates
(b) Truth table of basic flip-flop circuit with NAND gates
The D flip-flop shown in the given Figure bellow, is a modification of the clocked SR flip-flop. The D input goes
directly into the S input and the complement of the D input goes to the R input. The D input is sampled during the
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occurrence of a clock pulse. If it is 1, the flip-flop is switched to the set state (unless it was already set). If it is 0, the
flip-flop switches to the clear state.
(a) Logic diagram of Clocked D flip-flop implemented with NAND gates
From the truth table of the NAND based R- S flip flop and the logical diagram of the D flip flop it is clear that we can
omit the input (0 0) and (1 1) part of the truth table of the R-S flip flop as this case will not arise for the D flip flop. So
it’s truth table becomes as:
(b) Transition table and truth table of Clocked D flip-flop
Q. How can you realize-the edge triggered J-K Flip Flop from an S-R Flip Flop? Write the truth table of J-K
Flip Flop and explain how race-around problem can be solved in it.
Ans: The state of a flip-flop is changed by a momentary change in the input signal. This change is called a trigger and
the transition it causes is said to trigger the flip-flop. The basic circuits require an input trigger defined by a change in
signal level. This level must be returned to its initial level before a second trigger is applied. Clocked flip-flops are
triggered by pulses.
The clock pulse goes through two signal transitions: from 0 to 1 and the return from 1 to 0. As shown in the Figure the
positive transition is defined as the positive edge and the negative transition as the negative edge.
Figure. Definition of clock pulse transition
A clocked JK flip-flop or edged triggered JK f/f is shown in the Figure below. Output Q is ANDed with K and CP
inputs so that the flip-flop is cleared during a clock pulse only if Q was previously 1. Similarly, output Q' is ANDed
with J and CP inputs so that the flip-flop is set with a clock pulse only if Q' was previously 1.
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(a) Logic diagram of Clocked JK flip-flop
(b) Graphical symbol of Clocked JK flip-flop
(c) Transition table of Clocked JK flip-flop
The clocked flip-flops already introduced are triggered during the positive edge of the pulse, and the state transition
starts as soon as the pulse reaches the logic-1 level. If the other inputs change while the clock is still 1, a new output
state may occur. If the flip-flop is made to respond to the positive (or negative) edge transition only, instead of the
entire pulse duration, then the multiple-transition problem can be eliminated.
Note that because of the feedback connection in the JK flip-flop, a CP signal which remains a 1 (while J=K=1) after
the outputs have been complemented once will cause repeated and continuous transitions of the outputs. To avoid this,
the clock pulses must have a time duration less than the propagation delay through the flip-flop. The restriction on the
pulse width can be eliminated with a master-slave or edge-triggered construction. The same reasoning also applies to
the T flip-flop presented next.
By this process we can eliminate the race around condition.
Q. What is the race-around problem, and how is it rectified?

Ans: If the Flip Flop is level triggered then the output will change every time the input changes. But this change in
input may be due to noise. Thus at the end of noise cycle one can no longer be sure about the state of the output. This
situation may arise if the duration of clock pulse is greater than the clock propagation delay. This situation is called
the race around condition. It can be avoided with edge triggering.
To prevent any possibility of a "race" condition occurring when both the S and R inputs are at logic 1 when the CLK
input falls from logic 1 to logic 0, we must somehow prevent one of those inputs from having an effect on the master
latch in the circuit. At the same time, we still want the flip-flop to be able to change state on each falling edge of the
CLK input, if the input logic signals call for this. Therefore, the S or R input to be disabled depends on the current
state of the slave latch outputs.
If the Q output is a logic 1 (the flip-flop is in the "Set" state), the S input can't make it any more set than it already is.
Therefore, we can disable the S input without disabling the flip-flop under these conditions. In the same way, if the Q
output is logic 0 (the flip-flop is Reset), the R input can be disabled without causing any harm. If we can accomplish
this without too much trouble, the problem of the "race" condition will be solved.
The circuit below shows the solution. To the RS flip-flop we have added two new connections from the Q and Q'
outputs back to the original input gates. Remember that a NAND gate may have any number of inputs, so this causes
no trouble. To show that we have done this, we change the designations of the logic inputs and of the flip-flop itself.
The inputs are now designated J (instead of S) and K (instead of R). The entire circuit is known as a JK flip-flop.
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In most ways, the JK flip-flop behaves just like the RS flip-flop. The Q and Q' outputs will only change state on the
falling edge of the CLK signal, and the J and K inputs will control the future output state pretty much as before.
Q. Explain the operation of master-Slave Flip-flop?

Ans: One way of overcoming the problem with oscillation that occurs with a JK Flip-Flop when J=K=1 is to use a so-
called master-slave flip-flop which is illustrated below.
The master-slave flip-flop is essentially two back-to-back JKFFs, note however, that feedback from this device is fed
back both to the master FF and the slave FF.
Any input to the master-slave flip-flop at J and K is first seen by the master FF part of the circuit while CLK is High
(=1). This behaviour effectively "locks" the input into the master FF. An important feature here is that the complement
of the CLK pulse is fed to the slave FF. Therefore the outputs from the master FF are only "seen" by the slave FF
when CLK is Low (=0). Therefore on the High-to-Low CLK transition the outputs of the master are fed through the
slave FF. This means that the at most one change of state can occur when J=K=1 and so oscillation between the states
Q=0 and Q=1 at successive CLK pulses does not occur.
Q. Draw the circuit of an S-R Flip Flop using NOR gates. Write its truth table and explain why there is a
forbidden state. Is there any racing, if so explain it?
Ans: When a 1 is applied to both the set and reset inputs of the flip-flop in the Figure below, both Q and Q' outputs go
to 0. This condition violates the fact that both outputs are complements of each other. In normal operation this
condition must be avoided by making sure that 1's are not applied to both inputs simultaneously.
(a) Logic diagram of basic S-R flip-flop circuit with NOR gates
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(b) Truth table of basic S-R flip-flop circuit with NOR gates
Note that it is forbidden to have both inputs at a logic 1 level at the same time. That state will force both outputs to a
logic 0, overriding the feedback latching action. In this condition, whichever input goes to logic 0 first will lose
control, while the other input (still at logic 1) controls the resulting state of the latch. If both inputs go to logic 0
simultaneously, the result is a "race" condition, and the final state of the latch cannot be determined ahead of time.
This is the reason for which forbidden state will arise in S–R Flip-flop.
**Racing: An error condition in which two signals or sets of data collide. It can take place within a chip, a circuit, a
network or an application. It can be due to a timing malfunction in the hardware or poorly written software.
As because from the previous discussion we have seen that for the case where both the input of the S – R flip flop is
1,1 then there for the two outputs data is colliding, which is the reason of ambiguity of the output. So we can say that
though race around condition is not present here, but racing is present here.
MEMORY
Q. Explain the difference between the following memories:

(i) Static and dynamic.
(ii) Sequential and Random access.
(iii) Magnetic and semiconductor.
Ans:
(i) Static and dynamic.
Static Memory Dynamic Memory

1. Static memory allocation is before run time, but 1. Dynamic memory allocation is at runtime.
the values of variables may be changed at run time.
2. Static memory allocation stores its data in the 2. Dynamic memory allocation stores its
‘data segment’ of the memory. memory on heap.
3. Static memory must be declared at compile-time. 3. It can be declared at run-time using the
‘new’ and ‘delete’ operators (or ‘malloc’ and
‘free’ in C).
(ii) Sequential and Random access.
Sequential Access Memory Random Access Memory

1. In sequential access format, data is stored serially 1. In a typical random access format, data
on a sequential media such as a magnetic tape in sets is stored in defined areas on the media.
of data blocks, each block typically comprising 512 Another separate area is provided on the
bytes. Between each set of data block is an overhead media containing a directory (file
media area which contains such information as a file allocation table or FAT) indicating where
mark. Associated with each set of data block is the stored data is located. Because the
identification information and a cyclic redundancy sequential access media requires that
check (CRC). The file mark indicates an adjacent set overhead and other information be stored
of data block's sequential relationship to other data in a predetermined configuration and
blocks. Other areas of the media include information because this predetermined configuration is
indicating a beginning of media block, an end of the not present with the random access media,
media block, and an early warning area. The the two media's are incompatible.
beginning of media block is the starting location
where data can be stored, while the end of media
block is the last location where data can be stored. An
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early warning area indicates that an end of media

block is approaching when the media is scanned.
2. Sequential data storage devices, such as magnetic 2. File constructed in a manner in which
tape streamers, are widely used with computers to records may be placed in a random order;
back-up information stored on hard disk drives. The also called direct access file. Each record
tape streamers are fed information from the host in a random access file has associated with
computer in compliance with ANSI SCSI it a relative index number. Whenever a
specifications for sequential data. In the event of a record is read from a random access file, a
failure of the hard disk drive, the backed up computer program must produce a relative
information on the tape is transferred back to a index number for this record in order to
repaired hard drive. locate the record in the file.
(iii) Magnetic and semiconductor.
Magnetic Memory Semiconductor Memory

1. Magnetic storage uses different patterns of 1. Semiconductor memory uses
magnetization on a magnetically coated surface to semiconductor-based integrated circuits to
store information. Magnetic storage is non-volatile. store information. A semiconductor
The information is accessed using one or more memory chip may contain millions of tiny
read/write heads which may contain one or more transistors or capacitors. Both volatile and
recording transducers. A read/write head only covers a non-volatile forms of semiconductor
part of the surface so that the head or medium or both memory exist. In modern computers,
must be moved relative to another in order to access primary storage almost exclusively
data. In modern computers, magnetic storage will take consists of dynamic volatile
these forms: semiconductor memory or dynamic
(i) Magnetic disk random access memory. Since the turn of
(a) Floppy disk, used for off-line storage the century, a type of non-volatile
(b) Hard disk, used for secondary storage semiconductor memory known as flash
memory has steadily gained share as off-
line storage for home computers. Non-
(c) Magnetic tape data storage, used for volatile semiconductor memory is also
used for secondary storage in various
tertiary and off-line storage advanced electronic devices and
In early computers, magnetic storage was also used specialized computers.
for primary storage in a form of magnetic drum, or
core memory, core rope memory, thin film memory,
twistor memory or bubble memory. Also unlike today,
magnetic tape was often used for secondary storage.
Q. Discuss: Classification of memories.

Ans: The basic goal of digital memory is to provide a means to store and access binary data: sequences of 1's and 0's.
The digital storage of information holds advantages over analog techniques much the same as digital communication
of information holds advantages over analog communication. This is not to say that digital data storage is clearly
superior to analog, but it does address some of the more common problems associated with analog techniques and thus
finds immense popularity in both consumer and industrial applications. Digital data storage also complements digital
computation technology well, and thus finds natural application in the world of computers.
With some types of memory devices, the address in which certain data is stored can be called up by means of parallel
data lines in a digital circuit. However, some memory devices such as magnetic tapes have a one-dimensional type of
data addressing.
The access of data from a storage device falls roughly into two categories: random access and sequential access.
Random access means that we can quickly and precisely address a specific data location within the device, and non-
random simply means that you cannot.
The process of storing a piece of data to a memory device is called writing, and the process of retrieving data is called
reading. Memory devices allowing both reading and writing are equipped with a way to distinguish between the two
tasks. Some devices do not allow for the writing of new data, and are purchased "pre-written" from the manufacturer.
Such is the case for vinyl records and compact audio disks, and this is typically referred to in the digital world as read-
28
only memory, or ROM. Cassette audio and video tape, on the other hand, can be re-recorded (re-written) or purchased
blank and recorded fresh by the user. This is often called read-write memory.
Another distinction to be made for any particular memory technology is its volatility, or data storage permanence
without power. Many electronic memory devices store binary data by means of circuits that are either latched in a
"high" or "low" state, and this latching effect holds only as long as electric power is maintained to those circuits. Such
memory would be properly referred to as volatile. Storage media such as magnetized disk or tape is nonvolatile,
because no source of power is needed to maintain data storage. This is often confusing, because the volatile electronic
memory typically used for the construction of computer devices is commonly and distinctly referred to as RAM
(Random Access Memory). While RAM memory is typically randomly-accessed, so is virtually every other kind of
memory device in the computer. What "RAM" really refers to is the volatility of the memory, and not its mode of
access. Nonvolatile memory integrated circuits in personal computers are commonly (and properly) referred to as
ROM (Read-Only Memory), but their data contents are accessed randomly, just like the volatile memory circuits.
So ultimately the memory classification becomes as:
Cache memory Cache memory

Digital storage D latch, memory
Digital storage Computer storage, or computer memory, refers to the computer components, devices and recording
media that retain binary information for some interval of time
DRAM Asynchronous DRAM; SDRAM
DRAM: DDR3 SDRAM, RDRAM,
DRAM TECHNOLOGY DRAM (Dynamic Random Access Memory) is the main memory used for all desktop and
larger computers. Each elementary DRAM cell is made up of a single MOS transistor and a storage capacitor
Embedded memory Embedded memory is any non-stand-alone memory. It is an integrated on-chip memory that
supports the logic core to accomplish intended functions,
EPROM: electrically erasable programmable read only memory, rom, eprom, flash, prom, non volatile memory
Flash memory Flash memory technology, Flash memory technology is a mix of EPROM and EEPROM
technologies. The term Flash was chosen because a large chunk of memory could be erased at one time. The name,
therefore, distinguishes flash devices from EPROM’s, where each byte is erased individually.
Q. Discuss: Basic memory structure.

Ans: The basic goal of digital memory is to provide a means to store and access binary data: sequences of 1's and 0's.
The digital storage of information holds advantages over analog techniques much the same as digital communication
of information holds advantages over analog communication. This is not to say that digital data storage is clearly
superior to analog, but it does address some of the more common problems associated with analog techniques and thus
finds immense popularity in both consumer and industrial applications. Digital data storage also complements digital
computation technology well, and thus finds natural application in the world of computers.
With some types of memory devices, the address in which certain data is stored can be called up by means of parallel
data lines in a digital circuit. However, some memory devices such as magnetic tapes have a one-dimensional type of
data addressing.
The access of data from a storage device falls roughly into two categories: random access and sequential access.
Random access means that we can quickly and precisely address a specific data location within the device, and non-
random simply means that you cannot.
The process of storing a piece of data to a memory device is called writing, and the process of retrieving data is called
reading. Memory devices allowing both reading and writing are equipped with a way to distinguish between the two
tasks. Some devices do not allow for the writing of new data, and are purchased "pre-written" from the manufacturer.
Such is the case for vinyl records and compact audio disks, and this is typically referred to in the digital world as read-
only memory, or ROM. Cassette audio and video tape, on the other hand, can be re-recorded (re-written) or purchased
blank and recorded fresh by the user. This is often called read-write memory.
Another distinction to be made for any particular memory technology is its volatility, or data storage permanence
without power. Many electronic memory devices store binary data by means of circuits that are either latched in a
"high" or "low" state, and this latching effect holds only as long as electric power is maintained to those circuits. Such
memory would be properly referred to as volatile. Storage media such as magnetized disk or tape is nonvolatile,
29
because no source of power is needed to maintain data storage. This is often confusing, because the volatile electronic
memory typically used for the construction of computer devices is commonly and distinctly referred to as RAM
(Random Access Memory). While RAM memory is typically randomly-accessed, so is virtually every other kind of
memory device in the computer! What "RAM" really refers to is the volatility of the memory, and not its mode of
access. Nonvolatile memory integrated circuits in personal computers are commonly (and properly) referred to as
ROM (Read-Only Memory), but their data contents are accessed randomly, just like the volatile memory circuits.
Q. Write short notes on: Cache Memory.

Ans: In case of cache memory, It's really fast memory that the computer stores frequently used information in. This
allows the system to save itself from having to go out to the slow RAM or really slow hard drive if available in cache.
A cache, in computer terms, is a place to store information that's faster than the place where the information is usually
stored. Cache memory is fast memory that is used to hold the most recently accessed data in slower main memory.
The idea is that frequently accessed data will stay in cache, which allows the CPU to access it more quickly, which
means it doesn't have to wait for the data to arrive.
In reference to your processor, the Cache Memory is the Processor's internal quick-hand storage that it uses
for things that it's currently processing at that given time.
As with most things, the more cache memory a processor has, it will usually run smoother and faster than one
with less of about the same operating frequency.
There's also other types of cache, such as internet files are stored in a "cache" on your hard drive, databases
have their own "cache" memory areas, etc.
Q. Write down the memory hierarchy.

Ans: Most modern programs can benefit greatly from a large amount of very fast memory. A physical reality,
however, is that as a memory device gets larger, it tends to get slower. For example, cache memories are very fast but
are also small and expensive. Main memory is inexpensive and large, but is slow. The memory hierarchy is a
mechanism of comparing the cost and performance of the various places we can store data and instructions. The below
given Figure provides a look at one possible form of the memory hierarchy.
The Memory Hierarchy
Q. Differentiate between primary memory and secondary memory.

Ans:
Primary memory Secondary memory

1. Fast 1. Slow
2. Expensive 2. Cheap
3. Low capacity 3. Large capacity
4. Connects directly to the processor 4. Not connected directly to the processor
30
31

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Digital Electronics : Notes By Debanjan Patra

 Answer = (10111.011) 2 OR (010111.011) 2 (with sign bit)

Again (x – y) (by 2’s complement)

Q. Convert Hex CF 8.7 to binary, octal and decimal system.

1100 1111 1000 . 111

1100 1111 1000 . 111

110 011 111 000 . 111

12 x 162 + 15 x 161 + 8 x 160 + 7 x 16-1

= 3072 + 240 + 8 + 0.4375

Q. If A = 1001 and B = 1100 (Both in binary) find A+B and A-B.

A = 1001 (A+B) = 1001 (9)

B = 1100 +1100 (12)

sign bit 10101 (21)

 The result is (10011)2.

BOOLEAN ALGEBRA & LOGIC GATES

Q. Simplify the following functions by K-map:

1 001 011 111 101

 K – map of the expression is :-

 y = (xy + yz + xz) (Answer)

 The K-map representation is:

Now the SOP & POS form: -

a) Here the simplified POS form is y = (xy + z).

b) Now for SOP form: -

Q. Simplify the Boolean equation (A + AB).

OR, Another (K-map) method :-

Q. Realize function F = Z(0,1,4,5,8,9,11,13,15) using NOR gates only.

The K-map representation is :-

The K-map representation is :-

Q. Express the Boolean function F = xy + x′z in a product of maxterm form.

Now as this is in SOP form,

 xyz corresponds to 111

 The K-map representation of the above expression is:

 The K-map representation of the above expression is:

 F(xyz) = (yz + xz). (Answer).

Q. Realize the expression AB + AC + ABC using minimum NOR gates only.

After solving K-map, the expression becomes as y = (AB + AC) = A(B + C)

Hence, the implementation of the above expression by NOR gate is:

 The implementation of the expression y = BC, by NAND gate is:

Q. What is a multiplexer? Construct a 64-to-1 multiplexer using 4* 1 MUX.

Diagram of 64-to-1 multiplexer using 4 to 1 MUX :-

Q. What is the role of a half adder and half subtractor?

Full Adder in terms of Half Adder :-

Q. Draw the circuit of a 2 to 4 decoder and explain its function.

-- By this process, from select input, S1 = 0 & S2 = 0 to S1 = 1 & S2 = 1 - can be decodal.

Q. Explain how 3 to 8 decoder function can be obtained from a demultiplexer (1 to 8).

Now the (3 to 8) decoder: -

For example, the logical diagram of 3 to 8 decoder is :-

Q. Design BCD to gray converter for digital circuits.

Q. Draw the block diagram of Full adder using half adders.

Q. Draw the circuit diagram of 8:1 MUX using 2:1 MUXs.

Q. Implement BCD to Excess-3 Code converter.

 The K-map representation is as follows :-

Q. What are the various types of Flip Flop?

Table 1. Flip-flop Types

Figure: Logic diagram of a master-slave flip-flop

Figure. Timing relationship in a master slave flip-flop

(a) Logic diagram of basic flip-flop circuit with NAND gates

(b) Truth table of basic flip-flop circuit with NAND gates

(a) Logic diagram of Clocked D flip-flop implemented with NAND gates