NATIONAL INSTITUTE OF TECHNOLOGY, TIRUCHIRAPPALLI

DEPARTMENT OF COMPUTER SCIENCE AND ENGINEERING

COURSE PLAN – PART I

Name of the
programme and B.Tech. CSE
specialization
Course Title DIGITAL SYSTEMS DESIGN
Course Code CSPC33 No. of Credits 3
Course Code of Pre-
NIL
requisite subject(s)
Section
Session July 2021 A
(if, applicable)
R. LEELA VELUSAMY
Name of Faculty Department CSE

Official Email [email protected] Telephone No. 7598603413

Name of Course
Coordinator(s) NA
(if, applicable)
Course Type (please Core course Elective course
tick appropriately) X

Syllabus (approved in BoS)

Unit – I
Binary codes - Weighted and non-weighted - Binary arithmetic conversion algorithms,
Canonicaland standard boolean expressions - Truth tables, K-map reduction - Don't care
conditions - Adders / Subtractors - Carry look-ahead adder - Code conversion algorithms -
Design of code converters - Equivalence functions.
Unit – II
Binary/Decimal Parallel Adder/Subtractor for signed numbers - Magnitude comparator
- Decoders / Encoders - Multiplexers / Demultiplexers - Boolean function implementation
using multiplexers.
Unit – III
Sequential logic - Basic latch - Flip-flops (SR, D, JK, T and Master-Slave) - Triggering
of flip-flops - Counters - Design procedure - Ripple counters - BCD and Binary -
Synchronous counters, Registers - Shift registers - Registers with parallel load, Reduction
of state and flow tables - Race-free state assignment - Hazards.
Unit – IV
Introduction to VLSI design - Basic gate design - Digital VLSI design - Design of
general boolean circuits using CMOS gates. Verilog Concepts – Basic concepts – Modules
& ports & Functions – useful modeling techniques –Timing and delays–user defined
primitives. Modeling Techniques
Unit – V
Advanced Verilog Concepts – Synthesis concepts –Inferring latches and flip-flops–

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Modeling techniques for efficient circuit design. Design of high-speed arithmetic circuits–
Parallelism Pipelined Wallace tree tipliers - Systolic algorithms - Systolic matrix
multiplication.

Text Book
• Morris Mano and Michael D. Ciletti, "Digital Design", 5th edition, Prentice Hall of
India,2012
• Samir Palnitkar, "Verilog HDL", 2nd Edition, Pearson Education, 2003
Reference Books
• Michael D. Ciletti, "Advanced Digital Design with the Verilog HDL, 2nd Edition,
Pearson Education, 2010
• Stephen Brown, "Fundamentals of Digital Logic with Verilog", McGraw Hill, 2007
COURSE OBJECTIVES
 To understand the overview on the design principles of digital computing systems
 To learn the various number systems
 To learn Boolean Algebra and Understand the various logic gates
 To be familiar with various combinational circuits
 To be familiar with designing synchronous and asynchronous sequential circuits
 To be exposed to designing using PLD

MAPPING OF COs with POs

Programme Outcomes (PO)
Course Outcomes
(Enter Numbers only)
1. Ability to design and implement complicated digital systems PO1, PO3, PO5, PO7-9,
using Verilog PO12
2. Ability to design a VLSI circuit for an application PO1, PO3, PO5 - 7, PO12
3. Ability to comprehend the digital design logic PO1, PO3, PO7
4. Ability to design and analyze a digital circuit – combinational
PO1, PO7, PO12
and sequential
5. Ability to use Boolean simplification techniques to design a
PO1, PO5, PO7
combinational hardware circuit

COURSE PLAN – PART II

COURSE OVERVIEW
This course has two main goals: (1) to teach students how a digital computer works and (2) to
introduce students to Verilog programming. The hardware component of the course begins by
introducing the basic switching components of all digital circuits. It shows how to analyze circuits
and also how to build circuits that conform to specified computational properties. It introduces many
standard circuits used by all computers, such as logic and shift circuits, arithmetic circuits, and
memory circuits. The software part of this course explores the design aspects involved in the
realization of CMOS integrated circuits/systems from device up to the register/subsystem level.
Verilog HDL constructs that would help them to build combinational and sequential logic circuits in
CMOS.

COURSE TEACHING AND LEARNING ACTIVITIES ( Add more rows)

S.No. Week Topic Mode of Delivery

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 Binary codes - Weighted and non-
1 1 weighted Binary arithmetic ONLINE- PPT
conversion algorithms
Canonical and standard boolean
2 2 expressions - Truth tables - K-map ONLINE- PPT
reduction - Don't care conditions
Adders / Subtractors - Carry look-
ahead adder - Code conversion
3 3 ONLINE- PPT
algorithms - Design of code
converters - Equivalence functions
Binary/Decimal Parallel
4 4 Adder/Subtractor for signed numbers ONLINE- PPT
- Magnitude comparator
Decoders / Encoders - Multiplexers /
5 5 Demultiplexers Boolean function ONLINE- PPT
implementation using multiplexers
Sequential logic - Basic latch - Flip-
6 6 flops (SR - D - JK - T - Master-Slave) ONLINE- PPT
- Triggering of flip-flops -
Counters - Design procedure - Ripple
7 7 ONLINE- PPT
counters - BCD and Binary
Synchronous counters - Registers -
Shift registers - Registers with parallel
8 8 load - Reduction of state and flow ONLINE- PPT
tables - Race-free state assignment -
Hazards.
Introduction to VLSI design - Basic
gate design - Digital VLSI design -
9 9 ONLINE- PPT
Design of general boolean circuits
using CMOS gates -
Verilog Concepts - Basic concepts -
10 10 Modules & ports & Functions - useful ONLINE- PPT
modelling techniques -
Timing and delays - user defined
11 11 ONLINE- PPT
primitives - Modelling Techniques.
Advanced Verilog Concepts -
Synthesis concepts - Inferring latches
12 12 ONLINE- PPT
and flip-flops - Modelling techniques
for efficient circuit design
Design of high-speed arithmetic
circuits - Parallelism Pipelined
13 13 Wallace tree tipliers - Systolic ONLINE- PPT
algorithms - Systolic matrix
multiplication
COURSE ASSESSMENT METHODS (shall range from 4 to 6)
S.No. Mode of Assessment Week/Date Duration % Weightage
As per dept.
1 Written Test - 1 1 hour 20
schedule

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 Online assignments/surprise
2 Week 3, 6, and 8 offline 20
test
As per dept.
3 Written Test - 2 1 hour 20
schedule
4 Programming assignment Week 12 Online demo 10

As per dept.
CPA Compensation Assessment* 1 hour 20
schedule
As per institute
5 Final Assessment * 2 hours 30
schedule
*mandatory; refer to guidelines on page 5
COURSE EXIT SURVEY (mention the ways in which the feedback about the course shall be
assessed)

Feedback through online mode after Written test -1 and later through MIS

COURSE POLICY (including compensation assessment to be specified)

Students should not be absent for the written test 1 and 2. If the reason for absence is genuine, the
student can appear for compensation assessment. The medical certificate/on duty certificate should
be submitted within one week after rejoining. The portions for the compensation assessment will be
the entire portions covering test 1 and 2.

ATTENDANCE POLICY (A uniform attendance policy as specified below shall be followed)

 At least 75% attendance in each course is mandatory.

 A maximum of 10% shall be allowed under On Duty (OD) category.

 Students with less than 65% of attendance shall be prevented from writing the final
assessment and shall be awarded 'V' grade.

ACADEMIC DISHONESTY & PLAGIARISM

 Copying from others during an assessment will be treated as punishable dishonesty.

 Zero mark to be awarded for the offenders. For copying from another student, both students
get the same penalty of zero mark.

 The departmental disciplinary committee including the course faculty member, PAC
chairperson and the HoD, as members shall verify the facts of the malpractice and award
the punishment if the student is found guilty. The report shall be submitted to the Academic
office.

 The above policy against academic dishonesty shall be applicable for all the programmes.

ADDITIONAL INFORMATION, IF ANY

Students can approach me through mobile to clarify any doubt in any time during the working hours

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 FOR APPROVAL

Course Faculty __________ CC- Chairperson ________________ HOD ____________

Guidelines

a) The number of assessments for any theory course shall range from 4 to 6.

b) Every theory course shall have a final assessment on the entire syllabus with at least 30%
weightage.

c) One compensation assessment for absentees in assessments (other than final assessment)
is mandatory. Only genuine cases of absence shall be considered.

d) The passing minimum shall be as per the B.Tech.regulations.

(Peak/3) or (Class Average/2) whichever is lower

e) Attendance policy and the policy on academic dishonesty & plagiarism by students are
uniform for all the courses.

f) Absolute grading policy shall be incorporated if the number of students per course is less than
10.

g) Necessary care shall be taken to ensure that the course plan is reasonable and is objective

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