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2K views30 pages

OTIS DCSS 4 Basic Data - ImageShack

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Sting Eyes
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Part : 4 - C9

OTIS BASIC DATA No. : GDA24350AW


Otis Engineering Center
Berlin Vintage: 01 / 1

PRODUCT Page : 1 / 30
DCSS 4
ADMINISTRATION Date : 30-Nov.-1998

'&66%DVLF'DWD
*'$$: '2
*'$$: +3'6
*'$$: +6'6
*'$$: '&'6

Authorization Date D1 : . . . . . 01- April 2003. . . . . . . . . . . . . . . . . . . .


PCB : . . . . . . . . . . . . . . . . . . . GCA 24353 F1. . . . . . . . . . . . . . . . . . . .
Software Version : . . . . . . . . GAA 3032x AAA . . or higher . . . . . . .
.

Document Revision:
Date Author Comment
17-March-1997 M. Barten Original document
30-Nov.-1998 M. Barten Extended to F version of DCSS 4 PCB
01-April-2003 P. Herkel update for GDA packages

Copyright 1997, OTIS GmbH BerlinNo part of this document may be copied or reproduced in any form or by any means without the prior written
consent of OTIS GmbH.
Part : 4 - C9
OTIS BASIC DATA No. : GDA24350AW
Otis Engineering Center
Berlin Vintage: 01 / 1

PRODUCT Page : 2 / 30
DCSS 4
ADMINISTRATION Date : 30-Nov.-1998

1 Scope
Subject of this document is the DCSS 4 drive system an unique hardware platform for

x DO2000
x HPDS-VF
x HSDS-VF
x DCDS

applications. The DCSS 4 is an element of the Modular Elevator Control System (MCS). It
either interfaces with the Motion Command Subsystem (MCSS) in an MCS311/411 configu-
ration or with the Limited Car Board (LCB) in a MCS310/312 configuration.

The advanced door drive represents a microprocessor controlled freqency inverter suitable
for AC motor as well as DC motor applications. The proposed 3-phase inverter is the power
interface between the µP system and the motor. Ultrafast switching technology using a six
pack module IGBT device leads to noiseless operation and low current ripple due to the
high switching frequency of above 15kHz. A suitable gear reduces the speed of the motor
shaft according to the requirements of the mechanical environment.

The control and profile generation are done by a microprocessor system. Position recogni-
tion and security functions are implemented. Furthermore it has to establish the communi-
cation via the serial link with the MCSS or via discrete information lines with the LCB, from
where it gets the door commands.

The PWM generation is done by a specific IC (ELGA Gate Array).

The position could be is acquired by an incremental encoder or a switch position reference.

All In- and Outputs for signal use are optically insulated. Different signal levels can be
processed to fit all required system configurations.

To supply an alternate door an additional DCSS 4 system is necesssary.

The following will describe the basic configuration and function.


Part : 4 - C9
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Otis Engineering Center
Berlin Vintage: 01 / 1

PRODUCT Page : 3 / 30
DCSS 4
ADMINISTRATION Date : 30-Nov.-1998

2 Technical Overview

2.1 Design Concept


The DCSS consists of one printed circuit board with integrated:
x input filter/ burst and surge protection
x power supply
x microprocessor system
x serial- and discrete interface
x PWM generator
x 3-phase inverter power stage

as shown in the DCSS configuration below.

DCSS 4 Hardware-Configuration

All components are located on the PC board, no package internal wiring is necessary. The
enclosure is made of plastic material which is equipped at the inner side with a metal layer
in order to shield the electromagnetic dissipation caused by the frequency inverter.

The package is prepared to be fixed via double lock tape spots on every clean metal sur-
face where the tape spots could be glued on.

Please refer to the following chapters for detailed hardware information.


Part : 4 - C9
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DCSS 4
ADMINISTRATION Date : 30-Nov.-1998

2.2 Ratings

Nom. Voltage: 1x230V-240V AC, 50/60HZ, -15%/+10% (195V..264Vac)


Output Voltage: 3 * 0..230Vac / 3-Phase
Nom. Current: 3 * 1.5Aac / 3-Phase
Output Frequency: 0..128Hz / 3-Phase
Leakage Current: 13mA

Electrical Output Power: 550VA continuous (Un=230V, In=1.5A, Ipeak=8A)


Mechanical Output Power: M=
Appar.Outp.Power * Efficiency(AC motor) _* cosM
550W * 0.5 * 0.6 = 165W

2.3 Configuration Requirements


The supply will be provided in general directly by the main switch panel in the ma-
chine room. An automatic cut-off for each door system located in the elevator con-
troller protects the traveling cable and the DCSS 4 box.

Attention:

x In order to protect the traveling cable and the DCSS 4 box only automatic cut-off’s
with class C characteristic and a limit within the range of 2.5A...4A are permitted

x DCSS 4 requires a single phase 230V Ac supply. In case that a neutral is not avail-
able or the supply voltage is different from 230 Vac the elevator controller has to be
equipped with an additional transformer.

The DCSS 4 requires in D02000,HPDS-VF and HSDS an incremental speed encoder complying
to the following specification:

x two tracks with 500 or 1000 pulses per round


x phase shift between the tracks +/- 45°
x supply voltage 15V
x Output : Open Collector or NPN Push-Pull circuit
x shielded cable
Part : 4 - C9
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DCSS 4
ADMINISTRATION Date : 30-Nov.-1998

Use only the authorized encoder types:

Door System Encoder Type Remarks


DO1 (DO2000) Siko: IG06-ABX-500-E1-M1-PP-W04 standard for DO2000
DO2 (HPDS-VF) British Encoder : 755 HV standard for SEW motor

Siko: IG06- ABX- 500-E1-M1-PP-W04 released as second source


Baumer : BHU 03.24G500 ,,
DO3 (HSDS-VF)

The application of other encoders increases the risk of fail function.

For DCDS application apply two door open/close limit switches.

DCSS 4 is only released for authorized Motor types:

Door System Motor Type Remarks


DO1 (DO2000) SEW standard for SUPRA Door

Meidensha 200 W second source


Tornado
DO2 (HPDS-VF)
DO3 (HSDS-VF)
DO4 (DCDS)

For other motors a sufficient performance is not guaranteed.

The DCSS 4 fulfills the EMC requirements given in PREN 12015/16 under condition that
the:

x enclosure is closed
x motor cable shield is connected to motor case and the cable gland of heat sink
panel

In order to avoid disturbances of the encoder signal lines apply only shielded encoder cables and con-
nect the shield to plug pin P3.5
Part : 4 - C9
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DCSS 4
ADMINISTRATION Date : 30-Nov.-1998

3 Hardware Design

3.1 Power Supply


The supply of the IGBT drivers (4 x 24Vdc/150mA) as well as the 5V/1A supply of the µP
system and 15Vdc/200mA incremental encoder supply are provided by a switched mode cir-
cuit which is powered from the DC-Link.

3.2 The Frequency Inverter Power Stage

3.2.1 Power Circuit

,-----. ,-----. ,-----------------.


L O----------| |------| | |----o----| ---+----+----. |-------O
PE O---+---- | Fil-| | -+- | |+ | -|E -|E -|E | .--.
+---+----+ | ter |-| | /_\ | === | |-o |-o |-o|--O--( AC )
|ESD Prot| | | | | | | | -|E -|E -|E | `--‘
+---+----+ | |------| | |----o----| ---+----+----‘ |-------O
NE O---+------`-----‘ `-----‘ `-----------------‘
2 Phase AC DC Link 3 Phase AC
Mains Filter Rectifier Capacitor Inverter Asynchr.Motor

Inverter Power Stage

The inverter power stage consists of an ESD protection circuit (varistor and gas discharge
device), an input filter, an EMC reduction circuit (Print-Filter), an uncontrolled full-bridge
rectifier, the DC Link (buffer capacitor) and the 3 Phase Inverter stage.

Using PWM modulation techniques the requested (average) output values are obtained ac-
cording to the duty cycle of the bridge leg switching pattern. The power stage is able to
drive three phase AC motors as well as DC-motors. In DC-motor mode two half bridges
(U, V) are used for armature and the third (W) half bride is used for field control. The su-
pervising circuit will limitate each bridge leg current to it’s maximum of 8 A.

A supervising circuit will prevent the DC link current from beeing to high by interrupting the
inverter control.

Reverse motion can be achieved by PWM control. Braking mode is possible. However, the
recovered energy must be dissipated. The regained mechanical energy during braking will
be dissipated in the friction losses, motor losses (efficiency for small AC motors ca. 50%)
inverter losses and charging of the DC-Link capacitor. The max. voltage of the DC-Link ca-
Part : 4 - C9
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DCSS 4
ADMINISTRATION Date : 30-Nov.-1998

pacitor has to be greater than 357 Vdc (nominal suply voltage +15 %) plus the max. volt-
age swing during the generative mode of the motor.

3.2.2 Inverter Control and Protection Concept


After connected to the mains, the pre-loading status for the DC Link is controlled by the mi-
croprocessor system. The capacitor Cdcl is preloaded via the resistor Rdcl to reduce the
surge current. After a software controlled delay time the DC Link Relays SWdcl short-
circuits the resistor Rdcl.

The DC Link Current Idcl of the inverter stage is observed with a shunt resistor RSdc. All
short-circuit- and overload-conditions lead to an according voltage drop on the resistor, ex-
cept ground faults to the positive DC bus bar. Under normal operation the induced voltage
will be 0V.
+----+
+ )--o-|Rdcl|-o-------o----------------| +
| +----+ | | | |
| | | Cdcl |
+---o/o--’ | + |
SWdcl : ===== | Inverter
+-+ | |
--|/|-- | |
+-+ | +----+ |
- )-------------------o-|RSdc|---------| -
+----+
| |
V V

DC Link Control- and Supervisory Component

An active “OCURR” signal stops immediately the transmission of the pulsepattern to the
power stage and activates a microprocessor interrupt . The “OCURR” is transmitted by an
opto-coupler to achieve full insulation between the power stage and the microprocessor
unit.
Part : 4 - C9
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DCSS 4
ADMINISTRATION Date : 30-Nov.-1998

3.3 DCSS Microprocessor System


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DCSS 4
ADMINISTRATION Date : 30-Nov.-1998

The DCSS 4 microprocesor system is designed to communicate with an host system in two
different ways depending on the connected elevator controller type:

x discrete I/O lines for NE300, 310/312 and MCS 220 controller
x (L)MCSS serial link for MCS311/321/411/421 controller

All interface lines are optically insulated.

A second serial link is implemented for maintenance purpose using the Otis Service Tool.

A Customer specific ASIC (Elga) which mainly provides pulse width modulation controls the
3-phase power IGBT module. With this PWM-technique the frequency can be varied from 0
to 128 Hz (0.25 Hz solution) with a voltage range from 0 to 230V.

The microprocessor system consists of the embedded 8 Bit microcontroller SAB80C515A,


a 32k Byte Ram and a 1M Bit Flash Memory. The Flash Memory substitutes an EPROM
(program memory) and an EEPROM (parameter memory).

Flash Memory program control logic mainly located in a GAL 22V10 provides in co-
operation with a boot-up software kernel on board reprogramming of the Flash.

Addresslatch and Addresdecoder are both integrated in the ELGA chip

In order to guarantee a determined behaviour in case of a supply power failture the reset
logic observes the 5V microprocessor supply and activates the uP reset before the voltage
will reach the critical limit of 4.75 V. The reboot of the system caused by a reset or in
power up mode is checked by a microprocessor internal watchdog.

The microprocessor ready state is shown on the board with an Light Emitting Diode (LED).
Under normal conditions the “RUN” LED must be lit.

3.4Hardware Description

3.4.1Microcontroller 80C515A
The DCSS 4 board is controlled by an 80C515A microcontroller from SIEMENS. This one
chip microcomputer has integrated an internal RAM, serial interface, discrete I/O ports,
three timers, an Analog/Digital Converter and special capture and compare logic.

The microprocessor is clocked by a 18 MHz crystal.


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DCSS 4
ADMINISTRATION Date : 30-Nov.-1998

The 80535 is programmed for following features:

Discrete Input/Output ports

P0.0 to P0.7 multiplexed data/adressbus


P2.0 to P2.7 higher addressbus
P1.0 to P1.7 discrete outputs
P4.0 to P4.7 discrete inputs
P5.0 to P5.7 discrete I/O

Serial Input/Output port

Asynchronous full duplex serial link, baudrate 9600 generated by internal baudrate gen-
erator

Analog Inputs

Input 0..5V

Timers
.lt;
Timer 0 programmed as 16 bit counter for speed encoder measuring

Timer 1 programmed as counter to check if the speed encoder direction


toggles and a limit is set to find out if one channel is missing.
.el;
.le;^*Interrupt Controller\*
.lt;
1) hardware interrupt for system cycle each 4.096 msec

2) Timer-2-overflow interrupt with auto reload, so that an overflow


will happen all 10 ms.

Compare/Capture interrupt 3 to active the profile generator and


the control algorithm (start control interrupt).

Compare/Capture interrupt 1 to load the V/f values and to start


the PWM-chip (output control interrupt).

3) Serial interrupt for the service tool.


Part : 4 - C9
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DCSS 4
ADMINISTRATION Date : 30-Nov.-1998

4) Multidrop serial link


.el;
.le;internal RAM of 256 bytes at location 0 to FFH
.le;internal software watchdog
.le;clock signal output of 1MHz for system cycle generation
.els
.hl^&^*Address_ Decoding\&\*

The table below presents the external I/O and data memory configuration:
.LT

+------------+----------+-----------+---------------+
| | Address | | CS-Signal |
| Device | Size | CS-Signal | Adr. Space |
+------------+----------+-----------+---------------+
| RAM | 8k x 8 | /A15 | 0000H - 7FFFH |
+------------+----------+-----------+---------------+
| EEPROM | 2k x 8 | /CSEEP | C000H - EFFFH |
+------------+----------+-----------+---------------+
| PBM4 | 32 x 8 | /CS0 | F000H - F0FFH |
+------------+----------+-----------+---------------+
| KS82C450 * | 8 x 8 | /CS4 | F400H - F4FFH |
+------------+----------+-----------+---------------+
| DAC ** | 6 x 8 | /CS1 | F100H - F1FFH |
|(interface) | | /CS2 | F200H - F2FFH |
| | | /CS3 | F300H - F3FFH |
+------------+----------+-----------+---------------+

* serial link communication IC


** digital to analog converter engineering tool

.el
The CS-Signals are generated by the PBM4 IC.

.hl^*^&Program_ Memory\&\*
The EPROM program memory is selected by the /PSEN signal of the microcontroller
covering the complete address space. In this mode the /READ and /WRITE line are
not activated and no other memory can be selected.
The HPDS-VF program memory resides in up to 128k-byte of a 271001 EPROM.

The memory paging between the different blocks, where the program is
allocated, is done via the signal "page_mem" coming from the uP (P5.0)
at the address line A16.
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DCSS 4
ADMINISTRATION Date : 30-Nov.-1998

.hl^*^&Data_ memory\&\*
The data memory is divided into three different types:
.list '-';
.le; internal RAM with 256 bytes from address 0 to FFH.
.le; external CMOS-RAM implemented with one 6164 LP (8k-byte). It is activated
by the address lines A0 to A14 and a /WR or /RD signal. This storage area is
used for temporary storage of data, flags, variables and errorlog informations.
.le; EEPROM implemented with one 2816 (2k byte). It is selected by the address
C000H to C07FFH. This storage area is used for permanent storage of
installation variables. These values can be modified by the service tool.
.b;
To protect the EEPROM against false writing during power up and power down,
the precision voltage comparator Z14 disables the internal EEPROM write
logic. In addition the output pin ENE2P of Z102 has to be programmed to
low level to enable EEPROM read/write operations.
.els;
.page
.hl^*^&Watchdog_ /_ Resetlogic\&\*
^*Watchdog:\*
.b2; The HPDS-VF has two watchdogs. An internal WD, which must be set and triggered
by the software and an external one, which is triggered by a hardware
signal.
.b; The internal watchdog is a free running timer which must be cleared by the
software at least every 65532 µsec to avoid an overflow, which causes a
reset. The disadvantage of this watchdog is, that it must be enabled by
the program. In case of wrong start up the watchdog is not initialized and
no reset would appear.
.b2; The external watchdog generates an oszillating signal if it is not
triggered in time. This guarantees that the processor will be reset
until the program has started up and generates the necessary
trigger pulses.
.b; The external watchdog is implemented with 3 retriggerable monoflops.
The first monoflop, realized by a 74LS123 is used only to hold the
output at high level, if no trigger impulses are received. This is
necessary to bring the WD in an oscillating mode.
If trigger impulses are received, the monoflops transmit these to the
trigger input of the 74LS123. This circuit is a dual retriggerable
monoflop with external R-C networks, which causes a pulse-width-
modulation signal of 15ms or 7ms respectively. In normal operation
section 1 is triggered every 12 ms by a software generated output pulse.
In case of no retriggering for more than 15 msec, output Q1 will go
low, resulting in a system reset. Section 2 will be triggered
simultaneously and the reset signal will oscillate until the software
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DCSS 4
ADMINISTRATION Date : 30-Nov.-1998

sends pulses again.


.b4;
^*Hardware_ Reset:\*
.b2; The hardware reset logic has to reset the microprocessor until
the logic voltage Vcc is in stable condition. A Voltage Reference- and
Compare circuit disables the watchdog until the power supply gets in a
proper condition.
.b4;
^*Software_ Reset:\*
.b2; To check if the program runs properly a boardrun flag must be set in time.
This flag is set, if all required tasks have been executed within a
specific time interval. If the flag is not set periodically before a
specific time has elapsed (640 msec), the program restarts with the
initialisation routine.
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DCSS 4
ADMINISTRATION Date : 30-Nov.-1998

3.5Discrete Inputs/Outputs

The different external input signals (30V and 110V) are converted to logic level by optically
insulated level converters located on the DCSS Inverter board.

30V Inputs:

To cover most applications, two different control methods for 30V operation can be real-
ized:

Pull-Up (+): Two inputs (DOB [P5/7] and DO [P5/8]) are activated by a
voltage of 30V (I~12mA) referring to HL2.
- Pull-Down (__): Two inputs (/SO [P5/4] and /NDG [P5/5]) are activated by
pulling the appropriate input to HL2 (I~-12mA). A supply of
+30V must be provided at P5/1.

The inputs are protected against overvoltage (Uin > 80V).

Outputs:

Two output stages DOS and /DOL can switch +30V to connected devices. The supply con-
nected at +30V [P5/1] must be able to cover the requested power according to the con-
nected devices. The referring ground is HL2.
Recovery diodes prevent the transistors from overvoltage due to inductance at the output.

3.6Connector References:

Mains In : 3 pin Wago (male, 7.5 mm) :

- P1.1 L1
- P1.2 PE, note 1
- P1.3 N

Power Stage: Faston:

- P8 : Motor Output Phase U


- P9 : Motor Output Phase V
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- P10 : Motor Output Phase W


- P7 : DC+
- P11 : DC-
- P13 : PE

Safety Chain: 4 pin Wago (male, 5mm, pin 2 coded)

P2.1 : EDS, note 2


P2.2 : TCI, note 2
P2.3 : PE, note 1
P2.4 : HL1

Speed Encoder Connector: 5 pin Wago (male, 5mm)

P3.1 : +15V/200mA , output (power supply for position reference), Ref. P2.4
P3.2 : T1, input, note 3
P3.3 : T3, input, note 3
P3.4 : Gnd
P3.5 : Shield encoder cable

(L)MCSS Serial Link( RS485): 4 pin Wago (male, 5mm, pin 4 coded)

P4.1 : RxA0 RXB Input Receive, optically insulated


P4.2 : RxB0 ,,
P4.3 : TxA0 TXB Output Transmit (r5V)
P4.4 : TxB0 ,,

Discrete Inputs: 10 pin Wago (male, 5mm)

P5.1 : +30V input (discrete interface power supply)


P5.2 : DOS, note 4
P5.3 : DOL, note 4
P5.4 : /SO, note 5
P5.5 : /NDG (alternate function in serial configuration : /EDP), note 5
P5.6 : SPARE 1, note 5
P5.7 : DOB, note 6
P5.8 : DO (alternate function in serial configuration: LRD), note 6
P5.9 : SPARE 2, note 6
P5.10 : HL2
Part : 4 - C9
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Service Tool Connector ( RS485): 9 pin Canon (female)

P6.1 : +5V
P6.2 : nc
P6.3 : TxB1
P6.4 : RxA1
P6.5 : Gnd
P6.6 : +5V
P6.7 : TxA1
P6.8 : RxB1
P6.9 : Gnd

note 1: leading PE pin


note 2: input 110V, optically insulated, Ref. to HL1
note 3: input suitable for devices with push-pull or with open collector (NPN) output circuits
note 4: output +30V (30V/<1A; Pull Down 2k5)
note 5: input low active to HL2 (30V/10mA)
note 6: input high active +30V (30V/10mA)
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4Quality Criteria

3.4 Power Supply


The DCSS 4 system can be supplied with 230Vrms single phase via the connector P1. All
voltages for the electronic circuits on the PCBoard are generated by a switched power
mode supply:

Voltage Testpoint Referencepoint Min. Typ. Max. Unit


L1 P1_1 N (P1_3) 195 230 264 Vrms
V15 P3_5 Gnd (P3_1) 14.25 15 15.75 V
VCC Z11/68 Gnd (P3_4) 4.75 5 5.25 V
24V1 OC9/8 HLV1 (OC9/7) 22 24 26 V
24V2 OC12/8 HLV2 (OC12/7) 22 24 26 V
24V3 OC15/8 HLV3 (OC15/7) 22 24 26 V
24V4 OC18/8 HLV4 (P11) 22 24 26 V
VBIAS Z2/12 DCGND (OC18/7) 14 16 18 V
DCVCC DC+ (P7) DC- (P11) 276 325 374 V

Current values:
Circuit Min. Typ. Max Unit
L1 Input Current < 0.1 1 6 Arms
VCC : without SV-Tool 0,4 0,5 0,6 Arms
VCC : with SV-Tool 0,8 0.9 1,0 Arms
V15 : (incr. encoder) 0.01 0.1 0.2 Arms
24V1, 24V2, 24V3 001 0.1 < 0.2 Arms
24V4 0.03 0.3 < 0.9 Arms
VBIAS 0.02 0.05 < 0.2 Arms

3.5 Levelconverter 110V

Input Testpoint Referencepoint Min. Typ. Max. Unit


/EDS P2_1 HL1 (P2_4) 0 110 130 Vrms
/TCI P2_2 HL1 (P2_4) 0 110 130 Vrms

Stimulus : Input: P2_1 to P2_4: >78Vrms --> HC1/6 H-Level


<50Vrms --> HC1/6 L-Level
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Input P2_2 to P2_4: >78Vrms --> HC2/6 H-Level


<50Vrms --> HC2/6 L-Level

Current values: High -Level input current ( Vin = 110 Vrms): 8.5 mA

3.6 Discrete 30 V IO’s

Input Testpoint Referencepoint Min. Typ. Max. Unit


30 V P5_1 HL2 (P5_10) 0 30 39 V
/SO P5_4 HL2 (P5_10) 0 30 39 V
/NDG P5_5 HL2 (P5_10) 0 30 39 V
/SPARE P5_6 HL2 (P5_10) 0 30 39 V
DOB P5_7 HL2 (P5_10) 0 30 39 V
DO P5_8 HL2 (P5_10) 0 30 39 V
SPARE P5_9 HL2 (P5_10) 0 30 39 V

Stimulus : Input: P5_4 to P5_10: >18Vrms --> L-Level at Z11/6


< 7Vrms --> H-Level at Z11/6

Stimulus : Input: P5_5 to P5_10: >18Vrms --> L-Level at Z11/4


< 7Vrms --> H-Level at Z11/4

Stimulus : Input: P5_6 to P5_10: >18Vrms --> L-Level at Z11/2


< 7Vrms --> H-Level at Z11/2

Stimulus : Input: P5_7 to P5_10: >18Vrms --> H-Level at Z11/2


< 7Vrms --> L-Level at Z11/2

Stimulus : Input: P5_8 to P5_10: >18Vrms --> H-Level at Z11/10


< 7Vrms --> L-Level at Z11/10

Stimulus : Input: P5_9 to P5_10: >18Vrms --> H-Level at Z11/12


< 7Vrms --> L-Level at Z11/12

Current values: Input current : max. 5 mA


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Note : Propagation delay Inputs 30V

Min. Typ. Max. Unit


30 50 70 ms

DC operation requires 12Vdc instead of 18Vrms and 8Vdc instead of 7Vrms

3.7 Output Levelconverter

Output Testpoint Referencepoint H-Level. L-Level Unit


DOS P5_2 HL2 (P5_10) 29 (Note1) Note 2 V
/DOL P5_3 HL2 (P5_10) 29 Note(1) Note 2 V

Note 1: Value for nominal supply voltage of 30V.


Note 2: depends on Iol current (Ra = 2,5 kOhm).

Stimulus : Z5/11 : >3.5V P5_2 H-Level


<1 V P5_2 L-Level

Stimulus : Z5/13 : >3.5V P5_3 H-Level


<1 V P5_3 L-Level

Note : Propagation delay Inputs 30V

Min. Typ. Max. Unit


2 4 6 ms

Current values: Output current: max. 1A

3.8 (L)MCSS Serial Link

3.8.1 Input
Referencepoint: P4_2 (RXB0)

Stimulus : P4_1 (RXA0) : >2.25 V --> H-Level at Z7/12


< 1.25 V --> L-Level at Z7/12
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The input current depends on the on-board SER control line:

Ih (SER = H-Level) <= +/- 15m A


Ih(SER = L-Leve) <= +/- 5mA

3.8.2 Output
Referencepoint: P4_3 (TXA0) (note)

Min. Typ. Max

Stimulus : Z6/4 (TXD0) = L-Level,: --> P4_4 (TXB0) 3.5 5 V

Z6/4 (TXD0) = H-Level: --> P4_4 (TXB0) -3.5 -5 V

note: set Z7/9 (ENTX0) = L-Level, Z7/8= H-Level in order to enable output driver

3.9 SVT Serial Link

3.9.1 Input
Referencepoint: P6_8 (RXB1)

Stimulus : P6_4 (RXA1) : >2.25 V --> H-Level at Z15/1


< 1.25V --> L-Level at Z15/1

Current values: Input Current: max. : <= +/- 15m A

3.9.2 Output
Referencepoint: P6_7 (TXA1)

Min. Typ. Max


Stimulus : Z17/4 (TXD1): L-Level --> P6_3 (TXB1) 3.5 5 V

Z17/42 (TXD1): H-Level --> P6_3 (TXB1) -3.5 -5 V


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Current values: Input current: max. : <= +/- 15m A

3.10 Speed Encoder


Referencepoint: P5_5 (Gnd)

Input Testpoint Referencepoint Min. Typ. Max. Unit


T1 P3_2 P3_4 (Gnd) 0 15 V
T2 P3_3 ,, 0 15 V

Current values: Input current : max IL = 7 mA, max. Ih < 1mA

Stimulus: P3_2: L-Level --> Z3/2 : L-Level, Z5/2 H-Level


P3_2: H-Level --> Z3/2 : H-Level, Z5/2 L-Level

P3_3: L-Level --> Z3/1 : L-Level, Z5/8 H-Level


P3_3: H-Level --> Z3/1: H-Level, Z5/8 L-Level
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4 Interface Description

4.1 Connection to L C B (Discrete Interface)

The controller must be set to “Door Operator=DO2000” (if not available: “9550”).

The Limited Car Board has no serial link. The communication between the systems is done
by the discrete signals only. These are the DO and /NDG signals which are interpreted by
the DCSS as a door command.

The reversal device signal DOB, LRD, EDP and the /DOL output of the DCSS are read by
a Remote Station Board.

These discrete signals are converted by the RSB into a serial information and are sent to
the LCB via the serial link.

Reopening for passenger protection is signaled to the operational controller at the DOB in-
put by the Door Open Signal (DOS) of the DCSS.

Nudging operation is provided as standard by the DCSS and may be selected by the
operational controller, e.g. with delayed car operation, EFS etc.

DOB, EDP and LRD commands are processed by the operational controller and may be
disabled in specific modes.
The Door Open Limit (/DOL) output of the DCSS signals correct door opening to the opera-
tional controller.

Emergency Door Stop (/EDS) deenergizes the door according to code requirements and
will be connected to the safety chain.

Top of Car Inspection (/TCI) input indicates the inspection mode. In this mode a door com-
mand can be entered by the Service Tool.
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,---------------------------. Discrete ,----------.


| | Interface | |
| Operational / Motion |---------------->| Drive |
| Control |<----------------| |
| | | |
`-+---------------------+--+’ `----------‘
| | |
| REMOTE | |
| SERIAL | |
| LINK | | ,---------. ,---------.
| | `---------DO------>| | | |
| 4 | | | | DOOR |
/ ...>...|..o......../NDG.....>| +----+ MOTOR |
| ,----------+. | . /TCI ---->| D C S S | | |
| | | | . /EDS ---->| | ,---------.
o---+ R S Board | | . | | | |
| | |<----|--.-----------/DOL--<| +----+ SPEED |
| `+----+----+’ | . | | | ENCODER |
| : : o------|--.------------DOS--<| | | |
| : LRD | | . `---------‘ `---------‘
| EPR% DOB | .
| :..<EDP | .
| | . /NDG ,---------. ,---------.
| | ·.................>| | | |
| | ADO | | | DOOR |
| `-------------------->| +----| MOTOR |
| ,-----------. /TCI ---->| | | |
| | | /EDS ---->| D C S S | ,---------.
o---+ R S BOARD | | | | |
| | |<------------------/ADOL--<| +----+ SPEED |
| `-----+----+’ | | | ENCODER |
| : : o---------------------ADOS--<| | | |
| : ALRD | `---------‘ `---------‘
| EPR% ADOB
| :..<AEDP
|
|
| ,-----------.
| | |
`---+ R S Board |
| |
`+----+----+’
| | |
LWX LNS LWO

DCSS in MCS 110/220/310/312 Configuration


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4.2 DCSS in NE/NH 300 Configuration

The controller must be set to “Door Operator=DO2000” (if not available:“9550”).

The MS/NE 300 system uses the same system structure as described for the
MCS120/220/310/312 system above.

,---------------------------. Discrete ,----------.


| | Interface | |
| Operational / Motion |---------------->| Drive |
| Control |<----------------| |
| | | |
`-----------------------+--+’ `----------‘
: | | : |
: | | : | DO ,---------. ,---------.
: | | : `----------------->| | | |
: | | : /NDG | | | DOOR |
: | | `....................>| +----+ MOTOR |
: | | /TCI --->| | | |
: | | /EDS---->| D C S S | ,---------.
: | | /DOL | | | |
: | `------------------------------------<| +----+ SPEED |
: | DOS | | | ENCODER |
: `-----------------------------o---------<| | | |
: EPR | `---------‘ `---------‘
`.............o/o.......<EDP o----<DOB
`...<LRD

DCSS in NE 300 Configuration


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4.3 Connection to (L)MC S S (Serial Interface)

The (L)MCSS must be set to “Door Type = 1” (DO2000/HPDS)

The DCSS and the (L)MCSS are connected via the serial link for the data transmission and
by the discrete /Safe to Open signal /SO.

A 5-pole connector P4 with two twisted pair wires establishes the serial communication
between the (L)MCSS and the DCSS. It satisfies the RS 485 standard for differential data
transmission lines. Via this serial link commands and status information’s are transmitted.

For detailed information see Interface Control Document MCSS - DCSS.

The /Save to Open (/SO) input is connected to +30V via a 2.2k resistor and the photo cou-
pler on the DCSS. The MCSS has to pull down this input to HL2 to enable a door opening.
It can be enabled only, if the car is stopping in the door zone.

The /NDG input is re-assigned to be connected to an Electronic Door Protector (EDP). The
according output must be able to switch (+30V) to HL2 (=RTN on RS board).

The DO input is re-assigned to be connected to a Light Ray Device LRD. The according
output must be able to switch to +30V (supply of the RS boards).HL2 on P5.8 must be con-
nected to HL2(=RTN of the RS link).

The DOB input is assigned to be connected to the Door Open Button. It is switched to +30V
(supply of the RS boards). HL2 on P5.10 must be connected to HL2 (=RTN of the RS link).

With the Multidrop Serial Link 2*DCSS for front and alternate door and one loadweighing
device can be connected to the serial bus. To avoid an overload of the transmit driver on
the (L)MCSS board the impedance of the receiver of the DCSS can be adapted by setting
an electronic switch, operating as line terminator, during the installation routine. How the
line terminator has to be set depends on the configuration (see table):

DCSS Systems One Unit Two Units Three Units


Unit 1 Line Terminator Line Terminator ON* Line Terminator OFF
ON
Unit 2 Line Terminator OFF Line Terminator OFF
Unit 3 Line Terminator OFF
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*Physically Farthest !!!

,--------. ,----------. ,--------.


| | RS422 | | RS422 | |
| O C S S +--------/----+ M C S S +-------------/------+ D B S S |
| | 4 | | 4 | |
`-+-------´ `+-+------+-´ `---------´
| | | | RS485
| REMOTE | | | 4
| SERIAL | | / ,---------. ,---------.
| LINK | | | | | | |
| | | o------------<>| | | DOOR |
| 4 | | | | +----+ MOTOR |
/ | | | /EDS ----->| | | |
| | | | /TCI ----->| D C S S | ,---------.
| | | | | | | |
| | | | /SO | +----+ SPEED |
| | `-------------------->| | | ENCODER |
| | | | | | |
| | | `---------´ `---------´
| | | : | :
| | | EDP>..: DOB LRD
| | |
| | |
| | | ,---------. ,---------.
| | | | | | |
| | o------------<>| | | DOOR |
| | | | +----+ MOTOR |
| | | /EDS ---->| | | |
| | | /TCI --->| D C S S | ,---------.
| | | | | | |
| | | A/SO | +----+ SPEED |
| `--------|------------->| | | ENCODER |
| | | | | |
| | `---------´ `---------´
| | : | :
| | AEDP>..: ADOB ALRD
| |
| |
...|................... ...|...........................................
: | ,-----------. : : | ,---------. ,------------. :
: | | | : : | | | | LOAD | :
: `<>| R S BOARD | : : `------------<>| LWSS +---+ WEIGHING | :
: | | : : | | | TRANSDUCER | :
: `-----------´ : : `---------´ `------------´ :
: | | | : : :
: LWX LNS LWO : : :
: (only MCS 311/321): : (only MCS 411) :
:.....................: :..............................................:

DCSS in MCS 311/321/411 Configuration


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4.4 Top of Car Door Operation according to British Standard

To move a door from the top of car without additional tools (SVTOOL) the DCSS can be
commanded by the TDOS switch, located into the TCI box. The TDOS can be switched to
Top of car Door Opening Button (TDOB) for door opening or to Top of car Door Closing
Button (TDCB) for closing.

To enable the Top of Car Inspection operation the parameter 'TCI with BS7255', has to be
set in the sub-menu ‘CONFIG’ of the ‘SETUP’ menu (SVTOOL key sequence :3-3-1).

The connections to the DCSS differ between the serial, discrete and Relay Controller In-
terfaces (with additional Interface Box).

4.4.1 DCSS with Discrete Interface

To operate the door system from top of the car, the elevator must be set into Inspection
mode (TCI) and the Service Tool must be disconnected e.g. the SVT has the higher prior-
ity. With three discrete signals the door operator can be controlled. One signal (NDG input)
to enable a door movement only in the door zone and two signals (DOB and /SO) to control
the opening and closing of the door.

- The doorzone signal will be set by the controller and is sent to the DCSS (P5.5)
via the Remote Station.

- The door close command (TDCB) is read by the Remote Station, transferred to
the LCB, which set the Door Close Management (DCM) via the RS17. This signal is
read by the DCSS at input P5.4.

- The door open command (TDOB) is read directly by the DCSS at DOB input P5.7

The door operator starts moving the door with a delay of 2 seconds with a low speed profile
during Top of Car Inspection.
If no discrete signal is activated, the door system will stay in the shut down mode.

The software of the LCB must be revised to set the NDG output if TCI is set into inspection
and the car is in the door zone.
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Safety
Chain DO Controller: "NDG" OR ("TCI" AND "Door Zone")
| | |
110V | | v
| | ,---------. ,-----------.
| | | RS18 | | RS17 |--- NDG --------.
| | |TDOB TDCB| | DOS DOL|--- DCM ---. |
| | `---------' `-----------' v v
o o | ^ ^ ^ ^ ,---------. .---------.
/ .TES | | | | | |/SO NDG | | |
o etc +------|-----|------|-------|------DO-->| | | |
| | | | | | | | DOOR |
| | | | | | +----+ MOTOR |
| +-----|------|-------|------DOB->| | | |
| | | | | | | | |
o----------------|-----|------|-------|-----/EDS->| D C S S | | |
| | | | | | (DO2000)| | |
| o o--------|-----|------|-------|--- -/TCI->| | .---------.
| TCI / | | | | | " BS " | | |
o-----o | | | | | | | |
| o o o-------|-----/DOS-<| +----+ SPEED |
| TDOB/ /TDCB /DOB | | | | ENCODER |
V o o o +-----/DOL-<| | | |
| | | ,------. `---------' `---------'
`-----`--o o---TCI--->| RS16 |
/ | |
o `------'
|
30V

DCSS with a discrete Interface Connection

Control signals: (seen from the door system, electrical state)


____
BS-Door-Opening: /TCI ^ NDG ^ DOB ^ /SO
____ ____ ____
BS-Door-Closing: /TCI ^ NDG ^ DOB ^ /SO

LCB-II NDGsignal = (/TCI ^ NDG) or


____
(/TCI ^ Door Zone)

4.4.2 DCSS with Serial Interface


To operate the DCSS must be configured to British Standard by re-assigning the discrete
inputs. If the TCI is set to Inspection the input 'DOB' generates an "Open" command
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(TDOB) and the 'LRD' input will be recognized as a "Close" command (TDCB). Due to the
code requirements a door movement from the top of the car without a Service Tool is al-
lowed only if the car is in the door-zone, recognized by the '/SO'- signal.

The door operator only provides a slow speed (initialize) during Top of Car Inspection.

If no discrete signal is activated, the door system will stay in the shut down mode.

Safety
Chain
|
|110V
|
|
o o ,---------. .---------.
/ TES ,--------------o-------------------DOB->| | | |
o etc. | | | | | |
| | | | | | DOOR |
| | ,--------|------o---------LRD=DO·>| +----+ MOTOR |
| | | | | | | | |
| | | | | | | | |
o-----------|-----|--------|------|-----------/EDS->| D C S S | | |
| | | | | | | | |
| | | | | | | | |
| TCI o o--|-----|--------|------|-----------/TCI->| | .---------.
| / | | | | | | | |
o-----o o o o o -----/SO->| +----+ SPEED |
| / / / / | | | ENCODER |
V o o o o --RS485-><| | | |
| | | | `---------' `---------'
`-----o--o o--o------'
TDOB TDCB / DOB LRD
o TCI
|
| +30 V

DCSS in "MCS311/321/411-British Standard" -Configuration

Control-signals: (seen from the door system, electrical state)


____ ___
BS-Door-Opening: /TCI ^ /SO ^ DOB ^ DO
____ ____
BS-Door-Closing: /TCI ^ /SO ^ DOB ^ DO
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4.5 Emergency Firemen Service

During the first phase of the Emergency Firemen Service (EFS) a door reversal must be
disabled, to guarantee that the doors can be closed to drive the car to the EFS floor. Due to
the different kinds of controller interfaces there are different ways to indicated the EFS
mode.

- Discrete Interface:

To indicate the EFS mode the input '/SO' at plug P5.4 must be pulled down to
HL2 by the Remote Station output 'DCM' (Door Close Management). With this
information the internal Passenger Protection of the DCSS will be disabled.

- Serial Interface:

The door system will be informed of the EFS mode by receiving the respective
door command via the serial link. No additional actions are necessary.

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