Assignment 5
Assignment 5
Topics: Fixed Point Toolbox Analysis & FIR Filter Maximum Marks: 100
Due Date: Mon, 31-Oct-22 Due Time: 23:59hours
Instructor: Prof. Dr. Rehan Hafiz TAs: Hazoor & Emad
Important Instructions:
● This is an individual assignment. Each student must work alone, without help from any other person.
Plagiarism is NOT allowed. Copying material from the web or from documents and submitting it for this
assignment without giving credit/reference is plagiarism. Copied assignment will be marked ZERO.
● The Verilog Code should be synthesizable. The Verilog code should be properly commented. An optimized
implementation will result in more credits.
● 10 marks/day will be deducted in case of late submission after the due date.
● ONLY upload your PDF FILE on Google Classroom. Must name your file YourName_RollNumber.pdf
o The snapshot of the Simulator results
o Answer to any subjective question asked in the Assignment
o References
In this question, you will use your function for 1-D Convolution from Assignment 1. The convolution where
asked is of type “Full”.
a) Convolving triangular pulses using Built-in and Custom Functions:
Generate two triangular pulses (input 𝒙 and filter 𝒉).
%x = input
a = -5:0.5:5;
x = 64*triangularPulse(-3,3,a);
stem(x);
%h = filter
b = -3:0.5:3;
h = 2*triangularPulse(-1,1,b);
stem(h);
Find the convolution from built-in function
y_built = conv(x,h,’full’);
Calculate the convolution from your own function made in Assignment 1.
y_cust = MyConv1D(x,h,’full’);
Compare both outputs of y_built and y_cust.
b) Quantization of inputs for built-in "conv" Function:
We can use Fixed-Point Toolbox from MATLAB to convert inputs to a Quantized. The command “x_fixed =
fi(x,IsSigned,WordLength,FractionLength) will take “x” as input and return “x_fixed” as a quantized signal.
The arguments of “fi” are as follows:
1. First argument is the input signal.
2. Second argument is 1 for signed quantization and 0 for unsigned quantization.
3. Third argument is the required # of bits of the output signal.
4. Forth argument is the required # of bits of the fractional part of the output signal.
For example, after running run the following command:
x_fixed = fi(x, 1, 16, 8)
we will see the following in command window:
x_fixed =
Columns 1 through 14
0 0 0 0 0 10.6680 21.3320 32.0000 42.6680 53.3320 64.0000 53.3320 42.6680
32.0000
Columns 15 through 21
21.3320 10.6680 0 0 0 0 0
DataTypeMode: Fixed-point: binary point scaling
Signedness: Signed
WordLength: 16
FractionLength: 8
This means “x_fixed” is a signed 16bit quantized form of “x” with 8bit fraction.
In the similar way quantize your filter “h” and determine the convolution of quantized signals. The following
commands:
h_fixed = fi(h, 1, 16, 8);
y_fixed_in = conv(x_fixed, h_fixed)
will output the following in command window:
y_fixed_in =
Columns 1 through 14
0 0 0 0 0 0 0 0 0 0 10.6680 42.6680 85.3320 128.0000
Columns 15 through 28
170.6680 213.3320 234.6641 213.3320 170.6680 128.0000 85.3320 42.6680 10.6680 0 0
0 0 0
Columns 29 through 33
0 0 0 0 0
DataTypeMode: Fixed-point: binary point scaling
Signedness: Signed
WordLength: 36
FractionLength: 16
Now calculate the MSE for “y” and “y_fixed_in” and fill the Table 1 as follows:
1. In the third column of Table 1, m is the integer part size whereas n is the fraction part size.
Therefore, we use following relation for calculating m and n:
n = FractionLength
m = WordLength – n
In the first row of Table 1, n is 16 and m is 36-16 = 20.
2. The MATLAB command “error = mse(y, y_fixed_in)” can be used to calculate the MSE of y
and y_fixed_in.
>> mse(w_built,y_fixed_in)
ans =
7.1595e-07
Follow the same procedure as above and change the quantization of inputs and fill the remaining rows of
Table 1.
Write Verilog module and testbench for the Finite Impulse Response (FIR) Filter shown in Figure 1.
• 𝑋𝑛 , 𝑋𝑛−1 , 𝑋𝑛−2 , 𝑋𝑛−3 , 𝑋𝑛−4 are 8-bit wide and 𝑌𝑛 is 16-bit wide. The values of 𝑋𝑛 for your simulation
are
𝑋𝑛 = [1 2 3 4 5 6 7 8 9]
• The coefficients 𝐶𝑛 , … 𝐶𝑛−4 are 8-bit constants, while simulating you can suppose them to be five
digits of your roll no. For example, Hazoor’s roll no is PhDEE17004, therefore, 𝐶𝑛 = 1, 𝐶𝑛−1 =
7, 𝐶𝑛−2 = 0, 𝐶𝑛−3 = 0, 𝑎𝑛𝑑 𝐶𝑛−4 = 4.
Your Report should contain a) Verilog Module, b) Verilog Testbench, c) RTL Schematics, d) Resource Utilization, e)
Power Estimation, f) Simulation Waveform, g) Produced Outputs