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ARM Processor - Instruction Set - Module 5

This document contains a lecture on the ARM7 instruction set. It discusses the register organization, condition mnemonics, instruction set and processor state. It describes the different types of instructions including data processing, branch, load-store, software interrupts and program status register instructions. It provides examples of various instructions like data movement, arithmetic, logical, comparison, multiply and branch instructions. It also covers barrel shifter operations, swap instructions and coprocessor instructions.

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Raghu Ram
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154 views24 pages

ARM Processor - Instruction Set - Module 5

This document contains a lecture on the ARM7 instruction set. It discusses the register organization, condition mnemonics, instruction set and processor state. It describes the different types of instructions including data processing, branch, load-store, software interrupts and program status register instructions. It provides examples of various instructions like data movement, arithmetic, logical, comparison, multiply and branch instructions. It also covers barrel shifter operations, swap instructions and coprocessor instructions.

Uploaded by

Raghu Ram
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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ARM Processor – Instruction Set

Lecture on ARM7 Instruction set

By
Harish V. Mekali
Assistant Professor, Dept. of ECE
BMSCE, Bangalore - 19
Register Organization - CPSR

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Condition Mnemonics

Fig : Condition mnemonics that can be added to basic instructions


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Instruction Set & Processor State

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Instruction set

Classification of instructions
1. Data Processing Instruction
- Data movement , Arithmetic, Logical, Comparison, Multiply
2. Branch instructions
3. Load – store instructions
- Single register, Multiple register, Stack operations, Swap
4. Software interrupt instructions
5. Program Status Register instructions

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Data Processing Instructions
- Most of the data processing instructions can process one operand using
barrel shifter
Data movement instructions
- “S” suffix with MOVE operations can update the C, Z, N flags in CPSR

- “N” can be register or immediate data


- Example : MOV instruction without and with barrel shifter operations

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Barrel Shifter Operations

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Arithmetic Instructions

- “N” is the result of shift operation


- Example :

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Logical Instructions

- Updates CPSR only if suffix “S” is added and logical instructions


can also use barrel shifter in the same way as MOVE and
arithmetic
- Example :

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Comparison Instructions

- Updates CPSR only without affecting the register content and this
can be used in conditional execution
- TST is logical AND and TEQ is a logical XOR operation
- Example :

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Multiply Instructions

- Example :

05-01-2017 ARM Processors - Instruction Set 11


Branch Instructions

- Address label is stored with instruction as a PC relative offset and it must


be approximately 32 MB
- BX and BLX are primarily used for branch to and from Thumb code . “T”
bit in CPSR is updated by least significant bit of branch register

05-01-2017 ARM Processors - Instruction Set 12


Branch Instructions

- Example :

05-01-2017 ARM Processors - Instruction Set 13


Load and Store Instructions

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Load and Store Instructions

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Load and Store Instructions

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Load and Store Instructions

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Swap Instructions

- Its an atomic operation – It reads and writes


location in the same bus operation
preventing any other instruction from
reading and writing to the location until it
completes

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Program Status Register Instructions

- CPSR_<fields> refer to Control (C) , Extension (x) , Status (s) , Flags (f)

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Coprocessor Instructions

- “cp” field in the syntax refer to coprocessor number p0 to p15.


- “opcode” field refer to operation to take place on coprocessor
-

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Thank you

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Harish V. Mekali
Assistant Professor, Dept. of ECE, BMSCE

[email protected] / [email protected]

+91-9538765141

http://harishvmekali.blogspot.in/p/technology.html

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I acknowledge and appreciate ARM University Program(AUP)

and ARM Embedded Systems pvt. Ltd. for their continuous

support.

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References
Video lectures :
1. Mr. Chrish Shore, ARM Training Manager, UK
The ARM University Program, ARM Architecture Fundamentals
( https://www.youtube.com/watch?v=7LqPJGnBPMM )
2. Dr. Santanu Chaudhury, Dept. of Electrical Engineering, IIT Delhi
Lecture - 5 ARM : ( https://www.youtube.com/watch?v=4VRtujwa_b8 )

Website :
3. http://infocenter.arm.com/help/index.jsp

Textbooks:
1. ARM system developers guide, Andrew N Sloss, Dominic Symes and Chris
Wright, Elsevier, Morgan Kaufman publishers, 2008.
2. ARM System-on-Chip Architecture, Steve Furber, Second Edition,
Pearson, 2015

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