CAN-CTRL

CAN Controller Core

For CAN 2.0B and CAN FD

Users Guide

October 2015

IP Product Version
5H(V)97N00S00

Document Signature
CAN-CTRL–USG–5H(V)97N00S00–131

CAST, Inc.

CONFIDENTIAL
CAN-CTRL Core Users Guide

Document Version
This document with its associated Release Notes applies to the version(s) of the core specified on the
cover. See the Release Notes for any updates and additional information not included here.
Table 1-1 Document Version History

Version Date Person Changes from Previous Version

4H(V)00N00S00-100 2011/08/24 R.H. First release
Acceptance filtering clarification
4H(V)01N00S00-101 2011/09/16 R.H.
New synthesis parameter - NO_STBUFS
change of behavior: ACF_x are not readable if
RESET=0.
4H(V)02N00S00-102 2011/10/20 R.H. Reset values of ACF_x changed.
New synthesis parameter - NR_OF_ACF
Software example (ANSI C) for host controller added.
4H(V)03N00S00-103 2011/12/16 B.S. Enhanced test status report added.
4H(V)03N00S00-104 2012/01/11 P.D. Core name changed.
Verilog version testbenches added, VHDL testbench
4H(V)04N00S00-105 2012/02/23 B.S. and Verilog testbench “tbench.v(hd)” modified to be the
same for RTL code and netlist simulation
Pin name “int” renamed to “irq” because of System
4H(V)05N00S00-106 2012/04/04 B.S.
Verilog key words
4H(V)05N00S00-107 2012/09/17 R.H. Documentation: RTR and DLC
4H(V)06N00S00-107 2012/11/12 R.H. Bugfix for Verilog, see release notes
4H(V)07N00S00-107 2012/12/14 R.H. Improvements for ATPG, see release notes
4H(V)08N00S00-108 2013/01/28 R.H. AMBA APB interface added
Behaviour of TECNT, RECNT corrected in
4H(V)08N00S00-109 2013/04/08 R.H.
documentation
4H(V)09N00S00-109 2013/04/23 R.H. Improvements for ATPG, see release notes
4H(V)10N00S00-109 2013/05/23 R.H. Floating net in VHDL removed, see release notes
4H(V)11N00S00-110 2013/06/02 R.H. New container for multiple CAN-CTRL instances added
5H(V)00N00S00-111 2013/10/23 R.H. CAN FD support added
5H(V)01N00S00-112 2013/11/13 R.H. CAN FD support fixed and completed
5H(V)02N00S00-113 2013/12/09 R.H. Bit timing calculator added
5H(V)03N00S00-114 2013/12/16 R.H. Code cleanup
5H(V)03N00S00-115 2014/01/07 R.H. Typing errors corrected
5H(V)04N00S00-116 2014/02/21 R.H. Specification change for host read access
5H(V)05N00S00-117 2014/03/04 R.H. Improvements for host read access
5H(V)06N00S00-118 2014/03/10 R.H. Loop Back Mode and Standby Mode added
5H(V)07N00S00-118 2014/04/16 R.H. Testbench and kind of error correction
5H(V)08N00S00-118 2014/05/06 R.H. Source code improvements for LINT checkers
5H(V)09N00S00-118 2014/05/06 R.H. Source code improvements for Xilinx Vivado
5H(V)10N00S00-119 2014/08/05 R.H. AMBA APB interface redesigned
5H(V)11N00S00-120 2014/08/08 R.H. AMBA APB interface bugfix: no strobe signal for read
5H(V)12N00S00-121 2014/08/21 R.H. AMBA AHB interface added
AMBA APB: byte access protection
5H(V)13N00S00-122 2014/09/02 R.H.
New register map (better address alignment)
5H(V)14N00S00-123 2014/09/17 R.H. Release package cleanup
5H(V)15N00S00-123 2014/12/17 R.H. Bugfixes, new bits AIDEE and AIDE, new register TDC
5H(V)16N00S00-123 2015/04/14 R.H. Timing path optimizations
Transformation to 32 bit peripheral
5H(V)93N00S00-128 2015/07/28 R.H.
New memory map

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CAN-CTRL Core Users Guide

New RBUF, TBUF and ACF organization

AMBA interface updated, documentation of host
interfaces updated
CAN FD ISO compatibility
LOM and LBM updated
5H(V)94N00S00-128 2015/08/06 R.H. Improved CAN FD error handling for fixed stuff bits
5H(V)95N00S00-129 2015/08/13 R.H. Prescalers can now be set to 1.
New register BITTIME_3
5H(V)96N00S00-130 2015/09/11 R.H.
Bit timing documentation improved
New method for interrupt flag reset
Unlimited number of STB slots
5H(V)97N00S00-131 2015/10/05 R.H.
New behaviour of TSSTAT
CAN FD ISO CRC fix

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CAN-CTRL Core Users Guide

Table of Contents
1. Introduction ............................................................................................................................ 8
1.1 The CAN-CTRL Core ...................................................................................................... 8
1.2 The CAN Protocol ........................................................................................................... 8
1.3 Using the CAN-CTRL Core ............................................................................................. 9
2. Features ................................................................................................................................ 10
2.1 Feature List ................................................................................................................... 10
2.2 Upward Compatibility .....................................................................................................11
2.3 Message Buffers ............................................................................................................11
2.3.1 Message Buffers Concept .....................................................................................11
2.3.2 Receive Buffer.......................................................................................................11
2.3.3 Transmit Buffer ..................................................................................................... 12
2.3.4 Transmit Buffer Application Example ................................................................... 12
2.3.5 Aborting a Transmission ....................................................................................... 13
2.4 CAN 2.0 and CAN FD Frames ...................................................................................... 13
3. Interfaces .............................................................................................................................. 15
3.1 Hardware Interface........................................................................................................ 15
3.2 Configuration Parameters ............................................................................................. 16
3.3 Definitions ..................................................................................................................... 16
3.4 Clock Domain Crossing ................................................................................................ 17
3.5 Software Interface ......................................................................................................... 17
3.6 General Operation......................................................................................................... 33
3.6.1 The Bus Off State ................................................................................................. 33
3.6.2 Acceptance Filters ................................................................................................ 33
3.6.3 Message Reception ............................................................................................. 34
3.6.4 Handling message receptions .............................................................................. 35
3.6.5 Message Transmission ........................................................................................ 35
3.6.6 Message transmission abort ................................................................................ 36
3.6.7 A Full STB ............................................................................................................ 37
3.6.8 Extended Status and Error Report ....................................................................... 37
3.6.8.1. Programmable Error Warning Limit ...................................................... 37
3.6.8.2. Arbitration Lost Capture (ALC) ............................................................. 38
3.6.8.3. Kind Of Error (KOER) ........................................................................... 38
3.6.9 Extended Features ............................................................................................... 38
3.6.9.1. Single Shot Transmission ..................................................................... 38
3.6.9.2. Listen Only Mode (LOM) ...................................................................... 38
3.6.9.3. Bus Connection Test ............................................................................. 39
3.6.9.4. Loop Back Mode (LBMI and LBME) ..................................................... 39
3.6.9.5. Transceiver Standby Mode ................................................................... 40
3.6.10 Software Reset................................................................................................... 40
4. CAN Bit Time ........................................................................................................................ 42
4.1 Data Bit Rates ............................................................................................................... 42
4.2 Definitions ..................................................................................................................... 42
4.3 Example Configuration .................................................................................................. 44
4.4 CAN Bit timing Calculator (CBC) .................................................................................. 45
4.5 Bit Rate Switching and the Sample Point ..................................................................... 45
4.6 Bit Timing Configuration for CAN FD Nodes ................................................................. 46
4.7 TDC and RDC ............................................................................................................... 46
4.8 Bit Timing Recommendations ....................................................................................... 47
5. Host Interfaces ..................................................................................................................... 49
5.1 Generic 32 Bit Wide Synchronous Host Interface ........................................................ 49
5.1.1 Register Write ...................................................................................................... 49
5.1.2 Register Read ...................................................................................................... 49
5.1.3 Data Alignment ..................................................................................................... 50
5.2 Generic 8 Bit Wide Synchronous Host Interface .......................................................... 50

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CAN-CTRL Core Users Guide

5.3 AMBA APB .................................................................................................................... 51

5.4 AMBA AHB .................................................................................................................... 51
6. Functional Description ........................................................................................................ 53
6.1 CAN-CTRL Core Basic Block (can_core_nobuf) .......................................................... 53
6.1.1 Bit Timing Logic (BTL) .......................................................................................... 53
6.1.2 Transceiver Logic (TCL) ....................................................................................... 53
6.1.3 Interface Management Logic (IML) ...................................................................... 53
6.1.4 Error Management Logic (EML)........................................................................... 53
6.1.5 Status Buffer ......................................................................................................... 53
6.2 CAN-CTRL Core Wrapper (can_ctrl) ............................................................................ 54
6.2.1 Host Interface ....................................................................................................... 54
6.2.2 Receive Buffer (RBUF) ........................................................................................ 54
6.2.3 Transmit Buffer (TBUF) ........................................................................................ 54
6.2.4 Acceptance Filters (ACF) ..................................................................................... 54
6.3 Buffer Memories ............................................................................................................ 54
7. CAN Multicore....................................................................................................................... 55
8. Testbenches .......................................................................................................................... 56
8.1 Three-node Environment .............................................................................................. 56
8.1.1 Tbench ................................................................................................................. 56
8.2 CAN Multicore Testbench.............................................................................................. 57
9. RTL Source Code Version Supplied Files .......................................................................... 58
10. How to use the CAN-CTRL core ......................................................................................... 60
10.1 How to set up the HDL environment ............................................................................. 60
10.2 How to use the CAN-CTRL core as microcontroller peripheral .................................... 60
10.3 How to transmit or receive a frame ............................................................................... 60
10.4 How to learn about the testbench usage ...................................................................... 60
11. Support .................................................................................................................................. 61

List of Figures
Figure 1-1 Connection to CAN Bus and Main Features of the CAN-CTRL Core.......................... 8
Figure 2-1 Message Buffers Concept ...........................................................................................11
Figure 2-2 Transmit Buffer Application Example (TSALL=1) ...................................................... 13
Figure 2-3 CAN 2.0 and CAN FD Frame Types .......................................................................... 14
Figure 3-1 CAN-CTRL Core Pinout ............................................................................................. 15
Figure 3-2 Clock Domain Crossing ............................................................................................. 17
Figure 3-3 Memory Map for 8 / 16 / 32 Bit Interface ................................................................... 20
Figure 3-4 Access to the Acceptance Filters ............................................................................... 28
Figure 3-5 Schematic of the FIFO-like RB (example with 6 slots) .............................................. 30
Figure 3-6 Schematic of PTB and FIFO-like STB (empty PTB and 6 STB slots) ....................... 33
Figure 3-7 Example of acceptance filtering ................................................................................. 34
Figure 3-8 Schematic of the FIFO-like RB (example with 6 slots) .............................................. 35
Figure 3-9 Schematic of PTB and FIFO-like STB (empty PTB and 6 STB slots) ....................... 36
Figure 3-10 Loop Back Mode: Internal and External ................................................................... 39
Figure 4-1 CAN Bit Timing Specifications ................................................................................... 42
Figure 4-2 Clock Division for Bit Sampling .................................................................................. 44
Figure 4-3 Bit Rate Switching at bit BRS S _ PRESC  F _ PRESC  ................................... 46
Figure 4-4 Transmitter Delay ....................................................................................................... 46
Figure 5-1 Write Operation .......................................................................................................... 49
Figure 5-2 Read Operation .......................................................................................................... 49

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CAN-CTRL Core Users Guide

Figure 5-3 Generic 8 Bit Wide Host Interface (only relevant signals shown) .............................. 50
Figure 5-4 Write Operation with 8 Bit Host Interface ................................................................... 51
Figure 5-5 AMBA APB Wrapper (only relevant bits shown) ........................................................ 51
Figure 5-6 AMBA AHB Wrapper (only relevant bits shown) ........................................................ 52
Figure 6-1 Block Diagram ............................................................................................................ 53
Figure 7-1 CAN Multicore – Connection Options to the CAN Bus .............................................. 55
Figure 8-1 Concept of /tb/tbench.v(hd) ....................................................................................... 57
Figure 8-2 Testbench for the CAN Multicore ............................................................................... 57

List of Tables
Table 1-1 Document Version History ............................................................................................. 2
Table 2-1 CAN Bit Abbreviations ................................................................................................. 14
Table 3-1 Pin Description ............................................................................................................ 15
Table 3-2 Parameter Description ................................................................................................. 16
Table 3-3 Name Definitions ......................................................................................................... 16
Table 3-4 Register Map ............................................................................................................... 18
Table 3-5 Configuration and Status Register CFG_STAT ........................................................... 21
Table 3-6 Command Register TCMD .......................................................................................... 21
Table 3-7 Transmit Control Register TCTRL ............................................................................... 23
Table 3-8 Receive Control Register RCTRL ............................................................................... 23
Table 3-9 Receive and Transmit Interrupt Enable Register RTIE ............................................... 24
Table 3-10 Receive and Transmit Interrupt Flag Register RTIF .................................................. 24
Table 3-11 ERRor INTerrupt Enable and Flag Register ERRINT ................................................ 25
Table 3-12 Bit Timing Register BITTIME_0 ................................................................................. 25
Table 3-13 Bit Timing Register BITTIME_1 ................................................................................. 25
Table 3-14 Bit Timing Register BITTIME_2 ................................................................................. 26
Table 3-15 Bit Timing Register BITTIME_3 ................................................................................. 26
Table 3-16 Prescaler Registers S_PRESC and F_PRESC ........................................................ 26
Table 3-17 Transmitter Delay Compensation Register TDC ....................................................... 26
Table 3-18 Warning Limits Register LIMIT .................................................................................. 27
Table 3-19 Error and Arbitration Lost Capture Register EALCAP ............................................... 27
Table 3-20 Error Counter Registers RECNT and TECNT ........................................................... 27
Table 3-21 Acceptance Filter Control Register ACFCTRL .......................................................... 28
Table 3-22 Acceptance CODE ACODE_x ................................................................................... 28
Table 3-23 Acceptance MASK AMASK_x.................................................................................... 29
Table 3-24 Bits in Register ACF_3, if SELMASK=1 .................................................................... 29
Table 3-25 Acceptance Filter Enable ACF_EN_0 ........................................................................ 29
Table 3-26 Acceptance Filter Enable ACF_EN_1 ........................................................................ 29
Table 3-27 Version Information VER_1 and VER_0 .................................................................... 29
Table 3-28 Receive Buffer Registers RBUF – Standard Format (r-0) ......................................... 30
Table 3-29 Receive Buffer Registers RBUF – Extended Format (r-0) ........................................ 30
Table 3-30 Transmit Buffer Registers TBUF – Standard Format (rw-u) ...................................... 31
Table 3-31 Transmit Buffer Registers TBUF – Extended Format (rw-u) ..................................... 31
Table 3-32 Control bits in RBUF and TBUF ................................................................................ 32
Table 3-33 Definition of the DLC (according to the CAN 2.0 / FD specification) ......................... 32
Table 3-34 Software Reset .......................................................................................................... 40
Table 4-1 CAN Timing Segments (Minimum Configuration Ranges) .......................................... 43

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Table 4-2 CAN-CTRL Timing Settings (Available Configuration ranges) .................................... 43

Table 4-3 Abbreviations for Table 4-4, Table 4-5 and Table 4-6 .................................................. 47
Table 4-4 Recommendations for 20MHz can_clk ........................................................................ 47
Table 4-5 Recommendations for 40MHz can_clk ........................................................................ 47
Table 4-6 Recommendations for 80MHz can_clk ........................................................................ 48
Table 5-1 Active Byte Lanes (little endian) .................................................................................. 50
Table 5-2 AHB Signals Mapping to CAN-CTRL .......................................................................... 52
Table 9-1 Files ............................................................................................................................. 58

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CAN-CTRL Core Users Guide

1. Introduction

1.1 The CAN-CTRL Core

The CAN-CTRL core is a serial communications controller that performs serial communication according
to the CAN protocol. This CAN bus interface uses the basic CAN principle and meets all constraints of
the CAN-specification 2.0B active. Furthermore this CAN core can be configured to meet the
specification of CAN with flexible data rate CAN FD.
The CAN protocol uses a multi-master bus configuration for the transfer of frames (communication
objects) between nodes of the network and manages the error handling without any burden on the CPU.
The CAN-CTRL bus controller enables the user to set up economic and reliable links between various
components. The CAN-CTRL core appears to a microcontroller as a memory-mapped I/O device. A CPU
accesses the CAN-CTRL core to control transmission or reception of frames through a two wire CAN bus
system. The connection to a CAN bus is illustrated in Figure 1.

Figure 1-1 Connection to CAN Bus and Main Features of the CAN-CTRL Core

1.2 The CAN Protocol

CAN communication is organized in frames. Two types of frames exist: standard and extended frames.
For CAN 2.0 the maximum data payload is up to 8 bytes while for CAN FD up to 64 bytes can be
transmitted using one frame.
All CAN nodes are equal in terms of bus access. There is no super-node because the CAN is a multi-
master bus.
Data addressing is done using message identifiers. In a CAN network only one node shall transmit
messages with a certain identifier. All nodes receive all messages and the node host controller has to
decide if it was addressed by the appropriate message identifier. To reduce the load of a host controller a
CAN core may use acceptance filters. These filters compare all received message identifiers to user-
selectable bit patterns. Only if a message passes an acceptance filter, it will be signaled to the host
controller.
The identifiers of CAN frames are also used for bus arbitration. The CAN protocol machine stops
transmission of a message with a low-priority identifier when a message with a higher priority identifier is
transmitted by another CAN node. The CAN protocol machine automatically attempts to re-transmit the
stopped message at the next possible transmit position.
CAN 2.0B defines data bit rates up to 1Mbit/s. For CAN FD there is no fixed limitation. For CAN FD the
standard defines a bit rate switching. If enabled the transmission of the payload of frames can be done at
higher speed while the frame header is transmitted at lower speed.
The CAN FD frame format has been defined so that messages in CAN 2.0B format and in CAN FD
format may coexist within the same network.

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CAN-CTRL Core Users Guide

1.3 Using the CAN-CTRL Core

Chapter 10 provides a summary of the main steps on how to use the CAN-CTRL core. It can be used as
an overview during the first steps of learning how the core works as well as a summary when the main
features are understood.

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CAN-CTRL Core Users Guide

2. Features

2.1 Feature List

 Supports CAN specification
o CAN 2.0B (up to 8 bytes payload,
verified by Bosch reference model)
o Optional support for CAN FD (up to 64 bytes payload)
 Free programmable data rate:
o CAN 2.0B defines data rates up to 1Mbit/s
o CAN FD is limited by the transceiver and the clock frequency of the CAN-CTRL core.
 Programmable baud rate prescaler (1 to 1/256)
 Separate clock domains for host interface and CAN protocol machine
 Configurable receive buffer (RB) size
o Generic parameter selects number of buffer slots.
o FIFO-like behavior (based on dual-port memory)
o Received messages which are “not accepted” or “incorrect” don’t overwrite already
stored messages.
 Two Transmit Buffers
o one Primary Transmit Buffer (PTB)
o optional configurable Secondary Transmit Buffer (STB)
 The STB can be included or not. If included, a generic parameter selects the
number of buffer slots.
 FIFO-like behavior
o One dual-port memory block for PTB and STB
 Independent and programmable internal 29 bit acceptance filters
o Number of acceptance filters selectable by generic parameter in the range of 1 to 16
 Extended features
o Single Shot Transmission Mode (for PTB and / or for STB)
o Listen Only Mode
o Loop Back Mode (internal and external)
o Transceiver Standby Mode
 Extended status and error report
o Capturing of last occurred kind of error
o Capturing of arbitration lost position
o Programmable Error Warning Limit
 Different host controller interfaces
o 32 bit synchronous host controller interface; wrapper for 8 bit hosts
o AMBA APB and AHB
o Optional application specific interface to the host-controller on request.
 Configurable interrupt sources
 Fully synchronous and synthesizable HDL design (Verilog 2001, VHDL 93)

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CAN-CTRL Core Users Guide

2.2 Upward Compatibility

The CAN specification includes reserved bits (Figure 2-3) for protocol extension. This has been used to
build the CAN FD specification on top of the CAN 2.0B specification. Reserved bits are transmitted low
(dominant) if not used. Unfortunately the CAN 2.0B specification defines the behavior for the case that a
reserved bit is high (recessive) to accept this and proceed with the frame. Therefore if a CAN FD frame
(which has a different and unexpected form compared to a CAN 2.0B frame) is received by a CAN 2.0B
node that uses this behavior then this will result in an error frame by the CAN 2.0B node which destroys
the frame. This behavior is called “CAN FD intolerant”.
To be upward compatible to new protocol specifications a so-called protocol exception event shall take
place if a node detects a reserved bit high. This holds for CAN 2.0B as well as for CAN FD nodes. A
protocol exception event results in no action for a receiver. The receiver just ignores this frame, does not
generate an ACK, waits for bus idle and may transmit or receive the next frame. For a CAN 2.0B node
this is called “CAN FD tolerant” and enables coexistence of CAN 2.0B and FD frames within one
network.
Older CAN 2.0B conformance tests check for the “CAN FD intolerant” behavior but it is recommended to
use the new “CAN FD tolerant” behvaior or in general the protocol exception event to be upward
compatible regardless if the node is a CAN 2.0B or CAN FD node.
CAN-CTRL provides a generic parameter to select the behavior (chap. 3.2, parameter
UPWARD_COMPATIBILITY).

2.3 Message Buffers

2.3.1 Message Buffers Concept

The concept of the message buffers is illustrated in Figure 2-1. This schematic focuses on the buffers
and hides other details of the CAN-CTRL core. All buffer slots are big enough to store frames with the
maximum length.

Figure 2-1 Message Buffers Concept

2.3.2 Receive Buffer

To reduce the load of received frames for the host controller, the core uses acceptance filters. The CAN-
CTRL core checks the message identifier during acceptance filtering. If the received frame matches the
filter criteria of one of the acceptance filters then it will be stored in the Receive Buffer (RB), which has
FIFO-like behavior.
Depending on the number of available message slots, the host controller does not need to read incoming
messages immediately. The CAN-CTRL core is able to generate interrupts upon every received

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CAN-CTRL Core Users Guide

message, when the RB is full or filled to a user-selectable “almost full” limit. Because of the FIFO-like
behavior, the host controller always reads the oldest message from the RB.

2.3.3 Transmit Buffer

For frame transmission purposes, two Transmit Buffers (TB) are offered. The Primary TB (PTB) has a
higher priority, but is able to buffer only one frame. The Secondary TB (STB) has a lower priority, but
FIFO-like behavior. The priority decision between PTB and STB is fixed and fully independent from the
CAN bus arbitration. Bus arbitration is a priority decision based on the frame identifiers.
The STB can be commanded to transmit one or all stored frames. With every transmission, the oldest
frame is transmitted first.
A frame located in the PTB has always a higher priority for the CAN protocol machine than the frames in
the STB regardless of the frame identifiers. A PTB transmission stops and delays an STB transmission.
The STB transmission is automatically restarted after the PTB frame has been successfully transmitted.
A PTB transmission starts at the next transmit position that is possible by the CAN protocol (after the
next interframe space). Because of this, an STB transmission that has won the arbitration and is actually
transmitted, will be completed before.
Interrupting STB transmissions using a PTB transmission may happen in the following cases:
1. The STB is commanded to output all stored frames and the host controller decides to command
a PTB transmission before all STB transmissions are completed.
2. The STB is commanded to output a single frame and the host controller decides to command a
PTB transmission before the STB transmission is completed.
If the host controller waits until each commanded transmission is completed, then it can easily decide
which buffer shall transmit the next frame. As a drawback a message with a low-priority identifier may
block more important messages. Then the host could abort the message (chap. 2.3.5 ).
Both PTB and STB are mapped to one dual-port memory.

2.3.4 Transmit Buffer Application Example

A CAN node is used for sensor measurements. The CAN system engineer has decided to handle these
sensor measurements with low priority. Therefore frame identifiers with low priority are used for CAN
frames carrying the sensor data.
The host controller automatically acquires measurement results and places them as CAN frames in the
STB. Because of high traffic at the CAN bus, it may happen that the sensor data frames cannot be
transmitted immediately and several frames remain in the STB. Later, if there is less traffic at the CAN
bus, they will be transmitted.
In the situation where several frames remain in the STB, an event may happen that forces the host
controller to output an important high-priority frame. In such a situation, the host can use the PTB. A
frame in the PTB will be always transmitted before all frames in the STB.
The advantage of having two transmit buffers is the option to keep all messages. No message has to be
aborted (discarded) in case of a high-priority event.

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CAN-CTRL Core Users Guide

Figure 2-2 Transmit Buffer Application Example (TSALL=1)

The given application example is explained step by step in Figure 2-2. In this figure, LPF_x is the
abbreviation of “low priority frame” and HPF means “high priority frame”. As can be seen, LPF_1 is
blocked by other higher priority frames from other CAN nodes in the first part of the figure. The host
controller puts a fourth frame into the STB (LPF_4) and then decides to output the HPF. Meanwhile, the
CAN bus was free to transmit LPF_1 which is followed by HPF, LPF_2 and so on.
The priority decision between the PTB and STB is done by the CAN protocol machine, but the CAN
protocol itself uses another independent priority decision mechanism which is called bus arbitration. For
bus arbitration the frame identifier defines the priority level.
In the example given above, it would be possible to place a frame with a very low-priority identifier in the
PTB while higher priority frames remain in the STB. For the decision between PTB and STB always the
PTB wins regardless of the frame identifier. It is the task of the host controller to place frames with
meaningful identifier priorities in the appropriate buffers.

2.3.5 Aborting a Transmission

If the situation arises, where a message in a transmit buffer cannot be sent due to its low priority, this
would block the buffer for a long time. In order to avoid this, the host controller can withdraw the
transmission request and abort the message. Aborting is possible for PTB and STB as well as for single
or all frame transmission.

2.4 CAN 2.0 and CAN FD Frames

CAN FD is a protocol extension of CAN 2.0. The main differences are:
 Data payload: Up to 8 bytes for CAN 2.0 and up to 64 bytes for CAN FD
 One configurable bit rate for CAN 2.0, but 2 for CAN FD: slow for arbitration and fast for data
phase
All types of frames for CAN 2.0 and CAN FD are shown in Figure 2-3. The abbreviations are explained in
the CAN specification and in short in Table 2-1. For Classic CAN frames (CAN 2.0) some bit names are
renamed with the CAN FD ISO specification, but here the older names are still used for easier backward-
reference.

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CAN-CTRL Core Users Guide

Figure 2-3 CAN 2.0 and CAN FD Frame Types

Table 2-1 CAN Bit Abbreviations

Abbreviation Description Comment

ID IDentifier
RTR Remote Transmission Request Remote or Data frame
SRR Substitute Remote Request
RRS Remote Request Substitution
IDE IDentifier Extension Standard or Extended frame
DLC Data Length Code Number of payload bytes
EDL Extended Data Length CAN 2.0 or CAN FD frame
FDF FD Format indicator (=EDL) CAN 2.0 or CAN FD frame
BRS Bit Rate Switch
ESI Error State Indicator
r1, r0, res Reserved bits

The CAN FD specification by Bosch (non-ISO) uses the name EDL while the CAN FD ISO specification
uses the name FDF for the same bit. Both names are synonyms. This document uses the name EDL.
For CAN FD ISO frames the stuff count is transmitted as a part of the CRC field. For CAN FD non-ISO
frames the stuff count is not part of the frame. Therefore ISO and non-ISO frames are incompatible.
The CAN protocol machine in the CAN-CTRL core automatically transmits and receives the frames and
embeds the appropriate control and status bits. The host controller is required to select the desired frame
type (IDE, RTR, EDL), chose the identifier and set the data payload.

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3. Interfaces

3.1 Hardware Interface

This chapter describes the core interface of CAN-CTRL. Additionally several interface wrappers are
provided that connect this core interface to different host interfaces. Details about these wrappers can be
found in chap. 5.

Figure 3-1 CAN-CTRL Core Pinout

Table 3-1 Pin Description

Name Type Polarity Description

host_rst_b I Low asynchronous reset for host interface
host_clk I - clock for host interface
host_adr I - 6-bit address from host
host_di I - 32 bit data from host
host_do O - 32 bit data to the host
host_cs_b I Low chip select
host_rd_b I Low read control
host_wr_b I Low write control
host_rstrb I High 4 bit read strobe (select bytes to be read)
host_wstrb I High 4 bit write strobe (selects bytes to be written)
host_irq O High interrupt to the host
can_rst_b I Low asynchronous reset for CAN protocol machine
can_clk I - clock for CAN protocol machine
receive data from bus – input signal from the transceiver IC (signals the bit
rxd I -
level on the CAN bus)
transmit data to the bus – output signal to the transceiver IC (transmits bit to
txd O -
the CAN bus)
stby O High Transceiver Standby Mode Enable
CAN FD conformance can be enabled (1) or disabled (0) at runtime if the
necessary hardware is included by setting the parameter CAN_FD to 1 (Table
can_fd_enable I High
3-2). This input should stay unchanged as long a bit RESET in register
CFG_STAT is 0 (inactive).
test signal – shows the used sample points (activated one period after the
tst_sample O -
sample point).
test signal – shows the used bit time periods (activated one period before the
tst_clock O -
bit time starts)
reccnt O - 8-bit Receive Error Counter (for test purposes)
trcnt O - 9-bit Transmit Error Counter (for test purposes)

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The master resets can_rst_b and host_rst_b are asynchronous resets. It is recommended to use reset
synchronizers for these signals for protection against recovery and removal timing issues. This core does
not include such reset synchronizers. They should be added outside of the core.
CAN-CTRL includes two clock domains: one for the host interface and one for the CAN protocol
machine. All signals between the two clock domains are synchronized and should be declared as false
paths during synthesis. All top-level I/O signals in the host clock domain are named with the prefix
“host_”. It is possible to use the same clock for both clock inputs can_clk and host_clk.
For CAN FD operation the clock for the CAN protocol machine can_clk shall be set to 20MHz, 40MHz or
80MHz. This is a general recommendation for all CAN FD nodes. Further details are given in chap. 4.6.

3.2 Configuration Parameters

The CAN-CTRL core is configurable before synthesis. Several parameters can be chosen as defined in
Table 3-2. Synthesis parameters are located in the source files can_package_synparam.vhd /
can_package_synparam.v in the src directory. Beside these selectable parameters, various other
definitions are located in the files can_package.vhd / can_package.v, but these other shall not be
changed. Comments are given inside the package for clarification.
Table 3-2 Parameter Description

Parameter Range Description

Number of slots in the receive buffer
RBUF_SLOTS >0 Please note, that the core always uses one more (hidden) slot as
defined with RBUF_SLOTS, which is used to receive a new message
while the receive buffer is full and has not been released yet.
RBUF_MEMTYPE 1 to 2 Type of RBUF memory: Block RAM (1) or Distributed RAM (0)
PTB_MEMTYPE 1 to 2 Type of PTB memory: Block RAM (1) or Distributed RAM (0)
0 – STB_SLOTS defines the number of STB message slots
STB_DISABLE 0 to 1
1 – no STB included, STB_SLOTS ignored
STB_SLOTS >0 Number of slots in the secondary transmit buffer (STB)
STB_MEMTYPE 1 to 2 Type of STB memory: Block RAM (1) or Distributed RAM (0)
ACF_NUMBER 1 to 16 Number of acceptance filters (ACF)
ACF_MEMTYPE 1 to 2 Type of ACF memory: Block RAM (1) or Distributed RAM (0)
0 – only CAN 2.0B conformance
CAN_FD 0 to 1
1 – CAN FD conformance (an extension of CAN 2.0B)
0 – no protocol upward compatibility
UPWARD_COMPATIBILITY 0 to 1
1 – upward compatibility: protocol exception event (recommended)

3.3 Definitions
Table 3-3 Name Definitions

Abbreviation Description
ACF Acceptance Filter
PTB Primary Transmit Buffer (high priority)
RB Receive Buffer
RDC Receiver Delay Compensation (related to TDC)
SP Sample Point
SSP Secondary Sample Point (CAN FD)
STB Secondary Transmit Buffer (low priority)
TDC Transmitter Delay Compensation (CAN FD specification)
TQ Time Quanta (CAN specification)

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All register definitions are given including an access definition. Access definitions are given using an
abbreviation in the form <access>-<reset>. Possible abbreviations for the <access> attribute are “r” for
read, “w” for write and “rw” for read/write access. The <reset> attribute can be “0”, “1” and “u” for
uninitialized registers. Example: “rw-0” means “readable and writeable and reset to 0” while “r-u” means
“readable and uninitialized”. Unused bits are always r-0.

3.4 Clock Domain Crossing

Figure 3-2 Clock Domain Crossing

The core uses two clock domains: one for the host interface and one for the CAN protocol machine. This
enables the option to operate the CAN protocol machine with a clock that fits for the desired CAN bus
data rates best while the host is free to operate at a different (higher) clock speed.
The host interface as well as optional host interface wrappers (e.g. for AMBA busses) operate in the host
clock domain. This includes all memories and registers that are accessible using the host data bus
(chap. 3.5). Clock Domain Crossing (CDC) is done with double-buffered synchronizers and bi-directional
handshake mechanisms. The following gives some details about the CDC:
 Control and status registers are moved to the appropriate clock domain individually. E.g. interrupt
flags use a bi-directional handshake while status registers use unidirectional synchronizers.
 Acceptance filters are copied to the CAN clock domain during startup when bit RESET becomes
inactive. Copying the acceptance filters will be finished when the CAN node takes part in the
communication after the bus idle time.
 Received frames are stored in a small temporary reception buffer. This temporary buffer holds
only parts of the frames and these parts are copied to RBUF when necessary.
 Frames to be transmitted are copied step-by-step from the TBUF to a small temporary transmit
buffer.
Using synchronizers and handshake mechanisms results in some latency. Up to 3 clocks in each domain
are required for a bi-directional handshake. But in most cases for the host controller this will not be
problem.

3.5 Software Interface

CAN-CTRL has been initially developed as peripheral component for 8 bit systems and therefore control
and status registers defined as 8 bit groups (Table 3-4). Nevertheless CAN-CTRL is a 32 bit component
and offers downward-compatible interfaces for 8 and 16 bit hosts. The mapping of the registers for 8 / 16
/ 32 host interfaces is shown in Figure 3-3. Chapter 5 provides details about the various host interfaces.

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Table 3-4 Register Map

Bit position Register name

7 6 5 4 3 2 1 0
0x00
to Receive Buffer Registers RBUF
0x47
0x48
to Transmit Buffer Registers TBUF
0x8f
0x90 RESET LBME LBMI TPSS TSSS RACTIVE TACTIVE BUSOFF CFG_STAT
0x91 TBSEL LOM STBY TPE TPA TSONE TSALL TSA TCMD
0x92 FD_ISO TSNEXT - TSSTAT(1:0) TCTRL
0x93 - - ROV RREL - - RSTAT(1:0) RCTRL
0x94 RIE ROIE RFIE RAFIE TPIE TSIE EIE TSFF RTIE
0x95 RIF ROIF RFIF RAFIF TPIF TSIF EIF AIF RTIF
0x96 EWARN EPASS EPIE EPIF ALIE ALIF BEIE BEIF ERRINT
0x97 AFWL(3:0) EWL(3:0) LIMIT
0x98 - S_Seg_1(5:0) BITTIME_0
*)

0x99 F_Seg_2(2:0) S_Seg_2(4:0) BITTIME_1

*)

0x9a F_Seg_1(3:0) S_SJW(3:0) BITTIME_2

*)

0c9b - F_SJW(2:0) BITTIME_3

*)

0x9c S_PRESC(7:0) S_PRESC

*)

0x9d F_PRESC(7:0) F_PRESC

*)

0x9e TDCEN - - SSPOFF(4:0) TDC

*)

0x9f - -
0xa0 KOER(2:0) ALC(4:0) EALCAP
0xa1 - -
0xa2 RECNT RECNT
0xa3 TECNT TECNT
0xa4 - - SELMASK - ACFADR ACFCTRL
*)

0xa5 - -
0xa6 AE_7 AE_6 AE_5 AE_4 AE_3 AE_2 AE_1 AE_0 ACF_EN_0
0xa7 AE_15 AE_14 AE_13 AE_12 AE_11 AE_10 AE_9 AE_8 ACF_EN_1
0xa8 ACODE_x or AMASK_x (7:0) ACF_0
*)

0xa9 ACODE_x or AMASK_x (15:8) ACF_1

*)

0xaa ACODE_x or AMASK_x (23:16) ACF_2

*)

0xab - AIDEE AIDE ACODE_x or AMASK_x (28:24) ACF_3

*)

0xac VERSION(7:0) VER_0

0xad VERSION(15:8) VER_1
0xae - -
0xaf - -
*)
register can only be written if bit RESET in register CFG_STAT is set.
An write access to an addressable location not shown in the register map (Table 3-4) results in no action
and a read access will result in the value 0x00.
Register addresses are given as an example. They can be selected using generic parameters before
synthesis. The example shows the default setting. The example for 8 / 16 / 32 hosts in Figure 3-3
assumes that every byte is addressable even if the host uses a wider native width.

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Please mind the several gaps inside the register map. This is for better address segment alignment for a
wider host controller interface.
Please have in mind that configuration registers that are only for CAN FD cannot be used if the IP core is
reduced to only CAN 2.0B capability. Then these registers are tied to their reset values.

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Figure 3-3 Memory Map for 8 / 16 / 32 Bit Interface

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Table 3-5 Configuration and Status Register CFG_STAT

Bits Name Access Function

RESET request bit
1- The host controller performs a local reset of CAN-CTRL.
0- no local reset of CAN-CTRL
The node configuration (BITTIME_x, x_PRESC, acceptance code and mask) can only be
modified if RESET=1. The CAN-CTRL core continuously listens on the bus. Wrong timings and
acceptance filters may result in unpredictable and unwanted behavior. Therefore these
parameters can only be changed if the protocol machine is reset and therefore disconnected
from the bus.
7 RESET rw-1
Bit RESET forces several components to a reset state. A detailed definition is given in chap.
3.6.10 . RESET is automatically set if the node enters “bus off” state (chap. 3.6.1 ).
Note that a CAN node will participate in CAN communication after RESET is switched to 0
after 11 CAN bit times. This delay is required by the CAN standard.
If RESET is set to 1 and immediately set to 0, then it takes some time until RESET can be
read as 0 and becomes inactive. The reason is clock domain crossing from host to CAN clock
domain. RESET is held active as long as needed depending on the relation between host and
CAN clock.
Loop Back Mode, External
0- Disabled
6 LBME rw-0
1- Enabled
LBME should not be enabled while a transmission is active.
Loop Back Mode, Internal
0- Disabled
5 LBMI rw-0
1- Enabled
LBMI should not be enabled while a transmission is active.
Transmission Primary Single Shot mode for PTB
4 TPSS rw-0 0- Disabled
1- Enabled
Transmission Secondary Single Shot mode for STB
3 TSSS rw-0 0- Disabled
1- Enabled
Reception ACTIVE (Receive Status bit)
2 RACTIVE r-0 1- The controller is presently receiving data or a remote frame.
0- No receive activity.
Transmission ACTIVE (Transmit Status bit)
1 TACTIVE r-0 1- The controller is presently transmitting data or a remote frame.
0- No transmit activity.
Bus Off (Bus Status bit)
1- The controller status is “bus off”.
0 BUSOFF r-0
0- The controller status is “bus on”.
See detailed description in chap. 3.6.1 .

Table 3-6 Command Register TCMD

Bits Name Access Function

Transmit Buffer Select
Selects the transmit buffer to be loaded with a message. Use the TBUF registers for
access. TBSEL needs to be stable all the time the TBUF registers are written and when
7 TBSEL rw-0
TSNEXT is set.
0- PTB (high-priority buffer)
1- STB (FIFO like)
Listen Only Mode
0- Disabled
6 LOM rw-0 1- Enabled
LOM should not be enabled while a transmission is active. No transmission can be started
if LOM is enabled.
Transceiver Standby Mode
0- Disabled
1- Enabled
5 STBY rw-0
This register bit is connected to the output signal stby which can be used to control a
standby mode of a transceiver.
STBY cannot be set to 1 if TPE=1, TSONE=1 or TSALL=1.

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Bits Name Access Function

If the host sets STBY to 0 then the host needs to wait for the time required by the
transceiver to start up before the host requests a new transmission.
Transmit Primary Enable
1- Transmission enable of the message of the high-priority PTB
0- No transmission for the PTB
If TPE is set, the message from the PTB will be transmitted at the next possible transmit
position. A started transmission from the STB will be completed before, but pending new
messages are delayed until the PTB message has been transmitted.
TPE stays set until the message has been transmitted successfully or it is aborted using
4 TPE rw-0
TPA. Only, the host controller can set TPE.
The host controller can set TPE to 1 but can not reset it to 0. This would only be possible
using TPA and aborting the message.
During the short time while the CAN-CTRL core resets the bit, it cannot be set by the
host.
The bit will be reset to the hardware reset value if RESET=1, BUSOFF=1, STBY=1 or
LOM=1.
Transmit Primary Abort
1– Aborts a transmission from TPB which has been requested by TPE=1 but not
started yet.
(The data bytes of the message remain in the PTB.)
0– no abort
The bit has to be set by the host controller and will be reset by CAN-CTRL. Setting TPA
3 TPA rw-0
automatically de-asserts TPE.
The host controller can set TPA to 1 but can not reset it to 0.
During the short time while the CAN-CTRL core resets the bit, it cannot be set by the
host.
The bit will be reset to the hardware reset value if RESET=1 or BUSOFF=1.
TPA should not be set simultaneously with TPE.
Transmit Secondary ONE frame
1– Transmission enable of the oldest message in the STB.
The message format is stored in the IDE buffer which belongs to this message.
The controller starts the transmission as soon as the bus becomes vacant and
no request of the PTB (bit TPE) is pending.
0– No transmission for the STB.
TSONE stays set until the message has been transmitted successfully or it is aborted
2 TSONE rw-0
using TSA. Only the host controller can set TSONE.
The host controller can set TSONE to 1 but can not reset it to 0. This would only be
possible using TSA and aborting the message.
During the short time while the CAN-CTRL core resets the bit, it cannot be set by the
host.
The bit will be reset to the hardware reset value if RESET=1, BUSOFF=1, STBY=1 or
LOM=1.
Transmit Secondary ALL frames
1– Transmission enable of all messages in the STB.
The message format is stored in the appropriate IDE buffers.
The controller starts the transmission as soon as the bus becomes vacant and
no request of the PTB (bit TPE) is pending.
0– No transmission for the STB.
TSALL stays set until all messages have been transmitted successfully or they are aborted
using TSA. Only the host controller can set TSALL.
The host controller can set TSALL to 1 but can not reset it to 0. This would only be
1 TSALL rw-0
possible using TSA and aborting the messages.
During the short time while the CAN-CTRL core resets the bit, it cannot be set by the
host.
The bit will be reset to the hardware reset value if RESET=1, BUSOFF=1, STBY=1 or
LOM=1.
If during a transmission the STB is loaded with a new frame then the new frame will be
transmitted too. In other words: a transmission initiated by TSALL is finished when the
STB becomes empty.
TSALL cannot ne set to 1 if STBY=1.
Transmit Secondary Abort
1– Aborts a transmission from STB which has been requested but not started yet.
0 TSA rw-0
For a TSONE transmission, only one frame is aborted while for a TSALL
Transmission, all frames are aborted.

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Bits Name Access Function

One or all message slots will be released which updates TSSTAT. Because of
the FIFO-like behavior of the STB all aborted messages are lost because they
are not accessible any more.
0– no abort
The bit has to be set by the host controller and will be reset by CAN-CTRL. Setting TSA,
automatically de-asserts TSONE or TSALL respectively.
The host controller can set TSA to 1 but can not reset it to 0.
The bit will be reset to the hardware reset value if RESET=1 or BUSOFF=1.
TSA should not be set simultaneously with TSONE or TSALL.

Setting both TSONE and TSALL is meaningless. While TSALL is already set, it is impossible to set
TSONE and vice versa. If both TSONE and TSALL are set simultaneously then TSALL wins and TSONE
is cleared by the CAN-CTRL core.

Table 3-7 Transmit Control Register TCTRL

Bits Name Access Function

CAN FD ISO mode
0- Bosch CAN FD (non-ISO) mode
1- ISO CAN FD mode
7 FD_ISO rw-1 This bit is only writeable if RESET=1.
ISO CAN FD mode has a different CRC initialization value and an additional stuff bit count.
Both modes are incompatible and must not be mixed in one CAN network.
This bit has no impact to CAN 2.0B.
Transmit buffer Secondary NEXT
0- no action
1- STB slot filled, select next FIFO slot.
After all frame bytes are written to the TBUF registers, the host controller has to set
TSNEXT to signal that this slot has been filled. Then the CAN-CTRL core connects the TBUF
registers to the next FIFO slot. Once a slot is marked as filled a transmission can be started
6 TSNEXT rw-0 using TSONE or TSALL.
It is possible to set TSNEXT and TSONE or TSALL together in one write access.
TSNEXT has to be set by the host controller and is automatically reset by the CAN-CTRL
core immediately after it was set.
Setting TSNEXT is only meaningful, if the STB is selected by TBSEL=1. If TBSEL=0 then
TSNEXT is ignored and automatically cleared. It does not do any harm.
If all slots of the STB are filled, TSNEXT stays set until a slot becomes free (chap. 3.6.7 ).
5:2 - r-0 reserved
Transmission Secondary STATus bits
00 – STB is empty
01 – STB is less than or equal to half full
1:0 TSSTAT r-0
10 – STB is more than half full
11 – STB is full
If the STB is disabled using STB_DISABLE, then TSSTAT=00.

Table 3-8 Receive Control Register RCTRL

Bits Name Access Function

7:6 - r-0 reserved
Receive buffer OVerflow
1– Overflow. At least one message is lost.
5 ROV r-0
0– No Overflow.
ROV is cleared by setting RREL=1.
Receive buffer RELease
The host controller acknowledges the emptying of the actual RB slot. Afterwards the CAN-
4 RREL rw-0 CTRL core points to the next RB slot. RSTAT gets updated.
1– Release: The host has emptied the RB.
0– No release
3:2 - r-0 reserved
1:0 RSTAT r-0 Receive buffer STATus

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Bits Name Access Function

00 - empty
01 - > empty and < almost full (AFWL)
10 -  almost full (programmable threshold by AFWL) but not full and no overflow
11 - full (stays set in case of overflow – for overflow signaling see ROV)

Table 3-9 Receive and Transmit Interrupt Enable Register RTIE

Bits Name Access Function

Receive Interrupt Enable
7 RIE rw-1
0 – Disabled, 1 – Enabled
RB Overrun Interrupt Enable
6 ROIE rw-1
0 – Disabled, 1 – Enabled
RB Full Interrupt Enable
5 RFIE rw-1
0 – Disabled, 1 – Enabled
RB Almost Full Interrupt Enable
4 RAFIE rw-1
0 – Disabled, 1 – Enabled
Transmission Primary Interrupt Enable
3 TPIE rw-1
0 – Disabled, 1 – Enabled
Transmission Secondary Interrupt Enable
2 TSIE rw-1
0 – Disabled, 1 – Enabled
Error Interrupt Enable
1 EIE rw-1
0 – Disabled, 1 – Enabled
Transmit Secondary buffer Full Flag
1- The STB is filled with the maximal count of messages.
0 TSFF r-0
0- The STB is not filled with the maximal count of messages
If the STB is disabled using STB_DISABLE, then TSFF=0.

Table 3-10 Receive and Transmit Interrupt Flag Register RTIF

Bits Name Access Function

Receive Interrupt Flag
7 RIF rw-0 1- Data or a remote frame has been received and is available in the receive buffer.
0- No frame has been received.
RB Overrun Interrupt Flag
1- At least one received message has been overwritten in the RB.
6 ROIF rw-0
0- No RB overwritten.
In case of an overrun both ROIF and RFIF will be set.
RB Full Interrupt Flag
1- All RBs are full. If no RB will be released until the next valid message is received,
5 RFIF rw-0
the oldest message will be lost.
0- The RB FIFO is not full.
RB Almost Full Interrupt Flag
4 RAFIF rw-0 1- number of filled RB slots  AFWL_i
0- number of filled RB slots < AFWL_i
Transmission Primary Interrupt Flag
3 TPIF rw-0 1- The requested transmission of the PTB has been successfully completed.
0- No transmission of the PTB has been completed.
Transmission Secondary Interrupt Flag
2 TSIF rw-0 1- The requested transmission of the STB has been successfully completed.
0- No transmission of the STB has been completed successfully.
Error Interrupt Flag
1- The border of the error warning limit has been crossed in either direction,
1 EIF rw-0
or the BUSOFF bit has been changed in either direction.
0- There has been no change.
Abort Interrupt Flag
1- After setting TPA or TSA the appropriated message(s) have been aborted.
It is recommended to not set both TPA and TSA simultaneously because both
0 AIF rw-0 source AIF.
0- No abort has been executed.
The AIF does not have an associated enable register.
See also chap. 3.6.6 for further information.

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To reset an interrupt flag, the host controller needs to write an 1 to the flag. Writing a 0 has no effect. If a
new interrupt event occurs while the write access is active then this event will set the flag and override
the reset. This ensures that no interrupt event is lost.

Table 3-11 ERRor INTerrupt Enable and Flag Register ERRINT

Bits Name Access Function

Error WARNing limit reached
7 EWARN r-0 1- One of the error counters RECNT or TECNT is equal or bigger than EWL
0- The values in both counters are less than EWL.
Error Passive mode active
6 EPASS r-0 0- not active (node is error active)
1- active (node is error passive)
5 EPIE rw-0 Error Passive Interrupt Enable
Error Passive Interrupt Flag. EPIF will be activated if the error status changes from error
4 EPIF rw-0
active to error passive or vice versa and if this interrupt is enabled.
3 ALIE rw-0 Arbitration Lost Interrupt Enable
2 ALIF rw-0 Arbitration Lost Interrupt Flag
1 BEIE rw-0 Bus Error Interrupt Enable
0 BEIF rw-0 Bus Error Interrupt Flag

To reset an interrupt flag, the host controller needs to write an 1 to the flag. Writing a 0 has no effect. If a
new interrupt event occurs while the write access is active then this event will set the flag and override
the reset. This ensures that no interrupt event is lost.

Table 3-12 Bit Timing Register BITTIME_0

Bits Name Access Function

7:6 - r-0 reserved
Bit Timing Segment 1 (slow speed)
5:0 S_Seg_1(5:0) rw-0x3 The sample point will be set to tSeg_1  Seg_1  2  TQ after start of bit time.
S_Seg_1=0 is meaningless and automatically treated as 1.

Table 3-13 Bit Timing Register BITTIME_1

Bits Name Access Function

Bit Timing Segment 2 (fast speed)
7:5 F_Seg_2(2:0) rw-0x2 Time tSeg_2  Seg_2  1  TQ after the sample point.
F_Seg_2=0 is meaningless and automatically treated as 1.
Bit Timing Segment 2 (slow speed)
4:0 S_Seg_2(4:0) rw-0x2 Time tSeg_2  Seg_2  1  TQ after the sample point.
S_Seg_2=0 is meaningless and automatically treated as 1.

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Table 3-14 Bit Timing Register BITTIME_2

Bits Name Access Function

Bit Timing Segment 1 (fast speed)
7:4 F_Seg_1(3:0) rw-0x3 The sample point will be set to tSeg_1  Seg_1  2  TQ after start of bit time.
Setting F_Seg_1=0 is possible.
Synchronization Jump Width (slow speed)

3:0 S_SJW(3:0) rw-0x2

The Synchronization Jump Width tSJW  SJW  1  TQ is the maximum time for
shortening or lengthening the Bit Time for resynchronization, where TQ is a time
quanta.

Table 3-15 Bit Timing Register BITTIME_3

Bits Name Access Function

7:3 - r-0 reserved
Synchronization Jump Width (fast speed)
The Synchronization Jump Width tSJW  SJW  1  TQ is the maximum time for
2:0 F_SJW(2:0) rw-02
shortening or lengthening the Bit Time for resynchronization, where TQ is a time
quanta.

Table 3-16 Prescaler Registers S_PRESC and F_PRESC

Bits Name Access Function

Prescaler (slow and fast speed)
S_PRESC
7:0 rw-0x01 The prescaler divides the system clock to get the time quanta clock tq_clk.
F_PRESC
Valid range PRESC=[0x00, 0xff] results in divider values 1 to 256.

Table 3-17 Transmitter Delay Compensation Register TDC

Bits Name Access Function

Transmitter Delay Compensation ENable
7 TDCEN rw-0 TDC will be activated during the data phase of a CAN FD frame if BRS is active if TDCEN=1.
For more details about TDC see chap. 4.5.
6:5 - r-0 Reserved
Secondary Sample Point OFFset
4:0 SSPOFF rw-0x00 The transmitter delay plus SSPOFF defines the time of the secondary sample point for TDC.
SSPOFF is given as a number of TQ.

Writing to BITTIME_0, BITTIME_1, BITTIME_2, S_PRESC, F_PRESC and TDC is only possible if
RESET=1. A detailed description of the CAN bus bit timing is given in chap. 4. The reset value sets the
bit timing which is described in the example in chap. 4.3.
All timing parameters in are given for slow (prefix “S_”) and fast speed (prefix “F_”). Slow speed is used
for CAN 2.0 and the CAN FD arbitration phase. Fast speed is used for the CAN FD data phase.

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Table 3-18 Warning Limits Register LIMIT

Bits Name Access Function

receive buffer Almost Full Warning Limit
AFWL defines the internal warning limit AFWL_i with nRB being the number of available
RB slots.
 AFWL nRB  16

2  AFWL 16  nRB  32
AFWL_i  
4  AFWL 32  nRB  64
7:4 AFWL(3:0) rw-0x1   
AFWL_i is compared to the number of filled RB slots and triggers RAFIF if equal. The
valid range of AFWL_i  1nRB .
AFWL  0 is meaningless and automatically treated as 0x1.
(Note that AFWL is meant in this rule and not AFWL_i.)
AFWL_i  nRB is meaningless and automatically treated as nRB .
AFWL_i  nRB is a valid value, but note that RFIF also exists.
Programmable Error Warning Limit = (EWL+1)*8. Possible Limit values: 8, 16, … 128.
The value of EWL controls EIF.
3:0 EWL(3:0) rw-0xB
EWL needs to be transferred using CDC from host to CAN clock domain. During transfer
EWL register bits are write-locked for the host for a few clocks until CDC is complete.

Table 3-19 Error and Arbitration Lost Capture Register EALCAP

Reset
Bits Name Function
Value
Kind OfERror (Error code)
000 - no error
001 - BIT ERROR
010 - FORM ERROR
011 - STUFF ERROR
100 - ACKNOWLEDGEMENT ERROR
7:5 KOER(2:0) r-0x0
101 - CRC ERROR
110 - OTHER ERROR
(dominant bits after own error flag, received active Error Flag too long,
dominant bit during Passive-Error-Flag after ACK error)
111 - not used
KOER is reset after a successful transmission or reception of a frame.
4:0 ALC(4:0) r-0x0 Arbitration Lost Capture (bit position in the frame where the arbitration has been lost)

Table 3-20 Error Counter Registers RECNT and TECNT

Bits Name Access Function
Receive Error CouNT (number of errors during reception)
RECNT is incremented and decremented as defined in the CAN specification.
7:0 RECNT r-0x00
RECNT does not overflow. RECNT signals 0xff = 255 as maximum value. See chap. 3.6.1
for more details about RECNT and the “bus off” state.
Transmit Error CouNT (number of errors during transmission)
TECNT is incremented and decremented as defined in the CAN specification.
7:0 TECNT r-0x00
TECNT does not overflow. TECNT signals 0xff = 255 as maximum value. See chap. 3.6.1
for more details about TECNT and the “bus off” state.

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Table 3-21 Acceptance Filter Control Register ACFCTRL

Bits Name Access Function

7:6 - r-0 reserved
SELect acceptance MASK
0- Registers ACF_x point to acceptance code
5 SELMASK rw-0
1- Registers ACF_x point to acceptance mask.
ACFADR selects one specific acceptance filter. (See Figure 3-4.)
4 - r-0 Reserved
acceptance filter address
ACFADR points to a specific acceptance filter. The selected filter is accessible using the
registers ACF_x. Bit SELMASK selects between acceptance code and mask for the
3:0 ACFADR rw-0
selected acceptance filter. (See Figure 3-4.)
A value of ACFADR>NR_OF_ACF-1 is meaningless and automatically treated as value
NR_OF_ACF-1. (See chap. 0 and Figure 3-4 for details about NR_OF_ACF.)

The acceptance filter registers ACF_x provide access to the acceptance filter codes ACODE_x and
acceptance filter masks AMASK_x depending on the setting of SELMASK. (See Figure 3-4 and also
Table 3-4). Read / Write access to ACF_x is only possible if RESET=1. If RESET=0 then reading from
ACF_x results in the value 0.

Figure 3-4 Access to the Acceptance Filters

Table 3-22 Acceptance CODE ACODE_x

Bits Name Access Function
Acceptance CODE
1- ACC bit value to compare with ID bit of the received message
0- ACC bit value to compare with ID bit of the received message
ACODE_0 rw-0x00
7:0 ACODE_x(10:0) will be used for extended frames.
ACODE_x rw-u
ACODE_x(28:0) will be used for extended frames.
Only filter 0 is affected by the power-on reset. All other filters stay uninitialized.
See chap. 3.6.2 for further details.

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Table 3-23 Acceptance MASK AMASK_x

Bits Name Access Function
Acceptance MASK
1- acceptance check for these bits of receive identifier disabled
0- acceptance check for these bits of receive identifier enable
AMASK_x(10:0) will be used for extended frames.
AMASK_0 rw-0xFF
7:0 AMASK_x(28:0) will be used for extended frames.
AMASK_x rw-u
Disabled bits result in accepting the message. Therefore the default configuration after
reset for filter 0 accepts all messages.
Only filter 0 is affected by the power-on reset. All other filters stay uninitialized.
See chap. 3.6.2 for further details.

The AMASK_x includes additional bits in register ACF_3 (Table 3-24) which can be only accessed if
SELMASK=1. These bits can be used to accept only either standard or extended frames with the
selected ACODE / AMASK setting or to accept both frame types. Only acceptance filter 0 is affected by
the power-on reset and it is configured to accept both frame types after power-up.
Table 3-24 Bits in Register ACF_3, if SELMASK=1
Bits Name Access Function
Acceptance mask IDE bit check enable
rw-0 1- acceptance filter accepts either standard or extended as defined by AIDE
1 AIDEE
rw-u 0- acceptance filter accepts both standard or extended frames
Only filter 0 is affected by the power-on reset. All other filters stay uninitialized.
Acceptance mask IDE bit value
If AIDEE=1 then:
rw-0
0 AIDE 1- acceptance filter accepts only extended frames
rw-u
0- acceptance filter accepts only standard frames
Only filter 0 is affected by the power-on reset. All other filters stay uninitialized.

Table 3-25 Acceptance Filter Enable ACF_EN_0

Bits Name Access Function
Acceptance filter Enable
1- acceptance filter enabled
0- acceptance filter disable
Each acceptance filter (AMASK / ACODE) can be individually enabled or disabled. Only
filter number 0 is enabled by default after hardware reset.
7:0 AE_x rw-0x01
Disabled filters reject a message. Only enabled filters can accept a message if the
appropriate AMASK / ACODE configuration matches.
To accept all messages one filter x has to be enabled by setting AE_x=1,
AMASK_x=0xff and ACODE_x=0x00. This is the default configuration after hardware
reset for filter x=0 while all other filters are disabled.

Table 3-26 Acceptance Filter Enable ACF_EN_1

Bits Name Access Function
Acceptance filter Enable
1- acceptance filter enabled
0- acceptance filter disable
7:0 AE_x rw-0x00
Each acceptance filter (AMASK / ACODE) can be individually enabled or disabled.
Disabled filters reject a message. Only enabled filters can accept a message if the
appropriate AMASK / ACODE configuration matches.

Table 3-27 Version Information VER_1 and VER_0

Bits Name Access Function
Version of CAN-CTRL, given as decimal value. VER_1 holds the major version and
VER_0
15:0 r VER_0 the minor version.
VER_1
Example: version 5x16N00S00 is represented by VER_1=5 and VER_0=16.

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Table 3-28 Receive Buffer Registers RBUF – Standard Format (r-0)

Address Bit position Function

7 6 5 4 3 2 1 0
RBUF ID(7:0) Identifier
RBUF+1 - ID(10:8) Identifier
RBUF+2 - Identifier
RBUF+3 ESI - Identifier
RBUF+4 IDE=0 RTR EDL BRS DLC(3:0) Control
RBUF+8 d1(7:0) Data byte 1
RBUF+9 d2(7:0) Data byte 2
…
RBUF+71 d64(7:0) Data byte 64

Table 3-29 Receive Buffer Registers RBUF – Extended Format (r-0)

Address Bit position Function

7 6 5 4 3 2 1 0
RBUF ID(7:0) Identifier
RBUF+1 ID(15:8) Identifier
RBUF+2 ID(23:16) Identifier
RBUF+3 ESI - ID(28:24) Identifier
RBUF+4 IDE=1 RTR EDL BRS DLC(3:0) Control
RBUF+8 d1(7:0) Data byte 1
RBUF+9 d2(7:0) Data byte 2
…
RBUF+71 d64(7:0) Data byte 64

The RBUF registers point the message slot with the oldest received message in the RB as can be seen
in Figure 3-5. All RBUF registers can be read in any order.
Please mind the gap inside the addressing range of RBUF from RBUF+5 to RBUF+7. This is for better
address segment alignment for a wider host controller interface.

Figure 3-5 Schematic of the FIFO-like RB (example with 6 slots)

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Table 3-30 Transmit Buffer Registers TBUF – Standard Format (rw-u)

Address Bit position Function

7 6 5 4 3 2 1 0
TBUF ID(7:0) Identifier
TBUF+1 - ID(10:8) Identifier
TBUF+2 - Identifier
TBUF+3 - Identifier
TBUF+4 IDE=0 RTR EDL BRS DLC(3:0) Control
TBUF+8 d1(7:0) Data byte 1
TBUF+9 d2(7:0) Data byte 2
…
TBUF+71 d64(7:0) Data byte 64

Table 3-31 Transmit Buffer Registers TBUF – Extended Format (rw-u)

Address Bit position Function

7 6 5 4 3 2 1 0
TBUF ID(7:0) Identifier
TBUF+1 ID(15:8) Identifier
TBUF+2 ID(23:16) Identifier
TBUF+3 - ID(28:24) Identifier
TBUF+4 IDE=1 RTR EDL BRS DLC(3:0) Control
TBUF+8 d1(7:0) Data byte 1
TBUF+9 d2(7:0) Data byte 2
…
TBUF+71 d64(7:0) Data byte 64

The TBUF registers point the next empty message slot in the TB as can be seen in Figure 3-6. All TBUF
registers can be written in any order. For the STB it is necessary to set TSNEXT to mark a slot filled and
to jump to the next message slot.
Please mind the gap inside the addressing range of TBUF from TBUF+5 to TBUF+7. This is for better
address segment alignment. The memory cells in the gap can be read and written, but have no meaning
for the CAN protocol.
If the PTB is selected then the TBUF registers must not be read while a PTB transmission is active (TPE
is set). This is because the PTB data bytes are implemented as single port memory.
Both RBUF and TBUF include some frame-individual control bits (Table 3-32). For RBUF these bits
signal the status of the appropriate CAN control field bits of the received CAN frame while for TBUF
these bits select the appropriate CAN control field bit for the frame that has to be transmitted.

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Table 3-32 Control bits in RBUF and TBUF

Bit Description
IDentifier Extension
IDE 0 – Standard Format: ID(10:0)
1 – Extended Format: ID(28:0)
Remote Transmission Request
0 – data frame
1 – remote frame
Only CAN 2.0 frames can be remote frames. There is no remote frame for CAN FD. Therefore RTR
RTR
is forced to 0 if EDL=1 in the TBUF.
In general: CAN-CTRL is unable to generate CAN FD remote frames and converts the frame to a
data frame in such an attempt, but CAN-CTRL is capable of successfully receiving CAN FD remote
frames.
Extended Data Length
EDL 0 – CAN 2.0 frame (up to 8 bytes payload)
1 – CAN FD frame (up to 64 bytes payload)
Bit Rate Switch
0 – nominal / slow bit rate for the complete frame
BRS
1 – switch to data / fast bit rate for the data payload and the CRC
Only CAN FD frames can switch the bitrate. Therefore BRS is forced to 0 if EDL=0.
Error State Indicator
This is a read-only status bit for RBUF and is not available in TBUF.
The protocol machine automatically embeds the correct value of ESI into transmitted frames. ESI
is only included in CAN FD frames and does not exist in CAN 2.0 frames.
ESI
0 – CAN node is error active
1 – CAN node is error passive
ESI in RBUF is always low for CAN 2.0 frames.
The error state for transmission is shown with bit EPASS in register ERRINT.

The Data Length Code (DLC) in RBUF and TBUF defines the length of the payload – the number of
payload bytes in a frame. See Table 3-33 for further details.
Remote frames (only for CAN 2.0 frames where EDL=0) are always transmitted with 0 payload bytes, but
the content of the DLC is transmitted in the frame header. Therefore it is possible to code some
information into the DLC bits for remote frames. But then care needs to be taken if different CAN nodes
are allowed to transmit a remote frame with the same ID. In this case all transmitters need to use the
same DLC because otherwise this would result in an unresolvable collision.

Table 3-33 Definition of the DLC (according to the CAN 2.0 / FD specification)
DLC (binary) Frame Type Payload in Bytes
0000 to 1000 CAN 2.0 and CAN FD 0 to 8

1001 to 1111 CAN 2.0 8

1001 CAN FD 12

1010 CAN FD 16
1011 CAN FD 20

1100 CAN FD 24
1101 CAN FD 32

1110 CAN FD 48

1111 CAN FD 64

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Figure 3-6 Schematic of PTB and FIFO-like STB (empty PTB and 6 STB slots)

The TBUF registers and readable and writable. Therefore a host controller may use TBUF to
successively prepare a message bit-by-bit if necessary.
The PTB is a single-port memory while the STB is a dual-port memory. Therefore if there is an active
transmission using the PTB (in other words TPE is set), then it is impossible for the host controller to
read the contents of the PTB. Any attempt will result in unknown results.

3.6 General Operation

This chapter describes handling of CAN communication. Before communication is possible, the CAN-
CTRL core has to be configured to match the CAN bus timings. A detailed description of the CAN bus bit
timing is given in chap. 4.

3.6.1 The Bus Off State

The “bus off” state is signaled using the status bit BUSOFF in register CFG_STAT (Table 3-5). A CAN
node enters the “bus off” state automatically if its transmit error counter becomes >255. Then it will not
take part in further communications until it returns into the erroractive state again. Setting BUSOFF to 1
also sets the EIF interrupt if EIE is enabled. A CAN node returns to erroractive state if it is reset by a
power-on reset or if it receives 128 sequences of 11 recessive bits (recovery sequences).
In the “bus off” state, RECNT is used to count the recovery sequences while TECNT stays unchanged.
Please note that while entering bus off state TECNT rolls over and therefore may hold a small value.
Therefore it is recommended to use TECNT before the node enters bus off state and status bit BUSOFF
afterwards.
If the node recovers from “bus off” state then RECNT and TECNT are automatically reset to 0.
When BUSOFF gets set then RESET is automatically set. See chap. 3.6.10 for details about this
software reset. Therefore both RECNT and TECNT are not affected by the software reset.

3.6.2 Acceptance Filters

To reduce the load of received frames for the host controller, the core uses acceptance filters. The CAN-
CTRL core checks the message identifier during acceptance filtering. Therefore the length of each
acceptance filter is 29 bits.
If a message passes one of the filters then it will be accepted. If accepted, the message will be stored
into the RB and finally RIF is set if RIE is enabled. If the message is not accepted, RIF is not set and the
RB FIFO pointer is not increased. Messages that are not accepted will be discarded and overwritten by
the next message. No stored valid message will be overwritten by any not accepted message.
Independently of the result of acceptance filtering, the CAN-CTRL core checks every message on the
bus and sends an acknowledge or an error frame to the bus.

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Figure 3-7 Example of acceptance filtering

The acceptance mask defines which bits shall be compared while the acceptance code defines the
appropriate values. Setting mask bits to 0 enables the comparison of the selected acceptance code bits
with the corresponding message identifier bits. Mask bits that are set to 1 are disabled for the
acceptance check and this results in accepting the message.
The identifier bits will be compared with the corresponding acceptance code bits ACODE as follows:
 standard: ID(10:0) with ACODE(10:0)
 extended: ID(28:0) with ACODE(28:0)
Example: If AMASK_x(0)=0 and all other AMASK_x bits are 1 then the value of the last ID bit has to be
equal to ACODE(0) for an accepted message. All other ID bits are ignored by the filter.
Figure 3-7 gives an example of acceptance filtering using several filters. In this example the filter 0 and 1
are enabled by the appropriate AE_x bits in the ACF_EN_x registers. All other filters are disabled and
therefore do not accept any message. For the enabled filters the combination of AMASX_x and
ACODE_x defines if a message is accepted (like in the example for filter 0) or not accepted (like in the
example for filter 1).
Note: Disabling a filter by setting AE_x=0 blocks messages. In contrast to this disabling a mask bit in
AMASK_x disables the check for this bit which results in accepting messages.
The definitions of AMASK and ACODE alone do not distinguish between standard or extended frames. If
bit AIDEE=1 then the value of AIDE defines with frame type is accepted. Otherwise if AIDE=0 both types
are accepted.
After power-on reset the CAN-CTRL core is configured to accept all messages. (Filter 0 is enabled by
AE_0=1, all bits in AMASK_0 are set to 1 and AIDEE=0. All other filters are disabled. Filter 0 is the only
filter that has defined reset values for AMASK / ACODE while all other filters have undefined reset
values.)

3.6.3 Message Reception

The received data will be stored in the RB as shown in Figure 3-8. The RB is configurable by a pre-
synthesis parameter and has FIFO-like behavior. Every received message that is valid and accepted sets
RIF=1 if RIE is enabled. RSTAT is set depending of the fill state. When the number of filled buffers is
equal to the programmable value AFWL then RAFIF is set if RAFIE is enabled. In case, when all buffers
are full, the RFIF is set if RFIE is enabled.

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Figure 3-8 Schematic of the FIFO-like RB (example with 6 slots)

The RB always maps the message slot containing the oldest message to the RBUF registers.
The maximum payload length for CAN 2.0 messages is 8 bytes and for CAN FD messages 64 bytes.
The individual length of each message is defined by the DLC. Because of this the RB provides slots for
each message and the host controller is required to set RREL to jump to the next RB slot. All RBUF
bytes of the actual slot can be read in any order.
th
If the RB is full, the next incoming message will be stored temporarily until it passes for valid (6 EOF
bit). Then the oldest message will be overwritten by the newest and ROIF is set if ROIE is enabled. If the
host controller reads the oldest message and sets RREL before a new incoming message becomes valid
then no message will be overwritten.

3.6.4 Handling message receptions

Without acceptance filtering the CAN-CTRL core would signal the reception of every frame and the host
would be required to decide if it was addressed. This would result in quite a big load on the host
controller.
It is possible to disable interrupts and use the acceptance filters to reduce the load for the host controller.
For a basic operation RIF is set to 1 if RIE is enabled and the CAN-CTRL core has received a valid
message. To reduce the number of reception interrupts it is possible to use RAIE / RAIF (RB Almost full
Interrupt) or RFIE / RFIF (RB Full Interrupt) instead of RIE / RIF (Reception Interrupt). The “almost full
limit” is programmable using AFWL.
The RB contains a number of RB slots which is selectable before synthesis using a generic parameter.
Reading the RB shall be done as follows:
1. Read the oldest message from the RB FIFO using the RBUF registers.
2. Release the RB slot with RREL=1. This selects the next message (the next FIFO slot). RBUF will
be updated automatically.
3. Repeat these actions until RSTAT signals an empty RB.
If the RB FIFO is full, the oldest message will be overwritten if a new received message is recognized as
th
valid (6 EOF bit). Before this event, no message is overwritten. This should give enough time for the
host controller to read at least one frame from the RB after the RB FIFO has been filled and the selected
interrupt has occurred. To enable this behavior the RB includes one more (hidden) slot than specified by
the synthesis parameter RBUF_SLOTS. This hidden slot is used to receive a message, validate it and
check it if it matches the acceptance filters before overwriting older messages.

3.6.5 Message Transmission

Before starting any transmission, at least one of the transmit buffers (PTB or STB) has to be loaded with
a message (Figure 3-9). TPE signals if the PTB is locked and TSSTAT signals the fill state of the STB.
The TBUF registers provide access to both the PTB as well as to the STB. Below is the recommended
programming flow:
1. Set TBSEL to the desired value to select either the PTB or the STB.
2. Write the frame to the TBUF registers.
3. For the STB set TSNEXT=1 to finish loading of this STB slot.

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Figure 3-9 Schematic of PTB and FIFO-like STB (empty PTB and 6 STB slots)

The maximum payload length for CAN 2.0 messages is 8 bytes and for CAN FD messages 64 bytes.
The individual length of each message is defined by the DLC. For remote frames (bit RTR) the DLC
becomes meaningless, because remote frames always have a data length of 0 bytes. Because of DLC
and RTR, the host controller is required to set TSNEXT to jump to the next STB slot. All TBUF bytes can
be written in any order.
Setting TSNEXT=1 is meaningless if TBSEL=0 selects the PTB. In this case TSNEXT is automatically
cleared and does no harm.
Bit TPE should be set to start a transmission when using the PTB. To use the STB, TSONE has to be set
to start a transmission of a single message (the oldest) or TSALL to transmit all messages.
The PTB has always a higher priority than the STB. If both transmit buffers have the order to transmit,
the PTB message will be always sent first regardless of the frame identifiers. If a transmission from the
STB is already active, it will be completed before the message from the PTB is sent at the next possible
transmit position (the next interframe slot). After the PTB transmission is completed or aborted, the CAN-
CTRL core returns to process other pending messages from the STB. See also chap. 2.3.3 for further
details.
When the transmission is completed, the following transmission interrupts are set:
 For the PTB, TPIF is set if TPIE is enabled
 For the STB using TSONE, TSIF is set if one message has been completed and TSIE is
enabled.
 For the STB using TSALL, TSIF is set if all messages have been completed and if TSIE is
enabled. In other words: TSIE is set if the STB is empty. Therefore, if the host controller writes
an additional message to the STB after a TSALL transmission has been started then the
additional message will be also transmitted before TSIF will be set.
It is meaningless to set TSONE or TSALL while the STB is empty. In such a case TSONE respectively
TSALL will be reset automatically. No interrupt flag will be set and no frame will be transmitted.

3.6.6 Message transmission abort

If the situation arises, where a message in a transmit buffer cannot be sent due to its low priority, this
would block the buffer for a long time. In order to avoid this, the host controller can withdraw the
transmission request by setting TPA or TSA respectively, if the transmission has not yet been started.
Both TPA and TSA source a single interrupt flag: AIF. The CAN protocol machine executes an abort only
if it does not transmit anything to the CAN bus. Therefore the following is valid:
 There is no abort during bus arbitration.
o If the node loses arbitration, the abort will be executed afterwards.
o If the node wins arbitration, the frame will be transmitted.
 There is no abort while a frame is transmitted.

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o If a frame is transmitted successfully then a successful transmission is signaled to the

host controller. In this case no abort is signaled. This is done by the appropriate
interrupt and status bits.
o After an unsuccessful transmission where the CAN node does not receive an
acknowledge, the error counter is incremented and the abort will be executed.
o If there is at least one frame left in the STB, while the host has commanded all frames
to be transmitted (TSALL=1), then both the completed frame as well as the abort is
signaled to the host.
Because of these facts aborting a transmission may take some time depending on the CAN
communication speed and frame length. If an abort is executed, this results in the following actions:
 TPA releases the PTB which results in TPE=0.
The frame data is still stored in the PTB after releasing the PTB.
 TSA releases one single (the oldest) message slot or all message slots of the STB FIFO. This
depends on whether TSONE or TSALL was used to start the transmission. TSSTAT will be
updated accordingly.
Releasing a frame in the STB results in discarding the frame data because the host cannot
access it as a result of the FIFO-like behavior.
Setting both TPA and TSA simultaneously is not recommended. If a host controller decides to do it
anyway, then AIF will be set and both transmissions from PTB and STB will be aborted if possible. As
already stated if one transmission will be completed before the abort can be executed this will result in
signaling a successful transmission. Therefore the following interrupt flags may be set if enabled:
 AIF (once for both PTB and STB transmission abort)
 TPIF + AIF
 TSIF + AIF
 TPIF + TSIF (very seldom, will only happen if the host does not handle TPIF immediately)
 TPIF + TSIF + AIF (very seldom, will only happen if the host does not handle TPIF and TSIF
immediately)
To clear the entire STB both TSALL and TSA need to be set. In order to detect if a message cannot be
sent for a long time because it loses arbitration the host may use the ALIF / ALIE.

3.6.7 A Full STB

After writing a message to the STB, TSNEXT=1 marks a buffer slot filled and jumps to the next free
message slot. TSNEXT is automatically reset to 0 by the CAN-CTRL core after this operation.
If the last message slot has been filled and therefore all message slots are occupied then TSNEXT stays
set until a new message slot becomes free. While TSNEXT=1, then writing to TBUF is blocked by the
CAN-CTRL core.
When a slot becomes free, then the CAN-CTRL core automatically resets TSNEXT to 0. A slot becomes
free if a frame form the STB is transmitted successfully or if the host requests an abort (TSA=1). If a
TSALL transmission is aborted, then TSNEXT is also reset, but additionally the complete STB is
emptied. Then no message is in the STB anymore.

3.6.8 Extended Status and Error Report

During CAN bus communication transmission errors may occur. The following features support detection
and analysis of them.
3.6.8.1. Programmable Error Warning Limit
Errors during reception / transmission are counted by RECNT and TECNT. A programmable error
warning limit EWL, located in register LIMIT, can be used by the host controller for flexible reaction on
those events. The limit values can be chosen in steps of 8 errors from 8 to 128:
Limit of count of errors = (EWL+1)*8

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The interrupt EIF will be set if enabled by EIE under the following conditions:
 the border of the error warning limit has been crossed in either direction by RECNT or TECNT or
 the BUSOFF bit has been changed in either direction.
3.6.8.2. Arbitration Lost Capture (ALC)
The core is able to detect the exact bit position in the Arbitration Field where the arbitration has been
lost. This event can be signaled by the ALIF interrupt if it is enabled. The value of ALC stays unchanged
if the node is able to win the arbitration. Then ALC holds the old value of the last loss of arbitration.
The value of ALC is defined as follows: A frame starts with the SOF bit and then the first bit of the ID is
transmitted. This first ID bit has ALC value 0, the second ID bit ALC value 1 and so on. See Figure 2-3
for the bit order in all types of CAN 2.0 and CAN FD frames.
Arbitration is only allowed in the arbitration field (Figure 2-3). Therefore the maximum value of ALC is 31
which is the RTR bit in extended frames.
Additional hint: If a standard remote frame arbitrates with an extended frame, then the extended frame
loses arbitration at the IDE bit and ALC will be 12. The node transmitting the standard remote frame will
not notice that an arbitration has been taken place, because this node has won.
It is impossible to get an arbitration loss outside of the arbitration field. Such an event is a bit error.
3.6.8.3. Kind Of Error (KOER)
The core recognizes errors on the CAN bus and stores the last error event in the KOER bits. A CAN bus
error can be signaled by the BEIF interrupt if it is enabled. Every new error event overwrites the previous
stored value of KOER. Therefore the host controller has to react quickly on the error event. The error
codes are described in the table 3-15.
KOER is reset after a successful transmission or reception of a frame.

3.6.9 Extended Features

3.6.9.1. Single Shot Transmission
Sometimes an automatic re-transmission is not desired. Therefore the order to transmit a message only
once can be set separately for the transmit buffers PTB by the bit TPSS and for the transmit buffer STB
by the bit TSSS. In this case no re-transmission will be performed in the event of an error or arbitration
lost if the selected transmission is active.
In the case of an immediate successful transmission there is no difference to normal transmission. But in
the case of an error during the transmission TPIF gets set if enabled, the appropriate transmit buffer slot
gets cleared and KOER and the error counters get updated. Therefore for single shot transmission TPIF
alone does not indicate if the frame has been successfully transmitted or an error has occurred.
If single shot transmission is used with TSALL and there is more than one frame in the STB then for each
frame a single shot transmission is done. Regardless if any of the frames is not successfully transmitted
(e.g. because of an ACK error) the CAN-CTRL advances to the next frame and stops if the STB is empty.
Therefore in this scenario only the error counters indicate what has happened. This can be quite
complex to evaluate because if one of two frames got errors the host cannot detect which one was the
successful one.
3.6.9.2. Listen Only Mode (LOM)
LOM provides the ability of monitoring the CAN bus without any influence to the bus. LOM by CAN-CTRL
is compatible to the bus monitoring feature defined in the CAN FD specification.
Another application is the automatic bit rate detection where the host controller tries different timing
settings until no errors occur.
In LOM the core is not able to write dominant bits onto the bus (no active error flags or overload flags, no
acknowledge), but these dominant bits are rerouted internally in an internal loop back mode so that the
core receives its own bits. Errors will be monitored (KOER, BEIF) in LOM.
Important for LOM:

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 The error counters stay unchanged regardless of any error condition.

 If a frame is transmitted by a node then an ACK will be only generated if at least one additional
node is attached to the bus that is not in LOM. Then there will be no error and all nodes (also
those in LOM) will receive the frame.
If all nodes except for the transmitting node are in LOM, then there will be not ACK on the bus
and the transmitter will generate an ACK error and will maybe retransmit the frame. Because a
frame is received only valid if the bus is recessive till the 6th end of frame bit after the ACK and
the error frame will violate this rule, the frame is not received by the nodes in LOM.
LOM should not be enabled while a transmission is active. The host controller has to take care of this.
There is not additional protection from CAN-CTRL.
If LOM is enabled then no transmission can be started.
3.6.9.3. Bus Connection Test
To check if a node is connected to the bus the following steps shall be done:
 Transmit a frame. If the node is connected to the bus then its TX bits are visible on its RX input.
 If there are other nodes connected to the CAN bus, then a successful transmission (including an
acknowledge from the other nodes) is expected. No error will be signaled.
 If the node is the only node that is connected to the CAN bus (but the connection between the
bus, the transceiver and the CAN-CTRL core is fine) then the first regular error situation occurs
in the ACK slot because of no acknowledge from other nodes. Then a BEIF error interrupt will be
generated if enabled and KOER=“100” (ACK error).
 If the connection to the transceiver or the bus is broken then immediately after the SOF bit the
BEIF error interrupt will be set and KOER=“001” (BIT error).
3.6.9.4. Loop Back Mode (LBMI and LBME)
CAN-CTRL supports two Loop Back Modes: internal (LBMI) and external (LBME). Both modes result in
reception of the own transmitted frame which can be useful for self-tests. See Figure 3-10 for details.
In LBMI CAN-CTRL is disconnected from the CAN bus and the txd output is set to recessive. The output
data stream is feed back to the input.
In LBME CAN-CTRL stays connected to the transceiver and a transmitted frame will be visible on the
bus. In this mode CAN-CTRL receives its own frame. It does not matter if there will be an ACK from
another node or not.

Figure 3-10 Loop Back Mode: Internal and External

In Loop Back Mode the core receives its own message, stores it in the RBUF and sets the appropriate
receive interrupt flags if enabled. During a Loop Back Mode transmission ACK error generation is
disabled and the appropriate transmit interrupt will be set if enabled.
LBMI can be useful for chip-internal and software tests while LBME can test the transceiver and the
connections to it.
Both Loop Back Modes should not be activated while a transmission is active. The host controller has to
take care of this. There is not additional protection from CAN-CTRL.

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If the node is connected to a CAN bus then switching back from LBMI to normal operation must not be
done by simply setting LBMI to 0, because then it may be that this occurs just at the moment while
another CAN node is transmitting. In this case switching back to normal operation shall be done by
setting bit RESET to 1. This automatically clears LBMI to 0. Finally RESET can be disabled and the core
returns back to normal operation. In contrast to this LBME can be disabled every time.
3.6.9.5. Transceiver Standby Mode
Using the register bit STBY the output signal stby is driven. It can be used to activate a standby mode for
a transceiver. The behavior is compatible to the NXP TJA1049 transceiver.
Once standby is activated no transmission is possible and therefore TPE, TSONE and TSALL cannot be
set. On the other hand CAN-CTRL does not allow STBY to be set if a transmission is already active
(TPE, TSONE or TSALL is set).
If STBY is set the transceiver enters a low-power mode. In this mode it is unable to receive a frame at full
speed but monitors the CAN bus for a dominant state. If the dominant state is active for a time which is
defined in the transceivers data sheet the transceiver will pull the rxd signal low. If rxd is low CAN-CTRL
automatically clears STBY to 0 which disables standby mode for the transceiver. This is done silently
without an interrupt to the host controller.
Switching from standby mode to active mode takes some time for the transceiver and therefore the initial
wakeup frame cannot be received successfully. Therefore the node recently being in standby will not
respond with an ACK. If no CAN node at the bus responds to the wakeup frame with an ACK then this
results in an ACK error for the transmitter of the wakeup frame. Then the transmitter will automatically
repeat the frame. During the repetition the transceiver will be back in active mode and CAN-CTRL will
receive the frame and will respond with an ACK.
In summary: One node transmits a frame for wakeup. If all others nodes are in standby mode, then the
transmitter gets an ACK error and will automatically repeat the frame. During the repetition the nodes are
back in active mode and will respond with an ACK.
STBY is not affected by bit RESET.

3.6.10 Software Reset

If bit RESET in CFG_STAT is set to 1 then the software reset is active. Several components are forced to
a reset state if RESET=1 but no all components are touched by RESET. Some components are only
sensitive to a hardware reset. The reset values of all bits are always the same for software and hardware
reset.
Table 3-34 Software Reset
Register RESET Comment
RBUF Yes All RB slots are marked as empty. RBUF contains unknown data.
TBUF Yes All STB slots are marked as empty. Because of TBSEL TBUF points to the PTB.
LBME Yes -
LBMI Yes -
TPSS Yes -
TSSS Yes -
Reception is immediately cancelled even if a reception is active. No ACK will be
RACTIVE Yes
generated.
All transmissions are immediately terminated with RESET. If a transmission is active
TACTIVE Yes
this will result in an erogenous frame. Other nodes will generate error frames.
BUSOFF No -
TBSEL Yes TBUF fixed to point to PTB.
LOM Yes -
STBY No -
TPE Yes -
TPA Yes -
TSONE Yes -
TSALL Yes -

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Register RESET Comment

TSA Yes -
TSNEXT Yes -
TSSTAT Yes All STB slots are marked as empty.
ROV Yes All RB slots are marked as empty.
RREL Yes -
RSTAT Yes All RB slots are marked as empty.
RIE No -
ROIE No -
RFIE No -
RAFIE No -
TPIE No -
TSIE No -
EIE No -
TSFF Yes All STB slots are marked as empty.
RIF Yes -
ROIF Yes -
RFIF Yes -
RAFIF Yes -
TPIF Yes -
TSIF Yes -
EIF No -
AIF Yes -
EWARN No -
EPASS No -
EPIE No -
EPIF Yes -
ALIE No -
ALIF Yes -
BEIE No -
BEIF Yes -
BITTIME_x No Register is writeable if RESET=1 and write-locked if 0.
S_PRESC, F_PRESC No Register is writeable if RESET=1 and write-locked if 0.
AFWL No -
EWL Yes -
KOER Yes -
ALC Yes -
RECNT No -
TECNT No -
SELMASK No -
ACFADR No -
AE_x No -
ACODE_x No Register is writeable if RESET=1 and write-locked if 0.
AMASK_x No Register is writeable if RESET=1 and write-locked if 0.

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4. CAN Bit Time

4.1 Data Bit Rates

CAN 2.0B defines data bit rates up to 1Mbit/s. For CAN FD there is no fixed limitation. For real life
systems the data rates are limited by the used transceiver and the achievable clock frequency for the
CAN-CTRL core which depends on the used target cell library.
The CAN-CTRL core can be programmed to arbitrarily chosen data rates only limited by the range of the
bit settings in the appropriate bit timing and prescaler registers.

4.2 Definitions

Figure 4-1 CAN Bit Timing Specifications

The CAN bit time BT consists of several segments as shown in Figure 4-1. Each segment consists of a
number of time quanta units nTQ . The duration of a time quanta TQ is:

n prescaler
TQ
f CLOCK
The values of nTQ and n prescaler have to be chosen depending on the system clock frequency f CLOCK to
match BTreal as close as possible to BTideal  1 BR where BR is the CAN bus baud rate:
n prescaler  nTQ
BTideal  BTreal   t Seg_1  t Segt_2
f CLOCK
The CAN specification requires several relationships between the segment lengths (Table 4-1) which
results in relationships between t Seg _ 1 , tSeg _ 2 and the maximum synchronization jump width t SJW . Please
note that Table 4-1 lists the minimum configuration ranges.

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Table 4-1 CAN Timing Segments (Minimum Configuration Ranges)

Segment Description
SYNC_SEG Synchronization Segment = 1 TQ
Propagation Segment
[1...8] TQ CAN 2.0 bit rate CAN FD not enabled
PROP_SEG [1...48] TQ CAN 2.0 bit rate CAN FD enabled
[1…48] TQ CAN FD nominal bit rate
[0...8] TQ CAN FD data bit rate
Phase Buffer Segment 1
[1...8] TQ CAN 2.0 bit rate CAN FD not enabled
PHASE_SEG1 [1...16] TQ CAN 2.0 bit rate CAN FD enabled
[1...16] TQ CAN FD nominal bit rate
[1...8] TQ CAN FD data bit rate
Phase Buffer Segment 2
[2...8] TQ CAN 2.0 bit rate CAN FD not enabled
PHASE_SEG2 [2...16] TQ CAN 2.0 bit rate CAN FD not enabled
[2...16] TQ CAN FD nominal bit rate
[2...8] TQ CAN FD data bit rate
Synchronization Jump Width
[1...4] TQ CAN 2.0 bit rate CAN FD not enabled
SJW [1...16] TQ CAN 2.0 bit rate CAN FD not enabled
[1...16] TQ CAN FD nominal bit rate
[1...8] TQ CAN FD data bit rate
Information Processing Time = [0...2] TQ
IPT
PHASE_SEG2 ≥ IPT
As can be seen in Figure 4-1 the CAN-CTRL core collects SYNC_SEG, PROP_SEG and PHASE_SEG1
into one group and the length of the group is configurable with t Seg _ 1 . Table 4-2 lists the available
configuration ranges. Please note that the CAN-CTRL core does not check if all rules are met.
Table 4-2 CAN-CTRL Timing Settings (Available Configuration ranges)
Setting Requirements
[3…65] TQ CAN 2.0 bit rate (slow)
tSeg _ 1 [3…65] TQ CAN FD nominal bit rate (slow)
[2…17] TQ CAN FD data bit rate (fast)
[2…8] TQ t Seg _ 1  t Seg _ 2  2 CAN 2.0 bit rate (slow)

tSeg _ 2 [2…32] TQ t Seg _ 1  t Seg _ 2  2 CAN FD nominal bit rate (slow)

[2…8] TQ t Seg _ 1  t Seg _ 2  1 CAN FD data bit rate (fast)

[1…16] TQ tSeg _ 2  tSJW CAN 2.0 bit rate (slow)

t SJW [1…16] TQ tSeg _ 2  tSJW CAN FD nominal bit rate (slow)

[1…8] TQ tSeg _ 2  tSJW CAN FD data bit rate (fast)

For CAN 2.0 bit rate and CAN FD (slow) nominal bit rate the register settings S_Seg_1, S_Seg_2,
S_SJW and S_PRESC define the appropriate segment lengths. For CAN FD (fast) data bit rate the
register F_Seg_1, F_Seg_2, F_SJW and F_PRESC are valid.
t Seg _ 1  S _ Seg _ 1  2  TQ t Seg _ 1  F _ Seg _ 1  2  TQ
t Seg _ 2  S _ Seg _ 2  1  TQ t Seg _ 2  F _ Seg _ 2  1  TQ
t SJW  S _ SJW  1  TQ t SJW  F _ SJW  1  TQ
n prescaler  S _ PRESC  1 n prescaler  F _ PRESC  1
A CAN FD core switches from slow nominal bit rate to fast data bit rate at the sample point in the BRS bit
and switches back at the sample point in the CRC delimiter bit.

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f CLOCK
An illustration a suitable bit rate configuration is given in Figure 4-2 where f tq_clk  . The bit time
n prescaler
BTreal , the sample point and the synchronization jump width SJW will be derived from tq_clk.

Figure 4-2 Clock Division for Bit Sampling

Having the requirements from Table 4-2 in mind the host controller has to define the length of segment 1,
segment 2 and the synchronization jump width for the slow bit rate and if required for CAN FD for the fast
bit rate.
Some suggestions, given as rules of the thumb:
 Segment 1 must be slightly larger than segment 2. Then the sample point is in the a little bit later
than in the middle of the bit time.
 The synchronization jump width must not be bigger than segment 2. If SJW is too small the CAN
node may be too slow to resynchronize, if SJW is too big then the CAN node may resynchronize
too often. SJW being half as long as segment 2 seems to be a suitable value.
 All CAN nodes connected to a CAN bus should choose similar settings if possible.
The fastest CAN bus speed can be configured using the minimum timing values. But there are some
things that need to be considered:
 If the prescalers are bigger than one then all other timing parameters could be set to zero, but
this violates the rule t Seg _ 1  t Seg _ 2  2 (slow speed) resp. t Seg _ 1  t Seg _ 2  1 (fast speed) and
therefore S_Seg_1 and F_Seg_1 should be at least set to 1. But such a selecting of timing
parameters works in theory, but may not be robust enough for real nets.
 If the prescalers are set to one then synchronization becomes difficult. In general the CAN
specification requires one bit time to be at least 8 TQ long for CAN 2.0 and CAN FD slow
nominal bit rate. For CAN-CTRL one bit time of fast data bit rate needs to be also at least 8 TQ
long if the fast prescaler is set to 1.
 In summary the fastest CAN bus frequency is the can_clk frequency divided by 8: prescalers set
to 1 and 8 TQ bit time.

4.3 Example Configuration

This example refers to Figure 4-2. It is an example for CAN 2.0 / slow bit rate configuration but all
statements can be easily translated to CAN FD (fast) data bit rate. The following steps need to be carried
for the configuration of the CAN-CTRL core:
1. Set bit RESET=1.
2. Select register bits S_Seg_1 and S_Seg_2 in register BITTIME_0 and BITTIME_1:
In the example the data rate on the bus f BUS  1 Mbaud and the system clock is 16 MHz .
The values of nTQ and n prescaler have to be selected to fit BTreal as close as possible to BTideal .
In this example n prescaler  2 and nTQ  8 are chosen which results in a perfect match:
BTideal  BTreal  8 TQ .
With BTreal  tSeg_1  t Segt_2 and the time segment definitions given in chapter 4.1 t Seg_1  5 TQ

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and t Seg_2  3 TQ can be chosen as suitable values which finally results in the register settings
S_Seg_1=3 and S_Seg_2=2.
3. Load the acceptance code and mask registers (optional).
4. Set register bits S_SJW in BITTIME_2:
With t Seg_2  t SJW one is free to chose t SJW  3 which finally results in 2.

5. Load the clock prescaler register S_PRESC: n prescaler  PRESC  1 results in S_PRESC=1.
6. Set bit RESET=0.
The given order is not mandatory. It is merely necessary to set bit RESET=1 at the beginning, as
it is otherwise not possible to load the bit timing, ACODE and AMASK registers. RESET=0 is
required upon completion of the configuration. The controller then waits for 8 recessive bits
(frame end) and resumes its normal operation.
7. Continue with configuration of interrupts other configuration bits and execute commands.

4.4 CAN Bit timing Calculator (CBC)

The release package includes a software tool for MS Windows for the calculation of the CAN bit timings.
This tool can be used to calculate the CAN 2.0 as well as the CAN FD nominal and data bit rates.
Starting with the setting of the clock frequency of the CAN-CTRL core and the desired Baud rate this tool
outputs all possible settings for the prescaler, segment 1 and segment 2. For SJW the tool gives the
maximum value. Furthermore the tool outputs the position of the sample point as a factor of a bit time.
The tool gives on one hand the time in multiples of TQ as well as the register value. For example
“t_seg1=7” means that segment 1 is 7 TQ long and the register value needs to be set to S_Seg_1=5.
By default the tool tries to calculate the settings with a tolerance of 0%. In other words: With the given
clock speed and these settings the desired baud rate will be synthesized exactly. It is possible to modify
the tolerance setting to get also settings that will not match exactly. Please note that the tool does not
check if the selected tolerance is inside of the CAN specification.
This tool performs and exhaustive search for possible settings. The calculation time will increase for fast
baud rates and a big tolerance value. The tools searches for settings in steps of 1 Baud.

4.5 Bit Rate Switching and the Sample Point

In a CAN network when CAN FD frames with bit rate switching are used the exact position of the sample
point is important and needs to be for all nodes as similar as possible.
The bit rate is switched after the sample point of the BRS bit and the sample point of the CRC delimiter.
Therefore the lengths of these bits are intermediate. As can be seen in Figure 4-3 the position of the
sample point makes a big difference for the absolute length of the BRS bit. (1 TQ of the slow nominal bit
rate may be much bigger than several TQs of the fast data rate.) If the data rate is much higher than the
nominal bit rate then an earlier or later sample point may lead to false samples at fast data bit rate.

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Figure 4-3 Bit Rate Switching at bit BRS S _ PRESC  F _ PRESC 

4.6 Bit Timing Configuration for CAN FD Nodes
As stated in chap. 4.5 the position of the sample point is very important for bit rate switching. Therefore
there is the general recommendation for all CAN FD nodes to use exactly the same timing parameters in
a CAN network. In contrast to classic CAN where only the data rate needs to be the same for all nodes,
CAN FD requires the sample point at the same position. In others words segment 1 and segment 2 need
to be configured to the same length for all nodes. Furthermore it is recommended to use also the same
length of one TQ to make synchronization for all nodes equal.
This requirement can only be achieved if all nodes run with the same base clock frequency (called
can_clk for CAN-CTRL) or at least with compatible clock frequencies. The recommended settings are
20MHz, 40MHz or 80MHz.

4.7 TDC and RDC

For CAN FD nodes transmitter delay compensation (TDC) can be optionally enabled while receiver delay
compensation (RDC) is automatically active. These features have the following background: For
communication with CAN FD data bit rate it may be that the delay of the transmitting transceiver or the
delay of the bus is bigger than a bit time. This needs to be compensated. Without TDC, the bit rate in the
data-phase of FD frames is limited by the fact that the transmitter detects a bit error if it cannot receive its
own transmitted bit latest at the sample point of that bit.

Figure 4-4 Transmitter Delay

Figure 4-4 gives an example of the effect of a big transmitter delay. In this figure a txd data stream is
shown starting with bits A and B. One bit time consists of t Seg_1  5 TQ before the Sample Point (SP)
and t Seg_2  3 TQ behind. In this example the transmitter delay is longer than 2 bit times. Therefore the
original SP cannot be used to sample the correct bit value and the CAN FD specification defines an
additional Secondary Sample Point (SSP). If TDC is enabled with bit TDCEN=1 then CAN-CTRL
automatically determines the transmitter delay. The position of the SSP is the transmitter delay plus the
SSP Offset which is defined by the configuration bits SSPOFF. SSPOFF must be given as a number of
TQ and it is suggested to set t Seg_1 equal to SSPOFF. (Please remember that F_SEG_1 defines t Seg_1
during data bit rate. Therefore in the example given in Figure 4-4 SSPOFF=5 is chosen.)
CAN-CTRL is capable of automatically determining a transmitter delay of at least 4 bit times of the fast
data bit rate. The exact amount depends on the system clock and the chosen CAN bit timing
configuration.

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A delay bigger than a bit time needs to be taken into account also for receiving nodes. CAN FD defines
an additional hard synchronization at the falling edge between bit EDL=1 and the following r0 bit. (At this
time the slow nominal bit rate is active.) Synchronization for CAN and CAN FD is in general defined to
operate in time steps of one TQ. But steps of one TQ at nominal bit rate may be to coarse for a
synchronization for the fast data bit rate. Therefore the additional hard synchronization at the EDL bit
needs to violate this rule and needs to synchronize as exact as possible and only limited by the clock
frequency of the system. CAN-CTRL uses this special synchronization and this is called RDC. RDC is
automatically done during reception if EDL=1, no matter if TDC is enabled or not.

4.8 Bit Timing Recommendations

CAN FD timing configuration requires to use the same data rate and the same sample point for all nodes
in a CAN network. Therefore it is recommended to use 20MHz, 40MHz or 80MHz as source for the CAN
protocol machine (can_clk). In Table 4-4, Table 4-5 and Table 4-6 there are some recommendations for
the bit timing settings that should apply to all nodes in a CAN FD network.
Please note that the bit time should be at least 8 TQ if the prescaler is set to 1.
The decision if TDC is used or not depends on the CAN network. The tables only give a suggestion and
TDC can be enabled or disabled as needed.
Table 4-3 Abbreviations for Table 4-4, Table 4-5 and Table 4-6

Abbreviation Description
PSP Primary Sample Point
SSP Secondary Sample Point
Seg 1 Segment 1
Seg 2 Segment 2
TDC Transmitter Delay Compensation (see SSPOFF)

Table 4-4 Recommendations for 20MHz can_clk

Bit Rate PSP SSP Bit Time Seg 1 Seg 2 SJW TDC
Prescaler
[Mbit/s] [%] [%] [TQ] [TQ] [TQ] [TQ] [clk]
0.25
80 - 1 80 64 16 16 -
(arbitration)
0.5 80 Disable 2 20 16 4 4 -
1 80 80 1 20 16 4 4 16
2 80 80 1 10 8 2 2 8
2.5 75 75 1 8 6 2 2 6

Table 4-5 Recommendations for 40MHz can_clk

Bit Rate PSP SSP Bit Time Seg 1 Seg 2 SJW TDC
Prescaler
[Mbit/s] [%] [%] [TQ] [TQ] [TQ] [TQ] [clk]
0.5
80 - 1 80 64 16 16 -
(arbitration)
1 80 Disable 2 20 16 4 4 -
2 80 80 1 20 16 4 4 16
2.5 75 75 1 16 12 4 4 12
4 80 80 1 10 8 2 2 8
5 75 75 1 8 6 2 2 6

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Table 4-6 Recommendations for 80MHz can_clk

Bit Rate PSP SSP Bit Time Seg 1 Seg 2 SJW TDC
Prescaler
[Mbit/s] [%] [%] [TQ] [TQ] [TQ] [TQ] [clk]
1
80 - 1 80 64 16 16 -
(arbitration)
2 80 Disable 2 20 16 4 4 -
2.5 75 75 2 16 12 4 4 12
4 80 80 1 20 16 4 4 16
5 75 75 1 16 12 4 4 12
8 80 80 1 10 8 2 2 8
10 75 75 1 8 6 2 2 6

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5. Host Interfaces
CAN-CTRL is a 32 bit peripheral component which provides a generic 32 bit host interface. Additionally
various host interface wrappers are provided. These wrappers are described in the following chapters
and can be used in addition to CAN-CTRL.

5.1 Generic 32 Bit Wide Synchronous Host Interface

The generic 32 bit wide host interface is the native interface of CAN-CTRL. All other interfaces are
implemented as wrappers and therefore all definitions of this chapter are valid for the wrappers too.
Every byte of the register map (Table 3-4) is assigned to an address. Using the 32 bit host interface
therefore the 2 LSBs of the address (host_adr) are ignored by CAN-CTRL.

5.1.1 Register Write

The Address (host_adr), Data (host_di), Chip Select (host_cs_b) and Write Enable (host_wr_b) signals
must be valid throughout the write process. Writing into the registers occurs at the rising edge of the
system clock (host_clk). All mentioned signals have to be stable around the positive edge of host_clk
t SETUP t HOLD depending on the used technology.
with setup and hold times and

Figure 5-1 Write Operation

Signal host_wr_b is 4 bits wide and controls the bytes to be written. See chap. 5.1.3 for details.

5.1.2 Register Read

The Address (host_adr), Chip Select (host_cs_b) and Read Enable (host_rd_b) signals must be valid
throughout the read process. Reading occurs at the rising edge of the system clock (host_clk). All
mentioned signals have to be stable around the positive clock edge with setup and hold times t SETUP and
t HOLD depending on the used technology.
The read data value stays valid after the read access for only one clock cycle.

Figure 5-2 Read Operation

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5.1.3 Data Alignment

Table 5-1 Active Byte Lanes (little endian)
host_rd_b host_adr[1:0] data[31:24] data[23:16] data[15:8] data[7:0]
host_wr_b
1110b 00b - - - Active
1101b 01b - - Active -
1011b 10b - Active - -
0111b 11b Active - - -
1100b 00b - - Active Active
0011b 10b Active Active - -
0000b 00b Active Active Active Active

The 32 bit interface provides the capability of accessing a byte, a half word or a full 32 bit word as shown
in Table 5-1. Signal host_adr is given only for completeness as the 2 LSBs are ignored by CAN-CTRL
and only the host_rd_b and host_wr_b signals are relevant.
TBUF and ACF are implemented as true 32 bit wide memories. Therefore a write access to TBUF or ACF
is only executed if it is performed as a full 32 bit word access (host_wr_b=0000b). Read accesses and
write accesses to other memory locations are not restricted.

5.2 Generic 8 Bit Wide Synchronous Host Interface

The generic 8 bit wide interface (component can_sync_08) is a wrapper that enables CAN-CTRL to be
used by an 8 bit host controller.

Figure 5-3 Generic 8 Bit Wide Host Interface (only relevant signals shown)

The interface maps 8 bit wide accesses to 32 bit wide accesses. For a read operation this is
straightforward and the wrapper extracts the selected byte in the same way as shown in Figure 5-2 in a
single clock cycle.
For a write operation the wrapper needs a read-modify-write access where the full 32 bits of data are
read with the first rising edge of host_clk while signal host_ready becomes low. Then the 32 bits are
modified (the new 8 bits are embedded) and written back with the second rising edge of host_clk while
signal host_ready becomes high again. (See Figure 5-4 for details.) Therefore a write always takes two
clocks and a new write access can only be performed if signal host_ready is high.

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Figure 5-4 Write Operation with 8 Bit Host Interface

5.3 AMBA APB

The memory interface to the CAN core, which has been described in chap. 5.1, can be connected to a
32 bit AMBA APB interface using a wrapper. Source code for the wrapper is provided in the release
package (compatible to APB 2.0). The wrapper shall be connected to the CAN-CTRL core as shown in
Figure 5-5. The wrapper does not use the APB signal pprot.

Figure 5-5 AMBA APB Wrapper (only relevant bits shown)

The wrapper provides a 32 bit APB interface and executes write accesses with no wait state and read
accesses with one wait state.
The address paddr maps to the addresses of the register map (Table 3-4, chap. 3.4) with signal
host_adr. As stated in chap. 5.1 the two LSBs are ignored by CAN-CTRL.
If only one byte or some bytes shall be written then signal pstrb shall be used to mask the bytes. See
chap. 5.1.3 for details. (Signal host_wr_b maps to the inverse of pstrb.)
Attention: as defined by the APB specification pstrb only works with write accesses but not for read
accesses! Therefore always 4 bytes are read.
As stated in chap. 5.1.3 a write access to TBUF or ACF has to access a full 32 bit wide word
(pstrb=1111b). If not then an error is reported using signal pslverr and the access is not executed.

5.4 AMBA AHB

The memory interface to the CAN core, which has been described in chap. 5.1, can be connected to an
AMBA AHB interface using a wrapper. Source code for the wrapper is provided in the release package
(compatible to AMBA 3 AHB-Lite 1.0). The wrapper shall be connected to the CAN-CTRL core as shown
in Figure 5-6. The wrapper does not use the AHB signals hburst, hprot and hmastlock.

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Figure 5-6 AMBA AHB Wrapper (only relevant bits shown)

The wrapper provides a 32 bit AHB interface and executes write accesses with no wait state and read
accesses with one wait state. Please note that AHB uses a pipelined access consisting of an address
and a data phase. Both phases take 1 hclk. The data phase can be extended using wait states.
AHB is designed for high throughput. The required wait state has an impact to the system performance.
If this is a problem, then it is suggested to use the APB interface (chap. 5.3) instead of AHB.
The address haddr maps to the addresses of the register map (Table 3-4, chap. 3.4) with signal
host_adr. As stated in chap. 5.1 the two LSBs are ignored by CAN-CTRL.
AHB requires address alignment if more than one byte is accessed. For halfword accesses haddr[0]=0b
and for word accesses haddr[1:0]=00b is required. CAN_AMBA_AHB responds with an error using
signal hresp if the address alignment is wrong. A correct AHB master will never command such wrong
accesses. CAN_AMBA_AHB is a little-endian component. See chap. 5.1.3 and Table 5-2 for details.
Table 5-2 AHB Signals Mapping to CAN-CTRL
haddr[1:0] host_wr_b
hsize
host_rd_b
000b 00b 1110
000b 01b 1101
000b 10b 1011
000b 11b 0111
001b 00b 1100
001b 10b 0011
010b 00b 0000

CAN_AMBA_AHB is designed as 32 bit AHB wrapper and therefore supports byte, halfword or word
accesse (hsize = 000b, 001b or 010b). Other values are answered with an error using signal hresp.
All accesses can be made in a random way. CAN_AMBA_AHB does not require specific burst accesses
and therefore signal hburst is not used. Protected accesses (hprot) or locked accesses (hmastlock) are
not supported and therefore these signals are not used too.
Transfer types defined by htrans are supported but both types NONSEQ and SEQ will result in single
unrelated accesses. CAN_AMBA_AHB can not draw any advantage from burst accesses. Types IDLE
and BUSY will result in no access. No access will be done also if hsel=0.
Each AHB slave signals hready_out=1 if an access is completed. The AHB decoder collects all
hready_out signals from all AHB slaves and generates a final hready signal. This final hready needs to
be connected to the AHB master and to the inputs hready_in of all AHB slaves.
As stated in chap. 5.1.3 a write access to TBUF or ACF has to access a full 32 bit wide word
(hsize=010b). If not then an error is reported using signal hresp and the access is not executed.

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6. Functional Description

Figure 6-1 Block Diagram

6.1 CAN-CTRL Core Basic Block (can_core_nobuf)

6.1.1 Bit Timing Logic (BTL)

The BTL monitors the bus and synchronizes the internal actions to the bit stream on the CAN bus. Hard
synchronization is executed if a “recessive-to-dominant“ bus line transition occurs at the beginning of a
message. Re-synchronization takes place on further “recessive-to-dominant“ transitions during the
reception of a message. The timing registers (provided by host_interface) control the time segments to
compensate propagation delay times and phase shifts and define the sample point.
The BTL also includes the Baud Rate Prescaler. The external system clock will be divided by a
programmed value. The resulting period is called time quanta (TQ).

6.1.2 Transceiver Logic (TCL)

The TCL consists of the protocol state machine. It controls all functions for the rreception and
transmission of frames:

 checking of received bits and transferring to the receive buffer

 generation of bits to transmit to the bus (ID-, RTR-, IDE-, DLC-, Data-, CRC-, …)

 arbitration

 stuff bit handling

 error handling

 generation of error and overload frames

6.1.3 Interface Management Logic (IML)

The Interface Management Logic controls the behavior of the entire core depending on the commands
(register settings in host interface). The IML generates the addresses for the message buffers and
provides interrupts and status information to the host controller.

6.1.4 Error Management Logic (EML)

The EML consists of counters for receive and transmit errors. The counters are controlled depending of
the corresponding type of errors (Bit Error, Stuff Error, Form Error, CRC Error, and Acknowledgement
Error).

6.1.5 Status Buffer

The status buffer stores the header bits of the received messages. This information is needed on-the-fly
for the protocol handling and is later stored into the RBUF.

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6.2 CAN-CTRL Core Wrapper (can_ctrl)

6.2.1 Host Interface

The host interface includes control and status register bits. This includes the register map (Table 3-4)
except for the RBUF, TBUF and ACF.

6.2.2 Receive Buffer (RBUF)

RBUF contains the memory for the receive buffer. The number of RBUF slots is configurable before
synthesis by a generic parameter.

6.2.3 Transmit Buffer (TBUF)

The TBUF consists of the Primary Transmit Buffer PTB and the Secondary Transmit Buffer STB. The
PTB has a higher priority than the STB. A PTB transmission will suspend an STB transmission and is
executed first. The CAN protocol rules require that an STB transmission that is written to the CAN bus
must not be interrupted. Therefore, the PTB transmission will start afterwards (after the interframe
space).
The number of the STB slots is configurable before synthesis by a generic parameter from 0 to 16
message slots. The architecture is FIFO like.

6.2.4 Acceptance Filters (ACF)

The ACF consists of the control logic for acceptance filtering and the filter memory blocks.
The number of the acceptance filters ACF is configurable before synthesis by a generic parameter from 1
to 16 filters.

6.3 Buffer Memories

The CAN-CTRL core uses memories for the RBUF, PTB, STB and ACF. The HDL source code includes a
configurable memory model used by all of these components. This memory model supports FPGA Block
RAM or Distributed RAM which can be selected using synthesis parameters (chap. 0) individually for
each component.
For ASIC synthesis both supported memory models will synthesize to flipflops which is quite area-
consuming and inefficient for bigger memory sizes. For this purpose it is suggested to replace the HDL
source file containing these memory models (memory.v(hd)) by another one making an instance of the
preferred RAM IP core.

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7. CAN Multicore
The CAN multicore is an optional feature which can be purchased additionally.
The delivery package may include a container for multiple CAN-CTRL instances: the CAN multicore. This
container includes a generic parameter which defines the number of CAN-CTRL instances inside of the
container. All CAN-CTRL instances are connected to the same host controller data bus but provide
individual interrupt signals.

Figure 7-1 CAN Multicore – Connection Options to the CAN Bus

As can be seen in Figure 7-1 each CAN-CTRL instance can be connected to a separate CAN bus. As an
alternative some or all of the CAN-CTRL instances can be connected to the same CAN bus. Then it is
possible to use individual CAN bus transceivers or to connect the txd and rxd signals as shown in the
right example in Figure 7-1.
At runtime all CAN-CTRL instances are fully independent, but for synthesis all of them share the same
configuration settings in the can_package.v(hd). Therefore all instances have the same hardware
features if they are synthesized together. If it is required to have individual hardware configurations of the
CAN-CTRL instances then it is recommended to do individual synthesis for each instance and connect
them in a similar way as the CAN multicore container does it.

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8. Testbenches
The testbenches can be used to test the functionality of the core during pre- and post-synthesis
simulation.
If a testbench finishes without an error then “Simulation successful!” is written to the simulator console.
Additionally to this some statistical information is given.
The testbench file list can be found in the folder /tb in Table 9-1.

8.1 Three-node Environment

8.1.1 Tbench
The “tbench” test examines the host controller interface and the most important features offered by the
core to a host. It should be noted that the complete, exhaustive testing of the core has been done for
verification purposes, but it is not fully included in the testbench delivered.
The “tbench” test presents an example CAN communication including source comments. Figure 8-1
depicts the concept of the testbench. Each node has its own clock generator and error injector. A master
(tb) controls the slave testbench processes (tbslave) for each node. There are two test vectors included:
 example CAN communication, for start-up. This test is enabled when the constant (parameter)
“testvec_example” is equal 1. The “testvec_example” can be found in the header of the
tbench.v(vhd) file.
 detailed set of vectors to test the most important features and to check the components
configured by the pre-synthesis settings (NR_OF_RBUFS, etc.) For more detailed test vector
description refer to the testbench source: “tbench.v(hd)”. This test is executed when the constant
(parameter) “testvec_postsyn” is equal 1. The “testvec_postsyn” can be found in the header of
the tbench.v(vhd) file.
Tests can be turned on/off and comments are included at the beginning of the testbench source code.
Search in tbench.v(hd) for the string “START HERE” to get an entry point into the test bench.
The delivery package includes only a small, but sufficient set of tests in the three-node testbench. The
CAN-CTRL core has been exhaustively tested with the three-node testbench, but these testcases are not
included in the delivery package.

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Figure 8-1 Concept of /tb/tbench.v(hd)

8.2 CAN Multicore Testbench

For the CAN multicore container (chap. 7) a simple testbench is included in the delivery package. It
connects 3 CAN multicore containers to one single CAN bus. Each container includes 2 CAN-CTRL
cores (Figure 8-2).

Figure 8-2 Testbench for the CAN Multicore

The testbench for the CAN multicore verifies the system only with a very basic communication test. This
is sufficient because the CAN-CTRL core has been exhaustively tested.

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9. RTL Source Code Version Supplied Files

The source code of the core is available in VHDL (*.vhd) or Verilog (*.v). Therefore the files are named
using the operator “v(hd)” in Table 9-1.
Files related to the optional CAN multicore (chap. 7) are only included in the release package if
purchased.
Table 9-1 Files

Folder File(s) Description

/doc can-ctrl-usg.pdf This document
ms_tbench_v*.tcl ModelSim simulation: tb/tbench.v(hd)
ms_tbench_multicore_v*.tcl ModelSim simulation: tb/tbench_multicore.v(hd)
ms_init.tcl ModelSim initialization file
cds.lib NC-Sim library definition
nc_tbench_v*.sh NC-Sim simulation: tb/tbench.v(hd)
/scripts
nc_tbench_multicore_v*.sh NC-Sim simulation: tb/tbench_multicore.v(hd)
nc_tbench_netlist_v*.sh NC-Sim tb/tbench.v(hd) invoked with netlist
NC-Sim SDF command files (see
nc_sdf*.cmd
scripts/nc_tbench_netlist_v(hd).sh)
nc_trace.cmd NCSim command file (see scripts/nc_tbench_*.sh)
arithmetic_package.v(hd) Tools for HDL source calculations
can_package_synparam.v(hd) Configurable synthesis parameters (actual selection)
can_package.v(hd) Common settings and declarations
--- Inner core ---
btl.v(hd) Bit timing logic
eml.v(hd) Error management logic
iml.v(hd) Interface management logic
memory.v(hd) Memory model (BlockRAM, DistributedRAM)
crc_check.v(hd) CRC checker
/src tcl.v(hd) Transceiver logic
can_core_nobuf.v(hd) CAN-CTRL core without message buffers
acf_ctrl.v(hd) acceptance filters
status_buffer.v(hd) Receive buffer: status buffer (frame header)
rbuf.v(hd) Receive buffer
tbuf.v(hd) Transmit buffer (PTB and STB)
host_interface.v(hd) Host interface
ram_ctrl.v(hd) Controller for internal buffer RAM
can_ctrl.v(hd) IP core top-level module
can_multicore.v(hd) Container for multiple instances of the IP core
can_amba_ahb.v* AMBA AHB interface
/src/interface can_amba_apb.v* AMBA APB interface
can_sync_08.v* Synchronous 8 bit host interface
VHDL Package for extended test features for Bosch
can_bosch_tb_package.vhd
testbench
tbench.v(vhd) Behavioral testbench
tbench_package.v(hd) Behavioral testbench (package)
/tb tbench_multicore.v(hd) Behavioral testbench for multicore container
tbench_multicore_package.v(hd) Behavioral testbench for multicore container (package)
clk_gen.v(hd) Clock generator for /tb/tbench.v(hd)
can_bus.v(hd) CAN bus model for /tb/tbench.v(hd)

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Folder File(s) Description

can_tran.v(hd) CAN transceiver model for /tb/tbench.v(hd)
can_error.v(hd) CAN bus error stimulation for /tb/tbench.v(hd)
/syn * Example synthesis projects
The software example is specific for the compiler “IAR embedded workbench” for a MSP430-compatible
microcontroller. It can be easily adapted for different host controllers.
msp430/example/can.h Definition header file for host controller
/software
msp430/example/isr_compat.h Definition header file for host controller
msp430/example/mcu.h Definition header file for host controller
msp430/example/example.c Example application for host controller
can-ctrl_cbc.tar.gz CAN Bit timing Calculator (zipped Windows software tool)

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10. How to use the CAN-CTRL core

The following subchapters include a brief description on how to use the CAN-CTRL core. These
subchapters do not replace the detailed descriptions, but are dedicated to give a quick look at the
possible core’s usage.

10.1 How to set up the HDL environment

 Compile the sources to your working library.
 Make an instance of the IP core top module can_core in your system (file
src/can_core.v(hd)).
 If simulation is required it is very important to use a CAN bus model. It is suggested to use the
model from tb/can_bus.v(hd) as a basis for your own modifications.
It should be noted that the bus model tb/can_bus.v(hd) is used in the testbench, therefore it’s
strongly recommended to make a copy of that file before modifying.

10.2 How to use the CAN-CTRL core as microcontroller peripheral

 Make an instance of the CAN -CTRL core as a peripheral component (chapter 10.1).
 Have a look at can.h and example.c in the directory software/example.
 Refer to chapter 10.3 for further hints.

10.3 How to transmit or receive a frame

 Set up the CAN bit timings (chapter 4).
After a hardware reset the CAN-CTRL core is automatically configured to f BUS  1 Mbaud with
a system clock of 16 MHz .
 If necessary: Enable / Disable required interrupts.
o For transmission: TPIE or TSIE.
o For reception: RIE and if necessary RAFIE, RFIE, ROIE
 For transmission:
o Write a frame to a transmit buffer (PTB or STB).
o Enable the transmission: use TPE or TSONE or TSALL.
o If necessary wait for the selected interrupt.
 For reception:
o Wait for the selected interrupt.
o Read the received frame from the RB and use register RCTRL to determine the type of
frame.
 Additional features:
o Acceptance filter (section 3.6.2 )
o Buffer control: TSSTAT and RSTAT
o Error handling (bits EIE, EIF, bits EWL register ERRINT, RECNT, TECNT, EALCAP)

10.4 How to learn about the testbench usage

 The 3-node testbench is documented in the chapter 8.1.1 .
 Search in tbench.vhd for the string “START HERE” to get an entry point into the test bench.
 Follow the instructions in the comments and use the string search to jump to the pointed
locations.

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11. Support
Every effort has been made to ensure that this core functions correctly. If a problem is encountered
please contact CAST:
CAST, Inc.
11 Stonewall Court
Woodcliff Lake, New Jersey 07677 USA
Technical Support Hotline: +1-201-391-8300 ext. 2
Fax: +1-201-833-2682
E-mail: [email protected]
URL: www.cast-inc.com

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