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Lab 4 DSD

1) The document describes a digital systems design lab where the student implemented a 4-bit Booth multiplier and an 8-bit binary multiplier in Verilog. 2) For the 4-bit Booth multiplier, the student wrote the main code and testbench to multiply 4-bit numbers. 3) For the 8-bit multiplier, the student expanded the design to multiply 8-bit numbers by modifying the main code and testbench. 4) In conclusion, the student verified the 4-bit and 8-bit multiplier modules through simulation and achieved the goals of the lab.

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30 views6 pages

Lab 4 DSD

1) The document describes a digital systems design lab where the student implemented a 4-bit Booth multiplier and an 8-bit binary multiplier in Verilog. 2) For the 4-bit Booth multiplier, the student wrote the main code and testbench to multiply 4-bit numbers. 3) For the 8-bit multiplier, the student expanded the design to multiply 8-bit numbers by modifying the main code and testbench. 4) In conclusion, the student verified the 4-bit and 8-bit multiplier modules through simulation and achieved the goals of the lab.

Uploaded by

Rohaid
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Digital System Design

CPE – 344
Lab 4

Name Rohaid Ahmed Mirza

Registration Number FA19-BCE-006

Class BCE – 7A

Instructor’s Name Sir Bilal Qasim


In lab 1:
Main Code:
module booth4bit(X, Y, Prod);
parameter n = 4;
parameter x = 2 * n;
input signed [n-1:0] X, Y;
output signed [x-1:0] Prod;
reg signed [x-1:0] Prod;
reg signed [x-1:0] A;
reg [1:0] temp;
integer i;
reg Q;
reg [n-1:0] Y1;
always @ (X, Y)
begin
A[x-1:n] = 0;
A[n-1:0] = Y;
Q = 1'd0;
for (i = 0; i < n; i = i + 1)
begin
temp = {X[i], Q};
Y1 = (- Y);
if (temp == 2'b01)
begin
A[x-1:n] = A[x-1:n] + Y;
A = A >> 1;
end
else if(temp == 2'b10)
begin
A[x-1:n] = A[x-1:n] + Y1;
A = A >> 1;
end
else if(temp == 2'b11)
begin
A = A >> 1;
end
else if(temp == 2'b00)
begin
A = A >> 1;
end

A[x-1] = A[x-2];
Q = X[i];
Prod = A;
end

end

endmodule
Testbench:
module test;

// Inputs
reg [3:0] X;
reg [3:0] Y;

// Outputs
wire [7:0] Prod;

// Instantiate the Unit Under Test (UUT)


booth4bit uut (
.X(X),
.Y(Y),
.Prod(Prod)
);

initial begin
X = 7;
Y = 4;
#100;
X = 7;
Y = -4;
#100;
X = -7;
Y = 4;
#100;
X = -7;
Y = -4;

end

endmodule
In lab 2:

Post lab:
8-Bit Booth Multiplier:
Main Code:
module bomulti(X, Y, Prod);
parameter n = 8;
parameter x = 2 * n;
input signed [n-1:0] X, Y;
output signed [x-1:0] Prod;
reg signed [x-1:0] Prod;
reg signed [x-1:0] A;
reg [1:0] temp;
integer i;
reg Q;
reg [n-1:0] Y1;
always @ (X, Y)
begin
A[x-1:n] = 0;
A[n-1:0] = Y;
Q = 1'd0;
for (i = 0; i < n; i = i + 1)
begin
temp = {X[i], Q};
Y1 = (- Y);
if (temp == 2'b01)
begin
A[x-1:n] = A[x-1:n] + Y;
A = A >> 1;
end
else if(temp == 2'b10)
begin
A[x-1:n] = A[x-1:n] + Y1;
A = A >> 1;
end
else if(temp == 2'b11)
begin
A = A >> 1;
end
else if(temp == 2'b00)
begin
A = A >> 1;
end

A[x-1] = A[x-2];
Q = X[i];
Prod = A;
end
end
endmodule

Testbench:
module test;
reg [7:0] X;
reg [7:0] Y;
wire [15:0] Prod;
bomulti uut (
.X(X),
.Y(Y),
.Prod(Prod));
initial begin
X = 25; Y = 15;
#50;
X = 25; Y = -15;
#50;
X = -25; Y = 15;
#50;
X = -25;
Y = -15;
#50; $finish;
end
endmodule
8-Bit Binary Multiplier:

Conclusion:
In this lab, we implemented 4-bit booth multiplier. We also designed 8-bit multiplier by Verilog
programming. We verified our modules with simulations.

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