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Digital Design and Computer Organization Project Final Presentation

The document describes a Moore finite state machine (FSM) that detects the binary sequence "1011" from a digital input. It provides the circuit diagram and iVerilog code for the Moore FSM, which has 5 states and will output a 1 when it reaches the final state after detecting the sequence. Test waveforms from the FSM simulation in GTKWave are also included to show it correctly detecting two instances of the "1011" sequence.

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Himanshu
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83 views7 pages

Digital Design and Computer Organization Project Final Presentation

The document describes a Moore finite state machine (FSM) that detects the binary sequence "1011" from a digital input. It provides the circuit diagram and iVerilog code for the Moore FSM, which has 5 states and will output a 1 when it reaches the final state after detecting the sequence. Test waveforms from the FSM simulation in GTKWave are also included to show it correctly detecting two instances of the "1011" sequence.

Uploaded by

Himanshu
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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Digital Design and Computer Organization

(UE21CS251A) ~ MINI PROJECT

Moore FSM Sequence Detector

~Abstract
~Circuit Diagram
~Moore FSM layout
~iVerilog Code
~Gtkwave Output

PARTICIPANTS
 HIMANSHU NANDA – PES2UG21CS915
 KUSHAAGRA SHRIVASTAVA – PES2UG21CS917
 SATYAM – PES2UG21CS485

1
Abstract

Automata Theory is a tool which is used in multidisciplinary computing


and scientific research. It is the basis behind the traditional model of
computation and is used for many purposes such as controller circuit
design, sequential circuit design etc.

Sequence Detector: A Sequence detector is a sequential state machine used


to detect consecutive bits in a binary string. This technical paper examines
various sequences and gives output as 1 if the sequence is detected. The
types of the sequence examined are overlapping sequences. Realization of
the designed algorithm for detecting the sequence is with the help of flip-
flops. The flip-flops help to detect the pattern in the given string.

It is basically classified in two types:

Overlapping Sequence Detector: In a Sequence detector that allows


overlap, the final bits of one sequence can be the start of another sequence.
For example, will be an 1101sequence detector. It raises an output of 1
when the last 4 binary bits received are 1101.

Non-Overlapping Sequence Detector: The sequence detector with no


overlap allowed resets itself to the start state when the sequence has been
detected. After the initial sequence 1101 has been detected, the detector with
no overlap resets and starts searching for the initial 1 of the next sequence.

Fig. Sequence Detector

2
Moore machine: Simple Moore machines have one input and one output.
Output depends only upon the present state. Generally, it has more states
than Mealy Machine. Input change can cause change in output change as
soon as logic is done. In Moore machines, more logic is needed to decode
the outputs since it has more circuit delays.

Fig. A Simple Moore FSM


About
The Moore FSM keeps detecting a binary sequence from a digital input and
the output of the FSM goes high only when a “1011” sequence is detected.
The Moore FSM’s output depends on only the current state of the FSM.

3
Circuit Diagram

Moore FSM Layout

 If the output depicted in the figure is 1 then the machine is in its final
state.

4
iVerilog Code

`timescale 1ns / 1ps

module seq_detector(
input x,clk,reset,
output reg z
);

parameter S0 = 0 , S1 = 1 , S2 = 2 , S3 = 3 , S4 = 4;
reg [2:0] PS,NS ;

always @(posedge clk or posedge reset)


begin
if(reset)
PS <= S0;
else
PS <= NS ;
end
always @(PS, x)
begin
case(PS)
S0 : begin
NS = x ? S1 : S0 ;
$display(PS);
end
S1 : begin
NS = x ? S1 : S2 ;
$display(PS);
end
S2 : begin
NS = x ? S3 : S0 ;
$display(PS);
end
S3 : begin
NS = x ? S4 : S2 ;
$display(PS);
end
S4 : begin
NS = x ? S1 : S2 ;
$display(PS);
end
default: NS = S0;
endcase
end
always @(PS)
begin

5
case(PS)
S4: z = 1;
default: z = 0;
endcase
end
endmodule

Testbench
`timescale 1ns / 1ps

module testbench;
// Inputs
reg x;
reg clk;
reg reset;
// Outputs
wire z;
// Instantiate the Unit Under Test (UUT)
seq_detector uut (
.x(x),
.clk(clk),
.reset(reset),
.z(z)
);

always #5 clk = ~ clk;

initial begin
$dumpfile("dump.vcd");
$dumpvars(1, testbench);

fork
clk = 1'b0;
reset = 1'b1;
#15 reset = 1'b0;
begin
#12 x = 0;#10 x = 0 ; #10 x = 1 ; #10 x = 0 ;
#12 x = 1;#10 x = 1 ; #10 x = 0 ; #10 x = 1 ;
#12 x = 1;#10 x = 0 ; #10 x = 0 ; #10 x = 1 ;
#12 x = 0;#10 x = 1 ; #10 x = 1 ; #10 x = 0 ;
#10 $finish;
end
join
end
endmodule

6
Gtkwave~ Outputs

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