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OPA134, OPA2134, OPA4134

SBOS058A – DECEMBER 1997 – REVISED OCTOBER 2015

OPAx134 SoundPlus™ High Performance Audio Operational Amplifiers

1 Features 3 Description
•
1 Superior Sound Quality The OPA134 series are ultra-low distortion, low-noise
operational amplifiers fully specified for audio
• Ultra Low Distortion: 0.00008% applications. A true FET input stage is incorporated to
• Low Noise: 8 nV/√Hz provide superior sound quality and speed for
• True FET-Input: IB = 5pA exceptional audio performance. This, in combination
• High Speed: with high output drive capability and excellent DC
performance, allows for use in a wide variety of
– Slew Rate: 20 V/µs demanding applications. In addition, the OPA134 has
– Bandwidth: 8 MHz a wide output swing, to within 1 V of the rails,
• High Open-Loop Gain: 120 dB (600 Ω) allowing increased headroom and making it ideal for
use in any audio circuit.
• Wide Supply Range: ±2.5 V to ±18 V
• Single, Dual, and Quad Versions The OPA134 SoundPlus™ audio operational
amplifiers are easy to use and free from phase-
inversion and the overload problems often found in
2 Applications common FET-input operational amplifiers. They can
• Professional Audio and Music be operated from ±2.5-V to ±18-V power supplies.
• Line Drivers Input cascode circuitry provides excellent common-
mode rejection and maintains low input bias current
• Line Receivers over its wide input voltage range, minimizing
• Multimedia Audio distortion. OPA134 series operational amplifiers are
• Active Filters unity-gain stable and provide excellent dynamic
behavior over a wide range of load conditions,
• Preamplifiers
including high load capacitance. The dual and quad
• Integrators versions feature completely independent circuitry for
• Crossover Networks lowest crosstalk and freedom from interaction, even
when overdriven or overloaded.
THD+Noise vs Frequency
Single and dual versions are available in 8-pin DIP
0.01 and SO-8 surface-mount packages in standard
VO = 10Vrms
RL = 2kW configurations. The quad is available in 14-pin DIP
and SO-14 surface mount packages. All are specified
for –40°C to 85°C operation. A SPICE macromodel is
THD+Noise (%)

0.001
available for design analysis.
VS = ±16
Device Information(1)
0.0001
PART NUMBER PACKAGE BODY SIZE (NOM)
SOIC (8) 3.91 mm × 4.90 mm
VS = ±17 VS = ±18
OPA134
PDIP (8) 6.35 mm × 9.81 mm
0.00001
20 100 1k 10k 20k SOIC (8) 3.91 mm × 4.90 mm
OPA2134
Frequency (Hz) PDIP (8) 6.35 mm × 9.81 mm
OPA4134 SOIC (14) 3.91 mm × 8.65 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
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Table of Contents
1 Features .................................................................. 1 8 Application and Implementation ........................ 15
2 Applications ........................................................... 1 8.1 Application Information............................................ 15
3 Description ............................................................. 1 8.2 Typical Application ................................................. 16
4 Revision History..................................................... 2 9 Power Supply Recommendations...................... 18
5 Pin Configuration and Functions ......................... 3 10 Layout................................................................... 18
6 Specifications......................................................... 4 10.1 Layout Guidelines ................................................. 18
6.1 Absolute Maximum Ratings ...................................... 4 10.2 Layout Example .................................................... 19
6.2 ESD Ratings.............................................................. 4 11 Device and Documentation Support ................. 20
6.3 Recommended Operating Conditions....................... 4 11.1 Device Support .................................................... 20
6.4 Electrical Characteristics........................................... 5 11.2 Documentation Support ....................................... 20
6.5 Typical Characteristics .............................................. 7 11.3 Related Links ........................................................ 20
7 Detailed Description ............................................ 12 11.4 Community Resources.......................................... 21
7.1 Overview ................................................................. 12 11.5 Trademarks ........................................................... 21
7.2 Functional Block Diagram ....................................... 12 11.6 Electrostatic Discharge Caution ............................ 21
7.3 Feature Description................................................. 12 11.7 Glossary ................................................................ 21
7.4 Device Functional Modes........................................ 14 12 Mechanical, Packaging, and Orderable
Information ........................................................... 21

4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Original (September 2000) to Revision A Page

• Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section. ................................................................................................. 1

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5 Pin Configuration and Functions

OPA134: P and D Packages

8-Pin PDIP and 8-Pin SOIC OPA2134: P and D Packages
Top View 8-Pin PDIP and 8-Pin SOIC
Top View

Offset Trim 1 8 Offset Trim

Out A 1 8 V+
–In 2 7 V+
–In A 2 A 7 Out B
+In 3 6 Output
+In A 3 B 6 –In B
V– 4 5 NC
V– 4 5 +In B

OPA4134: P and D Packages

14-Pin PDIP and 14-Pin SOIC
Top View

Out A 1 14 Out D

–In A 2 13 –In D
A D
+In A 3 12 +In D

V+ 4 11 V–

+In B 5 10 +In C
B C
–In B 6 9 –In C

Out B 7 8 Out C

Pin Functions: OPA134

PIN
I/O DESCRIPTION
NAME NO.
Offset Trim 1 I Input offset voltage adjust
–In 2 I Inverting input
+In 3 I Noninverting input
V– 4 — Negative power supply
NC 5 — No internal connection. Can be left floating.
Output 6 O Output
V+ 7 — Positive power supply
Offset Trim 8 I Input offset voltage adjust

Pin Functions: OPA2134 and OPA4134

PIN
OPA2134 OPA4134 I/O DESCRIPTION
NAME
NO. NO.
Out A 1 1 O Output channel A
–In A 2 2 I Inverting input channel A
+In A 3 3 I Noninverting input channel A
V+ 8 4 — Positive power supply
+In B 5 5 I Noninverting input channel B
–In B 6 6 I Inverting input channel B
Out B 7 7 O Output channel B
Out C — 8 O Output channel C
–In C — 9 I Inverting input channel C
+In C — 10 I Noninverting input channel C

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Pin Functions: OPA2134 and OPA4134 (continued)

PIN
OPA2134 OPA4134 I/O DESCRIPTION
NAME
NO. NO.
V– 4 11 — Negative power supply
+In D — 12 I Noninverting input channel D
–In D — 13 I Inverting input channel D
Out D — 14 O Output channel D

6 Specifications
6.1 Absolute Maximum Ratings
(1)
over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
Supply voltage, V+ to V– 36 V
Input voltage (V–) –0.7 (V+) +0.7 V
Output short circuit (2) Continuous
Operating temperature –40 125 °C
Junction temperature 150 °C
Lead temperature (soldering, 10 s) 300 °C
Tstg Storage temperature –55 125 °C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Short-circuit to ground, one amplifier per package.

6.2 ESD Ratings

VALUE UNIT
OPA134 in PDIP and SOIC Package, OPA2134 and OPA4134 in PDIP Package
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) ±2000 V
OPA2134 in SOIC Package
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) ±2000
V(ESD) Electrostatic discharge Charged-device model (CDM), per JEDEC specification JESD22- V
±500
C101 (2)
OPA4134 in SOIC Package
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) ±2000
V(ESD) Electrostatic discharge Charged-device model (CDM), per JEDEC specification JESD22- V
±200
C101 (2)

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
VS Supply voltage, VS = (V+) – (V–) ±2.5 ±15 ±18 V
TA Specified temperature –40 85 °C

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6.4 Electrical Characteristics

At TA = +25°C, VS = ±15 V, unless otherwise noted
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
AUDIO PERFORMANCE
G = 1, f = 1 kHz, VO = 3 RL = 2 kΩ 0.00008%
Total Harmonic Distortion + Noise
Vrms RL = 600 Ω 0.00015%
Intermodulation Distortion G = 1, f = 1 kHz, VO = 1 Vp-p –98 dB
(1)
Headroom THD < 0.01%, RL = 2 kΩ , VS = 18 V 23.6 dBu
FREQUENCY RESPONSE
Gain-Bandwidth Product 8 MHz
(2)
Slew Rate ±15 ±20 V/µs
Full Power Bandwidth 1.3 MHz
Settling Time 0.1% G = 1, 10-V Step, CL = 100 pF 0.7 µs
Settling Time 0.01% G = 1, 10-V Step, CL = 100 pF 1 µs
Overload Recovery Time (VIN) × (Gain) = VS 0.5 µs
NOISE
Noise Voltage,
1.2 µVrms
Input Voltage f = 20 Hz to 20 kHz
Noise Noise Density,
8 nV/√Hz
f = 1 kHz
Current Noise Density, f = 1 kHz 3 fA/√Hz
OFFSET VOLTAGE
±0.5 ±2
Input Offset Voltage mV
TA = –40°C to 85°C ±1 ±3 (3)
Input Offset Voltage vs Temperature TA = –40°C to 85°C ±2 µV/°C
Input Offset Voltage vs Power Supply
VS = ±2.5 V to ±18 V 90 106 dB
(PSRR)
DC, RL = 2 kΩ 135
Channel Seperation (Dual, Quad) dB
f = 20 kHz, RL = 2 kΩ 130
INPUT BIAS CURRENT
Input Bias Current (4) VCM = 0 V 5 ±100 pA
See Typical
Input Bias Current vs Temperature (3) ±5 nA
Characteristics
Input Offset Current (4) VCM = 0 V ±2 ±50 pA
INPUT VOLTAGE RANGE
Common-Mode Voltage Range (V–)+2.5 13 (V+)–2.5 V
VCM = –12.5 V to 12.5 V 86 100
Common-Mode Rejection dB
TA = –40°C to 85°C 90
INPUT IMPEDANCE
Differential 1013 || 2 Ω || pF
Common-Mode VCM = –12.5 V to 12.5 V 1013 || 5 Ω || pF
OPEN-LOOP GAIN
RL = 10 kΩ , VO = –14.5 V to 13.8 V 104 120
Open-Loop Voltage Gain RL = 2 kΩ , VO = –13.8 V to 13.5 V 104 120 dB
RL = 600 Ω , VO = –12.8 V to 12.5 V 104 120

(1) dBu = 20*log (Vrms/0.7746) where Vrms is the maximum output voltage for which THD+Noise is less than 0.01%. See THD+Noise text.
(2) Proposed by design.
(3) Proposed by wafer-level test to 95% confidence level.
(4) High-speed test at TJ = 25°C.

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Electrical Characteristics (continued)

At TA = +25°C, VS = ±15 V, unless otherwise noted
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
OUTPUT
RL = 10 kΩ (V–)+0.5 (V+)–1.2
Voltage Output RL = 2 kΩ (V–)+1.2 (V+)–1.5 V
RL = 600 Ω (V–)+2.2 (V+)–2.5
Output Current ±35 mA
Output Impedance, Closed-Loop (5) f = 10 kHz 0.01 Ω
Output Impedance, Open-Loop f = 10 kHz 10 Ω
Short-Circuit Current ±40 mA
Capacitive Lead Drive (Stable See Typical
Operation) Characteristics
POWER SUPPLY
Specified Operating Voltage ±15 V
Operating Voltage Range ±2.5 ±18 V
Quiescent Current (per amplifier) IO = 0 4 5 mA
TEMPERATURE RANGE
Specified Range –40 85 °C
Operating Range –55 125 °C

(5) See Figure 14

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6.5 Typical Characteristics

At TA = 25°C, VS = 15 V, RL = 2 kΩ, unless otherwise noted.

0.1 5
RL G = +1
2kW f = 1kHz
1 RL = 2kW
600W
0.01
THD+Noise (%)

0.1

IMD (%)
0.001 OPA134
G = +10 OP176
0.010
OPA134
0.0001
G = +1 Baseline
VO = 3Vrms 0.001
0.00001 0.0005
10 100 1k 10k 100k 30m 0.1 1 10 30
Frequency (Hz) Output Amplitude (Vpp)

Figure 1. Total Harmonic Distortion + Noise vs Frequency Figure 2. SMPTE Intermodulation Distortion vs Output
Amplitude
0.01 1
VO = 10Vrms VS = ±18V THD < 0.01%
RL = 2kW RL = 2kW OPA134 – 11.7Vrms
f = 1kHz OP176 – 11.1Vrms
0.1
THD+Noise (%)

0.001
THD+Noise (%)

VS = ±16
0.010
OPA134
0.0001 OPA134
OP176

VS = ±17 VS = ±18 0.001

Baseline
0.00001 0.0005
20 100 1k 10k 20k 0.1 1 10 20
Frequency (Hz) Output Amplitude (Vrms)

Figure 3. Total Harmonic Distortion + Noise vs Frequency Figure 4. Headroom – Total Harmonic Distortion + Noise vs
Output Amplitude
0.01 1k
2nd Harmonic
OP176+
Amplitude (% of Fundamentals)

3rd Harmonic
Resistor
Voltage Noise (nV/ÖHz)

0.001 100

00W
=6
RL
0.0001 10
OPA134+
Resistor
= 2kW
RL
0.00001 1
Resistor Noise
VO = 1Vrms Only Vn (total) = Ö(inRS)2 + en2 + 4kTRS
0.000001 0.1
20 100 1k 10k 20k 10 100 1k 10k 100k 1M 10M
Frequency (Hz) Source Resistance (W)

Figure 5. Harmonic Distortion + Noise vs Frequency Figure 6. Voltage Noise vs Source Resistance

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Typical Characteristics (continued)

At TA = 25°C, VS = 15 V, RL = 2 kΩ, unless otherwise noted.
1k 100
RS = 20W
Voltage Noise (nV/ÖHz)
Current Noise (fA/ÖHz)

Noise Voltage (mV)

100 10
Peak-to-Peak
Voltage Noise

10 1
RMS

Current Noise
1 0.1
1 10 100 1k 10k 100k 1M 1 10 100 1k 10k 100k
Frequency (Hz) Noise Bandwidth (Hz)

Figure 7. Input Voltage and Current Noise Spectral Density Figure 8. Input-Referred Noise Voltage vs Noise Bandwidth
vs Frequency
160 0 50

140
40
120 –45 G = +100

Closed-Loop Gain (dB)

30
Voltage Gain (dB)

100
Phase Shift (°)

f
80 –90 20
G = +10
60 10
40 –135
0
20 G G = +1
–10
0 –180

–20 –20
0.1 1 10 100 1k 10k 100k 1M 10M 1k 10k 100k 1M 10M
Frequency (Hz) Frequency (Hz)

Figure 9. Open-Loop Gain and Phase vs Frequency Figure 10. Closed-Loop Gain vs Frequency
120 160
RL = ∞
100 –PSR
Channel Separation (dB)

140
PSR, CMR (dB)

80

60 120
Dual and quad devices. RL = 2kW
G = 1, all channels.
40 +PSR Quad measured channel
100 A to D or B to C—other
20 CMR combinations yield improved
rejection.
0 80
10 100 1k 10k 100k 1M 100 1k 10k 100k
Frequency (Hz) Frequency (Hz)

Figure 11. Power Supply and Common-Mode Rejection vs Figure 12. Channel Separation vs Frequency
Frequency

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Typical Characteristics (continued)

At TA = 25°C, VS = 15 V, RL = 2 kΩ, unless otherwise noted.
30 10
Maximum output voltage Note: Open-Loop

Closed-Loop Output Impedance (W)

VS = ±15V without slew-rate Output Impedance
induced distortion 1 at f = 10kHz is 10W
Output Voltage (Vp-p)

20
0.1

G = +100
0.01
10
VS = ±5V G = +10
0.001
G = +2
VS = ±2.5V G = +1
0 0.0001
10k 100k 1M 10M 10 100 1k 10k 100k
Frequency (Hz) Frequency (Hz)

Figure 13. Maximum Output Voltage vs Frequency Figure 14. Closed-Loop Output Impedance vs Frequency
100k 10
High Speed Test
9 High Speed Test
Warmed Up
10k
8
Input Bias Current (pA)

Input Bias Current (pA)

7
1k
6
100 5
Dual
4
10
3
2
1 Single
1
0.1 0
–75 –50 –25 0 25 50 75 100 125 –15 –10 –5 0 5 10 15
Ambient Temperature (°C) Common-Mode Voltage (V)

Figure 15. Input Bias Current vs Temperature Figure 16. Input Bias Current vs Input Common-Mode
Voltage
150 120

RL = 600W
140
RL = 2kW
Open-Loop Gain (dB)

110
CMR, PSR (dB)

130 PSR

120
100
RL = 10kW
110
CMR

100 90
–75 –50 –25 0 25 50 75 100 125 –75 –50 –25 0 25 50 75 100 125
Temperature (°C) Ambient Temperature (°C)

Figure 17. Open-Loop Gain vs Temperature Figure 18. CMR, PSR vs Temperature

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Typical Characteristics (continued)

At TA = 25°C, VS = 15 V, RL = 2 kΩ, unless otherwise noted.
4.3 60 15
VIN = 15V
14
Quiescent Current Per Amp (mA)

13 –55°C
4.2 50

Output Voltage Swing (V)

Short-Circuit Current (mA)
12 25°C
25°C
11 125°C
4.1 40
±I SC 10 85°C

–10
4.0 30 85°C
±I Q –11 125°C
–12
3.9 20 –13 25°C –55°C

–14
VIN = –15V
3.8 10 –15
–75 –50 –25 0 25 50 75 100 125 0 10 20 30 40 50 60
Ambient Temperature (°C) Output Current (mA)

Figure 19. Quiescent Current and Short-Circuit Current vs Figure 20. Output Voltage Swing vs Output Current
Temperature
18 12
Typical production Typical production
16 distribution of packaged distribution of packaged
10
14 units. units.

Percent of Amplifiers (%)

Percent of Amplifiers (%)

12 8

10
6
8

6 4

4
2
2

0 0
–2000
–1800
–1600
–1400
–1200
–1000
–800
–600
–400
–200
0
200
400
600
800
1000
1200
1400
1600
1800
2000

0.5

1.5

2.5

3.5

4.5

5.5

6.5

7.5

8.5

9.5

10.5

12.5
11.5
Offset Voltage (V) Offset Voltage Drift (µV/°C)

Figure 21. Offset Voltage Production Distribution Figure 22. Offset Voltage Drift Production Distribution
50mV/div

5V/div

200ns/div 1μs/div

Figure 23. Small-Signal Step Response G = 1, CL = 100 pF Figure 24. Large-Signal Step Response G = 1, CL = 100 pF

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Typical Characteristics (continued)

At TA = 25°C, VS = 15 V, RL = 2 kΩ, unless otherwise noted.
100 60

50 G = +1
Settling Time (µs)

10 0.01% 40

Overshoot (%)
G = –1

30
0.1%
1 20

10 G = ±10

0.1 0
±1 ±10 ±100 ±1000 100pF 1nF 10nF
Closed-Loop Gain (V/V) Load Capacitance

Figure 25. Settling Time vs Closed-Loop Gain Figure 26. Small-Signal Overshoot vs Load Capacitance

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7 Detailed Description

7.1 Overview
The OPA134 series are ultra-low distortion, low-noise operational amplifiers fully specified for audio applications.
A true FET input stage is incorporated to provide superior sound quality and speed for exceptional audio
performance. This, in combination with high output drive capability and excellent DC performance, allows for use
in a wide variety of demanding applications. In addition, the OPA134 has a wide output swing, to within 1 V of
the rails, allowing increased headroom and making it ideal for use in any audio circuit.

7.2 Functional Block Diagram

Input Offset
Adjust
(OPA134 only)

+IN +
Output
-IN ±

Input Offset
Compensation
Adjust
(OPA134 only)

7.3 Feature Description

7.3.1 Total Harmonic Distortion

The OPA134 series of operational amplifiers have excellent distortion characteristics. THD+Noise is below
0.0004% throughout the audio frequency range, 20 Hz to 20 kHz, with a 2-kΩ load. In addition, distortion remains
relatively flat through its wide output voltage swing range, providing increased headroom compared to other
audio amplifiers, including the OP176/275.
Headroom is a subjective measurement, and can be thought of as the maximum output amplitude allowed while
still maintaining a low level of distortion. In an attempt to quantify headroom, TI defines very low distortion as
0.01%. Headroom is expressed as a ratio which compares the maximum allowable output voltage level to a
standard output level (1 mW into 600 Ω, or 0.7746 Vrms). Therefore, OPA134 series of operational amplifiers,
which have a maximum allowable output voltage level of 11.7 Vrms (THD+Noise < 0.01%), have a headroom
specification of 23.6 dBu. See Figure 4.

7.3.2 Distortion Measurements

The distortion produced by OPA134 series of operational amplifiers is below the measurement limit of all known
commercially-available equipment. However, a special test circuit can extend the measurement capabilities.
Operational amplifier distortion can be considered an internal error source which can be referred to the input.
Figure 27 shows a circuit which causes the operational amplifier distortion to be 101 times greater than that
which the operational amplifier normally produces. The addition of R3 to the otherwise standard non-inverting
amplifier configuration alters the feedback factor or noise gain of the circuit. The closed-loop gain is unchanged,
but the feedback available for error correction is reduced by a factor of 101, thus extending the resolution by 101.
The input signal and load applied to the operational amplifier are the same as with conventional feedback without
R3. The value of R3 should be kept small to minimize its effect on the distortion measurements.

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Feature Description (continued)

R1 R2

SIG. DIST.
GAIN GAIN R1 R2 R3
1 101 ∞ 1kW 10W
11 101 100W 1kW 11W
R3 OPA134 VO = 3Vrms
R
Signal Gain = 1+ 2
101 101 10W 1kW ∞
R1

R2
Distortion Gain = 1+
R1 II R3
Generator Analyzer
Output Input

Audio Precision IBM PC

RL
System One or
1kW
Analyzer(1) Compatible

NOTE: (1) Measurement BW = 80kHz

Figure 27. Distortion Test Circuit

This technique can be verified by duplicating measurements at high gain or high frequency, where the distortion
is within the measurement capability of the test equipment. Measurements for this data sheet were made with an
Audio Precision distortion and noise analyzer, which greatly simplifies repetitive measurements. The
measurement technique can, however, be performed with manual distortion measurement instruments.

7.3.3 Source Impedance and Distortion

For lowest distortion with a source or feedback network with an impedance greater than 2 kΩ, the impedance
seen by the positive and negative inputs in noninverting applications should be matched. The p-channel JFETs in
the FET input stage exhibit a varying input capacitance with applied common-mode input voltage. In inverting
configurations, the input does not vary with input voltage, because the inverting input is held at virtual ground.
However, in noninverting applications the inputs do vary, and the gate-to-source voltage is not constant. The
effect is increased distortion due to the varying capacitance for unmatched source impedances greater than 2
kΩ.
To maintain low distortion, match unbalanced source impedance with the appropriate values in the feedback
network as shown in Figure 28. Of course, the unbalanced impedance may be from gain-setting resistors in the
feedback path. If the parallel combination of R1 and R2 is greater than 2 kΩ, use a matching impedance on the
noninverting input. As always, minimize resistor values to reduce the effects of thermal noise.
R1 R2

OPA134 VOUT
VIN

If RS > 2kW or R1 II R2 > 2kW

RS = R1 II R2

Figure 28. Impedance Matching for Maintaining Low Distortion in Non-Inverting Circuits

7.3.4 Phase Reversal Protection

The OPA134 series of operational amplifiers are free from output phase-reversal problems. Many audio
operational amplifiers, such as the OP176, exhibit phase-reversal of the output when the input common-mode
voltage range is exceeded. This can occur in voltage-follower circuits, causing serious problems in control loop
applications. The OPA134 series operational amplifiers are free from this undesirable behavior even with inputs
of 10-V beyond the input common-mode range.

Copyright © 1997–2015, Texas Instruments Incorporated Submit Documentation Feedback 13

Product Folder Links: OPA134 OPA2134 OPA4134
OPA134, OPA2134, OPA4134
SBOS058A – DECEMBER 1997 – REVISED OCTOBER 2015 www.ti.com

Feature Description (continued)

7.3.5 Output Current Limit
Output current is limited by internal circuitry to approximately ±40 mA at 25°C. The limit current decreases with
increasing temperature, as shown in Figure 19.

7.4 Device Functional Modes

7.4.1 Noise Performance

Circuit noise is determined by the thermal noise of external resistors and operational amplifier noise. Operational
amplifier noise is described by two parameters: noise voltage and noise current. The total noise is quantified by
the equation:

Vn (total) = (inRS )2 en2 + 4kTRS (1)

With low source impedance, the current noise term is insignificant and voltage noise dominates the noise
performance. At high source impedance, the current noise term becomes the dominant contributor.
Low-noise bipolar operational amplifiers such as the OPA27 and OPA37 provide low voltage noise at the
expense of a higher current noise. However, OPA134 series operational amplifiers provide both low voltage
noise and low current noise. This provides optimum noise performance over a wide range of sources, including
reactive source impedances; refer to Figure 6. Above 2-kΩ source resistance, the operational amplifier
contributes little additional noise; the voltage and current terms in the total noise equation become insignificant
and the source resistance term dominates. Below 2 kΩ, operational amplifier voltage noise dominates over the
resistor noise, but compares favorably with other audio operational amplifiers such as the OP176.

14 Submit Documentation Feedback Copyright © 1997–2015, Texas Instruments Incorporated

Product Folder Links: OPA134 OPA2134 OPA4134

 OPA134, OPA2134, OPA4134
www.ti.com SBOS058A – DECEMBER 1997 – REVISED OCTOBER 2015

8 Application and Implementation

NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.

8.1 Application Information

The OPA134 series operational amplifiers are unity-gain stable, and suitable for a wide range of audio and
general-purpose applications. All circuitry is independent in the dual version, assuring normal behavior when one
amplifier in a package is overdriven or short-circuited. Power supply pins should be bypassed with 10-nF ceramic
capacitors or larger to minimize power supply noise.

8.1.1 Operating Voltage

The OPA134 series of operational amplifiers operate with power supplies from ±2.5 V to ±18 V with excellent
performance. Although specifications are production tested with ±15-V supplies, most behavior remains
unchanged throughout the full operating voltage range. Parameters which vary significantly with operating
voltage are shown in Typical Characteristics.

8.1.2 Offset Voltage Trim

Offset voltage of OPA134 series amplifiers is laser-trimmed, and usually requires no user adjustment. The
OPA134 (single operational amplifier version) provides offset trim connections on pins 1 and 8, identical to 5534
amplifiers. Offset voltage can be adjusted by connecting a potentiometer as shown in Figure 29. This adjustment
should be used only to null the offset of the operational amplifier, not to adjust system offset or offset produced
by the signal source. Nulling offset could change the offset voltage drift behavior of the operational amplifier.
While it is not possible to predict the exact change in drift, the effect is usually small.
V+
Trim Range: ±4mV typ

10nF
100kW
7
2 1
8
OPA134 6
3

4 OPA134 single op amp only.

10nF Use offset adjust pins only to null
offset voltage of op amp—see text.

V–

Figure 29. OPA134 Offset Voltage Trim Circuit

Copyright © 1997–2015, Texas Instruments Incorporated Submit Documentation Feedback 15

Product Folder Links: OPA134 OPA2134 OPA4134
OPA134, OPA2134, OPA4134
SBOS058A – DECEMBER 1997 – REVISED OCTOBER 2015 www.ti.com

8.2 Typical Application

The OPAx134 family offers outstanding dc precision and AC performance. These devices operate up to 36-V
supply rails and offer ultralow distortion and noise, as well as 8-MHz bandwidth and high capacitive load drive.
These features make the OPAx134 a robust, high-performance operational amplifier for high-voltage professional
audio applications.
2.94 k

1 nF
590 499
Input ±
Output
39 nF +

Figure 30. OPA134 2nd Order 30-kHz, Low Pass Filter Schematic

8.2.1 Design Requirements

• Gain = 5 V/V (inverting)
• Low pass cutoff frequency = 30 kHz
• –40 db/dec filter response
• Maintain less than 3-dB gain peaking in the gain versus frequency response

8.2.2 Detailed Design Procedure

The infinite-gain multiple-feedback circuit for a low-pass network function is shown in Figure 30. The voltage
transfer function is:
Output 1 R1R3C2C5
s 2
Input s s C2 1 R1 1 R3 1 R4 1 R3R4C2C5 (2)
This circuit produces a signal inversion. For this circuit the gain at DC and the low pass cutoff frequency are
calculated using Equation 3.
R4
Gain
R1
1
fC 1 R3R 4 C2C5
2S (3)
Software tools are readily available to simplify filter design. WEBENCH® Filter Designer is a simple, powerful,
and easy-to-use active filter design program. The WEBENCH Filter Designer lets you create optimized filter
designs using a selection of TI operational amplifiers and passive components from TI's vendor partners.
Available as a web based tool from the WEBENCH® Design Center, WEBENCH® Filter Designer allows you to
design, optimize, and simulate complete multistage active filter solutions within minutes.

16 Submit Documentation Feedback Copyright © 1997–2015, Texas Instruments Incorporated

Product Folder Links: OPA134 OPA2134 OPA4134

 OPA134, OPA2134, OPA4134
www.ti.com SBOS058A – DECEMBER 1997 – REVISED OCTOBER 2015

Typical Application (continued)

8.2.3 Application Curve

20

Gain (db)
-20

-40

-60
100 1k 10k 100k 1M
Frequency (Hz)

Figure 31. OPA134 2nd Order 30-kHz, Low Pass Filter Response

Copyright © 1997–2015, Texas Instruments Incorporated Submit Documentation Feedback 17

Product Folder Links: OPA134 OPA2134 OPA4134
OPA134, OPA2134, OPA4134
SBOS058A – DECEMBER 1997 – REVISED OCTOBER 2015 www.ti.com

9 Power Supply Recommendations

The OPAx134 is specified for operation from 5 V to 36 V (±2.5 V to ±18 V); many specifications apply from
–40°C to 85°C. Parameters that can exhibit significant variance with regard to operating voltage or temperature
are presented in the Typical Characteristics.

CAUTION
Supply voltages larger than 36 V can permanently damage the device; see the
Absolute Maximum Ratings.

Place 10-nF bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or high-
impedance power supplies. For more detailed information on bypass capacitor placement, see the Layout
Guidelines.

10 Layout

10.1 Layout Guidelines

For best operational performance of the device, use good PCB layout practices, including:
• Noise can propagate into analog circuitry through the power pins of the circuit as a whole and operational
amplifier itself. Bypass capacitors are used to reduce the coupled noise by providing low-impedance power
sources local to the analog circuitry.
– Connect low-ESR, 10-nF ceramic bypass capacitors between each supply pin and ground, placed as
close to the device as possible. A single bypass capacitor from V+ to ground is applicable for single-
supply applications.
• Separate grounding for analog and digital portions of circuitry is one of the simplest and most-effective
methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground planes.
A ground plane helps distribute heat and reduces EMI noise pickup. Make sure to physically separate digital
and analog grounds paying attention to the flow of the ground current. For more detailed information refer to
Circuit Board Layout Techniques, SLOA089.
• In order to reduce parasitic coupling, run the input traces as far away from the supply or output traces as
possible. If these traces cannot be kept separate, crossing the sensitive trace perpendicular is much better as
opposed to in parallel with the noisy trace.
• Place the external components as close to the device as possible. As shown in Layout Example, keeping RF
and RG close to the inverting input minimizes parasitic capacitance.
• Keep the length of input traces as short as possible. Always remember that the input traces are the most
sensitive part of the circuit.
• Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly reduce
leakage currents from nearby traces that are at different potentials.
• Cleaning the PCB following board assembly is recommended for best performance.
• Any precision integrated circuit may experience performance shifts due to moisture ingress into the plastic
package. Following any aqueous PCB cleaning process, baking the PCB assembly is recommended to
remove moisture introduced into the device packaging during the cleaning process. A low temperature, post
cleaning bake at 85°C for 30 minutes is sufficient for most circumstances.

18 Submit Documentation Feedback Copyright © 1997–2015, Texas Instruments Incorporated

Product Folder Links: OPA134 OPA2134 OPA4134

 OPA134, OPA2134, OPA4134
www.ti.com SBOS058A – DECEMBER 1997 – REVISED OCTOBER 2015

10.2 Layout Example

VIN +
RG VOUT

RF

(Schematic Representation)

Place components
Run the input traces close to device and to
as far away from each other to reduce
the supply lines parasitic errors VS+
as possible RF

Offset trim Offset trim

RG
GND ±IN V+ GND

VIN +IN OUTPUT

Use low-ESR, ceramic

V± NC
bypass capacitor

Use low-ESR, GND VOUT

VS±
ceramic bypass Ground (GND) plane on another layer
capacitor

Figure 32. OPA134 Layout Example for the Noninverting Configuration

Copyright © 1997–2015, Texas Instruments Incorporated Submit Documentation Feedback 19

Product Folder Links: OPA134 OPA2134 OPA4134
OPA134, OPA2134, OPA4134
SBOS058A – DECEMBER 1997 – REVISED OCTOBER 2015 www.ti.com

11 Device and Documentation Support

11.1 Device Support

11.1.1 Development Support

11.1.1.1 WEBENCH Filter Designer Tool

WEBENCH® Filter Designer is a simple, powerful, and easy-to-use active filter design program. The WEBENCH
Filter Designer lets you create optimized filter designs using a selection of TI operational amplifiers and passive
components from TI's vendor partners.

11.1.1.2 TINA-TI™ (Free Software Download)

TINA™ is a simple, powerful, and easy-to-use circuit simulation program based on a SPICE engine. TINA-TI is a
free, fully-functional version of the TINA software, preloaded with a library of macro models in addition to a range
of both passive and active models. TINA-TI provides all the conventional dc, transient, and frequency domain
analysis of SPICE, as well as additional design capabilities.
Available as a free download from the Analog eLab Design Center, TINA-TI offers extensive post-processing
capability that allows users to format results in a variety of ways. Virtual instruments offer the ability to select
input waveforms and probe circuit nodes, voltages, and waveforms, creating a dynamic quick-start tool.

NOTE
These files require that either the TINA software (from DesignSoft™) or TINA-TI software
be installed. Download the free TINA-TI software from the TINA-TI folder.

11.1.1.3 TI Precision Designs

The OPAx134 is featured in several TI Precision Designs, available online at
http://www.ti.com/ww/en/analog/precision-designs/. TI Precision Designs are analog solutions created by TI’s
precision analog applications experts and offer the theory of operation, component selection, simulation,
complete PCB schematic and layout, bill of materials, and measured performance of many useful circuits.

11.2 Documentation Support

11.2.1 Related Documentation
For related documentation, see the following:
• EMI Rejection Ratio of Operational Amplifiers, SBOA128
• Circuit Board Layout Techniques, SLOA089

11.3 Related Links

The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.

Table 1. Related Links

TECHNICAL TOOLS & SUPPORT &
PARTS PRODUCT FOLDER SAMPLE & BUY
DOCUMENTS SOFTWARE COMMUNITY
OPA134 Click here Click here Click here Click here Click here
OPA2134 Click here Click here Click here Click here Click here
OPA4134 Click here Click here Click here Click here Click here

20 Submit Documentation Feedback Copyright © 1997–2015, Texas Instruments Incorporated

Product Folder Links: OPA134 OPA2134 OPA4134

 OPA134, OPA2134, OPA4134
www.ti.com SBOS058A – DECEMBER 1997 – REVISED OCTOBER 2015

11.4 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.

11.5 Trademarks
SoundPlus, TINA-TI, E2E are trademarks of Texas Instruments.
TINA, DesignSoft are trademarks of DesignSoft, Inc.
All other trademarks are the property of their respective owners.
11.6 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.

11.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.

12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

Copyright © 1997–2015, Texas Instruments Incorporated Submit Documentation Feedback 21

Product Folder Links: OPA134 OPA2134 OPA4134
 PACKAGE OPTION ADDENDUM

www.ti.com 26-Feb-2016

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)

OPA134PA ACTIVE PDIP P 8 50 Green (RoHS CU NIPDAU N / A for Pkg Type OPA134PA
& no Sb/Br)
OPA134PA3 OBSOLETE PDIP P 8 TBD Call TI Call TI
OPA134PAG4 ACTIVE PDIP P 8 50 Green (RoHS CU NIPDAU N / A for Pkg Type OPA134PA
& no Sb/Br)
OPA134UA ACTIVE SOIC D 8 75 Green (RoHS CU NIPDAU Level-3-260C-168 HR -40 to 85 OPA
& no Sb/Br) 134UA
OPA134UA/2K5 ACTIVE SOIC D 8 2500 Green (RoHS CU NIPDAU Level-3-260C-168 HR -40 to 85 OPA
& no Sb/Br) 134UA
OPA134UA/2K5E4 ACTIVE SOIC D 8 2500 Green (RoHS CU NIPDAU Level-3-260C-168 HR -40 to 85 OPA
& no Sb/Br) 134UA
OPA134UA3 OBSOLETE PDIP P 8 TBD Call TI Call TI
OPA134UAE4 ACTIVE SOIC D 8 75 Green (RoHS CU NIPDAU Level-3-260C-168 HR -40 to 85 OPA
& no Sb/Br) 134UA
OPA134UAG4 ACTIVE SOIC D 8 75 Green (RoHS CU NIPDAU Level-3-260C-168 HR -40 to 85 OPA
& no Sb/Br) 134UA
OPA2134PA ACTIVE PDIP P 8 50 Green (RoHS CU NIPDAU N / A for Pkg Type -40 to 85 OPA2134PA
& no Sb/Br)
OPA2134PAG4 ACTIVE PDIP P 8 50 Green (RoHS CU NIPDAU N / A for Pkg Type -40 to 85 OPA2134PA
& no Sb/Br)
OPA2134UA ACTIVE SOIC D 8 75 Green (RoHS CU NIPDAU Level-3-260C-168 HR -40 to 85 OPA
& no Sb/Br) 2134UA
OPA2134UA/2K5 ACTIVE SOIC D 8 2500 Green (RoHS CU NIPDAU Level-3-260C-168 HR -40 to 85 OPA
& no Sb/Br) 2134UA
OPA2134UA/2K5E4 ACTIVE SOIC D 8 2500 Green (RoHS CU NIPDAU Level-3-260C-168 HR -40 to 85 OPA
& no Sb/Br) 2134UA
OPA2134UAE4 ACTIVE SOIC D 8 75 Green (RoHS CU NIPDAU Level-3-260C-168 HR -40 to 85 OPA
& no Sb/Br) 2134UA
OPA2134UAG4 ACTIVE SOIC D 8 75 Green (RoHS CU NIPDAU Level-3-260C-168 HR -40 to 85 OPA
& no Sb/Br) 2134UA
OPA4134PA OBSOLETE PDIP N 14 TBD Call TI Call TI
OPA4134UA ACTIVE SOIC D 14 50 Green (RoHS CU NIPDAU Level-3-260C-168 HR -40 to 85 OPA4134UA
& no Sb/Br)

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 26-Feb-2016

Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)

OPA4134UA/2K5 ACTIVE SOIC D 14 2500 Green (RoHS CU NIPDAU Level-3-260C-168 HR -40 to 85 OPA4134UA
& no Sb/Br)
OPA4134UA/2K5E4 ACTIVE SOIC D 14 2500 Green (RoHS CU NIPDAU Level-3-260C-168 HR -40 to 85 OPA4134UA
& no Sb/Br)
OPA4134UAE4 ACTIVE SOIC D 14 50 Green (RoHS CU NIPDAU Level-3-260C-168 HR -40 to 85 OPA4134UA
& no Sb/Br)

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

Addendum-Page 2
 PACKAGE OPTION ADDENDUM

www.ti.com 26-Feb-2016

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 3
 PACKAGE MATERIALS INFORMATION

www.ti.com 26-Feb-2016

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
OPA134UA/2K5 SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
OPA2134UA/2K5 SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
OPA4134UA/2K5 SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 26-Feb-2016

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
OPA134UA/2K5 SOIC D 8 2500 367.0 367.0 35.0
OPA2134UA/2K5 SOIC D 8 2500 367.0 367.0 35.0
OPA4134UA/2K5 SOIC D 14 2500 367.0 367.0 38.0

Pack Materials-Page 2
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