AN-877

APPLICATION NOTE
One Technology Way • P.O. Box 9106 • Norwood, MA 02062-9106, U.S.A. • Tel: 781.329.4700 • Fax: 781.461.3113 • www.analog.com

Interfacing to High Speed ADCs via SPI

by the High Speed Converter Division

INTRODUCTION DEFINITION
This application note describes how to use the serial peripheral The SPI port consists of three pins: the serial clock pin (SCLK),
interface (SPI) port on Analog Devices, Inc., high speed converters. the serial data input/output pin (SDIO), and the chip select bar
In addition, this application note defines the electrical, timing, pin (CSB). Optionally, some chips may implement a serial data
and procedural requirements for interfacing to these devices. out pin (SDO), which is referred to as 3-wire mode. To minimize
The implementation is compatible with industry-standard SPI pin count, most chips omit this pin. However, if it is included, it is
ports and employs, at minimum, a 2-wire mode and optional used only for reading data from the device.
chip select.

CSB CSB
SCLK
CONVERTER
SPI SCLK SDIO INTERFACE
CONTROLLER
SDIO

05739-001
Figure 1. Single Device Control in 2-Wire Mode

CSB 0 CSB

CSB 1
SCLK CONVERTER
SPI INTERFACE
CONTROLLER SCLK DEVICE 1

SDIO
SDIO

CSB

SCLK CONVERTER
INTERFACE
SDIO DEVICE 2
05739-013

Figure 2. Multiple Device Control in 2-Wire Mode

Rev. B | Page 1 of 20
AN-877 Application Note

TABLE OF CONTENTS
Introduction................................................................................... 1 Address Bits................................................................................ 6
Definition....................................................................................... 1 Detection of SPI Mode and Pin Mode ......................................... 7
Revision History ............................................................................ 2 Hardware Interfacing ................................................................ 7
SPI Port Pins .................................................................................. 3 Chip Programming........................................................................ 8
Serial Clock (SCLK) .................................................................. 3 Configuration Register (0X 000)................................................ 8
Serial Data Input/Output (SDIO)............................................. 3 Transfer Register (Master-Slave Latching) (0x0FF) ................ 8
Chip Select Bar (CSB)................................................................ 3 Chip ID (0x001)......................................................................... 9
Serial Data Out (SDO) .............................................................. 4 Chip Grade (0x002) ................................................................... 9
Format ............................................................................................ 5 Device Indexing (0x004 and 0x005)......................................... 9
Instruction Phase ....................................................................... 5 Program Registers.................................................................... 10
Read/Write ................................................................................. 5 Programming Example ............................................................... 17
Word Length .............................................................................. 5 Control Register........................................................................... 18
Streaming ................................................................................... 6

REVISION HISTORY
4/2017—Rev. A to Rev. B 4/2007—Initial Version to Rev. A
Change CSB 0 to CSB in Figure 1..................................................1 Updated Format............................................................... Universal
Changes to Figure 2........................................................................1 Changes to Transfer Register Section............................................8
Change to Serial Clock (SCLK) Section........................................3 Changes to Figure 13....................................................................10
Changes to Table 2 Caption ...........................................................6 Added Table 6 ...............................................................................11
Changes to Table 3 Caption ...........................................................8 Added PLL Control (0x00A) Section..........................................11
Changes to Table 4 and Table 5....................................................10 Changes to Table 8........................................................................12
Changes to Table 6 and Table 7....................................................11
Changes to Table 8........................................................................12 12/2005—Revision 0: Initial Version
Changes to Table 9........................................................................13
Changes to Table 10 and Table 11................................................14
Changes to Table 12......................................................................15
Changes to Table 13......................................................................16
Change to Programming Example Section.................................17
Changes to Table 14......................................................................18

Rev. B | Page 2 of 20
Application Note AN-877

SPI PORT PINS

The following sections described the SPI port pins. CHIP SELECT BAR (CSB)
Caution: Refer to specific analog-to-digital converter (ADC) CSB is an active low control that gates the read and write cycles.
data sheets to determine the nominal and absolute maximum There are several modes in which the CSB can be operated. For
logic voltages. situations where the controller has a chip select output or other
SERIAL CLOCK (SCLK) means of selecting multiple devices, this pin can be tied to the
CSB line. When this line is low, the device is selected and infor-
The SCLK pin is the serial shift clock in pin. This pin is mation on the SCLK and SDIO lines is processed. If this pin is
implemented with a Schmitt trigger, to minimize sensitivity to high, the device ignores any information on the SCLK and
noise on the clock line, and it is pulled low by a nominal 50 kΩ SDIO lines. In this manner, multiple devices can be connected
resistor to ground. This pin may stall either high or low. to the SPI port. In cases where only one device is connected, the
SCLK is used to synchronize serial interface reads and writes. CSB line can be optionally tied low and the device is perma-
Input data is registered on the rising edge of this clock and nently enabled. (Tying the CSB line low excludes the possibility
output data transmissions are registered on the falling edge. of resetting the device if an error occurs on the port.) The CSB
Unless otherwise specified, the maximum clock speed of the line can also be tied high to enable secondary function of the
ADC SPI port is 25 MHz. See the specific product data sheet for SPI port. (See the Detection of SPI Mode and Pin Mode section
more information pertaining to SPI speeds supported for a for more details.) CSB is a high impedance line, pulled high by a
particular device. The typical hold time (tDH) is 0 ns, and a nominal 50 kΩ resistor.
minimum setup time (tDS) of 5 ns is required between SCLK CSB may stall high, that is, remain high for multiple clock cycles
and SDIO. (See the specific device data sheet to determine the (see Figure 5) in some configurations to allow for additional
exact interface timing requirements.) To optimize internal and external timing. If three or fewer words (not counting instruction
external timing, the bus is capable of turning around the state of information) are being transmitted through the interface at a
the SDIO line in half an SCLK cycle. This means that, after the time, CSB may stall high between bytes, including the bytes of
address information is passed to the converter requesting a the instruction information. If CSB stalls high in the middle of a
read, the SDIO line is transitioned from an input to an output byte, the state machine is reset and the controller returns to the
within one half of a clock cycle. This ensures that by the time idle state, awaiting the transmission of a new instruction. This
the falling edge of the next clock cycle occurs, data can be safely mechanism allows restoration after a fault has been detected. To
placed on this serial line for the controller to read. If the external detect the reset, at least one and no more than seven serial clocks
controller is insufficiently fast to keep up with the ADC SPI must occur. Once the state machine has entered the idle state,
port, the external device can stall the clock line to add additional the next falling edge of the CSB initiates a new transmission
time allowing for external timing issues. cycle.
SERIAL DATA INPUT/OUTPUT (SDIO) Some devices implement secondary functions with the SPI pins.
The SDIO pin is a dual-purpose pin. The typical role for this pin Typically, these functions include output data format, duty cycle
is as either an input or an output, depending on the instruction stabilizer, or other common features. These pin functions are
being sent (read or write) and the relative position (instruction or enabled by the CSB pin. If the CSB pin is tied high, the SPI
data phase) in the timing frame. During the first phase of a write functions are placed in a high impedance mode. In this mode,
or a read, this pin functions as an input that passes information secondary functions are then turned on, allowing control of
to the internal state machine. If the command is determined to features on-chip, without requiring the SPI to operate. These
be a read command, the state machine changes this pin (SDIO) features vary by device. Therefore, the individual device data
to an output, which then passes data back to the controller. (See sheet must be consulted to determine if this feature is supported
tEN_SDIO and tDIS_SDIO in Table 1.) If the device includes an SDO pin and what it controls.
and the configuration register is set to take advantage of it, the SDO For applications to be controlled by the SPI port, the secondary
becomes active instead of the SDIO pin changing to an output. function takes priority until the device has been accessed by the SPI
At all other times, the SDO pin remains in a high impedance state. port. By extension, any activity on the SCLK, SDIO, and SDO (if
If the command is determined to be a write command, the provided) is interpreted as a secondary function until the chip has
SDIO pin remains an input for the duration of the instruction. been accessed by the SPI port. Therefore, the chip needs to be
initialized as soon after power up as practical. (See the Detection of
SPI Mode and Pin Mode section for more details.)

Rev. B | Page 3 of 20
AN-877 Application Note
SERIAL DATA OUT (SDO) Table 1. Serial Timing Specifications 1
To determine if a device supports the SDO pin, refer to the device Symbol Description
data sheet. If SDO is present, it is in a high impedance state, unless tDS Setup time between data and rising edge of SCLK.
data is actively being shifted on this pin to allow tying multiple tDH Hold time between data and rising edge of SCLK.
devices together at the receiving end. Additionally, data is shifted tCLK Period of the clock.
out on the first falling edge of SCLK after the instruction phase is tS Setup time between CSB and SCLK.
complete. When data is returned to the controller, the information tH Hold time between CSB and SCLK.
is placed in the output shifters, within the time period between the tHI Minimum period that SCLK needs to be in a logic
last rising edge of SCLK associated with the instruction phase and high state.
the immediately next falling edge. This can be nominally 20 ns tLO Minimum period that SCLK needs to be in a logic
when operating at 25 MHz. low state.
tEN_SDIO Minimum time it takes the SDIO pin to switch
CSB CSB between an input and an output relative to SCLK
SCLK CONVERTER
INTERFACE
falling edge.
SPI SCLK SDIO tDIS_SDIO Minimum time it takes the SDIO pin to switch
CONTROLLER
SDO SDO HIGH-Z WHEN between an output and an input, relative to SCLK
SDI
NOT USED OR
INACTIVE rising edge.
05739-002

1 See device data sheet for minimum and maximum ratings.

Figure 3. 3-Wire Control

tDS tHI tCLK tH

tS tDH tLO
CSB

SCLK DON'T CARE DON'T CARE

05739-003
SDIO DON'T CARE R/W W1 W0 A12 A11 A10 A9 A8 A7 D5 D4 D3 D2 D1 D0 DON'T CARE

Figure 4. Setup and Hold Timing Measurements

CSB

SCLK DON'T CARE DON'T CARE

SDIO DON'T CARE R/W W1 W0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 DON'T CARE

05739-011
16-BIT INSTRUCTION HEADER REGISTER (N) DATA REGISTER (N–1) DATA REGISTER (N–2) DATA

MSB-FIRST 16-BIT INSTRUCTION, 3 BYTES DATA WITH STALLING

Figure 5. Most Significant Bit (MSB)-First Instruction and Data with Stalling

CSB

SCLK DON'T CARE

SDIO DON'T CARE R/W W1 W0 A11 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 DRIVEN OUTPUT DATA STREAM R/W W1 . . .

16-BIT INSTRUCTION HEADER REGISTER (N) DATA REGISTER (N – 1) DATA REGISTER (N – 2) DATA REGISTER (N – 3) DATA

MSB FIRST 16-BIT READ INSTRUCTION, 4 BYTES DATA 4-WIRE

SCLK SCLK

OUTPUT DRIVER OFF OUTPUT DRIVER ON OUTPUT DRIVER ON OUTPUT DRIVER OFF
05739-012

tEN_SDIO tDIS_SDIO

Figure 6. Typical SDIO Output Enable and Disable Timing

Rev. B | Page 4 of 20
Application Note AN-877

FORMAT
The falling edge of CSB, in conjunction with the rising edge of When the first bit in the data stream is low, a write phase is entered.
SCLK, determines the start of framing. Once the beginning of the At the completion of the instruction phase, the internal state
frame has been determined, timing is straightforward. The first machine uses the information provided to decode the internal
phase of the transfer is the instruction phase, which consists of address to be written. All data after the instruction is shifted in the
16 bits followed by data that can be of variable lengths in multiples SDIO pin and sent to the target addresses. Once all data specified
of 8 bits. If the device is configured with CSB tied low, framing by the word length has been transferred, the state machine returns
begins with the first rising edge of SCLK. to idle mode and awaits the next instruction phase.
INSTRUCTION PHASE In either read or write mode, the process continues until the word
The instruction phase is the first 16 bits transmitted. As shown length is reached or until the CSB line is lifted. If the end of
in Figure 4 and Figure 7, the instruction phase is divided into a memory is reached (either 0x000 or 0x0FF), the rollover occurs
number of bit fields. and the next address processed is 0x000, if the address is
incrementing, or 0x0FF, if the address is decrementing.
READ/WRITE
WORD LENGTH
The first bit in the stream is the read/write indicator bit (R/W).
W1 and W0 represent the number of data bytes to transfer for
When this bit is high, a read is being requested. At the com-
either read or write. The value represented by W1:W0 + 1 is the
pletion of the instruction phase (the first 16 bits), the internal
number of bytes to transfer. If the number of bytes to transfer is
state machine uses the information provided to decode the
three or less (00, 01, or 10), CSB can stall high on byte boundaries.
internal address to be read. The direction of the SDIO line is
Stalling on a nonbyte boundary terminates the communications
changed from input to output, and the appropriate number of
cycle. If these bits are 11, data can be transferred until CSB
words defined by the word length are shifted out of the device
transitions high. CSB is not allowed to stall during the streaming
(see the Word Length section). If the device is equipped with an
process. Once streaming has begun (defined as beyond the third
SDO and the configuration register is appropriately set, the
data byte), CSB is not allowed to return high until the operation is
SDO line is taken out of high impedance and data is passed out
complete. When CSB does go high, streaming is terminated, and
the SDO pin instead of the SDIO pin. Once all data specified by
the next time CSB goes low, a new instruction cycle is initiated. If
the word length has been shifted out, the state machine returns
CSB goes high on a non-8-bit boundary, the communications cycle
to idle mode and awaits the next instruction phase.
is terminated, and any incomplete bytes are lost. Completed data
bytes, however, are properly handled.

CSB

CL DON'T CARE

SDIO DON'T CARE R/W W1 W0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

05739-004

16-BIT INSTRUCTION HEADER

Figure 7. Instruction Phase Bit Field

Rev. B | Page 5 of 20
AN-877 Application Note
Table 2. Word Length Settings the CSB line low transfer data in 1-, 2-, or 3-byte blocks, unless
[W1:W0] CSB they are certain that they do not wish to read data from the
Setting Action Stalling internal registers. Although it is not required, it is recommended
00 1 byte of data can be transferred. Optional that users maintain control over the CSB line so the streaming
01 2 bytes of data can be transferred. Optional process can be interrupted and the state machine can be reset to
10 3 bytes of data can be transferred. Optional the idle state.
11 4 or more bytes of data can be No
transferred. CSB must be held low for
ADDRESS BITS
entire sequence; otherwise, the cycle is The remaining 13 bits represent the starting address of the data
terminated, and an instruction cycle is sent. If more than one word is being sent, sequential addressing
anticipated when CSB returns low.
is used, starting with the one specified, and it either increments
If the value represented by W0 and W1 is 0, one byte of data is or decrements based on the mode setting.
transferred. If the value represented by W0 and W1 is 1, two
Data Phase
bytes of data are transferred. If the value represented by W0 and
Data follows the instruction phase. The amount of data sent is
W1 is 2, then three bytes of data are transferred. Following
completion of the data transfer, the state machine returns to idle determined by the word length (Bit W0 and Bit W1). This can
state, awaiting the next instruction phase. be one or more bytes of data. All data is composed of 8-bit
words. If the state machine detects incomplete data being
STREAMING transmitted, the state machine resets and enters an idle state,
If the value represented by W0 and W1 is 3, data is constantly awaiting a new instruction to be initiated by the next falling
streamed to the device. As long as CSB remains low, the part edge of the CSB line. If CSB is physically tied low, fault
continues to accept new data, starting with the initial address correction is not possible unless the device includes a chip reset
and continuing to the next address with each new word function. (See the individual device data sheets for more detail.)
received. It is recommended that streaming not be combined Bit Order
with the CSB line physically tied low, because streaming can
Data can be sent in either MSB-first mode or LSB-first mode
only be terminated by lifting the CSB line high. If streaming is
(see the Configuration Register (0X000) section). On power up,
used with CSB tied low, the first instruction used is carried out
MSB-first mode is the default. This can be changed by program-
indefinitely. This means that once a write (or read) cycle is
ming the configuration register. In MSB-first mode, the serial
entered, data may not be read (or written) from the device.
exchange starts with the highest-order bit and ends with the
Similarly, the starting address is continually and automatically
least significant bit (LSB). In LSB-first mode, the order is reversed.
incremented/decremented, according to the mode, with no
The instruction is 16 bits long, consisting of 2 bytes, as described
chance to directly change the address of the state machine. (The
earlier. In MSB-first mode, the bit order is highest-order bit to
address generator continues to wrap around the terminal
lowest-order bit. In LSB-first mode, the entire 16 bits are reversed,
addresses in a predictable manner.) This may not be a problem
as shown in Figure 8.
if the user only wants to program the device with no possibility
of reading internal registers. It is recommended that users who tie
CSB

SCLK DON'T CARE DON'T CARE

SDIO DON'T CARE R/W W1 W0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 DON'T CARE

16-BIT INSTRUCTION HEADER REGISTER (N) DATA REGISTER (N–1) DATA

MSB-FIRST 16-BIT INSTRUCTION, 2 BYTES DATA

CSB

SCLK DON'T CARE DON'T CARE

SDIO DON'T CARE A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 W0 W1 R/W D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 DON'T CARE

05739-005

16-BIT INSTRUCTION HEADER REGISTER (N) DATA REGISTER (N–1) DATA

LSB-FIRST 16-BIT INSTRUCTION, 2 BYTES DATA

Figure 8. MSB-First and LSB-First Instruction and Data Phases

Rev. B | Page 6 of 20
Application Note AN-877

DETECTION OF SPI MODE AND PIN MODE

Some users may choose not to use an SPI port to configure their The only means to accomplish this are cycling the power on the
device. Where possible, devices are designed to power up using device or asserting the device pin reset, if the part is so equipped.
typical settings. (For exact details, consult the appropriate device Note that not all parts include a pin reset. See the device data
data sheet.) However, there may be cases where users want to sheet for details.
change the basic features without inclusion of an SPI controller. CSB CSB
Examples include controlling the duty cycle stabilizer or the SPI STATE SLAVE SPI
SCLK
format of the data output between twos complement and offset SDIO
MACHINE MEMORY

binary. For these types of options, the chip can be specified such SCLK OR
ALT 1
HI-Z WHEN
SDO NOT USED
that external controls can be used to change the options without OR INACTIVE

having to program the device. To minimize the number of FIRST SPI

INSTRUCTION
external pins, the SPI pins are reassigned to these alternate SDIO OR 1 TO 3 CONTROL BITS

functions. ALT 2

0
For devices that implement this option (see the device data sheet to 1 0/1
0 PIN
determine if this option is supported), the user can choose to SDO OPTIONAL
OR ALT 3
1 MUX
0

05739-006
enable the pin control modes. To do so, the CSB line must be 1

tied high. While this pin is high, the remaining SPI pins become
Figure 9. Hardware Interfacing
alternate functions, and any setting on those pins takes effect as
defined in the device data sheet. Once the user decides to enter HARDWARE INTERFACING
SPI mode, pin mode cannot be re-entered unless the device is Although these devices are designed to be interfaced to SPI
powered off first. controllers, it is not necessary to always use an SPI controller to
At power up, the device defaults to pin control mode as long as set up these devices. Pin mode provides one alternative, but in
CSB is logic high. If the CSB line is wired high, the device always cases where more flexibility is desired, it is possible to use either
functions in pin control mode. Likewise, if the CSB line is wired serial PIC or PROMS microcontrollers, as shown in Figure 10
low, the device powers up in SPI mode (see the Streaming section and Figure 11. For more details on programming these devices
for limitations in this mode). In most cases, the CSB line is used with PIC microcontrollers, see the AN-812 Application Note,
to select the chip. Typically, in this mode, CSB is taken high usually Microcontroller-Based Serial Port Interface (SPI) Boot Circuit.
at power up by the external SPI controller. Therefore, by default, GP2 CSB
the remaining SPI pins initially function in pin control mode. As GP0 SCLK
soon as the CSB line is taken low to select the chip, the SPI function GP1 SDIO
CONVERTER
INTERFACE
is enabled, which ignores the state of the other pins and places PIC 12F629

control strictly with the settings of the internal memory map.

05739-007
When the CSB line is low, the state machine expects an SCLK to
shift in data. After 9 clock cycles, representing the first byte (plus an Figure 10. Programming with a Low Cost PIC Microcontroller
extra cycle), the internal state machine no longer looks at the
CSB pin to determine if pin mode or SPI mode is used. The logic CSB
used for this is shown in Figure 9. As long as the CSB line is high SCLK SCLK
from power-up, an internal mux is used to select the alternate CONVERTER
INTERFACE
SPI SERIAL SDO SDIO
functions for the SPI pins. Once the CSB line is taken low, the PROM
DEVICE 1
SDIO
mux is deselected from the input pins and begins interpreting
ENABLE
these signals as SPI signals. After an SPI command is recognized,
the mux stays in the SPI position, regardless of the state of the SCLK
CLOCK
CSB line. Therefore, users cannot hop between SPI mode and CONTROLLER
GENERATOR
pin mode.
05739-008

Additionally, if the SPI port is being used for control, it is

recommended that the device be configured as part of other Figure 11. Programming with a Low Cost Serial PROM and
External Clock Source
start-up procedures to ensure that the device is ready in the
desired state if the pin mode is not to be used. Performing a soft
reset function does not cause the part to revert back to pin mode.

Rev. B | Page 7 of 20
AN-877 Application Note

CHIP PROGRAMMING
The SPI port is the mechanism for configuring the converter. In Bit 4—Reserved
addition, a structured register space is defined for programming Bit 4 must be mirrored by the user in Bit 3. This bit defaults to 1
the device. This structure is divided into addresses pointed to by and cannot be changed.
the address in the instruction phase of the data transfer. Each
address is divided into 8-bit bytes. Each byte can be further divided Table 3. Configuration Register 0x000
down fields, which are documented in the following sections. Bit Name Description Default
Bit 7 SDO When set, causes SDO to Clear. SDIO is
There are three types of registers: the configuration register, the become active (if present). used for both
active
transfer register, and the program register. When clear, the SDO pin input and output.
remains in tristate and all
CONFIGURATION REGISTER (0X000) read data is routed to the
The configuration register is located at Address 0x000. This register SDIO pin.
is used to configure the serial interface, and it contains only four Bit 6 LSB first When set, causes input Clear. MSB first
and output data to be and decrementing
active bits in the upper nibble. The lower nibble is not connected
oriented as LSB first and addressing.
and is held in reserve. Actively mirroring the data between the addressing increments.
upper and lower nibble is recommended. By doing so, any loss When this bit is clear, data
of synchronization and directional information can be easily is oriented as MSB first and
addressing decrements.
restored by writing to Address 0x000. Additionally, it enables
Bit 5 Soft reset When set, the chip enters Clear. On-chip
the chip to be soft reset and configured in a known state, regardless a soft reset mode, power up, any
of which direction data is currently being shifted. This ensures restoring any default register with a
positive attention by the device if a fault condition occurs. values to internal registers. default is set.
Registers with no default
Bit 7—SDO Active are not changed. Once this
Bit 7 must be mirrored by the user in Bit 0. This bit is responsible is complete, the state
machine clears this bit.
for activating SDO on devices that include this pin. If the device
Bit 4 Reserved Default cannot be changed. Set.
does not include an SDO pin, setting this bit has no effect. If this bit
is cleared, then SDO is inactive and read data is routed to the TRANSFER REGISTER (MASTER-SLAVE LATCHING)
SDIO pin. If this bit is set, read data is placed on the SDO pin, if (0x0FF)
so equipped. The default for this bit is low, making SDO inactive.
It is desirable for many of the registers in the register map to be
Bit 6—LSB First buffered with master and slave latches. Buffering enhances the
Bit 6 must be mirrored by the user in Bit 1. This bit is responsible ability to synchronize multiple devices in a system and aids in
for the order of information being sent and received. If this bit writing configurations that may be dependent on values written
is clear, then data is processed MSB first. If this bit is set, then in other parts of memory. Depending on the design, some registers
data is processed LSB first. In addition to the order of data shifting, may be buffered in this manner. Some registers are never buffered,
Bit 6 controls the direction of auto-incrementing of the internal such as 0x000, 0x004, 0x005, and 0x0FF, because they require
address pointer. If this bit is clear, that is, MSB-first mode, the immediate response for program and control purposes. (Consult
internal address counter is decremented for each new datum the device data sheet to determine which registers are buffered.)
processed. Contrarily, if this bit is set for LSB-first mode, the Regardless of buffering, the SPI port is responsible for placing
internal address counter is incremented for each new datum information in the registers. However, for registers that are
processed. The default for this bit is cleared, resulting in MSB- buffered, a transfer must be initiated to move the data to the
first operation. slave registers. There are two defined mechanisms that cause
Bit 5—Soft Reset Control the data to be transferred from the master register to the slave
Bit 5 must be mirrored by the user in Bit 2. This bit is the soft register. Unbuffered latches take effect immediately once
reset control. The default for this bit is clear; however, when set received by the SPI state machine.
high by the user, a chip soft reset is initiated. The soft reset returns On some devices, the transfer bit may be located higher in
all default values to the memory map registers except the memory if the device supports unique device-specific features.
configuration register (0x000). Values that have no defaults In these cases, the functionality of the transfer bit is the same;
remain in the state last programmed by the user. Once the soft only the location is different. See the device data sheet for details.
reset is processed, this bit is cleared, indicating that the reset
process is complete.

Rev. B | Page 8 of 20
Application Note AN-877
Bit 0—Software Transfer ADC channels to be written high. During a read process, only
A software transfer is initiated by setting Bit 0 of this register one bit at a time is recommended to be set high to prevent
as shown in Figure 10. When the state machine recognizes that confusion over which ADC is currently placed on the read bus.
this bit is set, it generates an internal transfer signal that moves Circuitry on-chip prevents bus contention, but the channel
data from the master register to the slave register. When complete, selected for readback is not known unless only one ADC at a
the state machine clears this bit, allowing the user to determine time is enabled.
if the transfer has occurred. It is recommended that all other Bit 7 to Bit 4—Auxiliary Devices
registers be configured as desired before initiating a transfer. The upper nibble is used to enable other devices that may be
Once the masters have been set, the last instruction should on-chip, such as clock generators or secondary converters.
cause the data to be transferred. Data are maintained in the
masters indefinitely, as long as power is applied. Therefore, it Bit 3 to Bit 0—Main Converters
is possible to set up many chips independently and initiate a The lower nibble is used to enable up to four ADCs. Because
transfer to occur simultaneously across multiple chips by there are two registers, a total of eight ADCs can be accessed.
broadcasting the transfer command to all chips at the same Writing
time. Broadcasting can be achieved by bringing all CSB lines
Because the ADC enables are not decoded, it is possible to write
low at the same time, which sends the same data to all chips at
to multiple devices at one time. To accomplish this, set Bit 0
once.
through Bit 3 to enable writing to the selected device. It is possible
Bit 7—Enable Hardware Transfer to write to a subset of these registers by setting only those bits
Not all devices support a hardware transfer mechanism (see the that correspond to the desired target converters. If both 0x004
device data sheet to determine applicability). Bit 7 of this register is and 0x005 are used, bit fields in both registers can be set to write to
assigned the purpose of enabling hardware synchronization. If Bit 7 any or all of the ADCs (0 through 7) as well as any or all of the
is clear, the default software synchronization is enabled. If this bit is auxiliary devices.
set, transfer control is passed to the specified external pin (see Reading
Figure 13).
When reading from devices, only one device at a time can be
CHIP ID (0x001) placed on the serial bus. No damage results if multiple devices
Register 0x001 is the chip ID register, a read-only register that are enabled, but the results may be indeterminate. Therefore,
returns the unique chip identifier that is coded during the care must be taken to enable only one device at a time during
design process, which typically indicates the child ID or grade readback operations.
of the device. This serves to identify which die is used in the
package when multiple grades or options exist (see the device INTERNAL TRANSFER
SIGNAL (MASTER-SLAVE)
data sheet to determine the correct ID).
DON'T CARE
CHIP GRADE (0x002) CSB

Register 0x002 is the chip grade register. This optional register SCLK DON'T CARE
may or may not contain end-user device information (see the
device data sheet to determine if this register is supported and SDIO A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 DON'T CARE

what the values mean). DATA

DEVICE INDEXING (0x004 AND 0x005) MSB-FIRST WRITE INSTRUCTION

Register 0x004 and Register 0x005 are used for indexing individual CSB DON'T CARE

converters on the same die. Register 0x005 references the lower-

DON'T CARE
order devices ADC0 through ADC3, while 0x004 references the SCLK

upper order devices ADC4 through ADC7. If there is only one W1 R/W D0 D1 D2 D3 D4 D5 D6 D7 DON'T CARE
SDIO
ADC in the package, this register is not used. However, if there
DATA
05739-009

are several ADCs, this register must be used to indicate which

LSB-FIRST WRITE INSTRUCTION
device is being written to or read from. During a write process,
Figure 12. Internal Latching Sequence
more than one device at a time can be written by setting multiple
bits in these registers that correspond to the

Rev. B | Page 9 of 20
AN-877 Application Note
Bit 4—Reserved
MASTER SPI SLAVE SPI Bit 3—Function Bypass
MEMORY MEMORY
0x0FF BIT 0 0x0FF When Bit 3 is set, on-chip analog signal processing blocks are
BIT 0 RESET BIT 7
bypassed and powered down (see the device data sheet for
specific details).
Bit 2 to Bit 0—Internal Power-Down Mode

OPTIONAL
0 Bit 2 to Bit 0 determine the mode of chip operation.
D SET Q 1
EXTERNAL
SYNC
The following settings are available for these bits:
ENCODE • 000 is normal chip operation.

05739-010
CLOCK CLR Q
• 001 is a full chip power-down of both analog and clock
Figure 13. Internal Latching Flow circuitry, that is, low power sleep mode.
• 010 shuts the chip down, but allows for a rapid restart.
PROGRAM REGISTERS • 011 is chip reset.
Program registers may or may not be indexed by Register 0x004 • 100 shuts down the core ADC of devices that include an
and Register 0x005 (see the device data sheet to determine how analog signal processing block or an analog front end
the device uses these registers). (AFE).
Modes (0x008) • 101 shuts down the AFE of devices that include analog
signal processing blocks of an AFE.
Register 0x008 controls the mode of the chip.
• 110 through 111 are reserved for future operating modes.
Bit 7—External Power-Down Enable
Bit 7 enables use of an external power-down pin, if available Table 5. Power Modes, Register 0x008, Bits[2:0]
(see the individual device data sheet to determine if this pin is Bit 2 to Bit 0 Chip Power Mode Description
provided). If this bit is clear, any register-based power settings 000 Chip run (default)
(Bit 0 through Bit 2) take priority. However, if this bit is set, the 001 Full power-down
external pin determines the operating mode of the chip, in 010 Standby mode
conjunction with Bit 6 and Bit 5. If Bit 7 is high and the external 011 Chip reset (after reset, the device defaults back
to chip run—same as 000)
pin is low, the chip mode is determined by Bits[6:5]. If Bit 7 is
100 ADC power-down (for chips with an AFE)
high and the external pin is high, the chip is placed in normal
101 AFE power-down (for chips with an AFE)
operating mode, as defined by other device settings. If no external
110 Reserved
power-down pin is provided, Bit 7 to Bit 5 are ignored.
111 Reserved
Bit 6 to Bit 5—External Power-Down Mode
If Bit 6 to Bit 5 are set to: Clock (0x009)
Register 0x009 is used to configure the chip clocking.
• 00, full power-down results when the external pin is active.
• 01, a standby state results when the external pin is active. Bit 7 to Bit 3—Reserved
• 10, this indicates a reserved mode. Bit 2—Phase-Locked Loops (PLL) Enable
• 11, the digital output is enabled when the external pin is Setting this bit enables any on-chip PLL.
active.
Bit 1—Clock Boost
Table 4. External Pin Modes, Register 0x008, Bits[6:5] Bit 1 is used to enhance the performance of the clock function.
Bit 6 to Bit 5 Mode Description of External Pin Control Setting this bit increases current levels in the clock circuit to
00 Enter full power-down when external pin is improve clock jitter performance. Clearing this bit reduces
active power, but increases the jitter of the clock circuit (see the device
01 Enter chip standby when external pin is active data sheet for additional details).
10 Reserved
11 Enable digital outputs when external pin is Bit 0—Duty Cycle Stabilizer
active (low) Bit 0 is used to disable or enable the internal duty cycle
stabilizer (DCS). If Bit 0 is set, then the DCS is enabled. The
default for this register is 0x01, which enables the DCS.

Rev. B | Page 10 of 20
Application Note AN-877
PLL Control (0x00A) Table 7. Enhancement Modes, Register 0x00C, Bits[1:0]
Register 0x00A is used to enable and control an on-chip PLL Bit 1 to Bit 0 Shuffle Modes
that may be used to generate a sample clock. 00 No shuffling
Bit 7—PLL Locked 01 Enable Shuffle Mode 1
10 Enable Shuffle Mode 2
This bit is controlled by the internal hardware and is set when
11 Enable Shuffle Mode 3
the PLL is locked. If this bit is clear, the chip has not yet locked.
Bit 6—PLL Auto Output Test Modes (0x00D)
When this bit is set, the PLL automatically chooses the most Register 0x00D enables available test modes (see the device data
appropriate PLL setting for the specified divider. sheet to determine what modes are supported). The default
setting for this register is 0x00; however, when this register is set
Bit 5 to Bit 0 to one of the documented settings, the ADC data is replaced
Set to the PLL divide ratio plus 1. with test mode data. For Test Modes numbered 1, 2, 3, 5, and 6,
the output format is determined by the setting of Register 0x014.
Clock Divider (0x00B)
All other output patterns provide logical output sequences and
Register 0x00B is used to divide the applied clock to a lower rate are not affected by the output format setting of Register 0x014.
for the encode. If set to all 0s, the divider is bypassed.
Otherwise, the divide ratio is the value in the register plus 1. Bit 7 to Bit 6—Sequencing

Enhancement Modes (0x00C) These bits are used in conjunction with Test Mode 8 defined by
Bit 3 to Bit 0.
Register 0x00C controls enhancement modes.
If these bits are set to:
Bit 7 to Bit 4—Reserved
• 00, then the test pattern stored in 0x019 and 0x01A is
Bit 3 to Bit 2—Chop Enable
statically placed on the output.
Chopping is used to improve noise performance at or near dc. • 01, the pattern alternates between the pattern stored in
If Bit 3 to Bit 2 are set to: User Pattern 1 (0x019 and 0x01A) and User Pattern 2
(0x01B and 0x01C).
• 00, internal chopping is disabled.
• 10, User Pattern 1 is placed on the output for one
• 01, Chopping Mode 1 is enabled.
conversion cycle. Then the output is set to all 0s.
• 10, Chopping Mode 2 is enabled.
• 11, User Pattern 1 is placed on the output followed by User
• 11, Chopping Mode 3 is enabled.
Pattern 2 on the next encode cycle. Further conversion
(See the device data sheet for details.) cycles result in all 0s as determined by the output data
Table 6. Enhancement Modes, Register 0x00C, Bits[3:2] format.
Bit 3 to Bit 2 Chopping Modes Bit 5—PN23 Reset
00 No chopping Bit 5 controls the reset long PN sequence (PN23). While this bit
01 Enable Chopping Mode 1 is set, the PN sequence is held in reset. When this bit is cleared,
10 Enable Chopping Mode 2 the PN sequence resumes from the seed value. The seed value is
11 Enable Chopping Mode 3 0x003AFF.
Bit 1 to Bit 0—Shuffle Mode Bit 4—PN9 Reset
Shuffling is used to improve the linearity of the ADC transfer Bit 4 controls the reset short PN sequence (PN9). While this bit
function. is set, the PN sequence is held in reset. When this bit is cleared,
the PN sequence resumes from the seed value. The seed value is
If Bit 1 to Bit 0 are set to:
0x000092.
• 00, internal shuffling is disabled.
Bit 3 to Bit 0—Test Modes
• 01, Shuffling Mode 1 is enabled.
• 10, Shuffling Mode 2 is enabled. When these bits are set to:
• 11, Shuffling Mode 3 is enabled. • 0000, the device functions as a normal ADC.
• 0001, the output is set to digital midscale.
• 0010, the output is set to +FS.
• 0011, the output is set to −FS.
• 0100, the output is set to an alternating checkerboard
pattern.

Rev. B | Page 11 of 20
AN-877 Application Note
• 0101, the output is set to a PN23 sequence, based on ITU User Pattern 1 and User Pattern 2, on the next encode
0.150 using the equation x23 + x18 + 1. The seed value is cycle, are placed on the output. Further conversion cycles
0x003AFF. (See the device data sheet for applicable result in all 0s as determined by the output data format.
deviations.) • 1001, the output is placed in a 1/0 bit toggle mode for serial
• 0110, the output is set to a PN9, based on ITU 0.150 using output testing. This forces an alternating 1/0 transition on
the equation x9 + x5 + 1. The seed value is 0x000092. (See the serial output stream.
the device data sheet for applicable deviations.) • 1010, the first half of the bits are set to 0 and the last half of
• 0111, the output words toggle between all 1s and 0s. the bits are set to 1. The cycle repeats for the next word
• 1000, the output is set to the user mode, controlled by Bit 7 frame (see Table 8 for details).
and Bit 6. If the output is in user mode 0x08 and Bit 7 and • 1011, the first bit of the serial word is set high and the
Bit 6 are set to 00, the pattern stored in the user pattern following bits in the word are set low.
memory is statically placed on the output. If set to 01, the • 1100, the serial words shown in Table 8 are shifted.
output toggles between User Pattern 1, stored in 0x019 and
Bit Mode 1101 and Bit Mode 1110 are reserved for future use.
0x01A, and User Pattern 2, stored in 0x01B and 0x01C. If
set to 10, User Pattern 1 is placed on the output for one Bit Mode 1111 is reserved for chip-specific test requirements.
conversion cycle; then the output is set to all 0s. If set to 11,
Table 8. Output Test Modes, Register 0x00D
Output Subject to
Test Data Format
Mode 1 Pattern Word 1 2 Word 22 Select Notes
0000 Off Not applicable Not applicable Yes
0001 Midscale short 1000000000000000 Not applicable Yes Offset binary code shown
0010 +FS short 1111111111111111 Not applicable Yes Offset binary code shown
0011 −FS short 0000000000000000 Not applicable Yes Offset binary code shown
0100 Checkerboard 1010101010101010 0101010101010101 No
0101 PN sequence long Not applicable Not applicable Yes PN23 3
ITU 0.150
x23 + x18 + 1
0110 PN sequence short Not applicable Not applicable Yes PN9 3
ITU 0.150
x9 + x5 + 1
0111 1/0 word toggle 1111111111111111 0000000000000000 No
1000 User input Register 19 to Register 1A Register 1B to Register 1C No
1001 1/0 bit toggle 1010101010101010 Not applicable No Useful in serial output mode
1010 1× sync 0000000011111111 Not applicable No Lower resolution truncates both
a leading and a trailing digit
1011 1 bit high 1000000000000000 Not applicable No Useful in serial output mode
1100 Mixed-frequency 101000110011 (12 bit) Not applicable No Useful in serial output mode
1001100011 (10 bit)
10100001100111 (14 bit)
10100011 (8 bit)
1101 Reserved Not applicable Not applicable Not applicable Not applicable
1110 Reserved Not applicable Not applicable Not applicable Not applicable
1111 Chip specific Chip specific Chip specific Chip specific Chip specific

1 All devices may not support all modes. See the device data sheet for details.
2 Truncated from the right for lower resolutions.
3 See the device data sheet for applicable deviations.

Rev. B | Page 12 of 20
Application Note AN-877
Built-In Self Test (0x00E) Analog Input (0x00F)
Register 0x00E configures and enables the built-in self test (BIST) Register 0x00F configures the analog input.
functions. The BIST is a user feature that provides a high degree Bit 7 to Bit 4—Bandwidth (Low-Pass)
of confidence that the core process of the chip is performing as
intended. BIST provides a simple means of determining, in a Bit 7 to Bit 4 determine the corner frequency or the on-chip
pass/fail manner, if the device is functioning. The results of the low-pass filter. Note that 0000 is the default bandwidth, as
BIST are available in 0x024 and 0x025, the multiple input status specified in the device data sheet. Alternate bandwidths are
register (MISR). defined with values 0001 through 1111. All options may not be
available. See the device data sheet for options available.
The BIST concept is a simple one. A PN sequence is fed to the
digital block of the converter. The output of the digital block is Table 9. Analog Input Bandwidth, Register 0x00F, Bits[7:4]
added to an accumulator that was cleared at the start of the Bit 7 to Bit 4 Bandwidth Mode
BIST cycle. The accumulated result consists of the sum of all PN 0000 Default bandwidth.
sequences passed through the digital block. If the converter core 0001 through 1111 Alternate bandwidth choices.
is functioning properly, it responds exactly the same every time
Bit 3—Reserved
it is called. Therefore, the results should be consistent.
Bit 2—Analog Disconnect
The results are placed in the MISR registers found at 0x024 and
0x025. The user can read these registers to determine if the Bit 2 is set to disconnect the analog input from the remainder of
digital section of the chip is functioning properly. This is done the ADC channel. When this bit is clear, the converter behaves
by comparing the values read with the values stored in the test normally. However, if this bit is set, the converter continues to
code. Because the digital back end has many different program- operate, but with the analog input disconnected from the front
ming options, there is no single value that represents a correct end of the circuit. This enables the user to determine the amount of
response. Instead, once the user has determined the configuration, internal noise due to the converter, for applications that need
the value from this register can be read on a working device to this information.
determine the correct response. All working devices in the Bit 1—Common-Mode Input Enable
specified configuration provide the same results. A different
Bit 1 enables any common-mode circuitry associated with the
result indicates a fault.
analog input of the ADC (see the device data sheet for additional
Bit 7 to Bit 3—Reserved details of application and functionality).
Bit 2—BIST Init Bit 0—Single Ended
Bit 2 is the BIST Init bit. If low, the MISR is not cleared before Bit 0 is set if the input is single ended, for a device that otherwise
the BIST cycle is initiated. If this bit is high, the MISR is cleared has a differential input, to enhance performance.
prior to the BIST cycle. This allows several tests to be cascaded
Offset Adjust (0x010)
and the final results to be viewed rather than having to view
each individual test. Register 0x010 allows the offset of the device to be tweaked. The
purpose of this register is to provide sufficient offset to move
Bit 1 to Bit 0—BIST Mode thermal noise off midscale. This is typically implemented as a
If the bit pattern is: digital offset, and the range for this adjustment is found in the
• 00, BIST mode is disabled and the chip operates normally. device data sheet. The default of this register is 0x00 (midscale)
• 01, BIST mode 1 is enabled. with representation using twos complement notation 0x7F is the
most positive offset adjustment, and 0x80 is the most negative
When BIST Mode 1 is set, the internal digital stream of the offset adjustment. An offset of positive 1 is represented as 0x01,
ADC is stimulated with a pseudorandom data stream and the and a negative 1 is represented as 0xFF. The actual range of this
output is accumulated in the MISR registers (24h and 25h). Any register varies by part (see the device data sheet).
configuration settings that change data (offset or gain, for example)
Gain Adjust (0x011)
or reformat data (offset binary or twos complement, for example)
affect the accumulation. Because the pseudorandom sequence is Register 0x011 allows the gain of the device to be adjusted. The
predictable, the accumulated value is always the same for any actual range and options vary by device (see the device data
given configuration. This allows for a high degree of confidence sheet for additional details).
that the digital back end is fully functional. The integration period
is fixed at 256 encode cycles. After the BIST cycle is complete,
this bit is cleared, unless Bit 2 is clear.
Note that 10 and 11 are reserved for future BIST modes.

Rev. B | Page 13 of 20
AN-877 Application Note
Output Mode (0x014) Table 11. Output Format, Register 0x014, Bits[1:0]
Bit 7 to Bit 6—Logic Type Bit 1 to Bit 0 Output Data Format
00 Offset binary
Bit 7 to Bit 6 control the output logic type. The setting of these
01 Twos complement
bits corresponds to the type of output logic selected. These are
10 Gray code
only specified as Level Option 0 through Level Option 3, and
11 Reserved
are defined in the device data sheet. Low voltage differential
signaling (LVDS) type outputs, if used, can also work with Output Settings (0x015)
0x015 to determine output termination and driver current.
Register 0x015 works with CMOS and LVDS modes to set
Complementary metal-oxide semiconductor (CMOS) type
outputs may also work with 0x015 to determine output drive output termination and output driver current levels.
strength. Bit 7 to Bit 4—Output Termination

Table 10. Output Logic Type, Register 0x014 Bits[7:6] Bit 7 to Bit 4 determine the output termination options for
LVDS and other controlled impedance driver outputs (see the
Bit 7 to Bit 6 Output Logic Levels
device data sheet for more details).
00 Option 0
01 Option 1 Bit 3 to Bit 0—Output Drive Current
10 Option 2 Bit 3 to Bit 0 determine the output drive current for various
11 Option 3 CMOS and LVDS options (see the device data sheet for more
details).
Bit 5—Output Multiplexer
Clock Divider Phase (0x016)
If Bit 5 is set, the output is muxed between two different outputs
or it interleaves two ADCs on the same output in a double data Registers 0x016 determine which phase of the clock divider is
rate fashion. used to latch data. This can be used in conjunction with either
Register 0x00B or with a PLL divider output used to supply a
Bit 4—Output Enable serial clock. The default for this register is 0x00, selecting the
Bit 4 is the output enable. If this bit is low, the output is enabled. first phase not inverted.
For CMOS/TTL devices, this places the output in high impedance Bit 7—Phase Invert
state. For other logic families, the output is placed in a mode
defined by the device data sheet. If an external output enable exists, Bit 7 inverts the internal phase.
then the function of this bit is defeated. If an external pin is defined Bit 6 to Bit 4—Reserved
as an alternate function (see the Modes (0x008) section), then this Bit 3 to Bit 0—Phase Select
bit controls the output.
Bit 3 to Bit 0 determine which phase is selected to drive the
Bit 3—Double Data Rate Enable serial clock.
Bit 3 allows fewer output pins to be used to produce the same Output Delay Adjust (0x017)
amount of data. When this bit is set, all data bits are sent using
Register 0x017 sets the fine delay in the output latch relative to
one-half of the output bits, but clocked at twice the sample rate.
when the internal output registers are strobed. Internal timing is
The remaining output bits are unused in this mode. When this
not altered by this setting. Only the output latch is changed to
bit is clear, the converter behaves in a normal manner with all
compensate for any external setup and hold time issues
output bits being used.
resulting from ADC timing issues. The range of this register is
Bit 2—Output Invert specified in the device data sheet.
Bit 2 inverts the outputs when set. Bit 7—Enable
Bit 1 to Bit 0—Output Coding For this feature, Bit 7 acts as an enable. If clear, default timing is
Bit 1 to Bit 0 determine the output coding. selected providing reference timing.
If set to: Bit 6—DLL Enable
• 00, the output is offset binary. Setting Bit 6 enables an on-chip delay locked loop (DLL) that is
• 01, the output is twos complement. used in the generation of the output latch. The DLL is used to
• 10, the output is gray code. maintain optimal timing between the output data eye and the
latch for that data. This is useful in applications where timing is
11 is reserved. critical and data must be optimized. If this bit is clear, the DLL
Only modes supported by the individual device are recognized. is off and the delay may be manually adjusted by Bit 5 to Bit 0
(See the device data sheet.) The default is 0x00. when enabled with Bit 7.

Rev. B | Page 14 of 20
Application Note AN-877
Bit 5 to Bit 0—Delay Table 12. Output Frame Length, Register 0x021, Bits[2:0]
Bit 5 to Bit 0 represent chip-specific offset timings, with 0x00 Bit 2 to Bit 0 Serial Output Frame Length
being the most negative adjustment and 3F being the most 000 Native bit length
positive. 001 Truncate/fill to 8 bits
010 Truncate/fill to 10 bits
Reference Adjust (0x018)
011 Truncate/fill to 12 bits
Register 0x018 allows the internal reference voltage to be 100 Truncate/fill to 14 bits
selected and/or adjusted. 101 Truncate/fill to 16 bits
Bit 7 to Bit 6—VREF Select 110 Reserved
111 Reserved
Bits[7:6] determine which VREF is used.
Serial Channel Power-Down (0x022)
If set to:
Serial channel power-down is used to control the state of each
• 00, the primary VREF is connected. serial channel in a serial output converter.
• 01, the secondary VREF is selected.
Bit 7 to Bit 2—Reserved
1× is reserved for additional reference options. Bit 1—Channel Output Reset
Bit 5 to Bit 0 When Bit 1 (CH_OUTPUT_RESET) is selected for either a data
Bit 5 to Bit 0 allow the internal VREF to be adjusted. The channel or clock channel, everything is left powered up.
adjustment range is specified in the device data sheet. However, the output flip-flop, prior to the LVDS driver
User Test Patterns (0x019 through 0x020) associated with that channel is held in reset.
These registers are used with test mode configurations allowing Bit 0—Channel Power-Down
the user to specify test patterns. These are paired registers with When Bit 0 (CH_POWER_DOWN) is selected for a data
0x019 paired with 0x01A, 0x01B with 0x01C, 0x01D with 0x01E, channel, the associated ADC and LVDS driver are powered
and 0x01F with 0x020. The low address is the least significant down while the associated digital circuitry is held in reset.
byte. (See the Output Test Modes (0x00D) section of this When Bit 0 (CH_POWER_DOWN) is selected for a clock
application note.) channel, the associated LVDS driver is powered down, and the
Serial Data Control Channel (0x021) associated digital circuitry is held in reset.
Register 0x021 is the high speed serial data control channel. It MISR Registers (0x024 Through 0x025)
may also be used in parallel output devices to control the Register 0x024 is the multiple input signature register (MISR)
number of output bits that are active (Bit 2 to Bit 0). least significant byte. Register 0x025 is the MISR most
Bit 7—LSB First significant byte. The MISR is a multiple input signature register.
This register is used in conjunction with the BIST (0x00E). This
When this bit is set, devices using a serial port for the converter register is a mirror of the core MISR and is read only.
data output, shift the data LSB first. If clear (default), the MSB is
shifted first. Features (0x02A)
Bit 7 to Bit 1—Reserved
Bit 6 to Bit 4—Reserved
Bit 0—Overrange Enable
Bit 3—PLL Optimize
When Bit 0 is set, the overrange pin is disabled. When clear, the
Bit 3 is used to optimize PLL operations for various frequency
ranges (see the device data sheet for details). overrange operates normally.

Bit 2 to Bit 0
These bits are used to determine the number of bits shifted in
the serial frame or parallel output. If set to 000, the native
number of bits of the converter are shifted. This control allows
for both truncation and padding of the bit stream. For example,
a 12-bit converter can be forced to appear as an 8-bit converter
by setting the lower 3 bits of this register to 001. Likewise, the
same 12-bit converter can be forced to look like a 16-bit
converter by padding the extra bits with zeroes (support for the
full range of this setting is described in the device data sheet.
Not all options may be present on all devices).

Rev. B | Page 15 of 20
AN-877 Application Note
High-Pass (0x02B) Table 13. High-Pass Filter Select, Register 0x02B, Bits[2:0]
Register 0x02B configures the high-pass filter. Bit 2 to Bit 0 Bandwidth Mode
000 Default bandwidth (dc)
Bit 7, Bit 5 to Bit 3—Reserved
001 through 111 Alternate high-pass choices
Bit 6—Tune
Bit 6 is used to calibrate either the high-pass or the low-pass on- Analog In (0x02C)
chip filters. Setting this bit initiates the bandwidth calibration Bit 7 to Bit 1—Reserved
process. Consult the device data sheet to determine which Bit 0—Input Impedance
filters are calibrated and additional details.
Bit 0 allows one of two input impedances to be selected (see the
Bit 2 to Bit 0—Bandwidth (High-Pass) device data sheet for details).
Bit 2 to Bit 0 determine the corner frequency or the on-chip Cross Point Switch (0x02D)
high-pass filter. Note that 000 is the default bandwidth and This function provides an analog cross point switch that may be
corresponds to dc coupling. Alternate bandwidths are defined used for connecting the analog input to the core ADC or to route
with values 001 through 111. Not all options may be available various analog inputs to various auxiliary analog outputs as
(see the device datasheet for options available). defined in the device data sheet.

Rev. B | Page 16 of 20
Application Note AN-877

PROGRAMMING EXAMPLE
Programming tools are available to assist in the development of This can be added to a C language project to set up the appro-
code for SPI devices. A user may wish to access the features priate writes and reads to ensure the device is configured per
available with SPI control, but not have access to a full featured the settings in the evaluation software. To use this pseudocode,
SPI controller. If this is the case, consult the AN-812 the user need only supply the hardware-specific read and write
Application Note for a low cost alternative to a full featured functions associated with their SPI controller. The example
controller. code in this section outlines a sample program sequence for the
A software tool is also available (see www.analog.com/FIFO) for devices.
controlling the devices used on the corresponding evaluation The second file format is assembly code that can be used with
board. This tool allows the registers to be configured to determine the microcontroller described in the AN-812 Application Note.
the optimal device configuration for the end application. In (See AN-812 for additional details on the usage of this output.)
addition, once this process is complete, the software tool For additional details on using these tools, see the AN-878
generates two files useful for programming the devices. The Application Note, High Speed ADC SPI Control Software.
first file format is a pseudocode format.

write(0, 18); //configure serial interface for MSB first

write(5, 3); //set Devices-Index to program ADC Channels 0 and 1
write(18, 80); //set vref to option 2 and adjustment to all zeros
write(14, 10); //set output_mode to level option 0, disable output MUX, enable output and
offset binary

write(17, 83); //set output_delay to enable and set to delay value of 3

write(FF, 1); //write transfer bit (for configurations that require a manual transfer)

write(5, 2); //set Device-Index to program ADC Channel 1

write(10, 3); //set offset to 3 (for Channel 1 only)
write(FF, 1); //write transfer bit (for configurations that require a manual transfer)

Write(5, 4); //set Devices Index to program ADC Channel 2

write(10, 9); //set offset to 9 (for Channel 2 only)
write(FF, 1); //write transfer bit (for configurations that require a manual transfer)

Rev. B | Page 17 of 20
AN-877 Application Note

CONTROL REGISTER
Table 14. Control Register Map
Default
Address 1, Register Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB) Value1 Comments
00, SDO active 2 LSB first Soft reset Should 18h The nibbles should be
CHIP_PORT_CONFIG be set. mirrored by the user so
Do not that LSB-first or MSB-first
clear. mode registers correctly
regardless of shift mode.
01, CHIP_ID 8-bit chip ID; Bits[7:0] Read Default is unique chip ID,
only different for each device.
This is a read-only register.
(See device data sheet for
more details.)
02, CHIP_GRADE 8-bit child ID Read Read only. Child ID used
only to differentiate graded
devices. (See device data
sheet for more details.)
04, AUX 7 AUX 6 AUX 5 AUX 4 ADC 7 ADC 6 ADC 5 ADC 4 FFh Bits are set to determine
DEVICE_INDEX_B which device on -chip
receives the next write
command. The default will
be all devices on-chip.
05, AUX 3 AUX 2 AUX 1 AUX 0 ADC 3 ADC 2 ADC 1 ADC 0 FFh Bits are set to determine
DEVICE_INDEX_A which device on-chip
receives the next write
command. The default is
all devices on-chip.
08, MODES External External power­down Function Internal power-down mode 00h Determines various
power-down mode bypass 0: chip run generic modes of chip
enable 00: full power-down 1: full power-down operation.
01: standby 2: standby
10: normal mode 3: reset
(output disabled) 4: ADC power-down
11: normal mode 5: analog front-end power-down
(output enabled) 6: reserved
7: reserved
09, CLOCK Reserved for additional clock input support PLL enable Clock boost Duty cycle 01h
stabilize
0A, PLL_CONTROL PLL locked PLL auto PLL multiplier; Bits[5:0] 00h Configures on-chip PLL by
enabling and setting
multiplier. MSB is set
when the PLL is locked.
0B, CLOCK_DIVIDE Clock divider; Bits[7:0] 00h The divide ratio is the
value plus 1.
0C, ENHANCE Reserved Reserved Reserved Chop enable Shuffle mode Shuffle mode determines
0: off 0: off how shuffling is
1: Mode 1 1: Mode 1 performed. Chopping
2: Reserved 2: Reserved determines how the input
3: Reserved 3: Reserved is processed to improve
noise near dc.
0D, TEST_IO User test mode Reset PN Reset PN Output test mode 00h When set, the test data is
00: single long gen short gen 0: off placed on the output pins
01: alternate 1: midscale short in place of normal data.
10: single once 2: +FS short
11: alternate once 3: −FS short
4: checkerboard output
5: PN23 sequence
6: PN9
7: 1/0 word toggle
8: User input
9: 1/0 bit toggle
10: 1× sync
11: 1 bit high
12: mixed-bit frequency (format
determined by OUTPUT_MODE)
0E, TEST_BIST BIST init Reserved BIST enable 00h BIST mode configuration

0F, ADC_INPUT Low-pass filter bandwidth Analog Common- Single 00h

0: default disconnect mode ended
Bits[1:15]: alternate corner frequencies input
(See device data sheet for details) enable
10, OFFSET 8-bit device offset adjustment; Bits[7:0] 80h Device offset trim

11, GAIN 8-bit device gain adjustment; Bits[7:0] 00h Device gain trim

Rev. B | Page 18 of 20
Application Note AN-877
Default
Address 1, Register Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB) Value1 Comments
14, OUTPUT_MODE 0: Level Option 0 Output Output DDR Output 0: Offset binary Device Configures the outputs
1: Level Option 1 mux enable enable invert 1: Twos complement specific and the format of the data.
2: Level Option 2 enable 2: Gray code
3: Level Option 3 (interleave) 3: Reserved
15, Output driver termination; Bits[7:4] Output driver current; Bits[3:0] Device Determines LVDS or other
OUTPUT_ADJUST specific output properties.
Primarily functions to set
the LVDS span and
common-mode levels in
place of an external
resistor.
16, OUTPUT_PHASE Output Output clock phase adjust; Bits[3:0] 00h On devices that utilize
polarity clock divide, determines
which phase of the divider
output is used to supply
the output clock. Internal
latching is unaffected.
17, OUTPUT_DELAY Enable DLL 6-bit output delay; Bits[5:0] 00h This sets the fine output
enable delay of the output clock
but does not change
internal timing.
18, VREF VREF select 6-bit internal VREF adjustment; Bits[5:0] 20h Select and/or adjust the VREF.
0: primary (0)
1: secondary (1)
2: Option 2
3: Option 3
19, B7 B6 B5 B4 B3 B2 B1 B0 00h User-Defined Pattern 1 LSB.
USER_PATT1_LSB
1A, B15 B14 B13 B12 B11 B10 B9 B8 00h User-Defined Pattern 1 MSB.
USER_PATT1_MSB
1B, B7 B6 B5 B4 B3 B2 B1 B0 00h User-Defined Pattern 2 LSB.
USER_PATT2_LSB
1C, B15 B14 B13 B12 B11 B10 B9 B8 00h User-Defined Pattern 2 MSB.
USER_PATT2_MSB
1D, B7 B6 B5 B4 B3 B2 B1 B0 00h User-Defined Pattern 3 LSB.
USER_PATT3_LSB
1E, B15 B14 B13 B12 B11 B10 B9 B8 00h User-Defined Pattern 3 MSB.
USER_PATT3_MSB
1F, B7 B6 B5 B4 B3 B2 B1 B0 00h User-Defined Pattern 4 LSB.
USER_PATT4_LSB
20, B15 B14 B13 B12 B11 B10 B9 B8 00h User-Defined Pattern 4 MSB.
USER_PATT4_MSB
21, LSB first PLL 000: normal bit stream 00h Serial stream control.
SERIAL_CONTROL optimize 001: 8 bits Default causes MSB first
010: 10 bits and the native bit stream.
011: 12 bits
100: 14 bits
101: 16 bits
22, Ch output Ch 00h Used to power down
SERIAL_CH_STAT reset power- individual sections of a
down converter (local).
24, MISR_LSB B7 B6 B5 B4 B3 B2 B1 B0 00h Least significant byte of
MISR (read-only).
25, MISR_MSB B15 B14 B13 B12 B11 B10 B9 B8 00h Most significant byte of
MISR (read-only).
2A, FEATURES OVR OVR output 00h Auxiliary feature set
alternate enable control.
pin
2B, HIGH_PASS Tune Corner frequency 00h High-pass filter control.
000: dc
000 through 111: Alternate corner
frequencies
2C, AIN Input 00h Analog input control.
impedance
2D, CROSS_POINT 00h Analog input cross point
switch.
FF, DEVICE_UPDATE Enable HW SW transfer 00h Synchronously transfers
transfer data from the master shift
register to the slave.

1 Hexadecimal.
2 Not supported on most devices.

Rev. B | Page 19 of 20
AN-877 Application Note

NOTES

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registered trademarks are the property of their respective owners.
AN05739-0-4/17(B)

Rev. B | Page 20 of 20