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Experiment 8

This document describes an experiment to verify the truth tables of half adders and full adders using logic gates. It begins by explaining what adders are and providing examples of basic binary addition. It then discusses half adders, showing their block diagram, truth table, and implementations using XOR/AND gates and NAND/NOR gates. Next, it covers full adders, including their block diagram, truth table, logic diagram, and implementations using AND/OR gates and NAND/NOR gates. It concludes by describing the procedure for the experiment, which involves entering input values and checking the output sum and carry.

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62 views5 pages

Experiment 8

This document describes an experiment to verify the truth tables of half adders and full adders using logic gates. It begins by explaining what adders are and providing examples of basic binary addition. It then discusses half adders, showing their block diagram, truth table, and implementations using XOR/AND gates and NAND/NOR gates. Next, it covers full adders, including their block diagram, truth table, logic diagram, and implementations using AND/OR gates and NAND/NOR gates. It concludes by describing the procedure for the experiment, which involves entering input values and checking the output sum and carry.

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vkr
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© © All Rights Reserved
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DEPARTMENT OF COMPUTER SCIENCE & ENGG.

BHILAI INSTITUTE OF TECHNOLOGY, DURG (C.G.)


DIGITAL ELECTRONICS LAB MANNUAL
EXPERIMENT 8

AIM: To verify the truth table of half adder and full adder by using XOR and NAND gates respectively
and analyze the working of half adder and full adder circuit.

Objective: To learn the basic concepts of digital electronics.

Introduction
Adders are digital circuits that carry out addition of numbers.
Binary addition is similar to that of decimal addition. Some basic binary additions are shown below.

Figure 1. Schematic representation of half adder


1) Half Adder
Half adder is a combinational circuit that performs simple addition of two binary numbers. If we assume
A and B as the two bits whose addition is to be performed, the block diagram and a truth table for half
adder with A, B as inputs and Sum, carry as outputs can be tabulated as follows.

Figure 2. Block diagram and truth table of half adder

The sum output of the binary addition carried out above is similar to that of an Ex-OR operation while the
carry output is similar to that of an AND operation. The same can be verified with help of Karnaugh Map.
The truth table and K Map simplification and logic diagram for sum output is shown below.

Figure 3. Truth table, K Map simplification and Logic diagram for sum output of half adder
Sum = A B' + A' B
DEPARTMENT OF COMPUTER SCIENCE & ENGG.
BHILAI INSTITUTE OF TECHNOLOGY, DURG (C.G.)
DIGITAL ELECTRONICS LAB MANNUAL
EXPERIMENT 8

The truth table and K Map simplification and logic diagram for carry is shown below.

Figure 4. Truth table, K Map simplification and Logic diagram for sum output of half adder
Carry = AB
If A and B are binary inputs to the half adder, then the logic function to calculate sum S is Ex – OR of A
and B and logic function to calculate carry C is AND of A and B. Combining these two, the logical circuit
to implement the combinational circuit of half adder is shown below.

Figure 5. Half Adder Logic Diagram


NAND and NOR are called universal gates as any logic system can be implemented using these two, the
half adder circuit can also be implemented using them. We know that a half adder circuit has one Ex –
OR gate and one AND gate.

1.1) Half Adder using NAND gates


Five NAND gates are required in order to design a half adder. The circuit to realize half adder using
NAND gates is shown below.
DEPARTMENT OF COMPUTER SCIENCE & ENGG.
BHILAI INSTITUTE OF TECHNOLOGY, DURG (C.G.)
DIGITAL ELECTRONICS LAB MANNUAL
EXPERIMENT 8

Figure 6. Realization of half adder using NAND gates

1.2) Half Adder using NOR gates


Five NOR gates are required in order to design a half adder. The circuit to realize half adder using NOR
gates is shown below.

Figure 7. Realization of half adder using NOR Gates


2) Full Adder
Full adder is a digital circuit used to calculate the sum of three binary bits. Full adders are complex and
difficult to implement when compared to half adders. Two of the three bits are same as before which are
A, the augend bit and B, the addend bit. The additional third bit is carry bit from the previous stage and is
called 'Carry' – in generally represented by CIN. It calculates the sum of three bits along with the carry.
The output carry is called Carry – out and is represented by Carry OUT.
The block diagram of a full adder with A, B and CIN as inputs and S, Carry OUT as outputs is shown below.
DEPARTMENT OF COMPUTER SCIENCE & ENGG.
BHILAI INSTITUTE OF TECHNOLOGY, DURG (C.G.)
DIGITAL ELECTRONICS LAB MANNUAL
EXPERIMENT 8

Figure 8. Full Adder Block Diagram and Truth Table

Figure 9. Full Adder Logic Diagram

Based on the truth table, the Boolean functions for Sum (S) and Carry – out (COUT) can be derived using
K – Map.

Figure 10. The K-Map simplified equation for sum is S = A'B'Cin + A'BCin' + ABCin

Figure 11. The K-Map simplified equation for COUT is COUT = AB + ACIN + BCIN
DEPARTMENT OF COMPUTER SCIENCE & ENGG.
BHILAI INSTITUTE OF TECHNOLOGY, DURG (C.G.)
DIGITAL ELECTRONICS LAB MANNUAL
EXPERIMENT 8

In order to implement a combinational circuit for full adder, it is clear from the equations derived above,
that we need four 3-input AND gates and one 4-input OR gates for Sum and three 2-input AND gates and
one 3-input OR gate for Carry – out.

2.1) Full Adder using NAND gates


As mentioned earlier, a NAND gate is one of the universal gates and can be used to implement any logic
design. The circuit of full adder using only NAND gates is shown below.

Figure 12. Full Adder using NAND gates

2.2) Full Adder using NOR gates


NOR gate is one of the universal gates and can be used to implement any logic design. The circuit of full
adder using only NOR gates is shown below.

Figure 13. Full Adder using NOR gates


PROCEDURE
Step 1: Enter the values of binary variable input.
Step 2: Enter the output sum and carry for your corresponding output.
Step 3: Click on check button to verify the output.
Step 4: Click print to get print out of truth table.

Result: …………………………………………………………………………………………

Precautions: verify the output for all state of inputs in sequence.

Reference:
http://vlabs.iitb.ac.in/vlabs-dev/labs/digital-electronics/experiments/verification-and-
interpretation-truth-table-gates-iitr/simulation.html

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