DIET, Dept.

, of ECE Verification of Truth Tables of Logic Gates

Experiment No: 1 Date:

Verification of Truth Tables of Logic Gates

AIM:
To Verify the truth tables of two input AND, OR, NOT, NAND, NOR,
EX-OR, EX-NOR logic gates using IC’s.

APPARATUS:

1. Digital IC trainer kit … 1 No.

2. IC 74LS08 (AND) … 1 No.
3. IC 74LS32 (OR) … 1 No.
4. IC 74LS04 (NOT) … 1 No.
5. IC 74LS00 (NAND) … 1 No.
6. IC 74LS02 (NOR) … 1 No.
7. IC 74LS86 (EX-OR) … 1 No.
8. IC74266 (EX-NOR) … 1 No.
9. Connecting wires
10. Digital Multimeter

THEORY:
AND gate: If two or more operands are ANDed, then the result will be logic 1 only

if all the operands are 1.A ‘.’ Sign is used to represent the AND operation. If A and B are
the logic operands and Y is the result of the AND operation, then Y is 1(TRUE) only if
both A AND B are 1(TRUE). For all other combinations of the inputs, Y is 0(FALSE). The
expression for AND operation is given as Y=A. B.
OR gate: If two or more operands are ORed, then the result will be logic 1 if any
of the operands is a logic1. A ‘+’ Sign is used to represent the OR operation. If A and B
are the logic operands and Y is the result of the OR operation, then Y is 1(TRUE) if either
A OR B is 1 (TRUE). Y is 0 (FALSE) only when both A and B are 0. The expression for
OR operation is given as Y=A + B.
NOT gate: The NOT operation corresponds to complementing the input variable.
In this there could be only one input and one output and the output is NOT the input. If
the input is 1 (TRUE) then the output is 0 (FALSE) and if the input is 0, the output is 1.
The NOT operation is given by the expression Y = Ā.

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Switching Theory and Logic Design Lab II B.Tech ECE, I Semester AY:2020-21
DIET, Dept., of ECE Verification of Truth Tables of Logic Gates

NAND gate: NAND gate is the gate indicating NOT AND i.e., the output of the
NAND gate will be the complement of the output of the AND gate. This is shown in the
table 1.1. In the table, A and B are the inputs, Y corresponds to the output of an AND
gate and Y corresponds to the output of a NAND gate. It can be seen that the output of
the NAND gate is the complement of that of the AND gate.

The NAND operation is given by the expression

NOR gate: NOR gate is the gate indicating NOT OR i.e., the output of the NOR
gate will be the complement of the output of the OR gate. This is shown in the table 1.1.
In the table, A and B are the inputs, Y corresponds to the output of an NOR gate. It can
be seen that the output of the NOR gate is the complement of that of the OR gate. The

NOR operation is given by the expression

X-OR gate: The X-OR logic is different from other gates whose output is one, only
when the applied inputs are different i.e., it is an odd function and is one when it contains
odd number of ones.
So, at A=0, B=1 or A=1, B=0 the output of X-OR is 1.
X-NOR gate: The X-NOR logic is different from other gates whose output is one, only
when the applied inputs are same i.e., it is an even function and is one when it contains
even number of ones.
So, at A=0, B=0 or A=1, B=1 the output of X-OR is 1.
CIRCUIT DIAGRAMS: i. IC 74LS08

Fig 1.1: IC 74LS08 Pin diagram for AND Gate

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Switching Theory and Logic Design Lab II B.Tech ECE, I Semester AY:2020-21
DIET, Dept., of ECE Verification of Truth Tables of Logic Gates

ii. IC 74LS32

Fig 1.2: IC 74LS32 Pin diagram for OR Gate

iii. IC 74LS04

Fig 1.3: IC 74LS04 Pin diagram for NOT Gate

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Switching Theory and Logic Design Lab II B.Tech ECE, I Semester AY:2020-21
DIET, Dept., of ECE Verification of Truth Tables of Logic Gates

iv. IC 74LS00

Fig 1.4: IC 74LS00 Pin diagram for NAND Gate

v. IC 74LS02

Fig 1.5: IC 74LS02 Pin diagram for NOR Gate

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Switching Theory and Logic Design Lab II B.Tech ECE, I Semester AY:2020-21
DIET, Dept., of ECE Verification of Truth Tables of Logic Gates

vi. IC 74LS86

Fig 1.6: IC 74LS86 Pin diagram for Ex-OR Gate

vii. IC 74266

Fig 1.7: IC 74266 Pin diagram for Ex-NOR Gate

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Switching Theory and Logic Design Lab II B.Tech ECE, I Semester AY:2020-21
DIET, Dept., of ECE Verification of Truth Tables of Logic Gates

PROCEDURE:
1. Place the IC on the Digital Trainer Kit.
2. Connect Vcc (Pin-14) and Ground (Pin-7) to respective pins of Digital Trainer Kit.
3. Connect the inputs (at pin no’s 1 & 2) to the input switches provided in the Digital
Trainer Kit.
4. Connect the outputs (Pin no-3) to the switches of output LED’s.
5. Apply Various combinations of the inputs according to the truth table and observe
the condition of LED’s.
6. Disconnect output from the LED’s and note down the corresponding multimeter
Voltage readings for various combinations of inputs.
PRECAUTIONS:
1. The open circuit voltage of the power supply must be stable and close to
5V.
2. Correct components should be connected on the bread board with proper
polarities.
3. A multimeter reading greater than VDD indicates an open connection in the
circuit. Verify the circuit before proceeding.
4. Use multimeter probe tip to gently ease the IC out of breadboard. The mid-
section groove of the breadboard can be used to gently lift the IC. Using
bare hands might cause IC pins to break.
5. In case the logic gate outputs do not make sense, check your circuit
thoroughly. If the problem is still not resolved, get the IC tested by the
technician.
Experiment Results and Observations:
Table 1.1: Truth tables and observation tables for AND Gate

AND gate
Inputs Outputs

SW1 SW0 LED Logic

(1 / 0) DMM (V)
(pin 2) (pin 1) (ON/OFF)

0 0

0 1

1 0

1 1

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Switching Theory and Logic Design Lab II B.Tech ECE, I Semester AY:2020-21
DIET, Dept., of ECE Verification of Truth Tables of Logic Gates

Table 1.2: Truth tables and observation tables for OR Gate

OR gate
Inputs Outputs

SW1 SW0 LED Logic

(1 / 0) DMM (V)
(pin 2) (pin 1) (ON/OFF)

0 0

0 1

1 0

1 1

Table 1.3: Truth tables and observation tables for NOT Gate

NOT gate
Inputs Outputs

SW1 SW0 LED Logic

(1 / 0) DMM (V)
(pin 2) (pin 1) (ON/OFF)

0 0

0 1

1 0

1 1

Table 1.4: Truth tables and observation tables for NAND Gate

NAND gate
Inputs Outputs

SW1 SW0 LED Logic

(1 / 0)) DMM (V)
(pin 2) (pin 1) (ON/OFF)

0 0

0 1

1 0

1 1

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Switching Theory and Logic Design Lab II B.Tech ECE, I Semester AY:2020-21
DIET, Dept., of ECE Verification of Truth Tables of Logic Gates

Table 1.5: Truth tables and observation tables for NOR Gate

NOR gate
Inputs Outputs

SW1 SW0 LED Logic

(1 / 0) DMM (V)
(pin 2) (pin 1) (ON/OFF)

0 0

0 1

1 0

1 1

Table 1.6: Truth tables and observation tables for EX-OR Gate

EX-OR gate
Inputs Outputs

SW1 SW0 LED Logic

(1 / 0) DMM (V)
(pin 2) (pin 1) (ON/OFF)

0 0

0 1

1 0

1 1

Table 1.7: Truth tables and observation tables for EX-NOR Gate

EX-NOR gate
Inputs Outputs

SW1 SW0 LED Logic

(1 / 0) DMM (V)
(pin 2) (pin 1) (ON/OFF)

0 0

0 1

1 0

1 1

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Switching Theory and Logic Design Lab II B.Tech ECE, I Semester AY:2020-21
DIET, Dept., of ECE Verification of Truth Tables of Logic Gates

RESULT:

……………………………………………
Signature of the Course coordinator

VIVA QUESTIONS
a) What changes should be made in the above circuits for negative logic?
b) Explain how NOT gate acts as inverter?
c) Draw logic symbols for logic gates.
d) What are the basic gates?
e) What are the universal gates?
f) What is the difference between basic gates and universal gates?
g) Explain about the binary numbers.
h) What is the characteristic equation for Exclusive-OR gate?
i) What is truth table?
j) What is the function of OR gate?

*****

9
Switching Theory and Logic Design Lab II B.Tech ECE, I Semester AY:2020-21
 DIET, Dept., of ECE Design a simple combinational circuit with four variables

Experiment No:2 Date:

Design a simple combinational circuit with four variables
AIM:
To design a simple combinational circuit with four variables and obtain minimal SOP
expression and verify the truth table using Digital Trainer Kit

Let us consider a four variable Boolean function:

APPARATUS:
1. Digital IC trainer kit … 1 No.
2. IC 74LS08 (AND) … 1 No.
3. IC 74LS32 (OR) … 1 No.
4. Connecting wires
5. Digital Multimeter

THEORY:
Theorems of Boolean algebra are useful in manipulating and simplifying the
Boolean Algebraic expressions. Two theorems that are an important part of Boolean
algebra were proposed by Demorgan.
The first theorem states that the complement of a product is equal to the sum of the
complements.
= +
The second theorem states that the complement of a sum is equal to the product of
the complements.
= .

The S-O-P representation of a Boolean function means “Boolean sum of the ANDed terms”.
Consider a three variable Boolean function F(A,B,C)
F(A,B,C) = A.B + A.C’ + A’B’C
This function is written as a Boolean sum (OR) of three product (AND) terms (i) A.B (ii) A.C’
and (iii)A’B’C and each term is formed by ANDing the literals. The ANDed terms are also
called “product” terms. This function F is represented in S-O-P form.

MINTERM : The ANDed term in the S-O-P expression in which all the variables of a function
are present either as complemented or as uncomplemented form is called a MINTERM. In
above example, A'.B'.C is a minterm but A.B and A.C' are simple AND term but not minterms.
CANNONICAL S-O-P Form: A function composed of a logical sum (OR) of only minterms is
said to be in CANNONICAL S-O-P form. Any Boolean expression has its equivalent canonical
S-O-P form. For example the equivalent canonical S-O-P form is
F(A,B,C) = A.B (C+C') + A.C'(C+C') + A'B'C
= ABC + ABC' + ABC' + AB'C' + A'B'C
= ABC + ABC' + AB'C' + A'B'C
= ∑(1,4,6,7)
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Switching Theory and Logic Design Lab II B.Tech ECE, I Semester AY:2020-21
DIET, Dept., of ECE Design a simple combinational circuit with four variables

The P-O-S representation of a Boolean function means “Boolean product of the ORed terms”.
Consider a three variable Boolean function F(A,B,C)
F(A,B,C) = (A+B)(A+C’)(A+’B’+C)
This function is written as a Boolean product (AND) of three sum (OR) terms (i) A+B (ii) A+C’
and (iii)A’+B’+C and each term is formed by ORing the literals. The ORed terms are also called
“sum” terms. This function F is represented in P-O-S form.

MAXTERM : The ORed term in the P-O-S expression in which all the variables of a function
are present either as complemented or as uncomplemented form is called a MAXTERM. In
above example, A'+B'+C is a maxterm but A+B and A+C' are simple OR term but not
maxterms.

CANNONICAL P-O-S Form: A function composed of a logical product (AND) of only maxterms
is said to be in CANNONICAL P-O-S form. Any Boolean expression has its equivalent
canonical P-O-S form. For example the equivalent canonical P-O-S form is
F(A,B,C) = (A+B+CC')(A+BB'+C')(A'+B'+C)
= (A+B+C)(A+B+C')(A+B+C')(A+B'+C')(A'+B'+C)
= (A+B+C)(A+B+C')(A+B'+C')(A'+B'+C)
= Π(0,1,3,6)

CIRCUIT DIAGRAMS:

Fig 2.1: Logic circuit for given Boolean equation

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Switching Theory and Logic Design Lab II B.Tech ECE, I Semester AY:2020-21
DIET, Dept., of ECE Design a simple combinational circuit with four variables

Table 2.1: Truth table for Boolean expression

IC Pin Diagrams:

i. IC 74LS08

Fig 2.2: IC 74LS08 Pin diagram for two input AND Gate

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Switching Theory and Logic Design Lab II B.Tech ECE, I Semester AY:2020-21
DIET, Dept., of ECE Design a simple combinational circuit with four variables

ii. IC 74LS32

Fig 2.3: IC 74LS32 Pin diagram for two input AND Gate

PROCEDURE:
1. Place the IC’s on the Digital Trainer Kit as per the circuit diagram.
2. Connect Vcc (Pin-14) and Ground (Pin-7) to respective pins of Digital Trainer Kit.
3. Connect the inputs (at pin no’s 1 & 2) to the input switches provided in the Digital
Trainer Kit.
4. Connect the outputs (Pin no-3) to the switches of output LED’s.
5. Apply Various combinations of the inputs according to the truth table and observe
the condition of LED’s.
6. Disconnect output from the LED’s and note down the corresponding multimeter
Voltage readings for various combinations of inputs.
PRECAUTIONS:
1. The open circuit voltage of the power supply must be stable and close to 5V.
2. Correct components should be connected on the bread board with proper
polarities.

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Switching Theory and Logic Design Lab II B.Tech ECE, I Semester AY:2020-21
DIET, Dept., of ECE Design a simple combinational circuit with four variables

3. A multimeter reading greater than VDD indicates an open connection in the

circuit. Verify the circuit before proceeding.
4. Use multimeter probe tip to gently ease the IC out of breadboard. The mid-
section groove of the breadboard can be used to gently lift the IC. Using bare
hands might cause IC pins to break.
5. In case the logic gate outputs do not make sense, check your circuit
thoroughly. If the problem is still not resolved, get the IC tested by the
technician.
Experiment Results and Observations:
Table 2.2: Truth tables and observation tables for Simplified Boolean
expression

Inputs Outputs
LED Logic
SW3 SW2 SW1 SW0 (1 / 0) DMM (V)
(ON/OFF)
0 0 0 0

0 0 0 1

0 0 1 0

0 0 1 1

0 1 0 0

0 1 0 1

0 1 1 0

0 1 1 1

1 0 0 0

1 0 0 1

1 0 1 0

1 0 1 1

1 1 0 0

1 1 0 1

1 1 1 0

1 1 1 1

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Switching Theory and Logic Design Lab II B.Tech ECE, I Semester AY:2020-21
DIET, Dept., of ECE Design a simple combinational circuit with four variables

RESULT:

……………………………………………
Signature of the Course coordinator

VIVA QUESTIONS
1. Simplify the Boolean expression using demorgans law.
2. What are the application of demorgan's theorem?
3. Explain the formal proof of demorgans law?
4. State Boolean law of Algebra.
5. Explain about distributive and associative laws.
6. What is canonical SOP form?
7. What is canonical POS form?
8. What is minterm?
9. What is maxterm?

*****

15
Switching Theory and Logic Design Lab II B.Tech ECE, I Semester AY:2020-21
 DIET, Dept., of ECE Verification of functional table of 3-to-8 line Decoder

Experiment No: 3 Date:

Verification of functional table of 3-to-8-line Decoder

AIM:
Implementation and verification the functional table of 3-to-8-line decoder.

APPARATUS:
1. Digital IC Trainer kit .… 1 No.
2. Bread board .… 1 No.
3. IC 74139 .… 1 No.
4. Connecting wires

THEORY:

A decoder is a device which does the reverse operation of an encoder,

undoing the encoding so that the original information can be retrieved. The same
method used to encode is usually just reversed in order to decode. It is a
combinational circuit that converts binary information from n input lines to a maximum
of 2n unique output lines. In digital electronics, a decoder can take the form of a
multiple-input, multiple-output logic circuit that converts coded inputs into coded
outputs, where the input and output codes are different. e.g. n-to-2n, binary-coded
decimal decoders. Enable inputs must be on for the decoder to function, otherwise
its outputs assume a single "disabled" output code word. In case of decoding all
combinations of three bits eight (23=8) decoding gates are required. This type of
decoder is called 3-8 decoder because 3 inputs and 8 outputs. For any input
combination decoder outputs are 1.

Fig 3.1: 3 to 8 Line Decoder Block Diagram

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Switching Theory and Logic Design Lab II B.Tech ECE, I Semester AY:2020-21
DIET, Dept., of ECE Verification of functional table of 3-to-8 line Decoder

CIRCUIT DIAGRAMS:

Fig. 3.2: 3 to 8 decoder logic circuit

TRUTH TABLE:

Table 3.3: Truth table for 3 to 8 decoder

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Switching Theory and Logic Design Lab II B.Tech ECE, I Semester AY:2020-21
DIET, Dept., of ECE Verification of functional table of 3-to-8 line Decoder

PROCEDURE:
1. Place the IC’s on the Digital Trainer Kit as per the circuit diagram.
2. Connect Vcc and Ground to respective pins of Digital Trainer Kit.
3. Connect the inputs to the input switches provided in the Digital Trainer Kit.
4. Connect the outputs to the switches of output LED’s.
5. Apply Various combinations of the inputs according to the truth table and observe
the condition of LED’s.
6. Disconnect output from the LED’s and note down the corresponding multimeter
Voltage readings for various combinations of inputs.

PRECAUTIONS:
1. The open circuit voltage of the power supply must be stable and close to
5V.
2. Correct components should be connected on the bread board with proper
polarities.
3. A multimeter reading greater than VDD indicates an open connection in the
circuit. Verify the circuit before proceeding.
4. Use multimeter probe tip to gently ease the IC out of breadboard. The mid-
section groove of the breadboard can be used to gently lift the IC. Using
bare hands might cause IC pins to break.
5. In case the logic gate outputs do not make sense, check your circuit
thoroughly. If the problem is still not resolved, get the IC tested by the
technician.

Experiment Results and Observations:

Table 3.2.1: Truth table and observation table for 3-to-8-line decoder

Inputs
Outputs
Enable Select LED (Low/High)

G2A G2B G1 C B A D0 D1 D2 D3 D4 D5 D6 D7

1 X X X X X

X 1 X X X X

X X 0 X X X

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Switching Theory and Logic Design Lab II B.Tech ECE, I Semester AY:2020-21
DIET, Dept., of ECE Verification of functional table of 3-to-8 line Decoder

0 0 1 0 0 0

0 0 1 0 0 1

0 0 1 0 1 0

0 0 1 0 1 1

0 0 1 1 0 0

0 0 1 1 0 1

0 0 1 1 1 0

0 0 1 1 1 1

Table 3.2.2: Truth table and observation table for 3-to-8-line decoder

Inputs
Outputs
Enable Select Logic (0 / 1)

G2A G2B G1 C B A D0 D1 D2 D3 D4 D5 D6 D7

1 X X X X X

X 1 X X X X

X X 0 X X X

0 0 1 0 0 0

0 0 1 0 0 1

0 0 1 0 1 0

0 0 1 0 1 1

0 0 1 1 0 0

0 0 1 1 0 1

0 0 1 1 1 0

0 0 1 1 1 1

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Switching Theory and Logic Design Lab II B.Tech ECE, I Semester AY:2020-21
DIET, Dept., of ECE Verification of functional table of 3-to-8 line Decoder

RESULT:

……………………………………………
Signature of the Course coordinator

VIVA QUESTIONS
1. What is decoder?
2. What do you mean by encoder?
3. Define priority encoder.
4. What is the difference between encoder and demultiplexer?
5. List out the application of decoders?
6. Distinguish between encoder and decoder?
*****

20
Switching Theory and Logic Design Lab II B.Tech ECE, I Semester AY:2020-21
 DIET, Dept., of ECE 4 variable logic function verification using 8 to 1multiplexer

Experiment No: 4 Date:

4 variable logic function verification using 8 to 1multiplexer

AIM:
To design and verify 4 variable logic function verification using 8 to 1multiplexer.

APPARATUS:
1. Digital IC Trainer kit … 1 No.
2. IC 74151 … 1 No.
3. Connecting wires

THEORY:
Multiplexing is transmitting a large number of signals over a smaller number of
channels or lines. A digital multiplexer is a combinational circuit that selects binary
information from one of the many input lines and directs its binary information to a
single output line. The selection of a particular input is controlled by a set of
selection lines. Normally there are 2n input lines and n selection lines whose bit
combinations determine which input is selected.

BLOCK DIAGRAM:

Figure 4.1: Block diagram of 8:1 multiplexer.

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Switching Theory and Logic Design Lab II B.Tech ECE, I Semester AY:2020-21
DIET, Dept., of ECE 4 variable logic function verification using 8 to 1multiplexer

Figure 4.2: Pin diagram

Table 4.1: Truth Table for 8 to 1 multiplexer

Input Output
Selec
t Y Y′
S2 S1 S0 Enable
x x x 1 0 1
0 0 0 0 D0 D0′
0 0 1 0 D1 D1′
0 1 0 0 D2 D2′
0 1 1 0 D3 D3′
1 0 0 0 D4 D4′
1 0 1 0 D5 D5′
1 1 0 0 D6 D6′
1 1 1 0 D7 D7′

PROCEDURE:
1. Place the IC’s on the Digital Trainer Kit as per the circuit diagram.
2. Connect Vcc and Ground to respective pins of Digital Trainer Kit.
3. Connect the inputs to the input switches provided in the Digital Trainer Kit.
4. Connect the outputs to the switches of output LED’s.
5. Apply Various combinations of the inputs according to the truth table and observe
the condition of LED’s.
6. Disconnect output from the LED’s and note down the corresponding multimeter
Voltage readings for various combinations of inputs.

22
Switching Theory and Logic Design Lab II B.Tech ECE, I Semester AY:2020-21
DIET, Dept., of ECE 4 variable logic function verification using 8 to 1multiplexer

PRECAUTIONS:
1. The open circuit voltage of the power supply must be stable and close to
5V.
2. Correct components should be connected on the bread board with proper
polarities.
3. A multimeter reading greater than VDD indicates an open connection in the
circuit. Verify the circuit before proceeding.
4. Use multimeter probe tip to gently ease the IC out of breadboard. The mid-
section groove of the breadboard can be used to gently lift the IC. Using
bare hands might cause IC pins to break.
5. In case the logic gate outputs do not make sense, check your circuit
thoroughly. If the problem is still not resolved, get the IC tested by the
technician.

Example: S2 S1 S0 = 010 code which corresponds to D2 input data line. Now apply D2
=0/1, this data 0/1 is transmitted to Y.
2. First express the function in the sum of min-terms form e.g. F(A,B,C,D) =
Σ(0,1,3,4,8,9,15), where A is MSB and D is LSB. Connect three variables B, C, D to
the selection lines of the multiplexer with B connected to the highest order selection
line S2 and the last variable D is connected to the lowest order selection line S0.
Consider now the single variable A, since this variable is in the highest order
position in the sequence of variables it will be complemented in the min-terms 0 to 7
which comprise the first half in the list of min-terms. The second half of the min-
terms 8 to 15 will have their A variable uncompleted as shown in observation table.
List all the inputs of the multiplexer and under them list all the min-terms in the
two rows. The first row lists all those min-terms where A is complimented and the
second row all the min terms with un-complimented as shown in Table 2. Circle all
min-terms. Of the function and inspect each column separately.
1. If the two min-term in a column is not circled apply 0 to the corresponding multiplexer
input.
2. If the two min-terms are circled, apply 1 to the corresponding multiplexer input.
3. If the bottom min-term is circled the top is not circled, Apply A to the corresponding
multiplexer input.
4. If the top min-term is circled and the bottom is not circled, apply A′ to the
corresponding multiplexer input.

Example: Implement the following function: F(A,B,C,D) = Σ (0,1,3,4,8,9,15).

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Switching Theory and Logic Design Lab II B.Tech ECE, I Semester AY:2020-21
DIET, Dept., of ECE 4 variable logic function verification using 8 to 1multiplexer

Experiment Results and Observations:

Table 4.2: Truth table and observation table for 8 to 1 Multiplexer for given
example
Inputs Output (F)
LED Logic
A B C D
(Low/High) (0 / 1)
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
1 0 0 1
1 0 1 0
1 0 1 1
1 1 0 0
1 1 0 1
1 1 1 0
1 1 1 1

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Switching Theory and Logic Design Lab II B.Tech ECE, I Semester AY:2020-21
DIET, Dept., of ECE 4 variable logic function verification using 8 to 1multiplexer

RESULT:

……………………………………………
Signature of the Course coordinator

VIVA QUESTIONS
1.Why is MUX called as “Data Selector”?

2.What do you mean by Multiplexing?

3.What is demultiplexer?

4.What is the role of select lines in a Demultiplexer?

5.How many 4:1 multiplexer will be required to design 8:1 multiplexer?

6.Multiplexer has only single output but demultiplexer has many outputs.

*****

25
Switching Theory and Logic Design Lab II B.Tech ECE, I Semester AY:2020-21
DIET, Dept., of ECE Design full adder circuit and verify its functional table.

Experiment No: 5 Date:

Design full adder circuit and verify its functional table

AIM:
To Design full adder circuit and verify its functional table using ICs.
APPARATUS:
1. Digital IC Trainer kit … 1 No.
2. Bread board … 1 No.
3. IC 7400: Quad 2-input NAND gates … 1 No.
4. IC 7486: Quad 2-input XOR gates … 1 No.
5. Connecting wires

THEORY:
So we know that Half-adder circuit has a major drawback that we do not have
the scope to provide ‘Carry in’ bit for addition. In case full adder construction, we
can actually make a carry in input in the circuitry and could add it with other two
inputs A and B. So, in the case of Full Adder Circuit we have three inputs A, B
and Carry In and we will get final output SUM and Carry out. So, A + B + CARRY
IN = SUM and CARRY OUT. Full Adder is the adder which adds three inputs and
produces two outputs. The first two inputs are A and B and the third input is an
input carry as C-IN. The output carry is designated as C-OUT and the normal
output is designated as S which is SUM. A full adder logic is designed in such a
manner that can take eight inputs together to create a byte-wide adder and
cascade the carry bit from one adder to the another.

Fig: 5.1 Block diagram of Full adder.

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Switching Theory and Logic Design Lab II B.Tech ECE, I Semester AY:2020-21
DIET, Dept., of ECE Design full adder circuit and verify its functional table.

Table 5.1 Truth table of Full Adder

Logical Expression for SUM:

= A’ B’ C-IN + A’ B C-IN’ + A B’ C-IN’ + A B C-IN
= C-IN (A’ B’ + A B) + C-IN’ (A’ B + A B’)
= C-IN XOR (A XOR B)
= (1,2,4,7)

Logical Expression for C-OUT:

= A’ B C-IN + A B’ C-IN + A B C-IN’ + A B C-IN
= A B + B C-IN + A C-IN
= (3,5,6,7)

Another form in which C-OUT can be implemented:

= A B + A C-IN + B C-IN (A + A’)
= A B C-IN + A B + A C-IN + A’ B C-IN
= A B (1 +C-IN) + A C-IN + A’ B C-IN
= A B + A C-IN + A’ B C-IN
= A B + A C-IN (B + B’) + A’ B C-IN
= A B C-IN + A B + A B’ C-IN + A’ B C-IN
= A B (C-IN + 1) + A B’ C-IN + A’ B C-IN
= A B + A B’ C-IN + A’ B C-IN
= AB + C-IN (A’ B + A B’)
Therefore COUT = AB + C-IN (A EX – OR B)

27
Switching Theory and Logic Design Lab II B.Tech ECE, I Semester AY:2020-21
DIET, Dept., of ECE Design full adder circuit and verify its functional table.

CIRCUIT DIAGRAMS:

Fig. 5.2: Full-adder logic circuit with pin numbers.

Pin Diagrams of IC 7486 (Ex-OR) and IC 7400 (NAND)

28
Switching Theory and Logic Design Lab II B.Tech ECE, I Semester AY:2020-21
DIET, Dept., of ECE Design full adder circuit and verify its functional table.

PROCEDURE:
1. Place the IC’s on the Digital Trainer Kit as per the circuit diagram.
2. Connect Vcc and Ground to respective pins of Digital Trainer Kit.
3. Connect the inputs to the input switches provided in the Digital Trainer Kit.
4. Connect the outputs to the switches of output LED’s.
5. Apply Various combinations of the inputs according to the truth table and observe
the condition of LED’s.
6. Disconnect output from the LED’s and note down the corresponding multimeter
Voltage readings for various combinations of inputs.

PRECAUTIONS:
1. The open circuit voltage of the power supply must be stable and close to
5V.
2. Correct components should be connected on the bread board with proper
polarities.
3. A multimeter reading greater than VDD indicates an open connection in the
circuit. Verify the circuit before proceeding.
4. Use multimeter probe tip to gently ease the IC out of breadboard. The mid-
section groove of the breadboard can be used to gently lift the IC. Using
bare hands might cause IC pins to break.
5. In case the logic gate outputs do not make sense, check your circuit
thoroughly. If the problem is still not resolved, get the IC tested by the
technician.

Experiment Results and Observations:

Table 5.2 Truth table and observation table for Full Adder

Inputs Outputs LED Outputs

(Low / High) Logic (0 / 1)

A B C Sum Carry Sum Carry

0 0 0

0 0 1

0 1 0

0 1 1

29
Switching Theory and Logic Design Lab II B.Tech ECE, I Semester AY:2020-21
DIET, Dept., of ECE Design full adder circuit and verify its functional table.

1 0 0

1 0 1

1 1 0

1 1 1

RESULT:

……………………………………………
Signature of the Course coordinator

VIVA QUESTIONS:
1) Write the expressions for Half-Adder, Full-Adder & Subtractor?
2) What is meant by fan out of a logic gate?
3) What is the difference between carry and borrow?
4) Design a full-adder circuit using two half adders.
5) Design a full-subtractor circuit using two half subtractors.
6) What is a don’t care condition?
7) What is the use of K-map in combinational logic circuit design?
8) What is a hazard? When does it occur?
9) How is the propagation delay of a combinational circuit determined?
9) Design a Full-adder using MUX?

*****

30
Switching Theory and Logic Design Lab II B.Tech ECE, I Semester AY:2020-21