VLSI Design

Unit II
Mrs. T.Sunitha, Asst.Prof
Dept. of Electronics and Telematics Eng.
GNITS, Hyderabad

3 October 2020 VLSI Design 1

 Unit II
VLSI Circuit Design Processes
• VLSI Design flow
• MOS layers, Stick diagrams
• Design rules and layout
• Layout diagrams for nMOS and CMOS
inverters and gates
• 2 mm CMOS design rules for wires, contacts
and transistors
• Scaling of MOS circuits
• Limitations of Scaling
3 October 2020 VLSI Design 2
 Design Rules and Layout
 Design rules are a set of geometrical specifications that
dictate the design of the layout

 Layout is top view of a chip

 Design process are aided by stick diagram and layout

 Stick diagram gives the placement of different

components and their connection details. But the
dimensions of devices are not mentioned

 Circuit design with all dimensions is Layout

3 October 2020 VLSI Design Chapter 3 Part 2 3
 Design Rules and Layout
 Fabrication process needs different masks, these masks are prepared
from layout

 Layout is an Interface between circuit designer and fabrication

engineer

 Layout is made using a set of design rules.

 Design rules allow translation of circuit (usually in stick diagram or

symbolic form) into actual geometry in silicon wafer

 These rules usually specify the minimum allowable line widths for
physical objects on-chip

 Example: metal, polysilicon, interconnects, diffusion areas,

minimum feature dimensions, and minimum allowable separations
between two such features.
3 October 2020 VLSI Design Chapter 3 Part 2 4
 Design Rules and Layout
• Designers always want to maximize
the performance of their circuits
by minimizing the dimensions.

• Objective:
To achieve a high overall yield and reliability
while using the smallest possible silicon area.

Design rules specify geometry of masks that

provide reasonable yield.

Ref [1]
3 October 2020 VLSI Design Ch. 3 Part 2 5
 Design Rules

• There are two approaches to describe the design rules:

1. Lambda rules:
Which specify the layout constraints in terms of single
parameter(λ), and thus, allow linear, proportional scaling of
all geometrical constraints.

2. Micron rules:
In which the layout constraints such as minimum
feature sizes and minimum allowable spacing, are stated in
terms of absolute dimensions (in micrometers).

Ref [R6]

3 October 2020 VLSI Design Ch. 3 Part 2 6

 Lambda (l)-based design rules

• Specify every dimension of a system in terms of a

parameter λ which assigns a value. The
technology used decide the value of λ.
• Simple set of rules for the designer
• Wide acceptance to the feature size of the
fabrication process
• Allows for scaling of designs to a limited extent
• If design rules are correctly obeyed, mask
layouts(designs) will produce working circuits
for a range of values to λ.

3 October 2020 VLSI Design Ch. 3 Part 2 7

 Lambda (l)-based design rules

λ = L/2; L = The minimum feature size of transistor

L=2λ
Example:
l = 1 mm,
then min. feature size = 2l = 2 mm

If min. feature size = 1 mm

then l = 0.5 mm

•These design rules also specify line width, separations and

extensions in terms of λ.
•Design rules are used for wires, transistors, contacts,
additional CMOS rules. Ref [1]

3 October 2020 VLSI Design Ch. 3 Part 2 8

 Design Rules: NMOS

3 October 2020 VLSI Design Chapter 3 Part 2 9

 Design Rules: NMOS

3 October 2020 VLSI Design Chapter 3 Part 2 10

 Design Rules: NMOS

3 October 2020 VLSI Design Chapter 3 Part 2 11

 Design Rules: NMOS

3 October 2020 VLSI Design Chapter 3 Part 2 12

 Design Rules: NMOS
 Minimum diff width 2l
 Minimum poly width 2l
 Minimum metal width 3l
 poly-poly spacing 2l
 diff-diff spacing 3l
(depletion regions tend to spread outward)
 metal-metal spacing 3l

 diff-poly spacing l

3 October 2020 VLSI Design Chapter 3 Part 2 13

3 October 2020 VLSI Design Chapter 3 Part 2 14
 Design Rules and Layout

Design Rules for wires (nMOS and pMOS)

Fig. 3.6
Design rules
for wires
nMOS and CMOS
Ref [1]

3 October 2020 VLSI Design Ch. 3 Part 2 15

 Design Rules and Layout
Transistor design rules (nMOS, pMOS), CMOS)

Fig. 3.7 Transistor

Design rules
nMOS, pMOS and
CMOS

Ref [1]

3 October 2020 VLSI Design Ch. 3 Part 2 16

 Design Rules and Layout

Contact Cuts :
Electrical connection can be established between
layers by special structures called contact cuts.

Contact – types between polysilicon and diffusion

are
1. Poly to Metal
2. Metal to diffusion
3. Buried contact
– poly to diffusion
4. Butting (overlapping) contact
- poly to diffusion using metal Ref [1]
3 October 2020 VLSI Design Ch. 3 Part 2 17
 Design Rules and Layout

Contacts (nMOS and CMOS) Metal 1 to PolySi

or Metal 1 to diffusion

Via : Metal 2 to Metal 1

Fig. 3.8.
Design rules
Metal 2 to diffusion for contact
nMOS and CMOS

Ref [1]

3 October 2020 VLSI Design Ch. 3 Part 2 18

 Contact Cuts

• Making contacts between metal and other

two layers
- 2lx2l cut indicates an area in which oxide is
to be removed down to the underlying poly or
diffusion surface.

- Deposition of metal layer makes contacts

through the cuts

3 October 2020 VLSI Design Chapter 3 Part 2 19

 Buried Contact

3 October 2020 VLSI Design Chapter 3 Part 2 20

 Buried Contact

3 October 2020 VLSI Design Chapter 3 Part 2 21

 Design Rules and Layout

Contacts – PolySi to diffusion – Buried contact

1. Buried contact

Fig. 3.9. Contacts

polysilicon to diffusion

Ref [1]
3 October 2020 VLSI Design Ch. 3 Part 2 22
 Butting Contact
• The gate and diffusion of NMOS device can be
connected by a butting contact.

• Two contact cuts are adjacent to each other

• Therefore effective contact area is less

• Here metal makes contact to both the diffusion forming

the drain of the transistor and to the polySi forming this
device’s gate.
3 October 2020 VLSI Design Chapter 3 Part 2 23
 Design Rules and Layout
Contacts – PolySi to diffusion – Butting contact
Butting contact

Metal 1 PolySi Diffusion

Fig. 3.9. Contacts

polysilicon to diffusion

Ref [1]

3 October 2020 VLSI Design Ch. 3 Part 2 24

 Design Rules and Layout
Contacts
Buried Contacts
• Contact cut is made
• Thin oxide is removed
• Polysilicon is deposited directly on crystalline silicon
• During diffusion, both poly and silicon get doped
Thus good connection between poly and Si.

Butting Contacts
• 2λx2λ cut is made to each of the layers to be connected
• The layers are butted together so that the two contacts are
contiguous
• Contact is made through metal deposition

3 October 2020 VLSI Design Ch. 3 Part 2 25

Ref [1]
 Design Rules and Layout

Cross section of contacts

PolySi Metal 1 Diffusion
PolySi Diffusion

Buried contact Butting contact

Fig. 3.10. Cross-sections through some Contact structures
3 October 2020 VLSI Design Ch. 3 Part 2 26
Ref [1]
 Design Rules and Layout

Double metal CMOS process

• M2 is used for Global VDD and VSS rails

• M1 is used for local distribution of power
and for signal lines
• Metal 1 and Metal 2 are orthogonal wherever
possible
• Connection between Metal 1 and Metal 2
through vias
• M2 is coarser than M1
• M2 is thicker and wider
• Insulation between layers is also thicker
Ref [1]
3 October 2020 VLSI Design Ch. 3 Part 2 27
 Design Rules and Layout
Cross section of contacts

Metal 2 Via
Metal 1 Contact

n-diffusion

Metal 2 to Metal 1 to n-diffusion

Fig. 3.10. Cross-sections through some Contact structures
3 October 2020 VLSI Design Ch. 3 Part 2 28
Ref [1]
 Design Rules and Layout

• Oxide between poly and M1 is deposited using

CVD (chemical vapor deposition )
• Oxide between M1 and M2 is deposited using
CVD
• Oxide between M1 and M2 is planarized using
etch back technique or
chemical mechanical planarization
(CMP)

Ref [1]
3 October 2020 VLSI Design Ch. 3 Part 2 29
 Design Rules and Layout

Double poly CMOS process

• A thin layer of oxide is deposited over Poly 1
• Poly 2 is deposited on top of the oxide
• Poly 2 is used as additional interconnection
layer
• Poly 2 transistors are formed by intersection
of poly 2 with diffusion
• EEPROM transistor structures use 2 poly
layers

Ref [1]
3 October 2020 VLSI Design Ch. 3 Part 2 30
 Design Rules and Layout

Rules for p-well CMOS process

Fig. 3.11. particular rules for p-well CMOS process

Ref [1]
3 October 2020 VLSI Design Ch. 3 Part 2 31
 Design Rules and Layout

Rules for p-well CMOS process

Fig. 3.11. particular rules for p-well CMOS process

Ref [1]
3 October 2020 Ch. 3 Part 2 32
VLSI Design
 Design Rules and Layout
CMOS based design rules

Ref [1]
Fig. 3.11. particular rules for p-well CMOS process
3 October 2020 VLSI Design Ch. 3 Part 2 33
 Design Rules and Layout
Design Rules for Contacts/Vias

Fig. 3.12. Design rules

for contacts, including
factors contributing to
higher yield/reliability

Ref [1]

3 October 2020 VLSI Design Ch. 3 Part 2 34

 Design Rules and Layout
Design Rules for contacts

Fig. 3.12. Design rules for contacts, including

factors contributing to higher yield/reliability
Ref [1]

3 October 2020 VLSI Design Ch. 3 Part 2 35

 Design Rules and Layout
CMOS based design rules
CMOS process
- More complex than nMOS process
- Design rules consist of > 100 Separate rules
- This figure shows rules specific to CMOS
- Additional rules are related to p-well, p+ mask and
substrate/well contacts

Ref [1]
3 October 2020 VLSI Design Ch. 3 Part 2 36