VLSI Design

Unit II
Mrs. T.Sunitha, Asst.Prof
Dept. of Electronics and Telematics Eng.
GNITS, Hyderabad

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 Unit II
VLSI Circuit Design Processes
• VLSI Design flow
• MOS layers, Stick diagrams
• Layout diagrams for nMOS and CMOS
inverters and gates
• Design rules and layout
• 2 µm CMOS design rules for wires, contacts
and transistors
• Scaling of MOS circuits

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 MOS Layers

• MOS circuits are formed on 4 basic Layers

- n-diffusion
- p-diffusion
- Polysilicon
- Metal
• These are isolated from each other by thick or
thin (thinox) silicon dioxide insulating layers.
• The thin oxide mask region includes n-diffusion,
p-diffusion and transistor channels.
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 MOS Layers

• Polysilicon and thinox regions interact, so that a

transistor is formed where they cross one
another.
• BJTs can be included in this design process by
the addition of extra layers to a CMOS process is
called BiCMOS technology.
• Set the simple diagrams which convey both
layer information and topology.

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22 October 2022 VLSI Design 5
 Stick diagrams
• VLSI design aims to translate circuit concepts
onto silicon.
Stick diagrams :

• The layout of the stick diagrams reflect

the topology of the actual layout in siliconRef [1]

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 Stick diagrams
• To describe logic networks, it is convenient to use stick
diagrams which helps to visualize the function as well as the
topology of the network.
• Does show all components/vias.
• – Via is used to connect higher level metals from metal
connection
• It shows relative placement of components.
• Goes one step closer to the layout
• Helps plan the layout and routing

• A stick diagram is a cartoon of a layout.

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 Stick diagrams

• Does not show

– Exact placement of components
– Transistor sizes
– Wire lengths, wire widths, tub boundaries
– Any other low level details such as
parasitics

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 Stick diagrams- Colour Codes

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 nMOS Design Style
Single metal, single poly process Ref [1]
Layers involved:
• n-diffusion (n-diff) and other thin oxide regions
(thinox or active) (green)
• Polysilicon 1 (poly) (red)
• Metal 1 (blue)
• Implant (yellow yellow)
• Contacts (black or brown [buried] )
Important note:
A transistor is formed wherever poly crosses n-diff
(red over green)
All diffusion wires (interconnections) are n-type (green)
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 Single Metal nMOS Process
Color plate 1(a)
Color coding for stick diagrams - nMOS

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 Stick Diagrams – Some Rules
Rule 1:
When two or more ‘sticks’ of the same type cross or touch
each other that represents electrical contact.

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 Stick Diagrams – Some Rules
Rule 2:
When two or more ‘sticks’ of different type cross or touch each
other there is no electrical contact.
(If electrical contact is needed we have to show the connection
explicitly)

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 Stick Diagrams – Some Rules
Rule 3:
When a poly crosses diffusion it represents a transistor.

Note: If a contact is shown then it is not a transistor.

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 Stick Diagrams – Some Rules
Rule 4:
In CMOS a demarcation line is drawn to avoid touching of p-diff
with n-diff. All PMOS must lie on one side of the line and all
NMOS will have to be on the other side.

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 Single Metal nMOS Process
Color plate 1(a)
Color coding for stick diagrams - nMOS

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 Double Metal CMOS p-well Process
Color plate 1 (b)

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VLSI Design
 Double Metal CMOS p-well Process
Color plate 1 (b)

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VLSI Design
 Double Metal Double poly
BiCMOS n-Well Process – Plate 1(c)

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VLSI Design
 Double Metal Double poly
BiCMOS n-Well Process – Plate 1(c)

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VLSI Design
 nMOS Design Style

nMOS Design Style

Single metal, single poly process

Ref [1]

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VLSI Design
 nMOS Design Style
Single metal, single poly process
General Rule: Need to have concept of
regularity and generality
so that design effort can be minimized and
interconnection of cells and
subsystems facilitated.

Procedure
1. Draw metal (blue) VDD and GND rails
2. Draw thinox (green) paths, with contacts
3. Draw poly (red) to make transistors
4. Draw implants (yellow)
for depletion mode transistors Ref [1]

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 nMOS Design Style
5. Write the L:W ratio for each transistor
6. Input signal may be switched by
pass transistor
7. Long signal lines require metal lines (blue)
8. Leaf-cell boundaries are marked
Note : Run control signals in poly at right angles to
Metal 1
(Leaf cell = A cell that does not contain
any instances of other cells. It is at the bottom
of the hierarchy)

Ref [1]

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 Aspect Ratio For Pull-up andPull-down
 The size of a MOSFET depends on the reference inverter design.

 The reference inverter for nMOS logic design is the inverter with depletion
mode load.

 ZPD = Aspect Ratio of pull-down= LPD/WPD

 ZPU = Aspect Ratio of pull-up= LPU/WPU

 The ratio of aspect ratio of Pull-up and Pull-down is known as Inverter

Ratio i.e.Rinv = ZPU / ZPD

 When we draw a stick diagram, inverter ratio should be mentioned for that
gate.

 When a we draw a stick diagram, aspect ratio should be mentioned for all
the MOSFETs.
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 Aspect Ratio For Pull-up andPull-down

 For example, if we say, the reference design has

Rinv = 4:1, then, ratio of effective ZPU and effective ZPD,
should be equal to 4:1.
 Rchannel = (L/W)Rsc

 Therefore:
 if MOSFETs are connected in series, the effective
L/W = (L/W)1+(L/W)2+….

 if MOSFETs are connected in parallel, the effective

L/W = (L/W)1= (L/W)2

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 Aspect Ratio For Pull-up andPull-
down
For NMOS:
 There are two values of Rinv, that are sufficient
for all NMOS basic gates:

 Rinv = 4:1
 To save space.

 Rinv = 8:1
 When input is taken from a pass transistor.

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 Inverter Ratio for NMOS Gates

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 nMOS Design Style

nMOS Stick layout design style

Shift Register cell Logic function

Ref [1]

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 nMOS Design Style

nMOS Stick layout design style

Shift Register cell Logic function

A’ X’
B
A
A
C

Ref [1]
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 nMOS Design Style

nMOS Stick layout design style

Shift Register cell Logic function

Ref [1]
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 Examples of Stick Diagrams

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 Examples of Stick Diagrams
f= [(xy) +z] using NMOS Transistors

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 CMOS Design Style
 Steps for CMOS are similar to NMOS

 But one difference is that depletion mode FETs are not

used.

 Here, yellow/ brown is used to identify PMOS.

 The two types of FET, n and p, are separated in the diagram

by the demarcation line.

 Above this line are all p-type MOSFETs.

 Below this line are all n-type MOSFETs.

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 CMOS Design Style

CMOS Design Style

• Extension of nMOS design style
• Consider Single metal, single poly process

Layers involved:
• n-diffusion (n-diff) and other thin oxide regions
(thinox) (green)
• p-difusion (p-diff) (yellow)
• Polysilicon 1 (poly) (red)
• Metal 1 (blue)
• Contacts (black or brown [buried] )

Ref [1]
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 Double Metal CMOS p-well Process
Color plate 1 (b)

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 Double Metal CMOS p-well Process
Color plate 1 (b)

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 CMOS Design Style
CMOS Design Style
Important note:
• Two types of transistors, n and p types, used.
• A demarcation line is drawn .
• p-transistors above this line and n-transistors
below this line.
• Diffusion paths must not cross
the demarcation line.
• n-diffusion and p-diffusion wires must not join.
• No indication of actual p+ mask in stick diagram, but
will show in the layout.
• Place crosses on VDD and VSS rails to represent
substrate and p-well connections. Ref [1]
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 CMOS Design Style

CMOS Design Style

Procedure
1. Draw metal (blue) VDD and GND rails.
2. Draw an imaginary demarcation line
in between transistors.
3. Place n-transistors below this line
closer to VSS.
4. Place p-transistors above this line,
but below VDD.
5. Place the diffusion paths parallel
to the rails (horizontal in the diagram).
6. Interconnect and n- and p-transistors
Ref [1]
with metal.
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 CMOS Design Style

7. Connect the transistors to the rails.

8. Only metal and poly can cross
the demarcation line,
wires can run in diffusion also.
9. Finally appropriate
interconnections are made.
10. Place crosses for
VSS contacts (for every 4 n-transistors)
VDD contacts (for every 4 p-transistors).
11. Bounding box for the cell.

Ref [1]

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22 October 2022 VLSI Design 41
 Aspect Ratio

For CMOS:
Rinv = 1:1(Ratioless)

 As one of the device is always off.

 1:1 inverter ratio gives more
symmetric layout

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 n-MOS & p-well CMOS inverter
stick diagrams – Plate 1(d)

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 CMOS Design Style

CMOS Design Style

Fig. 3.5 Example of CMOS stick layout design style

Ref [1]

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 Examples of Stick Diagrams

VDD

x x

Gnd

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 Examples of Stick Diagrams
• NAND

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 Examples of Stick Diagrams

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 Double Metal Double poly
BiCMOS n-Well Process – Plate 1(c)

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 Double Metal Double poly
BiCMOS n-Well Process – Plate 1(c)

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 n-well based Bi-CMOS inverter
Plate 1(d)

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 n-well based Bi-CMOS inverter
Plate 1(d)

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 Layout Diagrams

Introduction
• Layout diagram is a schematic of the IC which
describes the exact placement of the components
for fabrication.
• Can be hand drawn on 5 mm square paper
each square representing λ.
• CAD tools can be used.
• Butting contacts need to be avoided.

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 Layout Diagram of CMOS Inverter
Plate 2
CMOS inverter

VSS

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 Monochrome code CMOS Inverter
Plate 2
CMOS inverter

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 Symbolic Diagrams
Translation to Mask form
• Symbolic diagrams
Can be translated into layout form
• Example:
• 1-bit CMOS shift Register

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 1-bit CMOS shift register cell
Plate 7
CMOS Design Style – Shift Register

Simpler representation is symbolic diagram Ref [1]

This diagram facilitates transistor merging
Readily translated into mask layouts
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 1-bit CMOS shift register cell
Plate 7
(b) Derived mask layout

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 Text Books
1. Essentials of VLSI circuits and Systems,
Kamran Eshraghian, Douglas A. Pucknell,
PHI, 2005 edition
2. VLSI Design, K. Lal Kishore, V.S.V.
Prabhakar, I.K. International, 2009.
3. CMOS VLSI Design – A circuit and systems
perspective, Neil H. Weste and David
Harris, Ayan Banerjee, Pearson, 2009.

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 References
1. CMOS logic circuit design, John P.
Uyemura, Springer, 2007.
2. Modern VLSI Design, Wayne Wolf, Pearson
Education, 3rd edition, 1997.
3. VLSI Design, A. Albert Raj, Latha, PHI, 2008.
4. Introduction to VLSI – Mead and Conway,
BS Publications, 2010.
5. VLSI design, M. Michael Vai, CRC Press,
2009.
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