Department of Electrical Engineering

Faculty Member:______Mr. Mugheez ______________ Dated: ________________

Semester:__________3rd________________ Section: __B______________

Group No.:14

EE-221: Digital Logic Design

Lab 8: 2-bit binary Adder and Subtractor

PLO4/CLO4 PLO4/CLO4 PLO5/CLO5 PLO8/CLO6 PLO9/CLO7

Name Reg. No Viva / Lab Analysis Modern Ethics and Individual Total
Performanc of data in Tool Usage Safety and Team marks
e Lab Report Work Obtained

5 Marks 5 Marks 5 Marks 5 Marks 5 Marks 25 Marks

AHMED RAZI ULLAH 366191

OMAIS WASEEM 390616

EE-221: Digital Logic Design Page 1

Lab 8: 2-bit binary Adder and Subtractor

This Lab Activity has been designed to familiarize the students with design and working of binary
adders using basic logic gates.

Objectives:

✓ Design and Implementation of Half Adder

✓ Design and Implementation of a Full Adder using Half Adders
✓ Extending the design to add 2-bit binary numbers
✓ Verification of 4-bit adder IC
✓ Gate-Level Verilog code for 4-bit adder

Lab Instructions

✓ This lab activity comprises three parts, namely Pre-lab, Lab tasks, and Post-Lab Viva
session.
✓ The lab report will be uploaded on LMS three days before scheduled lab date. The students
will get hard copy of lab report, complete the Pre-lab task before coming to the lab and
deposit it with teacher/lab engineer for necessary evaluation. Alternately each group to
upload completed lab report on LMS for grading.
✓ The students will start lab task and demonstrate design steps separately for step-wise
evaluation (course instructor/lab engineer will sign each step after ascertaining functional
verification)
✓ Remember that a neat logic diagram with pins numbered coupled with nicely patched circuit
will simplify trouble-shooting process.
✓ After the lab, students are expected to unwire the circuit and deposit back components
before leaving.
✓ The Total duration for the lab is 3 hrs.
✓ A lab with in-complete lab tasks will not be accepted.
✓ The students will complete lab task and submit complete report to Lab Engineer before
leaving lab.
✓ There are related questions at the end of this activity. Give complete answers.

EE-221: Digital Logic Design Page 2

Pre-Lab Tasks: (2 marks)

1.What do you understand by half and full adders and why are these circuits so
named?

Half Adder is a combinational logic circuit that adds two 1-bit digits. The half
adder produces a sum of the two inputs. A full adder is a combinational logic
circuit that performs an addition operation on three one-bit binary numbers.
The full adder produces a sum of the three inputs and carry value

2. Give the truth table and circuit for half adder and half subtractor.
HALF ADDER HALF SUBSTRACTOR

A B S C A B D B

0 0 0 0 0 0 0 0

0 1 1 0 0 1 1 1

1 0 1 0 1 0 1 0

1 1 0 1 1 1 0 0

EE-221: Digital Logic Design Page 3

 3. Design a full adder/subtractor using the above designed half adders/subtractor

HARDWARE IMPLEMENTATION:

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 4. Now add the subtraction option in your design and show the logic diagram of full adder with
subtractor.

HARDWARE IMPLEMENTATION:

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 5. Can you extend your design to n-bit binary addition? How does input carry propagates through
full adder stages for such design and influences the speed? How can you overcome this
problem?

• This design can be extended to n-binary addition by cascading the circuit n time. The S of each
circuit will represent the result for each digit of the final number. The Cout must be connected
to the Cin of the following circuit. The last circuit will give the final carry out.

• Such design will be slow because each stage will have to wait for the preceding stage to
generate and a carry out to proceed. This is known as the ripple carry circuit.

• To reduce the time taken we can replace the circuit with lookahead carry arrangement, but
this is cost for hardware.

Lab Tasks: (3 marks)

6. Extend your design to 2-bit binary adder and subtractor. Draw the block diagram of the circuit
with inputs, outputs and carry

EE-221: Digital Logic Design Page 6

 BLOCK DIAGRAM:

7. Draw the schematic diagram of the circuit with complete pin configuration, number, each gate
input output and carry. Carry out the hardware implementation of your 2-bit adder subtractor
and show the results to lab instructor

HARDWARE IMPLEMENTATION:

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 8. Get the 4-bit binary adder IC from the lab and verify its functionality. Give IC number and pin-
layout of the IC.

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 IC 74LS83

HARDWARE IMPLEMENTATION:

EE-221: Digital Logic Design Page 9

 9. Give the Gate-Level Verilog Code for four-bit adder and show the results on Simulation. Your
code should contain following modules:
half adder
full adder (by instantiating half adder)
4_bit_ binary_ adder (by instantiating full adder)
test bench_ 4_bit_binary_adder (for 4_bit_ binary_ adder)

Verilog Code:
Waveform/Output:

//Declare the ports of Half adder module

module half_adder(sum,carry,A,B);
input A,B;
output sum,carry;
xor x1(sum,A,B);
and a1(carry,A,B);
endmodule

//now the module for full adder

module fulladder(sum,carry,A,B,C);
input A,B,C;
output sum,carry;
half_adder h1(sum1,carry1,A,B);
half_adder h2(sum,carry2,sum1,C);
or o1(carry,carry1,carry2);
endmodule

module bitadder(E1,E2,E3,E4,Co,Cin,A1,A2,A3,A4,B1,B2,B3,B4);
input A1,A2,A3,A4,Cin,B1,B2,B3,B4;

EE-221: Digital Logic Design Page 10

 output E1,E2,E3,E4,Co;
fulladder f1(E1,c1,A1,B1,Cin);
fulladder f2(E2,c2,A2,B2,c1);
fulladder f3(E3,c3,A3,B3,c2);
fulladder f4(E4,Co,A4,B4,c3);
endmodule

module test3;
reg A1,A2,A3,A4,Cin,B1,B2,B3,B4;
wire E1,E2,E3,E4,Co;
bitadder c1(E1,E2,E3,E4,Co,Cin,A1,A2,A3,A4,B1,B2,B3,B4);
integer i,j,k,l,m,n,o,p,q;
initial
begin
for( i=0;i<2;i=i+1)begin
#100 Cin=i;
for(j=0;j<2;j=j+1)begin
#100 A4=j;
for(k=0;k<2;k=k+1)begin
#100 A3=k;
for(l=0;l<2;l=l+1)begin
#100 A2=l;
for(m=0;m<2;m=m+1)begin
#100 A1=m;
for(n=0;n<2;n=n+1)begin
#100 B4=n;
for(o=0;o<2;o=o+1)begin
#100 B3=o;
for(p=0;p<2;p=p+1)begin
#100 B2=p;
for(q=0;q<2;q=q+1)begin
#100 B1=q;
end
end
end
end
end
end
end
end
end
end
endmodule
WAVEFORM:

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