SN75179B

SLLS003F – OCTOBER 1985 – REVISED OCTOBER 2022

SN75179B Differential Driver and Receiver Pair

1 Features 2 Description
• Meets or exceeds the requirements of The SN75179B is a differential driver and
TIA/EIA-422-B, TIA/EIA-485-A, and ITU receiver pair designed for balanced transmission-line
Recommendation V.11 applications and meets TIA/EIA-422-B, TIA/EIA-485-
• Bus voltage range: –7 V to 12 V A, and ITU Recommendation V.11. The device is
• Positive- and negative-current limiting designed to improve the performance of full-duplex
• Driver output capability: 60 mA Max data communications over long bus lines.
• Driver thermal-shutdown protection
The SN75179B driver output provides limiting for
• Receiver input impedance: 12 kΩ Min
both positive and negative currents. The receiver
• Receiver input sensitivity: ±200 mV
features high input impedance, input hysteresis for
• Receiver input hysteresis: 50 mV Typ
increased noise immunity, and input sensitivity of
• Operates from single 5-V supply
±200 mV over a common-mode input voltage range
• Low power requirements
of –7 V to 12 V. The driver provides thermal
shutdown for protection from line fault conditions.
Thermal shutdown is designed to occur at a junction
temperature of approximately 150°C. The SN75179B
is designed to drive current loads of up to 60 mA
maximum.
The SN75179B is characterized for operation from
0°C to 70°C.
Package Information
PART NUMBER PACKAGE(1) BODY SIZE (NOM)
D (SOIC) 4.9 mm x 3.91 mm
SN75179B P (PDIP) 9.81 mm x 9.43 mm
PS (SOP) 6.2 mm x 5.3 mm

(1) For all available packages, see the orderable addendum at

the end of the data sheet.

A. This symbol is in accordance with ANSI/IEEE Std 91-1984 and

IEC Publication 617-12. Logic Diagram (Positive Logic)
Logic Symbol

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN75179B
SLLS003F – OCTOBER 1985 – REVISED OCTOBER 2022 www.ti.com

Table of Contents
1 Features............................................................................1 5.9 Typical Characteristics................................................ 7
2 Description.......................................................................1 6 Parameter Measurement Information............................ 9
3 Revision History.............................................................. 2 7 Detailed Description......................................................10
4 Pin Configuration and Functions...................................3 7.1 Functional Block Diagram......................................... 10
5 Specifications.................................................................. 4 7.2 Device Functional Modes..........................................11
5.1 Absolute Maximum Ratings........................................ 4 8 Device and Documentation Support............................12
5.2 Recommended Operating Conditions.........................4 8.1 Documentation Support............................................ 12
5.3 Thermal Information....................................................4 8.2 Receiving Notification of Documentation Updates....12
5.4 Electrical Characteristics: Driver................................. 5 8.3 Support Resources................................................... 12
5.5 Switching Characteristics............................................5 8.4 Trademarks............................................................... 12
5.6 Symbol Equivalent...................................................... 5 8.5 Electrostatic Discharge Caution................................12
5.7 Electrical Characteristics: Receiver............................ 6 8.6 Glossary....................................................................12
5.8 Switching Characteristics ...........................................6 9 Mechanical, Packaging, and Orderable Information.. 12

3 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision E (June 2008) to Revision F (October 2022) Page

• Changed the data sheet format to the latest data sheet format..........................................................................1
• Changed the Thermal Information table............................................................................................................. 4

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www.ti.com SLLS003F – OCTOBER 1985 – REVISED OCTOBER 2022

4 Pin Configuration and Functions

Figure 4-1. D, PS, or P Package

Top View

Table 4-1. Pin Functions

PIN
TYPE(1) DESCRIPTION
NAME NO.
1 VCC P 5V Voltage Supply

2 R O RS485 Logic Output

3 D I RS485 Logic Input
4 GND G Ground
5 Y O Non-Inverting RS485 Bus Output
6 Z O Inverted RS485 Bus Output
7 B I Inverted RS485 Bus Input
8 A I Non-Inverting RS485 Bus Input

(1) I = Input, O = Output, I/O = Input or Output, G = Ground, P = Power.

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5 Specifications
5.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
VCC Supply voltage(2) 7 V
Voltage range at any bus terminal –10 15 V
VID Differential input voltage (3) ±25 V
Tstg Storage temperature –65 150 °C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
(2) All voltage values are with respect to network ground terminal.
(3) Differential input voltage is measured at the noninverting input with respect to the corresponding inverting input.

5.2 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
VCC Supply voltage 4.75 5 5.25 V
VIH High-level input voltage Driver 2 V
VIL Low-level input voltage Driver 0.8 V
VIC Common-mode input voltage –7(1) 12 V
VID Differential input voltage, ±12 V
Driver –602 mA
IOH High level output current
Receiver –400 µA
Driver 60 mA
IOL Low level output current
Receiver 8 mA
TA Operating free-air temperature 0 70 °C

(1) The algebraic convention, where the less positive (more negative) limit is designated minimum, is used in this data sheet for
common-mode input voltage and threshold voltage.

5.3 Thermal Information

SOIC (D) PDIP (P) SOP (PS)
THERMAL METRIC(1) UNIT
8 PINS 8 PINS 8 PINS
RθJA Junction-to-ambient thermal resistance 116.7 109.5 84.3
RθJC(top) Junction-to-case (top) thermal resistance 56.3 53.9 65.4

RθJB Junction-to-board thermal resistance 63.4 65.7 62.1

°C/W
ψJT Junction-to-top characterization parameter 8.8 11.6 31.3
ψJB Junction-to-board characterization parameter 62.6 64.5 60.4
RθJC(bot) Junction-to-case (bottom) thermal resistance N/A N/A N/A

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC package thermal metrics application
report.

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5.4 Electrical Characteristics: Driver

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT
VIK Input clamp voltage II = –18 mA –1.5 V
VO Output voltage IO = 0 0 6 V
|VOD1| Differential output voltage IO = 0 1.5 6 V
1/2 VOD1
RL = 100 Ω See Figure 6-1 V
|VOD2| Differential output voltage 2(2)
RL = 54 Ω See Figure 6-1 1.5 2.5 5 V
|VOD3| Differential output voltage See (4) 1.5 5 V
Δ|VOD| Change in magnitude of differential output voltage ±0.2 V
3
VOC Common mode output voltage RL = 54 Ω or 100 Ω, See Figure 6-1 V
–1
Change in magnitude of common-mode output
Δ|VOC| ±0.2 V
voltage(3)
IO Output current VCC = 0 VO = -7 V to 12 V ±100 µA
IIH High-level input current VIH = 2.4 V 20 µA
IIL Low-level input current VIL = 0.4 V –200 µA
VO = –7 V –250
IOS Short circuit output current VO = VCC 250 mA
VO = 12 V 250
ICC Supply current (total package) No load 57 70 mA

(1) All typical values are at VCC = 5 V and TA = 25°C.

(2) The minimum VOD2 with 100-Ω load is either 1/2 VOD2 or 2 V, whichever is greater
(3) Δ|VOD| and Δ|VOC| are the changes in magnitude of VOD and VOC, respectively, that occur when the input is changed from a high level
to a low level.
(4) See TIA/EIA-485-A, Figure 3.5, Test Termination Measurement 2.

5.5 Switching Characteristics

VCC = 5 V, TA = 25°C
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
td(OD) Differential output delay time RL = 54 Ω , See Figure 6-3 15 22 ns
tt(OD) Differential output transition time RL = 54 Ω , See Figure 6-3 20 30 ns

5.6 Symbol Equivalent

DATA-SHEET PARAMETER TIA/EIA-422-B TIA/EIA-485-A
VO Voa, Vob Voa, Vob
| VOD1 | Vo Vo
| VOD2 | Vt(RL = 100 Ω) Vt(RL = 54 Ω)
| VOD3 | Vt (Test Termination Measurement 2)
D | VOD | || Vt|– |Vtt | || Vt|– |V t| |
VOC | Vos | | Vos |
D | VOC | | Vos – Vos | | Vos – V os |
IOS |Isa|, | Isb|
IO |Ixa|, | Ixb| Iia, Iib

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5.7 Electrical Characteristics: Receiver

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT
VIT+ Positive-going input threshold voltage VO = 2.7 V IO = –0.4 mA 0.2 V
VIT- Negative-going input threshold voltage VO = 0.5 V IO = 8 mA –0.2(2) V
Vhys| Hysteresis voltage (VIT+ – VIT– ) 50 mV
VOH High-level output voltage VID = 200 mV IOH = -400 µA See Figure 6-2 2.7 V
VOL Low-level output voltage VID = -200 mV IOL = 8 mA See Figure 6-2 0.45 V
VI = 12 V 1 mA
II Line input current Other input at 0 V See (3)
VI = –7 V –0.8 mA
rI Input resistance 12 kΩ
IOS Short-circuit output current –15 –85 mA
IOS Supply current (total package) No load 57 70 mA

(1) All typical values are at VCC = 5 V and TA = 25°C.

(2) The algebraic convention, where the less positive (more negative) limit is designated minimum, is used in this data sheet for
common-mode input voltage and threshold voltage levels only.
(3) See TIA/EIA-422-B for exact conditions.

5.8 Switching Characteristics

VCC = 5 V, TA = 25°C
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tPLH Propagation delay time, low- to high-level output VID = –1.5 V to 1.5 V 19 35 ns
tPHL Propagation delay time, high- to low-level output CL = 15 pF See Figure 6-4 30 40 ns

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5.9 Typical Characteristics

Figure 5-1. Driver High-Level Output Voltage vs High-Level Figure 5-2. Driver Low-Level Output Voltage vs Low-Level
Output Current Output Current

Figure 5-3. Driver Differential Output Voltage vs Output Current Figure 5-4. Receiver Output Voltage vs Differential Input Voltage

Figure 5-5. High-Level Output Voltage vs High-Level Output Figure 5-6. High-Level Output Voltage vs Free-Air Temperature
Current

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5.9 Typical Characteristics (continued)

Figure 5-7. Receiver Low-Level Output Voltage vs Low-Level Figure 5-8. Receiver Low-Level Output Voltage vs Free-Air
Output Current Temperature

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6 Parameter Measurement Information

Figure 6-1. Driver VDD and VOC

Figure 6-2. Receiver VOH and VOL

A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 1 MHz, 50% duty cycle, tr ≤ 6 ns, tf ≤ 6 ns, ZO =
50 Ω.
B. CL includes probe and jig capacitance.

Figure 6-3. Driver Test Circuit and Voltage Waveforms

A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 1 MHz, 50% duty cycle, tr ≤ 6 ns, tf ≤ 6 ns, ZO =
50 Ω.
B. CL includes probe and jig capacitance.

Figure 6-4. Receiver Test Circuit and Voltage Waveforms

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7 Detailed Description
7.1 Functional Block Diagram

A. Driver input: R(eq) = 3 kΩ NOMR(eq) = equivalent resistor

Figure 7-1. Equivalent of Driver Input
Figure 7-2. Typical of All Driver Outputs

Figure 7-3. Equivalent of Each Receiver Input

Figure 7-4. Typical of All Receiver Outputs

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7.2 Device Functional Modes

Table 7-1. Driver(1)
INPUT OUTPUTS
D Y Z
H H L
L L H

(1) H = high level, L = low level, ? = indeterminate

Table 7-2. Receiver(1)

DIFFERENTIAL INPUTS OUTPUT
A–B R
VID ≥ 0.2 V H
–0.2 V < VID < 0.2 V ?
VID ≤ –0.2 V L
Open ?

(1) H = high level, L = low level, ? = indeterminate

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8 Device and Documentation Support

TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device,
generate code, and develop solutions are listed below.
8.1 Documentation Support

8.1.1 Related Documentation

8.2 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
8.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
8.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
8.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.

8.6 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.

9 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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 PACKAGE OPTION ADDENDUM

www.ti.com 18-Nov-2022

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

SN75179BD LIFEBUY SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 75179B

SN75179BDE4 LIFEBUY SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 75179B
SN75179BDR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 75179B Samples

SN75179BDRG4 ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 75179B Samples

SN75179BP ACTIVE PDIP P 8 50 RoHS & Green NIPDAU N / A for Pkg Type 0 to 70 SN75179BP Samples

SN75179BPE4 ACTIVE PDIP P 8 50 RoHS & Green NIPDAU N / A for Pkg Type 0 to 70 SN75179BP Samples

SN75179BPSR ACTIVE SO PS 8 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 A179B Samples

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 18-Nov-2022

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 12-Oct-2022

TAPE AND REEL INFORMATION

REEL DIMENSIONS TAPE DIMENSIONS

K0 P1

B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2 Q1 Q2

Q3 Q4 Q3 Q4 User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN75179BDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
SN75179BPSR SO PS 8 2000 330.0 16.4 8.35 6.6 2.4 12.0 16.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 12-Oct-2022

TAPE AND REEL BOX DIMENSIONS

Width (mm)
H
W

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN75179BDR SOIC D 8 2500 340.5 336.1 25.0
SN75179BPSR SO PS 8 2000 356.0 356.0 35.0

Pack Materials-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 12-Oct-2022

TUBE

T - Tube
height L - Tube length

W - Tube
width

B - Alignment groove width

*All dimensions are nominal

Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm)
SN75179BD D SOIC 8 75 507 8 3940 4.32
SN75179BDE4 D SOIC 8 75 507 8 3940 4.32
SN75179BP P PDIP 8 50 506 13.97 11230 4.32
SN75179BPE4 P PDIP 8 50 506 13.97 11230 4.32

Pack Materials-Page 3
 PACKAGE OUTLINE
D0008A SCALE 2.800
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT

SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A PIN 1 ID AREA
6X .050
[1.27]
8
1

.189-.197 2X
[4.81-5.00] .150
NOTE 3 [3.81]

4X (0 -15 )

4
5
8X .012-.020
B .150-.157 [0.31-0.51]
.069 MAX
[3.81-3.98] .010 [0.25] C A B [1.75]
NOTE 4

.005-.010 TYP
[0.13-0.25]

4X (0 -15 )

SEE DETAIL A
.010
[0.25]

.004-.010
0 -8 [0.11-0.25]
.016-.050
[0.41-1.27] DETAIL A
(.041) TYPICAL
[1.04]

4214825/C 02/2019

NOTES:

1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.

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 EXAMPLE BOARD LAYOUT
D0008A SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT

8X (.061 )
[1.55]
SYMM SEE
DETAILS
1
8

8X (.024)
[0.6] SYMM

(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE:8X

SOLDER MASK SOLDER MASK

METAL METAL UNDER
OPENING OPENING SOLDER MASK

EXPOSED
METAL EXPOSED
METAL
.0028 MAX .0028 MIN
[0.07] [0.07]
ALL AROUND ALL AROUND

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED

SOLDER MASK DETAILS

4214825/C 02/2019

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

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 EXAMPLE STENCIL DESIGN
D0008A SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT

8X (.061 )
[1.55] SYMM

1
8

8X (.024)
[0.6] SYMM

(R.002 ) TYP
5 [0.05]
4
6X (.050 )
[1.27]
(.213)
[5.4]

SOLDER PASTE EXAMPLE

BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X

4214825/C 02/2019

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

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