KAM 500databook

KAM-500 Databook
This is the April 2009 release of the KAM-500 Databook (HW/BK/0002 | 1 Apr. 2009). The KAM-500 Databook comprises
data sheets for ACRA CONTROL modules and chapters on Environmental Specifications, Equipment Interface and so on. All
controlled documents contained in the KAM-500 Databook are issued by date. The following is a list of the controlled
documents contained in the KAM-500 Databook and their issue dates.
(KAM-500 Databook ordering code: DOC/DBK/001)
Data sheets Data sheets (continued)
Hardware product Issue date | reference number Hardware product Issue date | reference number
ACC/HSK/001 23 Jan. 2008 | DST/J/064 CBM/101 5 Sep. 2008 | DST/P/064
ACC/TRF/001 21 Jan. 2008 | DST/L/057 CBM/102 1 May 2008 | DST/L/043
ACD/BAC/002 23 Jan. 2008 | DST/R/010 CDC/002 18 Oct. 2006 | DST/R/017
ACD/BAC/003 23 Jan. 2008 | DST/R/011 CDC/101 10 Jun. 2008 | DST/S/032
ACD/BAC/004 17 Jan. 2008 | DST/S/043 CHS/03F 15 Apr. 2008 | DST/P/062
ACD/CJB/001 23 Jan. 2008 | DST/P/014 CHS/03U/D 30 May 2008 | DST/S/024
ACM/EXT/001/B 23 Jan. 2008 | DST/K/003 CHS/04L/B 26 May 2008 | DST/N/043
ADC/002/C 10 Jun. 2008 | DST/R/053 CHS/06U/D 12 Nov. 2008 | DST/S/013
ADC/008 3 Nov. 2008 | DST/N/053 CHS/09U/D 30 May 2008 | DST/S/014
ADC/010/C 10 Jun. 2008 | DST/R/046 CHS/12R/D 28 Jan. 2008 | DST/S/029
ADC/011/C 11 Aug. 2008 | DST/R/044 CHS/13U/D 30 May 2008 | DST/S/028
ADC/012/C 10 Jun. 2008 | DST/R/045 CON/KAD/002/CP 23 Jan. 2008 | DST/R/008
ADC/014/D 10 Jun. 2008 | DST/R/022 CON/KAD/002/SR 23 Jan. 2008 | DST/R/009
ADC/105/B 18 Aug. 2008 | DST/U/028 CON/KAD/005/CP 23 Jan. 2008 | DST/S/041
ADC/106/C 14 Jan. 2009 | DST/U/033 CON/KAD/005/SR 23 Jan. 2008 | DST/T/095
ADC/109C/QB120 22 Aug. 2008 | DST/U/032 DAC/001 3 Sep. 2008 | DST/N/077
ADC/109/C/QB350 25 Feb. 2009 | DST/U/030 DEC/003 27 Nov. 2008 | DST/N/039
ADC/109/C/S1 22 Aug. 2008 | DST/T/097 DMY/001 23 Jan. 2008 | DST/U/002
ADC/109/C/S2 22 Aug. 2008 | DST/U/031 DPI/002 22 Dec. 2008 | DST/N/067
ADC/113 28 Jul. 2008 | DST/T/055 DRE/CFM/002 5 Jan. 2009 | DST/R/023
ADC/116 10 Jun. 2008 | DST/S/083 DSI/002 29 Sep. 2008 | DST/N/068
ADC/117/B 22 Aug. 2008 | DST/U/034 DSI/003/B 29 Jan. 2009 | DST/N/091
ADC/118 28 Jul. 2008 | DST/P/065 EBM/101 25 Mar. 2009 | DST/R/049
ADC/120 28 Jul. 2008 | DST/R/006 ENC/005/B 3 Nov. 2008 | DST/P/005
ARI/001/B 4 Sep. 2008 | DST/P/030 ENC/106 10 Nov. 2008 | DST/S/092
ARI/002 3 Sep. 2008 | DST/N/071 ETH/101 2 Mar. 2009 | DST/T/052
ARI/103 24 Mar. 2009 | DST/R/018 FBM/001/B 27 Nov. 2008 | DST/N/027
BIT/101 30 Sep. 2008 | DST/R/015 FBM/102 10 Nov. 2008 | DST/P/052
BCU/101/C 29 Aug. 2008 | DST/S/087 FBM/103/B 5 Feb. 2008 | DST/T/085
BCU/105/B 11 Feb. 2009 | DST/U/006 Handling precautions 3 Mar. 2009 | DST/U/055
Cables 25 Feb. 2009 | DST/J/062 JIG/UNI/001/C 21 Oct. 2008 | DST/R/048
CBC/101 11 Nov. 2008 | DST/P/046 KIT/001 26 Mar. 2009 | DST/J/063
LDC/101 18 Dec. 2008 | DST/P/048
i
Data sheets (continued) KAM-500 Databook Chapters
Hardware product Issue date | reference number
Chapter of KAM- Reference number | issue date
LID/001 23 Jan. 2008 | DST/J/061 500 Databook
MBI/001/B 18 Dec. 2008 | DST/P/019 Introducing KAM-500 11 Sep. 2007
MDC/002 3 Nov. 2008 | DST/N/150 Environmental QD/HW/SPF/L/0001 | 30 May 2008

Specifications
MDC/103 3 Sep. 2008 | DST/S/052
Equipment Interface QD/HW/SPF/L/0002 | 29 Jan. 2008
MEM/003/E 5 Jan. 2009 | DST/T/087
MEM/004/B 15 Jul. 2008 | DST/T/054 See “Revision histories” on page 685 for details of any
revisions to hardware products and controlled documents
MEM/103 6 Jan. 2009 | DST/U/016 since the last release of the KAM-500 Databook.
MSB/001/B 11 Nov. 2008 | DST/N/079
MSB/103/B 25 Mar. 2009 | DST/S/053
PBM/001 10 Nov. 2008 | DST/N/074
PBM/002 18 Oct. 2006 | DST/N/126
PSU/011 6 Nov. 2008 | DST/S/026
PSU/012 6 Nov. 2008 | DST/R/098
RTC/003 16 Sep. 2008 | DST/R/063
SAM/DEC/007/C 29 Oct. 2008 | DST/R/083
SBM/001 18 Dec. 2008 | DST/J/059
SDC/001 25 Sep. 2008 | DST/N/064
SDI/001 23 Dec. 2008 | DST/N/069
SDI/103 20 Jan. 2009 | DST/U/015
TCG/001/C 19 Dec. 2008 | DST/P/033
TCG/102/C 1 May 2008 | DST/T/096
TDC/001 15 Dec. 2008 | DST/M/056
TDC/002/D 28 Jul. 2008 | DST/P/059
UAR/001 10 Nov. 2008 | DST/N/076
UAR/002/C 22 Dec. 2008 | DST/N/133
UAR/102 2 Feb. 2009 | DST/R/004
UAT/101 4 Oct. 2007 | DST/T/071
VDC/001 25 Sep. 2008 | DST/N/065
VID/103 29 Jul. 2008 | DST/P/045
ii
About this book
This book gives a full technical overview of the KAM-500, an advanced rugged and compact system for airborne data acquisi-
tion developed by ACRA CONTROL. It contains the following major sections and appendices:
• Introduction to KAM-500 introduces the KAM-500, explaining key concepts and design goals.
• Data Sheets contains data sheets for all chassis, user-modules and accessories for the KAM-500.
• Environmental Specifications describes the standards the KAM-500 meets and the design considerations taken by ACRA
CONTROL to meet them. All KAM-500 modules have been specifically designed to operate in harsh aerospace test
environments.
• Equipment Interface describes wiring considerations for the KAM-500.
• Appendices contains lists of Abbreviations and Controlled Documents from this book.
• Revision Histories outlines the revision histories of all hardware products and controlled documents in the KAM-500 Databook
The information in this publication is provided for reference only. All information contained in this publication is believed to be
correct and complete. ACRA CONTROL shall not be liable for errors contained herein nor for incidental or consequential dam-
ages in connection with the furnishing, performance, or the use of this material. All product specifications, as well as the infor-
mation contained in this publication are subject to change without notice.
This publication may contain or reference information and products protected by copyrights or patents and does not convey any
license under the patent rights of ACRA CONTROL, nor the rights of others. ACRA CONTROL does not assume any liability
arising out of any infringements of patents or other rights of third parties.
ACRA CONTROL makes no warranty of any kind with regard to this material, including but not limited to, the implied warranties
or merchantability and fitness for a particular purpose.
All world rights reserved. No part of this publication may be stored in a retrieval system, transmitted, or reproduced in any way,
including but not limited to, photocopy, photograph, magnetic or other record, without the prior written permission of
ACRA CONTROL.
2008
KAM-500 DATABOOK
©ACRA CONTROL, 2008
All Rights Reserved
Suggested Reading Paths
Managers or other personnel requiring a brief overview of the features of the KAM-500 “Introducing the KAM-500”
Engineers responsible for installing KAM-500 modules “Handling precautions”
Engineers requiring a full technical overview of any or all chassis, user-modules and “Introducing data sheets”
accessories for the KAM-500
Engineers seeking evidence of the KAM-500’s ruggedness and ability to operate in harsh “Introducing the KAM-500”
aerospace test environments “Environmental specifications”
Engineers responsible for wiring to and from the KAM-500 “Introducing the KAM-500”
“Equipment interface”
Test engineers responsible for power consumption and dissipation analysis “Introducing the KAM-500”
Engineers responsible for installing the KAM-500 “Introducing the KAM-500”

“Equipment interface”
Personnel responsible for ordering KAM-500 components “Introducing the KAM-500”

“Introducing data sheets”
“Ordering information”
Engineers wishing to know the revision histories of hardware products and controlled “Revision histories”
documents
iii
Part-numbering scheme
The part numbering scheme describes the different module ordering information, which is shown at the top of the first page of a
data sheet. See “Introducing data sheets” on page ix.
For modules:
Module top connector:

KAD: 52-way double density module top
connector
KAM: 51-way micro-miniature module top
connector
MKM: MicroKAM module with 51-way micro- ‘1’ indicates a QB350 is an ordering option
miniature module top connector 100 series of the ADC/109/B module
KAD/ADC/109/B/QB350/ET
Module type: ‘B’ is the ET: extended
ADC: Analog design temperature, is a non-
DSI: Digital revision standard ordering option
MSB: Bus
BCU: Backplane
Controllers
ENC: PCM Encoders
For chassis:
KAM/CHS: KAM-500 chassis ‘D’ is the design ET: extended temperature, is a

MKM/CHS: MicroKAM chassis form factor revision non-standard ordering option
KAM/CHS/03U/D/SML/ET
Chassis form factor: SML is an ordering
03U: Standard form factor option.
04L: Long form factor
12R: Round form factor
iv
ACRA Table of contents
C O N T R O L
Handling precautions Handling procedures for KAM-500 modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vii

Introducing data sheets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ix
Chassis and basic modules

BCU/101 KAM-500 backplane controller with IRIG-106 PCM encoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
BCU/105 Fast Ethernet KAM-500 backplane controller and packet generator . . . . . . . . . . . . . . . . . . . . . . . . . .15
PSU/011 +5V, ±7V and ±12V power supply unit for KAM-500 chassis with 9-way connector. . . . . . . . . . . . . . .25
PSU/012 +5V, ±7V and ±12V power supply unit for KAM-500 chassis with 6-way connector. . . . . . . . . . . . . . .29
CHS/03F KAM-500 chassis with 3 user-slots, built with base-mounted power supply and housing . . . . . . . . . .33
CHS/03U KAM-500 chassis with 3 user-slots . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
CHS/04L KAM-500 narrow form chassis with 4 user-slots. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
CHS/12R KAM-500 circular form chassis with 12 user-slots . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
CHS/13U KAM-500 chassis with 13 user-slots . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
SAM/DEC/007 KAM-500 programming interface with IRIG-106 PCM decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
Analog modules
ADC/002 2 channel D/E analog-to-digital converter at 100ksps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
ADC/008 3-phase power monitor module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79
ADC/010 2 channel D/E analog-to-digital converter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85
ADC/011 48 channel S/E analog-to-digital converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93
ADC/012 24 channel D/E analog-to-digital converter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101
ADC/014 16 channel bridge A/D converter with voltage excitation and signal conditioning. . . . . . . . . . . . . . . .109
ADC/105 8 channel D/E analog-to-digital converter with signal conditioning. . . . . . . . . . . . . . . . . . . . . . . . . . .119
KAD/ADC/106 6-channel S/E accelerometer (ICP) analog-to-digital converter with sig. conditioning . . . . . . . . . . . .127
ADC/109/QB120 8-ch. A/D converter, with current exc. and sig. cond. for ¼-bridge 120Ω strain gages. . . . . . . . . . . .137
ADC/109/QB350 8-ch. A/D converter, with current exc. and sig. cond. for ¼-bridge 350Ω strain gages. . . . . . . . . . . .145
ADC/109/S1 8-ch. bridge A/D converter module, with voltage excitation and signal conditioning . . . . . . . . . . . . .153
ADC/109/S2 8-ch. bridge A/D converter with voltage excitation, sense lines and signal conditioning . . . . . . . . . .163
ADC/113 16 channel ¼-bridge A/D converter with excitation and signal conditioning for PT100 . . . . . . . . . . .173
ADC/116 12-ch. accelerometer A/D converter, with current excitation and signal conditioning. . . . . . . . . . . . .181
ADC/117 8 channel A/D converter with bridge signal conditioning & constant current excitation . . . . . . . . . . .191
ADC/118 12-ch. bridge A/D converter with voltage excitation, balancing & signal conditioning . . . . . . . . . . . .201
ADC/120 12-ch. bridge A/D converter with voltage excitation & signal conditioning . . . . . . . . . . . . . . . . . . . . .211
CDC/002 24 channel current to digital convertor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .221
CDC/101 4-channel charge-to-digital converter for piezoelectric devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . .225
LDC/101 4 channel LVDT/RVDT to digital convertor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .233
MDC/002 2 x 64 channel multiplexing A/D converter, with external temperature compensation . . . . . . . . . . . .241
MDC/103 2 x 64 channel multiplexing A/D converter, with polynomial temperature compensation . . . . . . . . . .247
SDC/001 2-channel synchro-to-digital converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .255
TDC/001 16-ch. A/D converter with excitation & sig. conditioning for 2K2 & 10K thermistors . . . . . . . . . . . . . .261
TDC/002 15 channel thermocouple analog-to-digital converter with reference compensation . . . . . . . . . . . . .267
VDC/001 2 channel CVSD voice-to-digital converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .275
Digital modules
DPI/002 16K x 16 bit external dual-port RAM reader . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .283
DSI/002 24 channel discrete input module with counters and time tagging . . . . . . . . . . . . . . . . . . . . . . . . . . .289
DSI/003 24 channel bi-level input module with counters and time tagging. . . . . . . . . . . . . . . . . . . . . . . . . . . .297
Bus modules
SDI/001 8 channel serial data input module (clock out/data in) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .309
ARI/001 8 channel ARINC-429 bus monitor with parity option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .313
ARI/002 Single channel ARINC-429 transmitter module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .321
ARI/103 Single-channel ARINC-573 bus monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .327
v
CBC/101 CAIS (Common Airborne Instrumentation Systems) bus controller . . . . . . . . . . . . . . . . . . . . . . . . . .335
CBM/101 4 channel cross channel data Link (CCDL) monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .341
CBM/102 CAN bus monitor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .351
DEC/003 2 channel IRIG-106 PCM decoder/merger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .359
EBM/101 Ethernet bus monitor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .367
ENC/005 IRIG-106 PCM encoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .379
ENC/106 IRIG-106 PCM encoder with premodulation filter (PMF) output . . . . . . . . . . . . . . . . . . . . . . . . . . . . .387
FBM/001 Single EF-2000 FCS bus monitor module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .395
FBM/102 FireWire bus monitor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .399
FBM/103 S200 beta mode FireWire bus monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .407
MBI/001 A MIL-STD-1553 remote terminal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .415
MSB/001 Dual redundant MIL-STD-1553 bus monitor with D/C and T/C inputs . . . . . . . . . . . . . . . . . . . . . . . .421
MSB/103 Dual redundant MIL-STD-1553 bus monitor with Mode Code 17 support . . . . . . . . . . . . . . . . . . . . .429
PBM/001 8 channel Panavia bus monitor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .441
PBM/002 A parser for the MC (and ENMC) link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .447
SBM/001 Stanag-3910 bus monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .453
KAD/SDI/103 Serial data bus parser. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .459
TCG/001 IRIG-B time code reader and generator with external battery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .467
UAR/001 8 channel RS-232 or RS-422/485 universal asynchronous receiver . . . . . . . . . . . . . . . . . . . . . . . . .475
UAR/002 4 channel RS-232 or RS-422/485 universal asynchronous parser. . . . . . . . . . . . . . . . . . . . . . . . . . .479
UAR/102 4 channel RS-232, RS-422 or RS-485 universal asynchronous parser and snarfer . . . . . . . . . . . . .489
UAT/101 4-channel RS-232 and 4-channel RS-422 universal asynchronous transmitter . . . . . . . . . . . . . . . . .499
Other user-modules
BIT/101 Built-in self test module. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .509
DAC/001 8 channel analog outputs, with 16 channel discrete outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .523
ETH/101 2.5Msample/sec data acquisition and programming over Ethernet . . . . . . . . . . . . . . . . . . . . . . . . . .531
MEM/003 KAM-500 high speed CompactFlash® memory module. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .539
MEM/004 A CompactFlash® memory module with data extraction via Fast Ethernet . . . . . . . . . . . . . . . . . . . .547
MEM/103 KAM-500 series 100 CompactFlash® memory module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .555
RTC/003 Real-time clock generator with memory status outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .563
TCG/102 Combined GPS and IRIG input module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .569
VID/103 Single channel MPEG-4 encoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .587
Accessories and spares

ACD/BAC/002 Electroless nickel-plated aluminum straight-through backshell for KAD connectors . . . . . . . . . . . . .597
ACD/BAC/003 Electroless nickel-plated aluminum 30° double density backshell for KAD connectors . . . . . . . . . . .601
ACD/BAC/004 Electroless nickel-plated aluminum double-density backshell for CON/KAD/003/CP. . . . . . . . . . . . .605
ACD/CJB/001 15 channel reference junction block for thermocouples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .609
ACC/TRF/001 6-channel power transformer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .613
ACC/HSK/001 Optional heat sinks for the KAM-500 system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .617
ACM/EXT/001 Extender board for the KAM-500 system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .621
Cables Standard cables used for KAM-500 system assembly . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .623
DRE/CFM/002 MEM/003 and MEM/103 compatible CompactFlash® cards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .629
DMY/001 Dummy module for empty KAM-500 chassis user-slot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .633
JIG/UNI/001 Universal test jig for KAM-500 modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .635
CON/KAD/002/CP 52-way double-density KAD module mating connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .637
CON/KAD/002/SR 2-way double-density connector for temperature sensor in the module connector . . . . . . . . . . . . . .641
CON/KAD/005/CP 52-way double-density KAD module mating connector with rear grommet . . . . . . . . . . . . . . . . . . . .645
CON/KAD/005/SR 52-way double-density mating connector for TDC/002 with rear grommet. . . . . . . . . . . . . . . . . . . . .649
KIT/001 Standard tools used for KAM-500 system assembly . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .653
LID/001 Spare user-slot lids and spare screws for the KAM-500 system . . . . . . . . . . . . . . . . . . . . . . . . . . . .657
Chapters and controlled lists

Introducing the KAM-500 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 661
Environmental specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 665
Equipment interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 669
Appendices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 681
Revision histories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 685
vi
KAM-500
Handling precautions Handling procedures for KAM-500 modules
Inserting or removing a module

The greatest risk of damage to hardware is when removing modules. If care is not taken, surface mount components can be
dislodged or broken off. To reduce this risk, follow all precautions in this section.
Keyed to prevent
incorrect insertion Work from this end of the chassis when
of module removing modules (towards J1)
SERIAL No.
MODEL
ACRA CONTROL
J1 When removing a
Ensure power single module, loosen
is disconnected the screws on adjacent
modules
Work from this end of the chassis when

inserting modules (away from J1)
Ensure the module is perpendicular Tilting the module to either side can
to the chassis when inserting or damage components on adjacent
removing it. modules.
90°
Chassis groove
Chassis connector
Removing a module
When removing more than one module, start at the slot furthest from J1 (power connector).
1. Disconnect the power cable from the KAM-500 chassis.
2. Loosen adjacent module screws. This allows some “wriggle room” for the module you are removing.
3. Remove any cables/mating connectors from the module that you are removing.
4. Completely loosen the captive thumbscrews.
5. Holding the loosened thumbscrews, firmly pull the module upwards approximately 7mm (0.25 inch) to free it from the
connector on the chassis.
6. Once free from the connector, keep the module perpendicular to prevent it touching adjacent modules as you remove it
from the chassis.
3 Mar. 2009 | DST/U/055 vii

Inserting a module
When inserting more than one module, start at the slot nearest J1 (power connector).
1. Disconnect the power cable from the KAM-500 chassis.
2. With the module perpendicular to the chassis and aligned with the chassis grooves, insert the module into the chassis.
3. Press the module firmly into the connector on the chassis.
4. Tighten the captive thumbscrews to torque 0.25Nm (0.18 foot pound-force).
Module screw torque settings

The following are the recommended torque settings for module screws:
Screw type Location Recommended torque setting
Spring-mounted captive thumbscrews On each KAM-500 module 0.25Nm (0.18 foot pound-force)
4-40 UNC stainless steel screw Mating connector: 0.25Nm (0.18 foot pound-force)
(See warning below on overtightening these CON/KAD/002/CP When tightening the 4-40 UNC connectors,
screws.) CON/KAD/002/SR turn each side alternately one turn until
CON/KAD/002/SR tightened.
Do not overtighten the 4-40 UNC screws.

If the 4-40 UNC screws on the mating connectors have too much torque applied to them, they can damage the module by
loosening the nut that holds the jack post in place.
If you are using a torque screwdriver, apply the correct torque.
If you do not have a torque screwdriver, tighten the screws firmly, but do not overtighten them.
SERIAL No.
MODEL
ACRA CONTROL
4-40 UNC screw

J1 locations
KAM-500 electrostatic considerations

Always ensure that proper ElectroStatic Discharge (ESD) precautions are in place before
handling or storing ACRA CONTROL equipment.
KAM-500 modules outside the KAM-500 chassis are vulnerable to electrostatic damage. Specifically the pins that connect to the
KAM-500 backplane are at risk.
• When transporting or storing KAM-500 modules, ensure that they are placed in antistatic bags.
• In a laboratory environment, use antistatic mats and wrist straps.
• When antistatic equipment is not available, touch some metal frame (on an aircraft for example) to discharge static from your
body before removing the module from the antistatic bag. Only handle the module by the electrically-isolated orange top block.
• Do not touch any pins on the module.
Data sheet text and specifications are subject to change without notice. © 2009 ACRA CONTROL. All rights reserved.
ACRA CONTROL INC, 44145 Airport View Drive, Hollywood, MD 20636, USA, Phone: (301) 373-9220, Fax: (301) 373-9223, Email: [email protected]
ACRA CONTROL LTD, Landscape House, Landscape Road, Dublin 14, Ireland, Phone: +353-1-2951264, Fax: +353-1-2951265, Email: [email protected]
www.acracontrol.com
viii 3 Mar. 2009 | DST/U/055

ACRA Introducing data sheets
C O N T R O L
KAD/ADC/109/B/S1, KAM/ADC/109/B/S1 Module variations
Title of the data sheet

A C R A KAM-500 ADC/109/S1
C O N T R O L 8 channel bridge A/D module, with voltage excitation and signal conditioning
Unique description of the
DESCRIPTION
module.
ADC/109/B/S1
The ADC/109/S1 has eight channels of signal conditioning

and data acquisition for differential voltages/strain gage/
bridge measurements. In addition to the measurement
channel, the ADC/109/S1 provides independent bipolar
Key features, especially those that

excitation for up to eight channels. Each differential-ended
signal has a separate programmable amplifier, filter and A/D
converter.
A full description of the
differentiate this product from other FEATURES
At the heart of the ADC/109/S1 is a hard-wired state-machine
that over-samples all channels at a rate between 96ksps and
module and its key
features
192ksps and digitally filters any noise above the user
revisions.
• 8 full or ½-bridge, potentiometer or differential-ended (D/E)
programmable cutoff frequency. This is achieved using
input channels
cascaded, half-band, decimate by two, fifteen tap, finite-
• 16-bit simultaneous sampling on all channels
impulse-response (FIR) filters with 32-bit coefficients followed
• High accuracy
by an 8th order Butterworth IIR filter with a default cutoff point
• Programmable excitation, balance current and range per
set at 25% of the sampling frequency.
channel
• 8th order Butterworth filter with programmable cutoff All signals are sampled simultaneously. Thus, when several
frequency per channel channels are sampled at different sampling rates, at the start
• Short to ground on any channel does not affect others of an acquisition cycle all channels will be aligned.
• Bipolar excitation and balancing before instrumentation The ADC/109/S1 is available with two different connector
amplifier options – the KAM/ADC/109/S1 has a 51-way micro-
• Up to 24,000 samples per second per channel
Suggested uses for the module.

miniature connector and the KAD/ADC/109/S1 has a 52-way
double density connector.
APPLICATIONS
• Bridge sensors
• Differential voltage measurement
• Strain gage measurement
EXC_V(0)+
- DIGITAL m
A block diagram of the module. It

2 + ANALOG
+ VREF
-
STANDARD BUS INTERFACE AND LOGIC

also shows, where possible, the GAIN [1, 10, 100, 1000]
essential pin numbers (for ANALOG(0)+
ANALOG(0)-
5
4
+
-
ANALOG
oDIGITAL
6
u
COUNTS
o UNITS
example, the first channel or bus).

AAAF DIGITAL FILTER LOOKUP TABLE
INST. AMP
-
EXC_V(0)- +
3 +
-
1 VADJ
ADJUST(0) DIGITAL m
6
ANALOG
34.8K [RADJ ] ADC/109/S1
1 Optional connection for strain gage balance adjust
First of 8 channels on the ADC/109/S1

DST/R/061 4 Oct. 2006
Selection guide and ordering information

Selection Paths
The selection guide describes where Airborne Data Acquisition o KAM-500 o Modules o Analog o Bridge
Ordering Information
the most recent datasheet can be Part Number Mating Connector Description
found on www.acracontrol.com.
KAD/ADC/109/B/S1
KAM/ADC/109/B/S1
CON/KAD/002/CP
ACC/CON/008/04
ADC/109/B/S1 module, with 52-way double density module top connector.
ADC/109/B/S1 module, with 51-way micro-miniature module top connector.

Ordering information
By default, the standard mating connector above is included with each module in the shipment. Its part number will be added to
the Confirmation of Order unless an alternative option is specified (see Cables data sheet).
addresses questions such as
The ADC/109/B/S1 requires power from a ±7V supply for excitation and cannot be used in chassis without this supply, e.g.
The revision history lists the

CHS/04L (See relevant chassis datsheets for voltage supplies available).
Revision History
“Does this part come as
differences between this module and
Revision Differences Status standard when I order any
ADC/109/B/S1 Reduced power consumption on the ±7V power lines. Recommended for new programs
earlier revisions. ADC/109/S1 8 channel bridge A/D converter with excitation and signal
conditioning.
Not recommended for new programs other part?”
“What else do I need to order?”
In this data sheet ADC/109/S1 refers to both the KAD and KAM version of the module.
Similar modules and related software Related Products

Module Details
for the module. ADC/109/B/QB/350 8 channel 350: ¼-bridge ADC module with voltage excitation.
“What ordering options are
ADC/109/B/S2 Has two excitation sense lines for each channel to compensate for lead resistances and internal
KSM-500
offset-adjust.
This module is supported by the KSM-500 suite of software tools.

there?”
Related documentation for the Related Documentation
module.
Document Details
TEC/NOT/001 Strain gages and ideal bridges
TEC/NOT/002 Bridge balancing and shunt calibration
TEC/NOT/017 Accuracy on KAM-500 modules
DOC/MAN/018 KSM-500 Databook
DOC/HBK/002 Environmental Qualification Handbook
DOC/DBK/001 KAM-500 Databook
www.acracontrol.com
ix
Details the specifications of the inputs
and outputs for each module. Specifications
General specifications
Parameter Min Typ Max Units Condition/Details
Slots used 1 - - - Can be placed in any user-slot in any combination
Mass - 98 100 g
- 3.45 3.52 oz.
Height above chassis For recommended clearance requirements, see
bare connector - 11 - mm CON/KAD/002/CP datasheet for KAD modules, and ACC/
bare connector - 0.43 - in CON/008/04 for KAM modules.
Throughput
aggregate - - 192 sps
Power consumption Figures given do not include current used for excitation.
+5 - 135 150 mA
+12 - 65 70 mA
-12 - 45 50 mA
+7 - 42 52 mA
-7 - 27 32 mA
total power - 2.5 2.8 W
Environmental ratings1 Chassis base/side plate temperature.
operating temperature -40 - +85 °C
storage temperature -55 - +125 °C
1. Please refer to Environmental Qualifications Handbook for further details of environmental specifications.
Differential ended analog inputs

Parameter Min Typ Max Units Condition/Details
Inputs 8
Sampling rate 1 - 24x103 sps While the sampling rate can be set up indvidually, each must
have a power of two time any other. (¼, ½ ...2, 4).
Input voltages
primary gain=1 - - ±10 V
primary gain=10 - - ±1 V
primary gain=100 - - ±100 mV
primary gain=1000 - - ±10 mV
overvoltage protection ±40 - - V Voltages outside of this range may damage input.
DC error DC signal averaged over 200 samples without excitation.
gain=1, 10, 100 - - 0.08 % FSR
gain=2, 20, 200 - - 0.14 % FSR
gain=4, 40, 400 - - 0.25 % FSR
gain=8, 80, 800 - - 0.44 % FSR
gain=1000 - - 0.3 % FSR
gain=2000 - - 0.6 % FSR
gain=4000 - - 1.2 % FSR
Effective number of bits
gain=1, 10, 100 - 13.5 - bits
gain=1000 - 9.5 - bits
Crosstalk Between channels on the same module.
gain=1, 10, 100 - - -60 dB
gain=1000 - - -40 dB
Common mode
voltage range ±10 ±12 - V Operational voltage range.
rejection ratio 53 72 - dB Applies within the above CM voltage range, 0df dfc.
Ripple ratio
0 df 0fc - - 0.01 dB
Analog filter
poles - - 2
filter cutoff -3dB 10.25 12.5 13.75 kHz
filter delay - 0.02 - S
3 DST/R/061
These tables show parameter,

instrumentation, packages, and
Setting up parameters
For channels Analog(0) to Analog(7)
datalink setup information required Set-up data

Name
Choice
No limit to characters
Default/Example
MySignal
Notes
or supplied by the module, in

Base Unit Volt Volt
maximum -10 to +10 +10 Dependent on excitation.
minimum -10 to +10 -10 Dependent on excitation.
particular parameters to be read or

Data Format Offset binary Offset binary
Size In Bits 4 to 16 16
Balance
written to the module and settings settings

current shunt ±0.071839 0 Required shunt current (in mA) for the bridge.
available within the module. Please It is recommended that names are less than 20 characters, have no white space, bold or italic characters or contain any of the
following five characters "/><\.
see www.xidml.org for more details Setting up instrumentation

about XidML. This module uses the X-Module-Analog-In XidML schema. (See http://www.xidml.org)

Set-up Data Choices Default/Example Notes
Manufacturer
name ACRA CONTROL ACRA CONTROL
part reference KAD/ADC/109/B/S1 KAD/ADC/109/B/S1 ACRA CONTROL part number.
serial number Fixed 6 characters FE1234 Unique number for each module.
Sub location 1 to 80 characters MyDAU Name of DAU.
slot 3 to N 3 The DAU slot the module fits into. First user-module goes into slot 3,
where N is the number of user-slots +2 in the DAU.
Settings
filter cutoff 0.25, 0.5, 1, 2, 4, 8, 0.25 Required cutoff point for the filter is the chosen value multiplied by
16 the user sampling frequency. 0.25 is recommended as any higher
may lead to aliasing. 1 is the sample rate.
excitation 0 to 5.1 0.2 Required excitation (in V) for the top of the bridge. Excitation is
bipolar so entering 5V means 10V across the bridge.
9 Nov. 2006 | DST/R/061 5
x
Getting the most from is an informal Getting the most from the ADC/109/S1
discussion on how best to use the

EXC_V(1)+ - DIGITAL m
In bridge applications, if the lead resistance can be measured 8
+
+
-
ANALOG VREF
or estimated, add the voltage drop across the leads to the

excitation voltage. For example, for 0.5: leads in a 350:
module. This section highlights

full-bridge where ±5V (10V) is desired across the bridge the GAIN [1, 10, 100, 1000]
excitation should be set to 5V + (0.5 x 10/350) = ±5.014. ANALOG(1)+

11 + ANALOG
oDIGITAL
6 COUNTS
o UNITS
10 - u
Otherwise if sense lines are required, please refer to the ANALOG(1)-

INST. AMP
common mistakes and answers some

ADC/109/S2. -
EXC_V(1)- +
9 +
As illustrated opposite, the analog inputs can be used as -
VADJ
differential inputs (that is, not from a bridge). In this case, if ADJUST(1)
12
DIGITAL m
frequently asked questions.

ANALOG
34.8K [RADJ ] ADC/109/S1
the signal source is isolated with respect to the KAM-500 (for 51
example a battery), a common-mode resistance between the

negative input and ground (GND) should be used to provide a Figure 3: Second of 8 independent ½-bridge channels
return for bias currents and reduce common-mode noise
pick-up. Because the bias currents are in the order of nAs
resistors up to 10k: can be used. In most cases a short (0:)
is recommended. EXC_V(2)+
14
-
+
+
DIGITAL m
ANALOG VREF
-
The recommended cutoff point is one quarter the sampling

frequency as this means the maximum filtering of aliasing
GAIN [1, 10, 100, 1000]
frequencies. However for gains above 1000 the ANALOG(2)+
17
gain-bandwidth product of the amplifier reduces the ANALOG(2)-
16
+
-
ANALOG
oDIGITAL
6
u
COUNTS
o UNITS
AAAF
bandwidth to 1000Hz. In order to simplify the time-correlation INST. AMP DIGITAL FILTER LOOKUP TABLE
of data when processing (especially in real-time) it may be EXC_V(2)- +

-
15 +
worth considering setting the same cutoff point on all -
channels even if the sampling rates are different. ADJUST(2)

18
VADJ
DIGITAL m
ANALOG
34.8K [RADJ ] ADC/109/S1
51
Modelling 8th order Butterworth filter by the IIR digital filter
causes small phase and amplitude errors shown on the
graphs below. The ADC/109/S1 has additional delay of 3.5Ps Figure 4: Third of 8 independent potentiometer channels
from the filter on the daughterboard. Also, primary gains
higher than 1 cause additional delay from 1st order filter in
instrumentation amplifier. That additional delay is 3Ps for gain EXC_V(3)
20
-
+
DIGITAL m
ANALOG VREF
+
of 10 and 13.6Ps for gain of 100. -

y ( y)
3 Delay error (Ideal minus actual delay)

GAIN [1, 10, 100, 1000]
2.5
[degrees]
ANALOG(3)+
2 23 + ANALOG 6 COUNTS
22 - oDIGITAL u o UNITS
1.5 ANALOG(3)-
INST. AMP
1
Error (Ideal-acc [degrees]

Error (Ideal-acc
0.5 -
ADJUST(3) +
21 +
0 -
0.01 0.1 1 10
-0.5
VADJ
EXC_V(3) DIGITAL m
24 ANALOG
-1
34.8K [RADJ ] ADC/109/S1
51
-1.5
-2
-2.5
-3
Fin/Fc Figure 5: Fourth of 8 independent differential-ended channels
Figure 1: Delay error
100 Amplitude error (ideal minus actual attenuation)
0
Error[mdB] 0.01 0.1 1 10
-100
Error [mdB]
-200
-300
-400 Fin/Fc
Figure 2: Amplitude error
6 9 Nov. 2006 | DST/R/061
Name and description of each connector Connector pinout of KAD/ADC/109/S1

pin. For more information refer to the 1
Pin
NC
Name I/O Description
Do not connect
Comment
“Equipment interface” section of the KAM- 2

3
EXC_V(0)+
EXC_V(0)-
Excitation pos.
Excitation neg.
Excitation to top of bridge
Excitation to bottom of bridge
Excitation for channel 0
500 Databook.
4 ANALOG(0)- Analog D/E In Analog input
5 ANALOG(0)+ Analog D/E In Analog input
6 ADJUST(0) Adjust current Used to balance/calibrate bridge
7 NC Do not connect
8 EXC_V(1)+ Excitation pos. Excitation to top of bridge Excitation for channel 1
9 EXC_V(1)- Excitation neg. Excitation to bottom of bridge Excitation for channel 1
Pins that are part of address/data busses

or multiple channels have a bracketed

13 NC Do not connect
number as suffix. These numbers always 16

17
18
ANALOG(2)-
ANALOG(2)+
ADJUST(2)
Analog D/E In
Analog D/E In
Adjust current
Analog input
Analog input
Used to balance/calibrate bridge
start with 0. 19
20
21
NC
EXC_V(3)+
EXC_V(3)-
Excitation pos.
Excitation neg.
Excitation to top of bridge
Excitation to bottom of bridge
Do not connect
Connector pinout comments are
intended for the engineer
responsible for wiring.
+ and - suffix always indicate a differential-
ended pair
51 GND KAM-500 internal ground
52 CHASSIS KAM-500 chassis DD connector only
Data sheet text and specifications are subject to change without notice. © 11/9/06 ACRA CONTROL. All rights reserved.
www.acracontrol.com
7 9 Nov. 2006 | DST/R/061

Document reference number.
xi
This page is intentionally blank
A C R A Chassis and basic modules
C O N T R O L
1
KAD/BCU/101/C, KAM/BCU/101/C
A C R A KAM-500 BCU/101
KAM-500 backplane controller with IRIG-106 PCM encoder
C O N T R O L
APPLICATIONS
• PCM encoding
DESCRIPTION
The BCU/101 functions as two modules in one; an encoder
and a backplane controller. The encoder is functionally
identical to the ENC/005 and encodes data from any
KAM-500 module in an IRIG-106 Chapter 4 PCM stream.
Parameters to be transmitted are stored in pre-defined
locations in RAM. Each parameter has a word definition that
FEATURES includes the bits per word, MSB sent first/last, and parity. The
encoder has differential-ended (D/E) RS-422 outputs for
ENCODER clock and data along with buffered TTL outputs for NRZ-L
• 100% IRIG-106 compliant and the bit/word/minor-frame/major-frame pulses.
• Fully software programmable Up to 15 formats (instruction sequences), can be stored at
• Up to 13 PCM codes at up to 20Mbps any time. Format selection is via four single-ended (S/E)
• 5 to 250k words per major frame discrete (0-5V) input pins on the I/O connector. Because up
• 5 to 32k words per minor frame to 64 chassis can be programmed using a single
• 4 to 64 bits per word, with even, odd or no parity programming link there are also six discrete I/O pins to set a
• Supports any syncword and sub-frame strategy chassis number. These six inputs are pulled to ground
• Pin-configurable to include RS-422 termination resistors internally if left open circuit.
• ARINC-573/717 compatible output
CONTROLLER
• Stores up to 15 formats
• Supports dynamic format switching
• Can operate as a MASTER or SLAVE in distributed systems
• Support for fast programming
• Support for programming via CAIS controller
ENCODER
+ 120
15 +
DATA(0)
- PARALLEL ←
16 - RAM
SERIAL
+ 120
17 +
DCLK(0)
- -
18
CONTROL
PROG_DATA_TRM+ 120
27
+
PROG_DATA
25 + PROGRAMMING
- FORMAT EEPROM
26 - INTERFACE
GND
51
CONTROLLER BCU/101
BCU/101: Encoder shown with D/E PCM outputs only; controller shown with programming I/O only
29 Aug. 2008 | DST/S/087 3

Selection Paths
Airborne Data Acquisition → KAM-500 → Modules → Backplane Controllers
Part Number Mating Connector Description
KAD/BCU/101/C CON/KAD/002/CP KAM-500 BCU/101/C module with 52-way double density module top
connector
KAM/BCU/101/C ACC/CON/008/04 KAM-500 BCU/101/C module with 51-way micro-miniature module top
connector
the Confirmation of Order unless an alternative option is specified (see the Cables data sheet).
Revision History
Revision Differences Status
BCU/101/C Extended common mode drivers for PCM and X-SYNC Recommended for new programs
BCU/101/B Supports ADC/005 programming (requires kProgram 1.6 Not recommended for new programs
or later) and supports distributed system with external
synchronization
BCU/101 First release Not recommended for new programs
In this data sheet BCU/101/C refers to both the KAD and KAM version of the module.
Related Products
Module Details
KSM-500 This module is supported by the KSM-500 suite of software tools
Related Documentation
Document Details
DOC/HBK/002 Environmental Qualifications Handbook
TEC/NOT/024 Evolution of Pulse Code Modulation
TEC/NOT/027 IRIG 106-96 Chapter 4
TEC/NOT/035 Rules for PCM placement
TEC/NOT/036 Capturing asynchronous IRIG-106 PCM streams
www.acracontrol.com
4 29 Aug. 2008 | DST/S/087

Specifications
All values provided in the following specification tables are valid within the operating temperature range specified under
“Environmental ratings” in the “General specifications” table.
Parameter Min. Typ. Max. Units Condition/Details

Slots – – 1 – Use in controller slot only (J2).
Mass
– 72 – g
– 2.53 – oz Design metric is grams.
Height above chassis For recommended clearance requirements see the
CON/KAD/002/CP data sheet for KAD modules, and see the
ACC/CON/008/04 data sheet for MicroKAM and KAM modules.
bare connector – – 11 mm
bare connector – – 0.43 in. Design metric is millimeters.
Access rate – – 2 Msps Maximum combined access rate for read and write.
Power consumption
+5V 800 – 990 mA
+7V 0 – 0 mA
-7V 5 – 5 mA
+12V 0 – 0 mA
-12V 800 – 990 mA
total power 4.06 – 5.01 W
Environmental ratings See Environmental Qualifications Handbook.
operating temperature -40 – 85 °C Chassis base/side plate temperature.
storage temperature -55 – 105 °C
RS-422 inputs

Inputs – – 1 –
Signaling rate
X_SYNC_IN – 1 – Mbps
Input voltage
operating range -7 – 12 V Do not exceed operating range.
logic ‘0’ – – -0.2 V VIN+ - VIN-
logic ‘1’ 0.2 – – V VIN+ - VIN-
overvoltage protection -60 – 60 V Voltages outside of this range can damage input.
ESD protection -15 – 15 kV Human Body Model.
Input resistance
between inputs (on) – 150 – kΩ Module powered on.
between inputs (off) – 60 – kΩ Module powered off.
between inputs (term, on) – 120 – Ω Module powered on and inputs terminated.
between inputs (term, off) – 120 – Ω Module powered off and inputs terminated.
each input to GND (on) – 30 – kΩ Module powered on.
each input to GND (off) – 50 – kΩ Module powered off.
29 Aug. 2008 | DST/S/087 5

BTTL inputs

Signaling rate
FORMAT[3:0] – – 500 kHz Must be stable for 8µs before start of acquisition cycle.
CHASSIS_ID[5:0] – – – – Is assumed never to change while powered up.
MEM-TRIGGER – – 1 MHz Minimum pulse width, signal active high.
Input voltage
operating range 0 – 5.5 V
logic ‘0’ – – 0.8 V
logic ‘1’ 2 – – V
Input resistance
each input to GND (on) 88 – – kΩ Module powered on.
each input to GND (off) 12 – – kΩ Module powered off.
High-speed RS-422 outputs

Outputs – – 8 –
Signaling rate
DATA[3:0] – – 20 Mbps RZ, NRZ-L/M/S, RNRZ-L 11/13/15/17.
DATA[3:0] – – 8 Mbps Biø-L/M/S, DM-M/S.
DCLK[3:0] – – 20 MHz
Output voltage
operating range -15 – 20 V
logic ‘0’ – – -2 V V0+ - V0- ; RLOAD = 100Ω
logic ‘1’ 2 – – V V0+ - V0- ; RLOAD = 100Ω
short circuit current – – 250 mA
short circuit duration 90 – – s Only one output may be shorted at a time.
overvoltage protection -27 – 27 V
Output resistance – 65 – Ω
Low-speed RS-422 outputs

Signaling rate
X_SYNC_OUTA – 1 – Mbps
X_SYNC_OUTB – 1 – Mbps
Output voltage
logic ‘0’ – – -2 V V0+ - V0- ; RLOAD = 100Ω
logic ‘1’ 2 – – V V0+ - V0- ; RLOAD = 100Ω
short circuit duration ∞ – – s Only one output may be shorted at a time.
6 29 Aug. 2008 | DST/S/087

BVDD outputs

Range 4.8 5 5.1 V
Current output
compliance1 – – 12 mA For driving chassis and format lines.
short circuit duration ∞ – – s To GND.
1. Currents in excess of the maximum value shown will result in output voltages below the minimum voltage required to be detected
as a logic ‘1’ for a standard BTTL input.
BTTL outputs

Signaling rate
DATA – – 16 Mbps
DCLK – – 16 MHz
NRZ_L – – 16 Mbps
WORD_PULSE – – 16 MHz High for last bit of any word.
MINOR_PULSE – – 4 MHz High for last word of minor frame.
MAJOR_PULSE – – 4 MHz High for last word of major frame.
Output voltage
logic ‘0’ – – 0.2 V Sinking 0.1mA through 100Ω output resistance.
logic ‘1’ 4.8 – – V Sourcing 0.1mA through 100Ω output resistance.
Output resistance 100 – – Ω
RS-485

Channels – – 1 –
Signaling rate
PROG_DATA – – 1 Mbps
Input voltage
logic ‘0’ – – -0.2 V VIN+ - VIN-
logic ‘1’ 0.2 – – V VIN+ - VIN-
Output voltage
logic ‘0’ – – -2 V V0+ - V0- ; RLOAD = 100Ω
logic ‘1’ 2 – – V V0+ - V0- ; RLOAD = 100Ω
Input resistance
between inputs (on) – 150 – kΩ Module powered on.
29 Aug. 2008 | DST/S/087 7

Setting up the BCU/101
For register TimeHi
Set-up data Choice Default/Example Notes

Name TimeHi BCU101_HI_TIME Hours and minutes time of the start of the acquisition cycle.
Base Unit Unitless Unitless R[15:13] Reserved
R[12:11] Tens of hours
R[10:7] Hours
R[6:4] Tens of minutes
R[3:0] Minutes
maximum 11D916 000216
minimum 0 0
Data Format BitVector BitVector
Size In Bits 16 16
For register TimeLo

Name TimeLo BCU101_LO_TIME Seconds and centiseconds time of the start of the acquisition cycle.
Base Unit Unitless Unitless R(15) Reserved
R[14:12] Tens of seconds
R[11:8] Ones of seconds
R[7:4] Tenths of seconds
R[3:0] Hundredths of seconds
maximum 599916 000216
minimum 0 0
Data Format BinaryCodedDecimal BinaryCodedDecimal
Size In Bits 16 16
For register MicroTime

Name MicroTime BCU101_MICRO_TI Microsecond time of the start of the acquisition cycle.
ME
Base Unit Unitless Unitless R[15:12] Milliseconds
R[11:8] Hundreds of milliseconds
R[7:4] Tens of microseconds
R[3:0] Microseconds
maximum 999916 000216
minimum 0 0
Size In Bits 16 16
For register STATUS

Name Status BCU101_status Status of module synchronization.
Base Unit Unitless Unitless R(15) MEM-TRIGGER pin status
R(14) Reserved for future use
R(13) X_SYNC in lock
R(11) Errors in X_SYNC since last read
R[10:0] Reserved for future use
maximum FFFF16 000216
minimum 0 0
Size In Bits 10 to 16-bits 16
8 29 Aug. 2008 | DST/S/087

Setting up instrumentation
This module uses the X-Module-Pcm-Out-1.1 schema. (See http://www.xidml.org.)
For transaction channels

Manufacturer
part reference KAD/BCU/101 KAD/BCU/101 ACRA CONTROL part number.
InterConnect 0 or 1 0 InterConnect associates a named datalink with a named datalink.
Setting up packages
This module uses the X-IRIG-106-Ch-4-1.1 schema. (See http://www.xidml.org.)

Packages per 1 The number of major frames per acquisition cycle.
acquisition
cycle
Data link No character limit MyTTL_PCMDataLink A named datalink.
reference
Major frame
Properties
parity Odd, Even, None None
data bits per word 4 to 64 16 Default number of bits per word can be changed for particular
words later on.
minor frames per 1 to 8192 1 Sets the number of minor frames in a major frame.
major frame
bits per minor 80 to 4194304 2048 Use of multiple formats restricts this to 512000 bits per frame when
frame 15 formats are programmed.
Synchronization
strategy
sync word 4 to 64 bits 32 Enter the sync word as hexadecimal. Synchronization bits is the
number of bits in the synchronization word.
In the XidML file, the sync word pattern is binary. Minimal word
length is four bits for bit-rates of 8MHz and less; for higher bit-rates
it is Bitrate[MHz]/2.
Modulation
PCM code NRZ-L/S/M NRZ-L Code used for bit transmission, the options are dependent on the
BIØ-L/S/M modules used.
DM-M/S
RZ
RNRZ-L 11/13/15/17
DCLK phase 0/180 0 Shifts the data clock in phase by 180°.
PCM polarity True/False True Inverts the PCM.
Content
parameter No character limit P1
minor frame 0 to 8191 0
number
minor frame offset 0 to 8191 0
words
occurrences
most significant First/Last First MSB transmitted can be changed for particular words.
bit
It is recommended that names are less than 20 characters, have no white space, bold or italic characters or contain any of the
29 Aug. 2008 | DST/S/087 9

Getting the most from the BCU/101 DCLK
The BCU/101 is divided into two parts; a backplane controller S/E BTTL clock output with 100Ω resistor in series. Becomes
and a PCM encoder. The backplane controller organizes data the inverse of the DATA output when the module is
transfer over the KAM-500 backplane, and the PCM encoder configured to generate an ARINC-573/717 data stream.
encodes data in a PCM stream.
WORD_PULSE
Backplane controller inputs and outputs S/E BTTL output with 100Ω resistor in series. High for the last
The BCU/101 has the following backplane controller inputs bit of each word. Its falling edge is aligned to the end of the
and outputs: last bit of each word.
PROG_DATA± MINOR_PULSE
D/E RS-485 bi-directional bus for data transfer during S/E BTTL output with 100Ω resistor in series. High for the last
programming (not terminated internally). These pins are word of each minor frame. Its falling edge is aligned to the
electrically repeated on the connector to ease use in end of the last bit of each minor frame.
distributed systems.
MAJOR_PULSE
CHASSIS_ID[5:0] S/E BTTL output with 100Ω resistor in series. High for the last
Six S/E BTTL inputs for setting the chassis number in word of each major frame. Its falling edge is aligned to the
distributed systems. When left unconnected these inputs set end of the last bit of each major frame.
the chassis number to 0, which is the ID number for the
master chassis in a distributed master/slave system. (See Timing, bit-rates and commutation
“Addressing multiple chassis” on page 11.)
Figure 2 shows examples of timing for NRZL and Bi-Phase L
(BIØ-L). For maximum bit-rates and supported PCM
Backplane controller and PCM encoder transmission see “Specifications” on page 5.
inputs
The following inputs affect both the backplane controller and DATA (BiøL)
the PCM encoder:
DATA (NRZL)
FORMAT[3:0]
DATA+ (NRZL)
Four S/E BTTL inputs for setting the format. (See
“Understanding formats” on page 11.) When left unconnected
these inputs set the format number to 0. After the format DATA- (NRZL)
select lines change, the new format takes effect on the first bit
DCLK
of the first word of the next major frame. Fifteen formats are
available (016 to E16 in HEX; FORMAT(0) is the LSB).
DCLK+
X_SYNC_IN±
D/E RS-422 input to slaves (CHASSIS_ID[5:0]≠0 in a
DCLK-
distributed system) is connected to the X_SYNC_OUT± of
the X_SYNC generating unit. A synchronization sequence is
WORD_PULSE
transmitted at the end each major frame to synchronize
operation in a distributed system. (See “Synchronization of
MINOR_PULSE
multiple chassis” on page 11.)
PCM encoder outputs MAJOR_PULSE
The BCU/101 has the following PCM encoder outputs:

Figure 2: Timing for outputs
DATA[3:0]±
The BCU/101 allows variable word lengths and non-standard
D/E RS-422 output. Differential PCM coded data output. commutation (that is, samples of a specific parameter not
evenly spaced in the PCM frame). However, ACRA
DCLK[3:0]± CONTROL recommends using a default word length (for
example, 16 bits) and evenly spaced commutation.
D/E RS-422 output. Differential data clock, consists of a
transition at the start and centre of each bit transmitted.
ARINC-573 setup
DATA When ARINC-573/717 mode of operation is selected, the
DCLK output becomes the logical inverse of the DATA output
S/E BTTL output with 100Ω resistor in series.
and is used as the DATA- output to the ARINC-573/717
system. The DATA output is used as the DATA+ output to the
ARINC-573/717 system.
10 29 Aug. 2008 | DST/S/087

Understanding formats We are most interested in information from:
Formats are user-created configurations used by KAM-500 • Channels 4/5/6 on Module 1 sampled at 1024sps
equipment. They are designed using software tools and • Channels 4/5/6 on Module 2 sampled at 512sps
programmed into the hardware. Typical formats contain • Channel 5 on Module 3 sampled at 4096sps
information about the following: A separate format can be created for each of the above
• PCM frame rate and PCM code used scenarios as in these examples:
• The number of bits per word (Scenario 1) Format 0 (FORMAT[3:0] = [0,0,0,0])
• The number of words per minor frame
• The number of minor frames in a major frame (Scenario 2) Format 1 (FORMAT[3:0] = [0,0,0,1])
• Parameters and sample rates for modules active in that The KAM-500 system will change to the appropriate format if
format the format select lines equal one of these values. There are
In the format example in Figure 3, a chassis contains one 15 available formats for user application.
backplane controller and three data acquisition modules. All
modules have six channels. Addressing multiple chassis
There are six chassis select lines permitting you to define any
address from 0-63. Any slot can be used to distribute
Module 3 information to and from two additional chassis using the
appropriate ACRA CONTROL equipment.
CHASSIS_ID[5:0] must be unique for each chassis in the
Module 2 distributed system, otherwise the system cannot be
programmed or used correctly.
Module 1 CHASSIS_ID[5:0] = 000000 is used to identify the master

chassis.
Backplane controller Synchronization of multiple chassis

Synchronization of multiple chassis is achieved using
X_SYNC. X_SYNC is a broadcast synchronization signal with
a 1µs resolution, transmitted by the X_SYNC source and
Figure 3: Format example received by all X_SYNC targets. X_SYNC contains
information about the time, format used and the start of the
During a series of tests, there could be two distinct test acquisition cycle.
scenarios.
The controller in the master chassis (CHASSIS_ID[5:0] = 0)
Scenario 1 will generate X_SYNC if no other X_SYNC source is installed
in the master chassis.
If an X_SYNC source is present in the master chassis, the
master chassis BCU/101 will act as an X_SYNC slave,
X_SYNC being provided by the alternative X_SYNC source.
M = Module; Ch. = Channel

X_SYNC_IN+_TRM
12 120Ω
Figure 4: Major frame structure (1)
X_SYNC_IN+
13
We are most interested in information from: X_SYNC_IN-
14
• Channels 1/2/3 on Module 1 sampled at 2048sps
• Channels 4/5/6 on Module 2 and Module 3 sampled at X_SYNC_IN+_COPY
30
1024sps
X_SYNC_IN-_COPY
31
Scenario 2
X_SYNC_OUTA+
32
X_SYNC_OUTA-
33
X_SYNC_OUTB+
35
M = Module; Ch. = Channel
X_SYNC_OUTB-
36
Figure 5: Major frame structure (2)
Figure 6: XSYNC in the BCU/101
29 Aug. 2008 | DST/S/087 11

Considerations when implementing a
distributed system
Distributed systems often have chassis separated by
distances of many feet. Sending X_SYNC over these cables
will result in delays. To compensate for this, review the data
sheet for the cable used and determine the delay induced by
that cable.
ACRA CONTROL recommends using high quality,

shielded twisted pair cabling between chassis.
The delay is calculated as cable length (feet) multiplied by

delay parameter per foot. These details can be entered into
the KSM-500 setup window when creating the distributed
system format.
The resolution for the adjustment of X_SYNC is 125ns. A
maximum of 1.5µs can be used as a delay. Consider the
following scenarios:
Master single slave scenario
Master Slave
chassis chassis
100ft
750ns delay
Figure 7: Master with single slave
In Figure 7, a master and slave chassis are separated by 100

feet of cable and the cable has a propagation delay of 7.5
ns/foot. The delay is 750ns to send X_SYNC to the slave. In
this case the master acquisition cycle is delayed by 750ns so
that the slave and master trigger simultaneously.
Master with two slaves scenario
Master Slave Slave

chassis chassis1 chassis2
100ft 100ft
750ns delay 750ns delay
Figure 8: Master with two slaves
In Figure 8, a master and two slaves are each separated by

100 feet of cable and the cable has a propagation delay of
7.5 ns/foot. The delay is 750ns to send X_SYNC to Slave
chassis1 and a further delay of 750ns to Slave chassis2.
In this case, the master acquisition cycle is delayed by 2 x
750ns = 1.5µs and the delay is programmed into Slave
chassis1 as 750ns so that both slaves and the master trigger
simultaneously.
12 29 Aug. 2008 | DST/S/087

Connector pinout of the KAD/BCU/101
Pin Name See specifications table Comment
1 FORMAT(0) BTTL inputs Format select line; internally pulled to 0; LSB
2 FORMAT(1) BTTL inputs Format select line; internally pulled to 0
3 FORMAT(2) BTTL inputs Format select line; internally pulled to 0
4 CHASSIS_ID(0) BTTL inputs Chassis identifier/address; internally pulled to 0; LSB
5 CHASSIS_ID(1) BTTL inputs Chassis identifier/address; internally pulled to 0
8 FORMAT(3) BTTL inputs Format select line; internally pulled to 0; MSB
10 BVDD BVDD outputs 5V buffered with 220Ω resistor; used to set FORMAT and
CHASSIS_ID
11 MEM-TRIGGER BTTL inputs Trigger for memory recording; internally pulled to 0
12 X_SYNC_IN_TRM+ RS-422 inputs Synchronization in; with internal 120Ω resistor
13 X_SYNC_IN+ RS-422 inputs Synchronization in; not internally terminated
14 X_SYNC_IN- RS-422 inputs Synchronization in; not internally terminated
15 DATA(0)+ High-speed RS-422 outputs PCM output 0; internally terminated with 120Ω
16 DATA(0)- High-speed RS-422 outputs PCM output 0; internally terminated with 120Ω
17 DCLK(0)+ High-speed RS-422 outputs Bit clock for PCM output 0; internally terminated with 120Ω
18 DCLK(0)- High-speed RS-422 outputs Bit clock for PCM output 0; internally terminated with 120Ω
19 WORD_PULSE BTTL outputs High for last bit of word
20 MINOR_PULSE BTTL outputs High for last word of minor frame
21 MAJOR_PULSE BTTL outputs High for last word of major frame
22 DATA BTTL outputs PCM output or DATA+ for ARINC-573 out
(See “ARINC-573 setup” on page 10.)
23 DCLK BTTL outputs Bit clock for PCM or DATA- for ARINC-573 out
(See “ARINC-573 setup” on page 10.)
24 NRZ_L BTTL outputs Uncoded PCM output
25 PROG_DATA+ RS-485 Programming data line; not internally terminated
26 PROG_DATA- RS-485 Programming data line; not internally terminated
27 PROG_DATA_TRM+ RS-485 Programming data line; with internal 120Ω resistor
28 PROG_DATA+_COPY RS-485 Copy of Pin 25
29 PROG_DATA-_COPY RS-485 Copy of Pin 26
30 X_SYNC_IN+_COPY RS-422 inputs Copy of Pin 13
31 X_SYNC_IN-_COPY RS-422 inputs Copy of Pin 14
32 X_SYNC_OUTA+ Low-speed RS-422 outputs Synchronization out; internally terminated with 120Ω
33 X_SYNC_OUTA- Low-speed RS-422 outputs Synchronization out; internally terminated with 120Ω
35 X_SYNC_OUTB+ Low-speed RS-422 outputs Synchronization out; internally terminated with 120Ω
36 X_SYNC_OUTB- Low-speed RS-422 outputs Synchronization out; internally terminated with 120Ω
38 CHASSIS_ID(5) BTTL inputs Chassis identifier/address; internally pulled to 0; MSB
50 CHASSIS KAM-500 chassis
www.acracontrol.com
14 29 Aug. 2008 | DST/S/087

KAD/BCU/105/B
A C R A KAM-500 BCU/105
Fast Ethernet KAM-500 backplane controller and packet generator
C O N T R O L
DESCRIPTION
The BCU/105 is a full-duplex 100BaseTX Ethernet KAM-500
backplane controller, programmer and packet generator.
In acquisition mode some or all acquired data is transferred
from the backplane to the on-board CVT. On-board, it is
packetized into a user-defined structure. Once full, the packet
is transmitted via UDP.
Any number of user-defined IENA packet structures can be
handled simultaneously. Different packet identifiers, packet
sizes and destination IP addresses can be individually
programmed for each packet type. Destination IP addresses
FEATURES can be unicast, multicast or broadcast.
• Programming and verification of KAM-500 chassis
Upon reception of a programming packet, the module
• Synchronization to an external Precision Time Protocol v1 immediately exits acquisition mode and switches to
(PTP) source
program/verify mode. In program/verify mode it can read or
• Bi-directional, full-duplex, 100BaseTX Ethernet connection
write data blocks to or from any module within a KAM-500
• Fixed user-assigned Internet Protocol (IP) address chassis.
• User Datagram Protocol (UDP) support for packets up to
64kbyte (32ksamples) via IP fragmentation The KAM-500 backplane controller supports chassis
• Current Value Table (CVT) of up to 1Msample programming via Ethernet. Synchronization is achieved using
• IPv4 protocol supported the IEEE 1588 PTP.
• Supports Address Resolution Protocol (ARP) and PING The BCU/105 supports IPv4 networks with fixed IP address
allocation, including user-assignment of the module’s IP
APPLICATIONS address. The module is factory-programmed with a unique
Ethernet MAC address.
• Ethernet based data acquisition systems
+ PACKETIZER
18 → ←
TX -
19 DEPACKETIZER
MAC/PHY CVT 1M DEEP

+
1
RX PTP
ENGINE COMMAND
- + EXCHANGE
2 TIMER
PPS_OUT 9
PPC_OUT 10
IP_ASSIGN 7
MEM_TRIGGER 6
GND 51
BCU/105
Ethernet interface, PPS and PPC outputs, MEM Trigger and IP Assign inputs of the BCU/105
11 Feb. 2009 | DST/U/006 15

Selection Paths
Airborne Data Acquisition → KAM-500 → Modules → Backplane controllers
Part Number Description
KAD/BCU/105/B Fast Ethernet KAM-500 backplane controller and packet generator
By default, the standard mating connector, CON/KAD/002/CP, is included with each module in the shipment. Its part number will
be added to the Confirmation of Order unless an alternative option is specified (see the Cables data sheet).
Revision History
BCU/105/B First release Recommended for new programs
Related Products
Module Details
ETH/101 A 100BaseTX Ethernet interface for programming and data acquisition
Document Details
TEC/NOT/032 Using Ethernet for data acquisition
TEC/NOT/034 Ethernet data acquisition networking
www.acracontrol.com
16 11 Feb. 2009 | DST/U/006

Specifications

Slots – – 1 – Use in controller slot only (J2).
Mass
– 74 – g
CON/KAD/002/CP data sheet.
Power consumption
+5V 311 – 414 mA
±7V 0 – 0 mA
±12V 0 – 0 mA
Synchronization specification

Time accuracy – 20 – ns The value represents a standard deviation measured using a
Meinberg M600 IEEE 1588 Grandmaster, supplying PTP v1
messages to the BCU/105 via OnTime T208 switch, configured
in IEEE 1588 transparent mode.
Time to synchronize Measured from a power-up of the test chassis, using a Meinberg
1µs – 15 – s M600 IEEE 1588 Grandmaster, supplying PTP v1 messages to
the BCU/105 via OnTime T208 switch, configured in IEEE 1588
50ns – 45 – s
transparent mode.
BTTL inputs

Input voltage
logic ‘0’ – – 0.8 V
logic ‘1’ 2 – 5.5 V
Input resistance
11 Feb. 2009 | DST/U/006 17

BTTL outputs

Signaling rate
PPS_OUT – – 4 Mbps
Output voltage
logic ‘0’ – – 0.44 V Sinking 24mA.
logic ‘1’ 3.76 – – V Sourcing 24mA.
BVDD outputs

Range 4.8 5 5.1 V
Current output
compliance1 – – 12 mA
1. Currents in excess of the maximum value shown will result in output voltages below the minimum voltage required to be detected
as a logic 1 for a standard BTTL input.
Ethernet interface

Inputs/outputs – – 1 – IEEE 802.3 compatible; 100BaseTX only.
18 11 Feb. 2009 | DST/U/006

Setting up the BCU/105
All module setup can be defined in XML using XidML® XidML Legend
schemas (see www.xidml.org).
DAU: Data Acquisition Unit ( PC: Personal Computer)
The following treeview provides an overview of setup
configurations available for this module: Instrument: Any component or module used in a data
acquisition system
DataLink: Connection for transmitting or receiving (defines

both the data link and the physical layer)
Package: Used to describe how data is transmitted or stored
Parameter: Any register that can be read from an instrument
Algorithm: Defines processing to be performed on data
11 Feb. 2009 | DST/U/006 19

Setting up the module
The following table lists the setup configurations available for the KAD/BCU/105/B.
Setup data Choice Default/example Notes

Manufacturer
Name ACRA CONTROL ACRA CONTROL Name of manufacturer.
PartReference KAD/BCU/105/B KAD/BCU/105/B ACRA CONTROL part number.
SerialNumber Unique name for each module.
InterConnects
ETHERNET-DATA No character limit Not Specified Connection between the module channel and IEEE
802.3 data bus.
PPS-OUT No character limit Not Specified A one pulse per second output signal.
PPC-OUT No character limit Not Specified A one pulse per acquisition cycle output signal.
MEM-TRIGGER-IN No character limit Not Specified Trigger for memory recording, internally pulled to 0.
IP-ASSIGN-MODE-IN No character limit Not Specified Assign IP mode, internally pulled to 0.
Settings – – –
DAU-Controller-Ethernet-Settings-1.0 – – –
DAU_ID 63:0 0 Uniquely identifies the DAU.
Module-Ethernet-1.1
MACAddress – 00-00-00-00-00-00 The module is factory-programmed with a unique
Ethernet MAC address, therefore this is a read only
field.
IPAddress – 0.0.0.0 –
Port 65535:0 1023 –
TimeToLive 255:1 1 Specifies the maximum number hops a packet is
allowed to make before it should be dropped by the
network.
Addendum
TimeSource PTP-Grand-Master PTP-Grand-Master Specifies the time synchronisation source type.
Internal
Parameter definitions
The following table lists all parameters that are available for the KAD/BCU/105/B.
Name/description Base unit Data format Bits Register definition

DayOfYear
Day of year at the start of the acquisition Unitless BitVector 16 R[15:10] Reserved for future use.
cycle R[9:0] DayOfYear [9:0] BCD 1 to 366.
TimeHi
Hours and minutes of the 44 bit time Unitless BitVector 16 R[15:13] Reserved for future use.
register at the start of the acquisition R[12:7] Time[43:38] BCD Hours 0 to 23.
cycle R[6:0] Time[37:31] BCD Minutes 0 to 59.
TimeLo
Seconds and centiseconds of the 44 bit Second BCD 16 R(15) Reserved for future use.
time register at the start of the acquisition R[14:8] Time[30:16] Seconds 0 to 59.
cycle R[7:0] Time[30:16] Centiseconds 0 to 99.
TimeMicro
Microseconds of the 44 bit time register Second BCD 16 R[15:0] Time[15:0] Microseconds 0 to 9999.
at the start of the acquisition cycle
20 11 Feb. 2009 | DST/U/006

Report
Reports status of module. Note: This Unitless BitVector 16 R[15] Event occurred since last read.
register cannot be read over KAM-500 R[14] Module in Programming mode.
backplane R[13] Module in Configuration mode.
R[12] Module in BIST mode.
R[11] MEM_TRIGGER pin status.
R[10] Reserved for future use.
R[9] Configuration reading failure.
R[8] Invalid configuration.
R[7] Unexpected Ethernet frame received.
R[6] Ethernet receive buffer overflow.
R[5] BIST failed.
R[4] Watchdog timeout.
R[3] Memory contention.
R[2] Memory overflow.
R[1] Missed more than 5 consecutive PTP packets.
R[0] On the last update PTP error was greater then
500ns.
Status
Reports status of memory trigger pin Unitless BitVector 16 R[15] MEM_TRIGGER pin status.
R[14:0] Reserved for future use.
FixedData
User definable data word, 0 to N fixed Unitless BitVector 16 R[15:0] 0000:FFFF (hex).
words can be defined
Setting up data links

A data link is a connection for transmitting and receiving data. It defines both the data link and physical layers of the link. The
following are data links supported by the KAD/BCU/105/B.
Non-programmable data links
Name Description
PPS-OUT A BTTL datalink definition.
PPC-OUT
MEM-TRIGGER-IN
IP-ASSIGN-MODE-IN
ETHERNET-DATA Differential Ethernet data line.
Setting up packages
A package is a logical description of how data is transmitted or stored.
EthernetPackage
IENA Package containing acquisition data to be transmitted.

ReferencedToAbsoluteTime – – –
PackageRate – 1 –
DataLinkReference No character Not Specified –
limit
Properties – – –
Key FFFF:0000 1F Unique identifier for each packet type.
NumberOfWords 65527:8 Not Specified –
ContentIdentifier – – –
DefaultNumberOfDataBits 16 16 –
NumberOfBitsInContentIdentifier 16 16 –
Status FFFF:0000 7F Status value (Synchronous/Asynchronous).
EndWord FFFF:0000 FFFF –
TimeToLive 255:1 255 –
11 Feb. 2009 | DST/U/006 21

Destination – – –
IPAddress 0.0.0.0 –
MACAddress 00-00-00-00-00-00 –
Port 65535:0 1023 –
Content – – –
Parameter – – –
Location – – –
Offset_Words 65526:7 Not Specified –
Occurrences 65526:1 1 –
Setting up algorithms
An algorithm describes how data should be processed. The following are algorithms supported by the KAD/BCU/105/B.
FIXED-ALGORITHM
Algorthim used to define a fixed data word.

Output
ParameterTypeReference No character Unitless See FixedData parameter definition.
limit
MapFixed
FixedValue 0000000000 1010101010101010 Defines the content of the fixed word in binary.
000000 to
1111111111
111111
It is recommended that names are less than 20 characters, have no white space or contain any of the following five characters
"/><\.
22 11 Feb. 2009 | DST/U/006

Getting the most from the BCU/105 Networked KAM-500 system and
The Ethernet cabling standard (EIA/TIA-568-B) recommends
acquisition cycles
the use of Category 5 cable. In a networked data acquisition system, all chassis with
BCU/105 controllers are able to acquire data synchronously
User-assignment of IP address by synchronizing their acquisition cycles using IEEE 1588
PTP (Precision Time Protocol) V1. A requirement is that the
Unlike the ETH/101, the BCU/105 does not have a 32-bit length of acquisition cycle is an integer divisor of two seconds
top-block pin-out, which enables the module's IP address to and the maximal length of acquisition cycle is two seconds.
be hard-wired. Instead, the KSM-500 software is used to The following table lists all possible acquisition cycle
configure the module with a user-assigned IP address. The
frequencies.
mechanism works as follows:
A top-block pin (pin#7 = IP_ASSIGN) is connected to BVDD Possible acquisition cycle frequencies (Hz)
to put the module into IP Assign mode. When in this mode,
0.5 2.5 12.5 62.5 312.5 1562.5
the module will assume a default hard-wired IP address. The
IP address 239.0.0.0 is used, as it is an administratively 1 5 25 125 625 3125
scoped IP multicast address (defined by IETF RFC2365), 2 10 50 250 1250 6250
within the local network control block of addresses. It can be 4 20 100 500 2500
used to transmit packets to a network element using a 8 40 200 1000 5000
multicast Ethernet MAC address (01-00-5E-00-00-00), and is 16 80 400 2000 10000
limited to the local network, such that it will not be forwarded
32 160 800 4000
by a router.
64 320 1600 8000
An IP address configuration packet is sent to the module for
128 640 3200
the purpose of configuring the module with a user-assigned
IP address. The user-assigned IP address is stored in 256 1280 6400
EEPROM on the module for subsequent reference. 512 2560
The BCU/105 module is then released from IP address

To get the most from networked KAM-500 data acquisition
configuration mode by removing BVDD from top-block pin#7.
systems, it is essential that IEEE 1558 PTP V1 Ethernet
Only one module on the network should be set to switches are used. For a list of suitable switches, contact
IP Assign mode at any time. This prevents other ACRA CONTROL.
BCU/105 modules from simultaneously processing
the configuration packets and thus mistakenly
acquiring the same user-assigned IP address.
Internet Group Management Protocol

The BCU/105 uses Internet Group Management Protocol
(IGMP) to inform switches that it wishes to receive PTP
messages. If a switch between the BCU/105 and PTP
grandmaster uses IGMP to control multicast traffic, the
BCU/105 will not start synchronizing to the PTP grandmaster
until after it receives, and responds to, an IGMP query from
the switch.
Packet fragmentation
Ethernet packet sizes range between 64 bytes and 1518
bytes. Packets larger than 1518 bytes (known as giants) can
be transmitted directly over Ethernet by high level protocols
such as Internet Protocol (IP). When being transmitted over
Ethernet, giant IP packets are fragmented (split into smaller
pieces). Fragmented packets must then be reassembled by
the receiving device to recreate the original IP packet.
Packet fragmentation is undesirable for the following
reasons:
• Fragments may arrive out of order and complicate
reassembly of the data.
• Fragments may be lost, rendering all other fragments of
the frame useless.
• The process of fragmenting and reassembling the data is
time-consuming.
Switches and routers which support IEEE 802.1Q

VLAN tagging support Ethernet packets of up to 1522
bytes, including the 4-byte IEEE 802.1Q VLAN tag.
11 Feb. 2009 | DST/U/006 23

Connector pinout of the KAD/BCU/105
1 RX+ Ethernet interface Ethernet interface
2 RX- Ethernet interface Ethernet interface
4 BVDD BVDD outputs 5V; internally buffered with 220Ω resistor
6 MEM_TRIGGER BTTL inputs Trigger for memory recording; internally pulled to 0
7 IP_ASSIGN BTTL inputs IP Assign mode; internally pulled to 0
8 DNC Do not connect
9 PPS_OUT BTTL outputs One pulse per second
10 PPC_OUT BTTL outputs One pulse per acquisition cycle; generated 250ns after the
beginning of the acquisition cycle
16 NC Not connected
17 NC Not connected
18 TX+ Ethernet interface Ethernet interface
19 TX- Ethernet interface Ethernet interface
33 NC Not connected
34 NC Not connected
47 NC Not connected
48 NC Not connected
The module has a 52-way double-density connector. For a micro-miniature connector version contact ACRA CONTROL.
www.acracontrol.com
24 11 Feb. 2009 | DST/U/006

KAM/PSU/011
A C R A KAM-500 PSU/011
C O N T R O L +5V, ±7V and ±12V power supply unit for KAM-500 chassis with 9-way connector
DESCRIPTION
The PSU/011 converts the nominal 28V aircraft power into
the voltages needed by the KAM-500 backplane.
The DC/DC converters used are the largest components of
any KAM-500 module, so the unit is split in two (one half at
each end). This enables the components to be bolted to the
housing and their weight to be evenly distributed in the
KAM-500 chassis.
The +5V supply is primarily for digital circuitry, the ±12V
supply is primarily for analog circuitry, and the ±7V is
exclusively for bridge excitation.
FEATURES
Unlike other KAM-500 modules the PSU/011 can only be
• Supplies 5V, ±7V and ±12V for backplane
removed by first removing the sides. The PSU/011 is only
• Fully isolated
supplied as part of the housing. The green LED indicates
• No derating with temperature (-40°C to 85°C) power on the +5V power line.
• Capacitor back-up: 24ms dropping from 28V @ 40W
typical
• Reverse polarity protection
• Indefinite short-circuit protection
• EMI filtering
• Supplies up to 4A on +5V power line
APPLICATIONS
• Power supplies for data acquisition systems
+ 1
+12V
DC →
POWER 5mF DC
-12V
2
-
I/O FILTER
+5V 6
+7V
LED DC →
Backplane
DC -7V
GND 5
+
3
12V DC → +5V
DC
- 4
GND 7
KAM-500 INTERNAL GROUND

PSU/011
KAM-500 PSU/011 power supply
6 Nov. 2008 | DST/S/026 25

Selection Paths
Airborne Data Acquisition → KAM-500 → Power Supply
KAM/PSU/011 ACC/ASY/007/04 +5V, ±7V and ±12V power supply unit for KAM-500 chassis with 9-way
connector
Revision History
PSU/011 First release Recommended for new programs
Related Products
Module Details
PSU/012 +5V, ±7V and ±12V power supply unit for KAM-500 chassis with 6-way connector
Document Details
TEC/NOT/016 Power dissipation - a worked example
TEC/NOT/049 Power estimation
www.acracontrol.com
26 6 Nov. 2008 | DST/S/026

Specifications

Slots – – 2 – Occupies PSU slots at opposites ends of chassis.
Mass
– 538 – g
Electrical specifications

Input range 18 28 40 V 3A max. therefore 54W at 18V supply.
Reverse polarity protection -40 – – V
Current available
+5V – – 4000 mA
±7V – – 2000 mA
±12V – – 1250 mA
Short circuit protection
+5V – – 4000 mA Indefinite to GND.
±7V – – 2000 mA Indefinite to GND.
Glitch immunity – 24 – ms 5mF capacitor with a 10% tolerance. (See “Getting the most
from the PSU/011” on page 28.)
Efficiency – 75 – % At full load.
Physical
connector – – – –
placement – – – – Not removable.
6 Nov. 2008 | DST/S/026 27

Getting the most from the PSU/011
When a KAM-500 chassis with a PSU/011 is operated from a MIL-STD-704E compliant supply, the chassis will be operational
with a supply voltage in the range of 18 to 40VDC. This voltage range covers the normal (22 to 29VDC) and emergency (18 to
29VDC) modes of operation as defined in MIL-STD-704E. The KAM-500 will be in a non-operational but safe mode for supply
voltages less than 18VDC. Operation with an input voltage greater than 40VDC is not permitted, except for very short transients
as described in MIL-STD-704E.
The PSU/011 incorporates a 5mF capacitor backup, which provides a glitch immunity of typically 24ms, dropping from 28V at
40W. The power glitch ride-through time depends on the load as shown in Figure 2.
Figure 2: Glitch immunity versus load
Connector pinout of the KAM/PSU/011
Pin Name Description Comment

1 POWER+ Nominal KAM-500 28V supply Isolated internally; aircraft power
2 POWER- Return for nominal 28V Isolated internally; aircraft power
3 +12V KAM-500 internal +12V out Current depends on internal loading
4 -12V KAM-500 internal -12V out Current depends on internal loading
www.acracontrol.com
28 6 Nov. 2008 | DST/S/026

KAM/PSU/012
A C R A KAM-500 PSU/012
C O N T R O L +5V, ±7V and ±12V power supply unit for KAM-500 chassis with 6-way connector
DESCRIPTION
The PSU/012 converts the nominal 28V aircraft power into
the voltages needed by the KAM-500 backplane.
The DC/DC converters used are the largest components of
any KAM-500 module, so the unit is split in two (one half at
each end). This allows the components to be bolted to the
housing and their weight to be evenly distributed in the
KAM-500 chassis.
The +5V supply is primarily for digital circuitry, the ±12V
supply is primarily for analog circuitry, and the ±7V is
exclusively for bridge excitation.
FEATURES
Unlike other KAM-500 modules the PSU/012 can only be
• Supplies 5V, ±7V and ±12V for backplane removed by first removing the sides. The PSU/012 is only
• Fully isolated
supplied as part of the housing. The green LED indicates
• No derating with temperature (-40°C to 85°C)
power on the +5V power line.
• Capacitor back-up: 24ms dropping from 28V@40W typical
• Reverse polarity protection
• Indefinite short-circuit protection
• EMI filtering
• Supplies up to 4A on +5V power line
APPLICATIONS
• Power supplies for data acquisition systems
+ 1 +12V
DC →
POWER 5mF DC
2
-12V
-
I/O FILTER
+12V 5
+7V
BACKPLANE
DC →
DC -7V
LED
+5V 6
+5V
DC →
DC
GND 4
KAM-500 INTERNAL GROUND PSU/012
KAM-500 PSU/012 power supply
6 Nov. 2008 | DST/R/098 29

Selection Paths
Airborne Data Acquisition → KAM-500 → Power Supply
KAM/PSU/012 CON/PSU/007/FL/100 +5V, ±7V and ±12V power supply unit for KAM-500 chassis with 6-way
connector
Revision History
PSU/012 First release Recommended for new programs
Related Products
Module Details
PSU/011 +5V, ±7V and ±12V power supply unit for KAM-500 chassis with 9-way connector
Document Details
TEC/NOT/016 Power dissipation – a worked example
TEC/NOT/049 Power estimation
www.acracontrol.com
30 6 Nov. 2008 | DST/R/098

Specifications

Slots – – 2 – Occupies PSU slots at opposites ends of chassis.
Mass
– 538 – g
Electrical specifications

Input range 18 28 40 V 3A max. therefore 54W at 18V supply.
Reverse polarity protection -40 – – V
Current available
+5V – – 4000 mA
±7V – – 2000 mA
±12V – – 1250 mA
Short circuit protection
+5V – – 4000 mA Indefinite to GND.
Glitch immunity – 24 – ms 5mF capacitor with a 10% tolerance. (See “Getting the most
from the PSU/012” on page 32.)
Efficiency – 75 – % At full load.
Physical
connector – – – –
placement – – – – Not removable.
6 Nov. 2008 | DST/R/098 31

Getting the most from the PSU/012
When a KAM-500 chassis with a PSU/012 is operated from a MIL-STD-704E compliant supply, the chassis will be operational
with a supply voltage in the range of 18 to 40VDC. This voltage range covers the normal (22 to 29VDC) and emergency (18 to
29VDC) modes of operation as defined in MIL-STD-704E. The KAM-500 will be in a non-operational but safe mode for supply
voltages less than 18VDC. Operation with an input voltage greater than 40VDC is not permitted, except for very short transients
as described in MIL-STD-704E.
The PSU/012 incorporates a 5mF capacitor backup, which provides a glitch immunity of typically 24ms, dropping from 28V at
40W. The power glitch ride-through time depends on the load as shown in Figure 2.
Figure 2: Glitch immunity versus load
Pin Name Description Comment

www.acracontrol.com
32 6 Nov. 2008 | DST/R/098

KAM/CHS/03F
A C R A KAM-500 CHS/03F
C O N T R O L KAM-500 chassis with 3 user-slots, built with base-mounted power supply and housing
DESCRIPTION
The CHS/03F is a compact three user-slot KAM-500 chassis,
which along with the housing and backplane, includes a
PSU/008/B power supply unit.
The backplane has three slots for user-modules, which are
polarized to prevent the insertion of the backplane controller
module. The backplane has power supply lines and the
standard 16-bit address/data bus with read/write control lines.
The only ICs on the backplane are demultiplexers for
user-module select.
This chassis has been specially designed for space-limited
FEATURES applications. As such, those modules which require excitation
• Power supply unit and three user-slots from ±7V are not suitable as the PSU/008/B does not supply
• 18 to 40VDC isolated power supply these voltage levels.
• Rugged aluminum housing
• 8MHz x 16-bit digital backplane
• Special mounting orientation
• Operates as MASTER or SLAVE in distributed system
APPLICATIONS
• Flight test instrumentation systems for limited spaces
Aluminum housing Power supply unit
Mounting lugs
User-slot (x 3)
Power supply
connectors
Lids (orange) Backplane Backplane

controller slot
CHS/03F with PSU and three user-slots
15 Apr. 2008 | DST/P/062 33

Selection Paths
Airborne Data Acquisition → KAM-500 → Chassis
KAM/CHS/03F ACC/ASY/007/04 KAM-500 chassis with 3 user-slots and 9-way micro-miniature mating
connector
Revision History
CHS/03F First release Recommended for new programs
Related Products
Product Details
PSU/008/B Regulates supplies, 28V nominal, uses 9-way micro-miniature connector
ACC/ASY/007/04 9-way micro-miniature mating connector with flying leads and banana plugs
Document Details
www.acracontrol.com
34 15 Apr. 2008 | DST/P/062

Specifications
Mechanical specifications

User slots – – 3 –
Dimensions Design metric is millimeters.
height – 84.2 – mm
height – 3.31 – in.
length – 121.5 – mm
length – 4.78 – in.
width – 64 – mm
width – 2.51 – in.
Mass Design metric is kilograms.
no modules or base plate – 0.52 – kg
no modules or base plate – 1.14 – lb
no modules, with base plate – 0.60 – kg
no modules, with base plate – 1.33 – lb
fully populated – 0.89 – kg Typical module weight of 74g.
fully populated – 1.97 – lb Typical module weight of 2.61oz.
Finish Electroless nickel plated.
top parts – – – – Painted REINORANGE RAL2004.
base, side and end plates – – – – Painted black GRIGIO SCURO OPACO C604.
Figure 2: CHS/03F mechanical drawing
15 Apr. 2008 | DST/P/062 35

Getting the most from the CHS/03F
Slot J2 is always reserved for the backplane controller module. A controller is required in slot J2 for control and programming of
user-modules. Due to mechanical constraints, only the BCU family of controllers can be used in the CHS/03F.
For mounting, ACRA CONTROL recommends the use of M3 x 10mm or 1/8th in. tooled steel or stainless steel screws to attach
the chassis mounting plate to the mounting frame. Alternatively, if the attached mounting plate is not used, the chassis can be
attached to the mounting frame or mounting plate using M3 screws pan/flat head with a maximum of 5mm of threaded insert.
Connector pinout of the KAM/PSU/008/B

4 AGND KAM-500 internal ground
Note that the PSU/008/B has two connectors which are wired in parallel.
www.acracontrol.com
36 15 Apr. 2008 | DST/P/062

KAM/CHS/03U/D, KAM/CHS/03U/D/MM
A C R A KAM-500 CHS/03U
C O N T R O L KAM-500 chassis with 3 user-slots
DESCRIPTION
The CHS/03U is a compact three user-slot KAM-500 chassis,
power supply module which regulates power supplies to the
backplane (isolated 28V nominal in).
The backplane has nine connectors for user-modules, which
are polarized to prevent the insertion of the backplane
controller module. The backplane distributes power and
connects address, data and control lines to the
user-modules.
FEATURES user-module select signal. Any user-module can be placed in
• Power supply unit and three user-slots any user-slot in any combination.
• 18 to 40VDC isolated power supply
2.0A is available for bridge excitation.
• LED power-on indicator
APPLICATIONS
• Flight test instrumentation systems for limited spaces
Power supply unit Power supply unit
Lids (orange)
Aluminum housing
Mounting lugs
Backplane User-slot Backplane

controller slot (x 3)
CHS/03U with PSU and three user-slots
30 May 2008 | DST/S/024 37

Selection Paths
KAM/CHS/03U/D CON/PSU/007/FL/100 KAM-500 chassis with 3 user-slots and PSU/012 with 6-way bayonet
connector and LED
KAM/CHS/03U/D/MM ACC/ASY/007/04 KAM-500 chassis with 3 user-slots and PSU/011 with 9-way
micro-miniature connector
Revision History
CHS/03U/D Includes PSU/012, 6-way bayonet connector, and Recommended for new programs
supplies up to 4A on +5V power line
CHS/03U/D/MM Includes PSU/011, 9-way micro-miniature connector, and Recommended for new programs
CHS/03U/C Includes PSU/010 with diode for power-up Not recommended for new programs
CHS/03U/C/MM Includes PSU/009 with diode for power-up Not recommended for new programs
CHS/03U/B Includes PSU/007 Not recommended for new programs
CHS/03U First release Not recommended for new programs
Related Products
Product Details
CHS/04L KAM-500 chassis with 4 user-slots, ‘narrow’ chassis form factor
CHS/06U KAM-500 chassis with 6 user-slots
CHS/12R KAM-500 chassis with 12 user-slots, ‘circular’ form factor
ACM/LID/001 For any unused user-slots a spare lid piece must be ordered separately
ACC/HSK/001/03U Optional heat sink for the KAM-500 system
Document Details
www.acracontrol.com
38 30 May 2008 | DST/S/024

Specifications
height – 98.5 – mm Includes module retention screws and ground bolt.
height – 3.88 – in. Includes module retention screws and ground bolt.
length – 140 – mm Includes mounting lugs.
length – 5.51 – in. Includes mounting lugs.
width – 80 – mm Excludes heat sinks.
width – 3.15 – in. Excludes heat sinks.
no modules 1.00 1.01 1.02 kg
no modules 2.20 2.23 2.25 lb
fully populated 1.30 1.31 1.32 kg Typical module weight of 74g.
fully populated 2.87 2.89 2.91 lb Typical module weight of 2.61oz.
operating temperature -40 – +85 °C Chassis base/side plate temperature.
storage temperature -55 – +125 °C
Details and dimensions of the chassis shown in the technical drawings refer to both standard and MM revisions; the PSU
connector is the only difference.
Ground Mounting Bolt:

Drill & Top to ault No. 10 24UNC
Torque (max); 4.5Nm (40.0lb fin)
Figure 2: CHS/03U/D mechanical drawing
30 May 2008 | DST/S/024 39

Getting the most from the CHS/03U
Where space permits, ACRA CONTROL recommends that one or two heat sinks (ACC/HSK/001/03U) be used. Heat sinks
must be ordered separately. Slot J2 is always reserved for the backplane controller module. A controller is required in slot J2 for
control and programming of user-modules.
Connector pinout of the KAM/PSU/012 supplied with the KAM/CHS/03U/D

5 +12V KAM-500 internal +12V Current depends on internal loading
Connector pinout of the KAM/PSU/011 supplied with the KAM/CHS/03U/D/MM

www.acracontrol.com
40 30 May 2008 | DST/S/024

KAM/CHS/04L/B
A C R A KAM-500 CHS/04L
C O N T R O L KAM-500 narrow form chassis with 4 user-slots
DESCRIPTION
The CHS/04L is a compact four user-slot KAM-500 chassis,
PSU/006 power supply unit.
The backplane has four slots for user-modules, which are
polarized to prevent the insertion of the backplane controller
module. The backplane has power supply lines and the
standard 16-bit address/data bus with read/write control lines.
user-module select signal.
Note that the CHS/04L does not contain any ±7V lines for
FEATURES excitation.
• Power supply unit and four user-slots
APPLICATIONS
• Flight test instrumentation systems
Ground Bayonet power

mounting bolt connector User-slots x4 Aluminum housing
Controller slot
CHS/04L with PSU and four user-slots
26 May 2008 | DST/N/043 41

Selection Paths
KAM/CHS/04L/B CON/PSU/007/FL/100 KAM-500 chassis with 4 user-slots, ‘narrow’ chassis form factor
Revision History
CHS/04L/B Uses chassis size identification circuit Recommended for new programs
CHS/04L/B/ET First release Recommended for new programs
Related Products
Product Details
CHS/12R KAM-500 chassis with 12 user-slots, ‘circular’ chassis form factor
Document Details
TEC/NOT/016 Power dissipation
www.acracontrol.com
42 26 May 2008 | DST/N/043

Specifications

no modules 1.10 1.11 1.12 kg Including power supply.
no modules 2.43 2.45 2.47 lb Including power supply.
Figure 2: CHS/04L/B mechanical drawing
26 May 2008 | DST/N/043 43

Getting the most from the CHS/04L
Modules requiring bridge excitation from ±7V lines cannot be used in this chassis. Some modules have ordering options to take
their excitation power from ±12V lines. Check individual module data sheets for further details.
The CHS/04L is recognized as a 4L chassis by KSM-500 tools (kSetup and xReport) when used with the BCU/001/B (and later
revisions). When the CHS/04L is used with controllers or revisions earlier than the BCU/001/B, and revisions of software tools
earlier than kConfig 1.2, kSetup 1.0, and xReport 1.2, it is displayed as CHS/13U.

3 CHASSIS KAM-500 internal +12V out
4 GND KAM-500 chassis
5 +12V KAM-500 internal ground Current depends on internal loading
www.acracontrol.com
44 26 May 2008 | DST/N/043

KAM/CHS/06U/D, CHS/06U/D/MM
DESCRIPTION
The CHS/06U is a six user-slot KAM-500 chassis, which
along with the housing and backplane, includes a power
supply module which regulates power supplies for the
The backplane has six connectors for user-modules, which
connects address, data and control lines to the user modules.
user-module select signal. Any user-module can be placed in
FEATURES any user-slot in any combination.
• Power supply unit and six user-slots
APPLICATIONS
Power supply unit
Lids (orange)
Aluminum housing
Mounting lugs

CHS/06U with PSU and six user-slots
12 Nov. 2008 | DST/S/013 45

Selection Paths
connector and LED
micro-miniature connector and LED
Revision History
Related Products
Product Details
Document Details
www.acracontrol.com
46 12 Nov. 2008 | DST/S/013

Specifications
0.118"
(3.00mm)
0.669"
(17.00mm)
HEAT SINK MOUNTING HOLES:
4 off Holes Drilled Ø2.50mm x 5.00mm
& Tapped M3 x 3.50mm Deep to suit
M3 Cap Screws.
3.878" 1.732"
3.347"
(98.5mm) (44.00mm)
(85.00mm)
0.669"
(17.00mm) 0.472"
(12.00mm)
0.158" 1.614" 3.937" 1.614"

(4.00mm) (41.00mm) (100.00mm) (41.00mm) 3.150"
7.165" (80.00mm)
(182.00mm)
Hole to suit High
Temperature GaAIAs Emitter
1.772"
0.551" 0.295"
(45.00mm)
(14.00mm) No. 2-56 UNC (7.50mm)
0.827" (Hexagonal Head)
(21.00mm)
0.394"
Bayonet (10.00mm)
Power
SERIAL No.
MODEL
ACRA CONTROL
Connector
0.906"
J1
(23.00mm)
0.906" M3 Low Profile

(23.00mm) Captive Panhead Screw
(52-34-33)
Torque (max): 0.4Nm (3.5Lbfin)
0.158"
(4.00mm)
Ground Mounting Bolt: No. 2-56 UNC

0.630" (Hexagonal Head)
Drill & Tap to suit No.10 24UNC
(16.00mm)
Torque (max): 4.5Nm (40.0Lbfin)
SCALE: 1:1 NOTE ON FINISH:
1st ANGLE PROJECTION ACRA CONTROL

TOP PARTS: Electroless nickel
MATERIAL(S): Aluminium Alloy
plated with top surface
6082-T6 (Din No: AlMgSi1) TITLE: Plan, elevation and end-view of
painted: REINORANGE RAL2004.
KAM/CHS/06U/D Chassis
BASE, SIDE & END PLATES:
TOLERANCES: Electroless nickel plated DOC Nº: KAM/CHS/06U/D Date:1 Nov'05
3 Decimal places= ±0.005" with surface painted Black:
2 Decimal places= ±0.01" GRIGIO SCURO OPACO C604 Sheet: 1 of 1
c Copyright 2005 ACRA CONTROL
12 Nov. 2008 | DST/S/013 47

Where space permits, ACRA CONTROL recommends that one or two heat sinks (ACC/HSK/001/06U) be used. Heat sinks
must be ordered separately.
user-modules.


8 NC Not connected
9 NC Not connected
www.acracontrol.com
48 12 Nov. 2008 | DST/S/013

DESCRIPTION
The CHS/09U is a nine user-slot KAM-500 chassis, which
The backplane has nine connectors for user-modules, which
user-modules.
• Power supply unit and nine user-slots any user-slot in any combination.
APPLICATIONS
Power supply unit
Lids (orange)
Aluminum housing
Mounting lugs

CHS/09U with PSU and nine user-slots
30 May 2008 | DST/S/014 49

Selection Paths
connector and LED
micro-miniature connector and LED
Revision History
Related Products
Product Details
Document Details
www.acracontrol.com
50 30 May 2008 | DST/S/014

Specifications
no modules 1.41 1.42 1.43 kg
no modules 3.11 3.13 3.15 lb

30 May 2008 | DST/S/014 51

Where space permits, ACRA CONTROL recommends that one or two heat sinks (ACC/HSK/001/09U) also be used. Heat sinks
user-modules.


8 NC Not connected
9 NC Not connected
www.acracontrol.com
52 30 May 2008 | DST/S/014

KAM/CHS/12R/D, KAM/CHS/12R/D/MM
A C R A KAM-500 CHS/12R
C O N T R O L KAM-500 circular form chassis with 12 user-slots
DESCRIPTION
The CHS/12R is a twelve user-slot KAM-500 chassis, which
The backplane has twelve connectors for user-modules,
which are polarized to prevent the insertion of the backplane
user-modules.
• Power supply unit and twelve user-slots any user-slot in any combination.
• Circular form factor
APPLICATIONS
• Helicopter data acquisition systems
Micro miniature (CHS/12R/MM) or

Bayonet (CHS/12R) power connector
J1 Power supply
J2
J3
J14 J5
User-slots X 12
Label
CHS/12R with PSU and twelve user-slots
28 Jan. 2008 | DST/S/029 53

Selection Paths
KAM/CHS/12R/D CON/PSU/007/FL/100 KAM-500 chassis with 12 user-slots and 6-way bayonet mating
connector. The mating connector must be ordered separately.
KAM/CHS/12R/D/MM ACC/ASY/007/04 KAM-500 chassis with 12 user-slots and 9-way micro-miniature

mating connector. The mating connector must be ordered separately.
Revision History
CHS/12R/D Includes PSU/012, 6-way bayonet connector, and Recommended for new programs
CHS/12R/D/MM Includes PSU/011, 9-way micro-miniature connector, and Recommended for new programs
CHS/12R/C Includes PSU/010 with diode for power-up, 6-way Not recommended for new programs
bayonet connector and LED
CHS/12R/C/MM Includes PSU/009 with 9-way micro-miniature connector Not recommended for new programs
and diode for power-up
CHS/12R/B Includes PSU/007 with 6-way bayonet connector and Not recommended for new programs
LED
CHS/12R First release Not recommended for new programs
Related Products
Product Details
ACC/WGT/006 Quantity of 6 anodized tooling steel 10g weight with 2mm Allen key head used for balancing
CHS/12R, this must be ordered separately
CHS/09U KAM-500 chassis with 9 user-slots, ‘circular’ chassis form factor
Document Details
www.acracontrol.com
54 28 Jan. 2008 | DST/S/029

Specifications

diameter – 250 – mm
diameter – 9.84 – in.
Figure 2: CHS/12R/D mechanical drawing
28 Jan. 2008 | DST/S/029 55

Getting the most from the CHS/12R
ACRA CONTROL recommends that balancing weights
(ACC/WGT/006) be used. There are two dowel holes
(6.00mm drilled H7 x 6mm deep), which are used as a guide
for mounting the chassis. The dowel holes are labeled “Ref
point A/B” in Figure 3.
Figure 3: View of mounting holes for base plate
Figure 4: View of chassis mounting options
Chassis mounting
Method 1: A 10-32 UNF stainless steel bolt can be used to
secure the chassis base plate from the mounting frame
(recommended tightening torque of 5Nm (3.69 foot
pound-force)).
Method 2: A 6mm stainless steel bolt can be used to secure
the chassis base plate to the mounting frame after first
removing the orange chassis lid and inserting the bolts
through the pockets (recommended tightening torque of
10Nm (7.38 foot pound-force)).
ACRA CONTROL recommends the use of H7 dowel
holes/pins for precision of assembly for both methods.
56 28 Jan. 2008 | DST/S/029

Connector pinout of the KAM/PSU/012 supplied with the KAM/CHS/12R/D
Connector pinout of the KAM/PSU/011 supplied with the KAM/CHS/12R/D/MM

8 NC Not connected
9 NC Not connected
www.acracontrol.com
58 28 Jan. 2008 | DST/S/029

DESCRIPTION
The CHS/13U is a thirteen user-slot KAM-500 chassis, which
The backplane has thirteen connectors for user-modules,
which are polarized to prevent the insertion of the backplane
user-modules.
• Power supply unit and thirteen user-slots any user-slot in any combination.
APPLICATIONS
Power supply unit
Lids (orange)
Aluminum housing
Mounting lugs

CHS/13U with PSU and thirteen user-slots
30 May 2008 | DST/S/028 59

Selection Paths
connector
micro-miniature connector
Revision History
Related Products
Product Details
CHS/12R KAM-500 chassis with 12 user-slots,’circular’ chassis form factor
Document Details
www.acracontrol.com
60 30 May 2008 | DST/S/028

Specifications

width – 3.15 – in. Excludes heat sinks

30 May 2008 | DST/S/028 61

Where space permits, ACRA CONTROL recommends that one or two heat sinks (ACC/HSK/001/13U) also be used. Heat sinks
user-modules.


8 NC Not connected
9 NC Not connected
www.acracontrol.com
62 30 May 2008 | DST/S/028

SAM/DEC/007/C
A C R A KAM-500 SAM/DEC/007
C O N T R O L KAM-500 programming interface with IRIG-106 PCM decoder
DESCRIPTION
The SAM/DEC/007 decommutates IRIG-106 Ch.4 PCM
streams and provides a high-speed programming link for
KAM-500 systems. The unit occupies a single PCMCIA slot
(Type II or III) in the ground station/programming PC.
The PCM decommutator accepts either differential ended
(D/E) RS-422 inputs or single ended (S/E) TTL inputs. With
BIØ-L codes only a single input is used. For NRZ-L an
additional data clock (DCLK) line is required. Any syncword
up to 34 bits can be used to identify the start of a minor frame
(including mask and alternating patterns). The word length (4
FEATURES to 16 bits), orientation (MSB first/last), parity (odd/even/none)
and store/don’t store options are programmable on a
• IRIG-106 Ch. 4 compliant PCM decommutator
word-by-word basis up to 16,349 words. Each word is stored
• PCMCIA 2.0 Type II compatible
in a unique location in a frame buffer. Multiple frame buffers
• High-speed programming link (1Mbps) to KAM-500
(up to 2K) are used depending on the size of the minor frame.
systems
• Choice of two PCM codes BIØ-L or NRZ-L+DCLK The programming link can be used to program multiple
• Choice of RS-422 or TTL inputs KAM-500s. A bi-directional, D/E (RS-422) pair of data lines
• Accepts PCM streams up to 10Mbps (5Mbps BIØ-L) (PROG_DATA±) are used to transmit or receive data at
• 4 to 16,349 words per minor frame 1Mbps.
• Word-by-word programmable features
APPLICATIONS
• PCM decoding
+ 6
+
PROG_DATA -
PC M C IA IN TER FAC E AN D L O G IC
- 8
+ 9
+ Programming Interface
PROG_DCLK -
- 11
PROGRAMMING
PCM + 3
+
DATA
-
- 4
LOCK
SERIAL →
PARALLEL VERIFY
+ 12 LOST
Bit Frame
+ Sync
DCLK Finder Buffer
- Word Tracker
- 13 Finder
GND 15
SAM/DEC/007
Programming link and D/E PCM inputs
29 Oct. 2008 | DST/R/083 63

Selection Paths
Airborne Data Acquisition → KAM-500 → PCMCIA Decoders
SAM/DEC/007/C CON/DEC/001/B KAM-500 PCMCIA card programming interface with IRIG-106 PCM
decoder and connector cable
SAM/DEC/007/C/UTP SAM/DEC/007 without 120Ω termination resistors on RS-422 inputs/outputs
Revision History
SAM/DEC/007/C Provides mechanical harness for support of the I/O cable Recommended for new programs
SAM/DEC/007/B Dual voltage card, i.e. it is 3.3V or 5V compatible Not recommended for new programs
Related Products
Module Details
CON/DEC/001/B 15-way cable which connects the PCMCIA card to a standard 15-way commercial D-type plug
connector cable
Document Details
QD/SW/BK/0011 SAM/DEC programming interface
www.acracontrol.com
64 29 Oct. 2008 | DST/R/083

Specifications

Slots – – 1 – PCMCIA 2.0 Type II compatible. Can be placed in any PCMCIA
slot, in any combination.
Mass
– 30 – g
Height above chassis
bare connector – 9 – mm
bare connector – 0.35 – in. Design metric is millimeters.
Access rate – – 625 ksps Maximum combined access rate for read and write.
Power consumption
+3.3V – 160 – mA
total power – 0.53 – W
operating temperature 0 – 60 °C Chassis base/side plate temperature.
BTTL inputs

Signaling rate
DCLK – – 10 MHz
Input voltage
logic ‘0’ – – 0.8 V
logic ‘1’ 2 – – V
overvoltage protection 0 – 3.6 V Voltages outside of this range can damage input.
Input resistance
each input to GND (on) – 27 – MΩ Module powered on.
29 Oct. 2008 | DST/R/083 65

RS-422 inputs

Signaling rate
DCLK – – 10 MHz
Input voltage
logic ‘0’ – – 0.2 V VIN+ - VIN-
logic ‘1’ 0.2 – – V VIN+ - VIN-
common mode voltage -7 – 12 V
Input resistance
RS-422 outputs

Signaling rate
PROG_DCLK – 1 – MHz
Output voltage
absolute operating range -0.3 – 6 V Absolute voltage of the operating signal must stay within this
range.
logic ‘0’ – – -2 V V0+ - V0- ; RLOAD = 100Ω
logic ‘1’ 2 – – V V0+ - V0- ; RLOAD = 100Ω
RS-485
Signaling rate
PROG_DATA – – 1 Mbps
Input voltage
logic ‘0’ – – 0.2 V VIN+ - VIN-
logic ‘1’ 0.2 – – V VIN+ - VIN-
66 29 Oct. 2008 | DST/R/083

RS-485 (continued)

Output voltage
logic ‘0’ – – -2 V V0+ - V0- ; RLOAD = 100Ω
logic ‘1’ 2 – – V V0+ - V0- ; RLOAD = 100Ω
Input resistance
Setting up the SAM/DEC/007
Type: D/E (RS-422) or S/E (TTL)
Code: BIØ-L or NRZ-L + DCLK and polarity (true/false)
Bit-rate: BIØ-L (350bps to 5Mbps) and NRZ-L + DCLK (350bps to 10Mbps).

A minimum time of 700ns per word is required for decommutation to work. Therefore, the minimum
number of allowable bits/word increases with increasing bit rate, as shown in the following example:
Bitrate = 10Mbps
F=1/T ⇒ T=100ns
Therefore, 700ns/100ns = 7 bits/word (minimum)
Word definition: Data bits/word (4 to 16), Orientation (MSB first/last), Parity (Odd/even/none), Store data word.
Syncword: 4 to 34 bits, plus mask, plus lock on true and inverse
Getting the most from the

SAM/DEC/007
The SAM/DEC/007 is not a KAM-500 module. It is designed
for insertion in a PCMCIA 2.0 Type II compatible socket in a
notebook PC, or desktop (or any other computer) fitted with a
PC Card reader.
It is important to ground (that is, connect to GND) the source
of the PCM stream or the KAM-500 being programmed.
Software is available, from a full graphical user interface to
low-level drivers, when using the SAM/DEC/007 as an
interface to the KAM-500 or as a PCM decoder. When
installing the decoder card, if using the Found New Hardware
wizard, ensure the auto-select option selects the correct
version of the driver for your operating system.
The PROG_DCLK± link is provided so that the Figure 2: SAM/DEC/007 with mechanical harness
SAM/DEC/007 can be used to program the KAM-500
controller. For NRZ-L and clock, better results are sometimes
obtained by inverting the clock.
Use 3mm (0.19in.) width cable ties to secure the I/O cable to
the mechanical harness attached to the SAM/DEC/007, as
shown in Figure 2.
29 Oct. 2008 | DST/R/083 67

Connector pinout on the SAM/DEC/007/C
Figure 3: Connector: 15-way LAN open to standard 15-way commercial D-type plug connector cable

1 DATA BTTL inputs PCM data stream; S/E alternative to pins 3 and 4
2 DCLK BTTL inputs PCM bit clock; S/E alternative to pins 12 and 13
3 DATA+ RS-422 inputs PCM data stream; D/E alternative to pin 1
4 DATA- RS-422 inputs PCM data stream; terminated by 120Ω resistor
6 PROG_DATA+ RS-485 Programming data; terminated by 120Ω resistor
8 PROG_DATA- RS-485 Programming data; terminated by 120Ω resistor
9 PROG_DCLK+ RS-422 outputs Programming clock; terminated by 120Ω resistor
11 PROG_DCLK- RS-422 outputs Programming clock; terminated by 120Ω resistor
12 DCLK+ RS-422 inputs PCM bit clock; D/E alternative to pin 2
13 DCLK- RS-422 inputs PCM bit clock; terminated by 120Ω resistor
www.acracontrol.com
68 29 Oct. 2008 | DST/R/083

ACRA Analog modules
C O N T R O L
69
KAD/ADC/002/C/10V, KAD/ADC/002/C/1V,
KAD/ADC/002/C/100M, KAM/ADC/002/C/10V
KAM/ADC/002/C/1V, KAM/ADC/002/C/100M
A C R A KAM-500 ADC/002
2 channel D/E analog-to-digital converter at 100ksps
C O N T R O L
DESCRIPTION
The ADC/002 is used to digitize up to two D/E channels at
rates of up to 100,000sps. Each channel has an independent
instrumentation amplifier, 6-pole anti-aliasing filter (fc=
12.5kHz) and A/D converter with digital filter. The input range
may be factory set at ±10V, ±1V or ±100mV. Fixed
independent bipolar excitation of ±5V is provided for each
channel.
At the heart of the ADC/002 is a hard-wired state machine
that over-samples all channels and digitally filters any noise
above the user-programmable cutoff frequency. This is
FEATURES achieved using cascaded, half-band, decimate by 2, 15 tap
• Two differential ended (D/E) channels finite-impulse-response (FIR) filters with 32-bit coefficients.
• Up to 100,000 samples per second per channel All signals are sampled simultaneously.
• 14-bit A/D simultaneous sampling for each channel
• Programmable offset and filter cutoff for each channel
• Factory-set input range: ±10V, ±1V or ±100mV
• Two independent excitation outputs of ±5V
• Accuracy: 0.25% FSR error from all sources
• Up to 12.5kHz bandwidth (AAAF filter)
APPLICATIONS
• Acoustic measurement
• Compatible with piezoresistive microphone models
8510B-1 and 8510B-2
• Compatible with piezoresistive pressure transducer models
8515C-15 and 8515C-50
+5V
+
EXC(0)+ 3 AMP-
+ G=100
1 + ANALOG Σ COUNTS
ANALOG(0) →DIGITAL → UNITS
- 2 - ×
Inst. amp. AAAF Digital filter Lookup

6 pole
anti-aliasing
+ -5V filter
EXC(0)- 4 AMP-
GND 51
ADC/002
First of 2 differential channels (wired for a range of ±100mV) with excitation
10 Jun. 2008 | DST/R/053 71

Selection Paths
Airborne Data Acquisition → KAM-500 → Modules → Analog → Wideband Voltage
KAD/ADC/002/C/10V CON/KAD/002/CP ADC/002/C/10V module with 52-way double-density module top connector
KAD/ADC/002/C/1V CON/KAD/002/CP ADC/002/C/1V module with 52-way double-density module top connector
KAD/ADC/002/C/100M CON/KAD/002/CP ADC/002/C/100M module with 52-way double-density module top

connector
KAM/ADC/002/C/10V ACC/CON/008/04 ADC/002/C/10V module with 51-way micro-miniature module top

connector
KAM/ADC/002/C/1V ACC/CON/008/04 ADC/002/C/1V module with 51-way micro-miniature module top connector
KAM/ADC/002/C/100M ACC/CON/008/04 ADC/002/C/100M module with 51-way micro-miniature module top

connector
Revision History
ADC/002/C/100M ADC/002/C module with occasional accidental erasing of Recommended for new programs
EEPROM address resolved and input range ±100mV
ADC/002/C/1V ADC/002/C module with occasional accidental erasing of Recommended for new programs
EEPROM address resolved and input range ±1V
ADC/002/C/10V ADC/002/C module with occasional accidental erasing of Recommended for new programs
EEPROM address resolved and input range ±10V
ADC/002/B Dual channel, wide-bandwidth analog module Not recommended for new programs
Related Products
Module Details
Document Details
www.acracontrol.com
72 10 Jun. 2008 | DST/R/053

Specifications

Slots – – 1 – Can be placed in any user-slot in any combination.
Mass
– 92 – g
Power consumption
+5V 300 – 340 mA
±7V 0 – 0 mA
+12V 30 – 50 mA Excludes current used by excitation.
-12V 20 – 30 mA Excludes current used by excitation.

Sampling rate While the sampling rate can be set individually, each must have
a power of two times any other (¼, ½ ...2, 4).
Channel[1:0] 1 – 100,000 sps
Input voltage
ADC/002/C/10V
ADC/002/C/1V
operating range -100 – 100 mV
ADC/002/C/100M
gain=1, 10, 100 – – 0.25 %FSR
gain=2, 20, 200 – – 0.45 %FSR
gain=4, 40, 400 – – 0.85 %FSR
gain=8, 80, 800 – – 1.6 %FSR
gain=1, 10, 100 8 10 – bits
Crosstalk
gain=1, 10, 100 – -72 -55 dB
Common mode
voltage range -10 – 10 V Operational voltage range.
rejection ratio 55 65 – dB Applies within the above common mode voltage range, 0≤f ≤fc.
(fc : filter cutoff frequency)
10 Jun. 2008 | DST/R/053 73

Differential ended analog inputs (continued)

Analog filter Analog filter is Butterworth.
poles – – 6 –
filter cutoff -3dB – 12.5 – kHz
Digital filter Digital filter is cascaded 15 tap FIR.
poles – – – –
filter cutoff 0.25 – 16 fs The maximum value is limited to 25kHz (fs: sampling frequency).
6dB
0.1dB bandwidth – 0.64 – fc
aliasing to 0.1dB band – – -40 dB
aliasing to fc – – -40 dB
Filter delay – 4.75 – ms Where fin = fc = 1kHz (fin : input signal frequency). See
“Understanding filter delays” on page 77.
Input resistance
between inputs (off) – 10 – MΩ Module powered off.
between inputs (on) – 100 – MΩ Module powered on.
each input to GND (off) – 10 – MΩ Module powered off.
Bipolar DC voltage excitation outputs

Output voltage
operating range – 5 – V Bi-polar excitation: 5V is 10V across the bridge.
compliance – – 15 mA Per channel.
short circuit current – 50 80 mA
DC error
error – 0.1 0.2 %FSR With a constant 350Ω load.
noise – 0.5 – mVrms As measured on analog input.
Output resistance – 0.6 – Ω
74 10 Jun. 2008 | DST/R/053

Setting up the ADC/002
acquisition system

Ordering options
The PartReference, RangeMinimum, and RangeMaximum settings are specific to each module variant. Only one variant is
shown below.

The following table lists the setup configurations available for the KAD/ADC/002/C/10V.
Manufacturer -
Name ACRA CONTROL ACRA CONTROL Name of manufacturer
PartReference KAD/ADC/002/C/10V KAD/ADC/002/C/10V ACRA CONTROL part number
SerialNumber Unique name for each module
Settings -
Module-Analog-In-1.2 -
Channel
Settings for this channel.
Channel(1:0)
Required cutoff point for the filter is the chosen value
multiplied by the user sampling frequency. 0.25 is
FilterCutoff 0.25, 0.5, 1, 2, 4, 8, 16 0.25
recommended as any higher may lead to aliasing. 1 is
the sampling rate.
The following table lists all parameters that are available for the KAD/ADC/002/C/10V.
Channel(1:0)
Volt OffsetBinary 16:4 R[15:0] 0000:FFFF (hex)
Analog signal data
10 Jun. 2008 | DST/R/053 75

Programmable elements
Channel(1:0)
RangeMaximum -10 to 10 10 -
RangeMinimum -10 to 10 -10 -
SizeInBits 16:4 16 R[15:0] 0000:FFFF (hex)
"/><\.
76 10 Jun. 2008 | DST/R/053

Getting the most from the ADC/002
The ADC/002 works with the following: piezoresistive
microphone models 8510B-1 and 8510B-2; piezoresistive
pressure transducer models 8515C-15 and 8515C-50.
Bias current return path

If the signal source is isolated with respect to the KAM-500
(for example a battery), a common-mode resistance between
the negative input and ground (GND) should be used to
provide a return for bias currents and reduce common-mode
noise pick-up. Because the bias currents are in the order of
nA, resistors up to 10kΩ can be used. In most cases a short
(0Ω) is recommended.
Understanding filter delays

The KAM-500 uniquely samples all signals at the start of an
acquisition cycle and at equal intervals of time thereafter.
Signals sampled at the same sample rate will always be
sampled at the same time independently of how they are
stored or transmitted. (This has significant advantages for
issues such as time correlation.) However, before signals are
sampled they are filtered to remove noise components that
might alias. The recommended cutoff point is one quarter the
sampling frequency, as this results in the maximum filtering of
aliasing frequencies.
The KAM-500 filters signals using over-sampling signal
processing techniques. All filters cause a delay inversely
proportional to the filter cutoff frequency (fc).
The filter delay for the ADC/002 is:
⎛ 20 ⎞ 1
TD ≈ TA + ⎜19.1 − N ⎟ ⋅
⎝ 2 ⎠ 4 ⋅ fC
N = INT(18.1 − log2 (4 ⋅ f C ))
INT is for the integer part of the value. For example, if x=13.5,
INT(x)=13.
fc is the filter cutoff frequency.
N cannot be lower than 1. If N is lower than 1, then use 1.
TA (analog filter delay) ≈ 50µs.
10 Jun. 2008 | DST/R/053 77

Connector pinout of the KAD/ADC/002

1 ANALOG(0)+ Differential ended analog inputs Analog input
2 ANALOG(0)- Differential ended analog inputs Analog input
3 EXC(0)+ Bipolar DC voltage excitation outputs Excitation output
4 EXC(0)- Bipolar DC voltage excitation outputs Excitation output
7 EXC(1)+ Bipolar DC voltage excitation outputs Excitation output
8 EXC(1)- Bipolar DC voltage excitation outputs Excitation output
9 NC Not connected
10 NC Not connected
11 NC Not connected
12 NC Not connected
13 NC Not connected
14 NC Not connected
15 NC Not connected
16 NC Not connected
17 NC Not connected
18 NC Not connected
19 NC Not connected
20 NC Not connected
21 NC Not connected
22 NC Not connected
23 NC Not connected
24 NC Not connected
25 NC Not connected
26 NC Not connected
27 NC Not connected
28 NC Not connected
29 NC Not connected
30 NC Not connected
31 NC Not connected
32 NC Not connected
33 NC Not connected
34 NC Not connected
35 NC Not connected
36 NC Not connected
37 NC Not connected
38 NC Not connected
39 NC Not connected
40 NC Not connected
41 NC Not connected
42 NC Not connected
43 NC Not connected
44 NC Not connected
45 NC Not connected
46 NC Not connected
47 NC Not connected
48 NC Not connected
49 NC Not connected
www.acracontrol.com
78 10 Jun. 2008 | DST/R/053

KAD/ADC/008, KAM/ADC/008
C O N T R O L 3-phase power monitor module
DESCRIPTION
The ADC/008 is a monitor for 3-phase power lines. It
measures 40 parameters associated with 3-phase power
lines:
• maximum, minimum, amplitude, root-mean-square and
average (5x6 = 30 parameters)
• active, apparent power and their ratio (3x3=9 parameters)
• period of the VOLTAGE(0) = 1 parameter
The ADC/008 has a programmable gain amplifier and
FEATURES analog-to-digital converter and a 16,384-point conversation
table for each of the six channels. All six channels are
• 3 voltage and 3 current single-ended (S/E) input channels sampled simultaneously at 125ksps.
• 10 to 1000Hz input range
The algorithm waits for a positive-going-zero crossing on
• ±10V, ±1V input range
channel 0 and resets the maximum/minimum registers for
• 12-bit or better resolution on all 40 parameters
each channel and the accumulators for the various averages.
• Accuracy: 0.3% total error from all sources at gain=1
The algorithm ends on a positive-going-zero-crossing after at
• Measures voltage, current and power (active and
least 50ms. The processing algorithm is a hard-wired state
apparent) RMS
machine with no micro-code or forbidden states.
• Measures period, power-factor and total-power
• Measures maximum, minimum, amplitude and average for The ADC/008 is available with two connector options: – the
each channel KAM/ADC/008 has a 51-way micro-miniature connector and
the KAD/ADC/008 has a 52-way double density connector.
APPLICATIONS
• 3-phase power monitoring
GAIN [1,10]
1 ANALOG COUNTS
→DIGITAL → UNITS
115VACRMS 5VACRMS
2 Inst. amp. AAAF Calculation Lookup
ACC/TRF/001
GAIN [1,10]
3 ANALOG COUNTS
I V=5V
4 Inst. amp. AAAF Calculation Lookup
External
sensor
GND
17
ADC/008
First of three phases on the ADC/008
3 Nov. 2008 | DST/N/053 79

Selection Paths
Airborne Data Acquisition → KAM-500 → Modules → Analog → AC Power Monitor
KAD/ADC/008 CON/KAD/002/CP ADC/008 module with 52-way double density module top connector
KAM/ADC/008 ACC/CON/008/04 ADC/008 module with 51-way micro-miniature module top connector
Revision History
ADC/008 3-phase power monitor module Recommended for new programs
In this data sheet ADC/008 refers to both the KAD and KAM version of the module.
Related Products
Module Details
ACC/TRF/001 External step-down transformer unit
Document Details
TEC/NOT/037 Using the KAD/ADC/008
www.acracontrol.com
80 3 Nov. 2008 | DST/N/053

Specifications
Channels
VOLTAGE 3 S/E voltages
CURRENT 3 S/E voltages
Inputs
range ±10V at gain = 1
±1V at gain = 10
type Single-ended
dc. response ±0.3%FSR (total error after offset adjust) G=1,10
ac. response 10Hz to 1kHz
input impedance 1GΩ (on) / 22kΩ (off)
overvoltage protection ±40V
Sampling Output registers are updated at a maximum rate of 20Hz
While the sampling rate for each channel can be individually set each must be a power of two times any other
(¼, ½, 1, 2, 4, and so on).
For channels Maximum and Minimum

Name No limit to characters Maximum The maximum or minimum value sampled over the sample period.
Base Unit Volt Volt R[15:4] (00016 - FFF16) for the range from -Vmax to +Vmax or -Imax
to +Imax.
maximum -10 to 10 +5
minimum -10 to 10 -5
For channel Average

Name No limit to characters Average The average values of the samples over the sample period.
Base Unit Volt Volt R[15:0] (000016 - FFFF16) for the range from -Vmax to +Vmax or -
Imax to +Imax.
maximum -10 to 10 0 Average of a sine wave is zero unless there is a DC offset present.
minimum -10 to 10 0
For channel Amplitude

Name No limit to characters Amplitude Maximum - Minimum.
Base Unit Volt Volt R[15:4] (00016 - FFF16) for the range from 0 to 2 X Vmax or 2 X Imax.
maximum 0 to 20 10
minimum 0 to 20 10
3 Nov. 2008 | DST/N/053 81

For channel RMS
Name No limit to characters Root MeanSquare N
1 2
The root-mean-square rms = ----
N ∑ Si
i=1
Base Unit Volt Volt R[15:0] (000016 - FFFF16) for the range from 0 to Vmax or Imax.
maximum 0 to 10 3.54
minimum 0 to 10 3.54
For channel 0 Period

Name No limit to characters Channel delay Average time between positive-going-zero crossings on
VOLTAGE(0).
Base Unit Seconds Seconds R[15:0] (000016 - FFFF16) for the range from 0 and 100ms.
maximum 100ms 2.5ms
minimum 100µs -2.5ms
For phase Active power

Name No limit to characters Active power N
1
The active power for each phase ACT = ----
N ∑ Vi • Ii
i=1
Base Unit Watt Watt R[15:0] (000016 - FFFF16) for the range from -VmaxImax to -VmaxImax.
maximum -100 to +100 +35
minimum -100 to +100 -20 If the phase angle between V and I is >180 then active power
becomes negative.
For phase App power

Name No limit to characters App power
The apparent power for each phase
Apparent y = V rms • I rms
y y
Base Unit Watt Watt R[15:0] (000016-FFFF16) for the range from 0 to VmaxImax.
maximum 0 to 100 25
minimum 0 to 100 25
For phase Power factor

Name No limit to characters App power The power factor for each phase FACTOR = ACT/APP.
Base Unit Ratio Ratio R[15:0] (000016-FFFF16) between -1 and +1.
maximum -1 to 1 1
minimum -1 to 1 -1
82 3 Nov. 2008 | DST/N/053

This module uses the X-Module-Analog-In XidML schema. (See http://www.xidml.org).

Manufacturer
part reference KAD/ADC/008 KAD/ADC/008 ACRA CONTROL part number.

The ADC/008 usually requires external step-down
transformers for voltage and requires external sensors for
current.
The ADC/008 does not assume a sine wave shape but does
assume each of the six channels is bipolar and is
synchronous.
3
Total power can be calculated by summing ∑ ACT .

i=1
The ADC/008 is DC coupled. If there is a DC component in

the input signal, it will be part of the measurement. To remove
this DC component, a high pass filter can be used. The cutoff
frequency of the filter will depend on the characteristics of the
input signal. However, ACRA CONTROL recommends to set
it at 50 to 80 times less than the input signal so as not to
attenuate it or change its phase angle. The filter should be
made up of an R/C network and not just a DC blocking cap,
as this takes too long to settle.
3 Nov. 2008 | DST/N/053 83

Pin Name I/O Description Comment

1 VOLTAGE(0) Analog S/E In Analog input This signal is considered 0° phase
3 CURRENT(0) Analog S/E In Analog input Voltage input (±10V)
5 VOLTAGE(1) Analog S/E In Analog input Voltage input (±10V)
9 VOLTAGE(2) Analog S/E In Analog input Voltage input (±10V)
www.acracontrol.com
84 3 Nov. 2008 | DST/N/053

KAD/ADC/010/C, KAM/ADC/010/C
2 channel D/E analog-to-digital converter
C O N T R O L
DESCRIPTION
The ADC/010 is used to digitize up to two differential ended
(D/E) channels.
For each channel there is a choice of two inputs depending
on the gain required. For example, ANALOG_A(0)± is used
for an input range of ±10V for channel 0 and ANALOG_B(0)±
is used for an input range of ±1V for channel 0. If in a setup, a
range between ±10V is selected then ANALOG_A will be
used; and if a range between ±1V is selected, then
ANALOG_B will automatically be used.
FEATURES that over-samples all channels and digitally filters any noise
• Two differential ended (D/E) input channels above the user programmable cutoff frequency. This is
• 14-bit simultaneous sampling on both channels achieved using cascaded, half-band, decimate by 2, 15 tap
• 14-bit A/D sampling for each channel finite-input response (FIR) filters with 32-bit coefficients.
• Accuracy: 0.25% error from all sources
Both signals are sampled simultaneously. A linearization
• Programmable gain, offset and filter cutoff for each channel table for each channel can be used to compensate for
• Input ranges ±10V and ±1V
non-linear sensors or to fine-tune gain and offset.
• Short to ground on one channel does not affect other
• Up to 22kHz bandwidth
APPLICATIONS
• High speed analog signal acquisition
• FTI, OLM, HUMS
+
1 + ANALOG
ANALOG_A(0)
- →DIGITAL
- 2
AAAF RANGE
INST. AMP SELECTION
G=1
Σ COUNTS
× → UNITS
DIGITAL FILTER LOOKUP TABLE
+
3 + ANALOG
ANALOG_B(0)
4 - →DIGITAL
-
AAAF
INST. AMP
G=10
GND 51
ADC/010
First of two differential channels on the ADC/010 set to use ±10V range signal path
10 Jun. 2008 | DST/R/046 85

Selection Paths
Airborne Data Acquisition → KAM-500 → Modules → Analog → Wideband Voltage
KAD/ADC/010/C CON/KAD/002/CP ADC/010/C module with 52-way double density module top connector
KAM/ADC/010/C ACC/CON/008/04 ADC/010/C module with 51-way micro-miniature module top connector
Revision History
ADC/010/C Corrected potential EEPROM overwrite problem at Recommended for new programs
address 0000016
ADC/010/B Power from 5V line reduced to 1.3W allowing for a 13U Not recommended for new programs
chassis to be filled with 13 modules of this type
ADC/010 First release Not recommended for new programs
Related Products
Module Details
ADC/002 2 channel D/E analog to digital converter at 100 ksps (±1V and ±100mV input options)
KSMv2 This module is supported in KSMv2 software
Document Details
TEC/NOT/019 An introduction to digital filtering
www.acracontrol.com
86 10 Jun. 2008 | DST/R/046

Specifications

Mass
– 75 – g
Access rate – – 0.5 Msps Maximum combined access rate for read and write.
Power consumption
+5V 200 – 330 mA
±7V 0 – 0 mA
±12V 5 – 30 mA

ANALOG_A[1:0] – – 10000 sps
ANALOG_B[1:0] – – 10000 sps
Input voltage
operating range -10 – 10 V Primary gain=1
(ANALOG_A[1:0])
(ANALOG_B[1:0])
DC error
gain=1, 10 – – 0.25 %FSR
gain=1, 10 – 9 – bits
Crosstalk
gain=1, 10 – -72 – dB
Common mode
rejection ratio – 72 – dB Applies within the above common mode voltage range, 0≤f ≤fc.
10 Jun. 2008 | DST/R/046 87


poles – – 1 –
filter cutoff -3dB – 22 – kHz ±15% error.
poles – – – – Not applicable for FIR type filters.
filter cutoff -6dB 0.25 – 16 fs The maximum value is limited to 25kHz (fs: sampling frequency).
Filter delay – 190 – ms Where fin = fc = 25Hz (fin : input signal frequency). See
Input resistance
between inputs (off) 25 – – kΩ Module powered off.
between inputs (on) 20 – – MΩ Module powered on.
each input to GND (on) 10 – – MΩ Module powered on.
88 10 Jun. 2008 | DST/R/046

acquisition system


The following table lists the setup configurations available for the KAD/ADC/010/C.
Manufacturer -
PartReference KAD/ADC/010/C KAD/ADC/010/C ACRA CONTROL part number
Settings - - -
Channel
Channel(1:0)
multiplied by the user sampling frequency. 0.25 is the
FilterCutoff 0.25, 0.5, 1, 2, 4, 8, 16 0.25
recommended as the any higher may lead to aliasing. I
is the sampling rate.
The following table lists all parameters that are available for the KAD/ADC/010/C.
Channel(1:0)
Analog signal data
Channel(1:0)
"/><\.
10 Jun. 2008 | DST/R/046 89

Input resistance
Because the input resistance changes when the input ranges
are exceeded, do not connect A and B together.


⎛ 20 ⎞ 1
TD ≈ TA + ⎜19.1 − N ⎟ ⋅
⎝ 2 ⎠ 4 ⋅ fC
N = INT(18.1 − log2 (4 ⋅ f C ))
INT(x)=13.
90 10 Jun. 2008 | DST/R/046


1 ANALOG_A(0)+ Differential ended analog inputs Analog input (gain = 1)
2 ANALOG_A(0)- Differential ended analog inputs Analog input (gain = 1)
3 ANALOG_B(0)+ Differential ended analog inputs Analog input (gain = 10)
4 ANALOG_B(0)- Differential ended analog inputs Analog input (gain = 10)
5 ANALOG_A(1)+ Differential ended analog inputs Analog input (gain = 1)
6 ANALOG_A(1)- Differential ended analog inputs Analog input (gain = 1)
7 ANALOG_B(1)+ Differential ended analog inputs Analog input (gain = 10)
8 ANALOG_B(1)- Differential ended analog inputs Analog input (gain = 10)
49 NC Not connected
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92 10 Jun. 2008 | DST/R/046

KAD/ADC/011/C/40V, KAD/ADC/011/C/10V
KAM/ADC/011/C/40V, KAM/ADC/011/C/10V
C O N T R O L 48 channel S/E analog-to-digital converter
APPLICATIONS
• Analog signal acquisition
• FTI, OLM, HUMS
DESCRIPTION
The ADC/011 is used to condition and digitize up to 48 single
ended (S/E) analog channels. At the heart of the ADC/011 is
a hard-wired state machine that over-samples all channels
and digitally filters any noise above the user programmable
cutoff frequency. This is achieved using cascaded, half-band,
decimate by 2, 15-tap, finite-impulse-response (FIR) filters
FEATURES with 32-bit coefficients.
• 48 single ended (S/E) input channels The signal conditioning on ADC/011 consists of unity gain
• 14-bit sampling on all channels buffer with the optional attenuation resistor at the input stage
• Simultaneous sampling on channels 0 to 23, and 24 to 47 such that the input options are ±10V or ±40V.
• Programmable secondary gain, offset and filter cutoff for
each channel Secondary gain and offset are achieved digitally according to
• Input ranges: ±10V or ±40V requested input range.
• ±0.3% FSR total error from all sources (no input
attenuation)
• ±0.55% FSR total error from all sources (with input
attenuation)
• Short to ground on any channel does not affect others
• Up to 8500 samples per second per channel
• Up to 0.66kHz bandwidth
249k
ANALOG Σ COUNTS
ANALOG(0) 1 →DIGITAL → UNITS
×
Buffer 1st order AAAF Digital filter Lookup
Ra
GND 51
ADC/011
First of 48 channels on the ADC/011
11 Aug. 2008 | DST/R/044 93

Selection Paths
Airborne Data Acquisition → KAM-500 → Modules → Analog → Voltage
KAD/ADC/011/C/40V CON/KAD/002/CP ADC/011/C module, input range ±40V, primary gain (analog) 0.25,
secondary gain (digital) 1 to 4 with 52-way double density module top
connector
KAD/ADC/011/C/10V CON/KAD/002/CP ADC/011/C, input range ±10V, primary gain (analog) 1, secondary gain
(digital) 1 to 4 module with 52-way double density module top connector
KAM/ADC/011/C/40V ACC/CON/008/04 ADC/011/C module, input range ±40V, primary gain (analog) 0.25,
secondary gain (digital) 1 to 4 with 51-way micro-miniature module top
connector
KAM/ADC/011/C/10V ACC/CON/008/04 ADC/011/C module, input range ±10V, primary gain (analog) 1, secondary
gain (digital) 1 to 4 module with 51-way micro-miniature module top
connector
Revision History
ADC/011/C Fixed possible EEPROM overwrite at address 0000016 Recommended for new programs
ADC/011/B Reduced power consumption on the +5V line Not recommended for new programs
Related Products
Module Details
ADC/012/C 24 channel D/E analog to digital (A/D) converter
Document Details
www.acracontrol.com
94 11 Aug. 2008 | DST/R/044

Specifications

Mass
– 75 – g
Power consumption
+5V 200 – 310 mA
±7V 0 – 0 mA
+12V 20 – 110 mA
-12V 20 – 80 mA
Single ended analog inputs

ANALOG[47:0] 1 – 8500 sps
Input voltage
(ADC/011/C/10V)
(ADC/011/C/40V)
DC error
ADC/011/C/10V – – 0.3 %FSR
ADC/011/C/40V – – 0.55 %FSR
Effective number of bits – 9 – bits
Crosstalk – -72 – dB
11 Aug. 2008 | DST/R/044 95

Single ended analog inputs (continued)

poles – – 2 –
filter cutoff -3dB – 660 – Hz ±15% error.
filter cutoff -6dB 0.25 – 16 fs The maximum value is limited to 2.125kHz (fs: sampling
frequency).
Input resistance
(ADC/011/C/10V)
each input to GND (on) 1 – – GΩ Module powered on.
(ADC/011/C/10V)
(ADC/011/C/40V)
(ADC/011/C/40V)
96 11 Aug. 2008 | DST/R/044

acquisition system


Manufacturer -
Settings -
Channel
Channel(47:0)
multiplied by the user sampling frequency. 0.25 is the
FilterCutoff 0.25, 0.5, 1, 2, 4, 8, 16 0.25
recommended as the any higher may lead to aliasing. I
is the sampling rate.
Channel(47:0)
Analog signal data
Channel(47:0)
11 Aug. 2008 | DST/R/044 97

"/><\.

stored or transmitted. The ADC/011 follows this rule, but with
one difference: The sampling time for channels 0 to 23 is
lined up with the start of the acquisition cycle as described
above; however the sampling time for channels 24 to 47 is
delayed by 55µs. For most applications such a difference is
negligible, but if the precise delay calculation is needed, then
55µs must be added to the filter delay formula below.
Before signals are sampled they are filtered to remove noise
components that might alias. The recommended cutoff point
is one quarter the sampling frequency, as this results in the
maximum filtering of aliasing frequencies.
⎛ 20 ⎞ 1
TD ≈ TA + ⎜19.1 − N ⎟ ⋅
⎝ 2 ⎠ 4 ⋅ fC
N = INT(14.15− log2 (4 ⋅ fC ))
INT(x)=13.
98 11 Aug. 2008 | DST/R/044


1 ANALOG(0) Single ended analog inputs Analog input
49 NC Not connected
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100 11 Aug. 2008 | DST/R/044

KAD/ADC/012/C/40V, KAD/ADC/012/C/10V
KAD/ADC/012/C/1V, KAD/ADC/012/C/100M
KAM/ADC/012/C/40V, KAM/ADC/012/C/10V
KAM/ADC/012/C/1V, KAM/ADC/012/C/100M
C O N T R O L 24 channel D/E analog-to-digital converter
DESCRIPTION
The ADC/012 is used to condition and digitize up to 24
differential ended (D/E) analog channels.
above the user programmable cutoff frequency. This is
achieved using cascaded, half-band, decimate by two,
15-tap, finite-impulse-response (FIR) filters with 32-bit
coefficients.
The signal conditioning on ADC/012 consists of a fixed-gain
instrumentation amplifier with additional attenuation resistors
FEATURES at the input stage. The combination of instrumentation
• 24 differential ended (D/E) input channels amplifier and attenuation resistor used defines the input
• Programmable digital gain, offset and filter cutoff for each range options of the card: ±40V (with attenuation resistor),
channel ±10V, ±1V and ±100mV. Secondary gain and offset are
• 14-bit simultaneous A/D sampling for each channel achieved digitally according to the requested range.
• Input ranges from ±100mV to ±40V
• ±0.3% FSR total error from all sources (no input
attenuation)
• ±0.55% FSR total error from all sources (with input
attenuation)
• Up to 1.2kHZ bandwidth
APPLICATIONS
• Differential voltage measurements
Z3
R1
+
ANALOG(0) AMP →DIGITAL → UNITS
2 - ×
-
R2 Inst.amp 2nd order AAAF Digital filter Lookup
Z4
GND 51
ADC/012
For the 40V version only, Z3=resistor R3; and Z4=resistor R4
For other versions Z3 and Z4 are capacitors
R1/Z3 and R2/Z4 determine attenuation (optional)
10 Jun. 2008 | DST/R/045 101

Selection Paths
KAD/ADC/012/C/40V CON/KAD/002/CP ADC/012/C module with ±40V input range with 52-way double density
module top connector
KAD/ADC/012/C/100M CON/KAD/002/CP ADC/012/C module with ±100mV input range with 52-way double density
KAM/ADC/012/C/40V ACC/CON/008/04 ADC/012/C module with ±40V input range with 51-way micro-miniature
KAM/ADC/012/C/100M ACC/CON/008/04 ADC/012/C module with ±100mV input range with 51-way micro-miniature
Revision History
ADC/012/C Occasional accidental erasing of single EEPROM Recommended for new programs
address (FFFFF16) resolved
ADC/012/B Lower power consumption (1.5W) at 5V allows a 13U Not recommended for new programs
chassis to be filled with modules of this type
ADC/012 24 channel D/E analog-to-digital converter Not recommended for new programs
Related Products
Module Details
Document Details
www.acracontrol.com
102 10 Jun. 2008 | DST/R/045

Specifications

Mass
– 75 – g
Power consumption
+5V 200 – 300 mA
±7V 0 – 0 mA
+12V 20 – 70 mA
-12V 20 – 40 mA

ANALOG[23:0] 1 – 17500 sps
Input voltage
operating range -0.1 – 0.1 V Primary gain=100
(ADC/012/C/100M)
(ADC/012/C/1V)
(ADC/012/C/10V)
operating range -40 – 40 V Primary gain=0.25
(ADC/012/C/40V)
DC error
ADC/012/C/100M – – 0.3 %FSR
ADC/012/C/1V – – 0.3 %FSR
ADC/012/C/10V – – 0.3 %FSR
ADC/012/C/40V – – 0.55 %FSR
gain=0.25, 1, 10, 100 – 9 – bits
Crosstalk
gain=0.25, 1, 10, 100 – -72 – dB
10 Jun. 2008 | DST/R/045 103


Common mode
(ADC/012/C/100M)
(ADC/012/C/1V)
(ADC/012/C/10V)
(ADC/012/C/40V)
rejection ratio 72 – – dB Applies within the above common mode voltage range, 0≤f ≤fc.
poles – – 2 –
filter cutoff -3dB – 1.2 – kHz ±15% error.
frequency).
Input resistance
(ADC/012/C/100M)
between inputs (on) 1 – – GΩ Module powered on.
(ADC/012/C/100M)
(ADC/012/C/100M)
(ADC/012/C/100M)
(ADC/012/C/1V)
(ADC/012/C/1V)
(ADC/012/C/1V)
(ADC/012/C/1V)
(ADC/012/C/10V)
(ADC/012/C/10V)
(ADC/012/C/10V)
(ADC/012/C/10V)
(ADC/012/C/40V)
between inputs (on) 100 – – kΩ Module powered on.
(ADC/012/C/40V)
(ADC/012/C/40V)
(ADC/012/C/40V)
104 10 Jun. 2008 | DST/R/045

acquisition system

Ordering options
shown below.

Manufacturer -
Settings -
Channel
Channel(23:0)
FilterCutoff 0.25, 0.5, 1, 2, 4, 8, 16 0.25
the sampling rate.
Channel(23:0)
Analog signal data
10 Jun. 2008 | DST/R/045 105

Channel(23:0)
"/><\.
106 10 Jun. 2008 | DST/R/045


⎛ 20 ⎞ 1
TD ≈ TA + ⎜19.1 − N ⎟ ⋅
⎝ 2 ⎠ 4 ⋅ fC
N = INT(15.15− log2 (4 ⋅ fC ))
INT(x)=13.
10 Jun. 2008 | DST/R/045

107

49 NC Not connected
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108 10 Jun. 2008 | DST/R/045

KAD/ADC/014/D/25M, KAD/ADC/014/D/100M
KAD/ADC/014/D/1V, KAD/ADC/014/D/10V
KAM/ADC/014/D/25M, KAM/ADC/014/D/100M
KAM/ADC/014/D/1V, KAM/ADC/014/D/10V
C O N T R O L 16 channel bridge A/D converter with voltage excitation and signal conditioning
APPLICATIONS
• Strain gage signal conditioning and digitalization
DESCRIPTION
Excitation on the ADC/014 is programmable using four
Digital/Analog converters (D/A), each of which is connected
to two pairs of drivers. If more than eight excitations are
required, each excitation output can be connected to two
bridges. Each differential ended return signal has a separate
amplifier, programmable filter and Analog/Digital converter
FEATURES (A/D).
• 16 full or ½-bridge, potentiometer or differential ended At the heart of the ADC/014 is a hard-wired state-machine
• (D/E) input channels that over-samples all channels and digitally filters any noise
• 14-bit simultaneous sampling on all channels above the programmable cutoff frequency. This is achieved
• Programmable offset adjust and filter cutoff for each using cascaded, half-band, decimate by 2, 15 tap,
channel finite-impulse-response (FIR) filters with 32-bit coefficients.
• Bipolar excitation and balancing before instrumentation All signals are sampled simultaneously. This means that even
amplifier when several channels are sampled at different sampling
• 8 excitation outputs from 4 programmable D/As rates, the sample at the start of the acquisition will always be
• Multiple format support for adjust, supporting pseudo shunt synchronized. A linearization table for each channel can be
and auto calibration used to compensate for non-linear sensors or to fine-tune
• Up to 26,000 samples per second per channel gain and offset.
• Up to 1.87kHz bandwidth (AAAF filter)
EXC_V(0)+ -
1 DIGITAL ←
+ ANALOG
ANALOG(0)+
4 - ×
ANALOG(0)-
EXC_V(0)- + +
2 AMP- AMP-
DIGITAL ←
ANALOG
34.8K Vadj
GND 51
ADC/014
10 Jun. 2008 | DST/R/022 109

Selection Paths
Airborne Data Acquisition → KAM-500 → Modules → Analog → Bridge
KAD/ADC/014/D/10V CON/KAD/002/CP ADC/014/D/10V module with 52-way double-density top connector
KAD/ADC/014/D/1V CON/KAD/002/CP ADC/014/D/1V module with 52-way double-density top connector
KAD/ADC/014/D/100M CON/KAD/002/CP ADC/014/D/100M module 52-way double-density top connector
KAD/ADC/014/D/25M CON/KAD/002/CP ADC/014/D/25M module with 52-way double-density top connector
KAM/ADC/014/D/10V ACC/CON/008/04 ADC/014/D/10V module with 51-way micro-miniature top connector
KAM/ADC/014/D/1V ACC/CON/008/04 ADC/014/D/1V module with 51-way micro-miniature top connector
KAM/ADC/014/D/100M ACC/CON/008/04 ADC/014/D/100M module with 51-way micro-miniature top connector
KAM/ADC/014/D/25M ACC/CON/008/04 ADC/014/D/25M module with 51-way micro-miniature top connector
The ADC/014 uses power from ±7V for excitation and therefore cannot be used with CHS/04L, CHS/05F, or CHS/03F.
Revision History
ADC/014/D Corrected EEPROM overwrite, module has ±10V, ±1V, Recommended for new programs
±100mV and ±25mV input voltage ordering options
ADC/014/C Multiple format support for adjust, supporting pseudo Not recommended for new programs
shunt and auto calibration, module has ±10V, ±1V and
±100mV input voltage ordering options
ADC/014/B Improved FPGA performance, module has ±10V, ±1V, Not recommended for new programs
±100mV and ±25mV input voltage ordering options
ADC/014 16 channel bridge A/D converter with voltage excitation Not recommended for new programs
and signal conditioning
Related Products
Module Details
KSM-2 This module is supported in KSM-2 software
Document Details
www.acracontrol.com
110 10 Jun. 2008 | DST/R/022

Specifications

Mass
– 88 – g
Power consumption
+5V 150 – 290 mA
±7V 30 – 50 mA Excludes current used by excitation.
±12V 20 – 40 mA

ANALOG[15:0] 1 – 26000 sps
Input voltage
(ADC/014/D/10V)
(ADC/014/D/1V)
(ADC/014/D/100M)
(ADC/014/D/25M)
ADC/014/D/10V – – 0.3 %FSR
ADC/014/D/1V
ADC/014/D/100M
ADC/014/D/25M – – 1.2 %FSR
ADC/014/D/10V – 9 – bits
ADC/014/D/1V
ADC/014/D/100M
ADC/014/D/25M – 8 – bits
Crosstalk
ADC/014/D/10V – -72 – dB
ADC/014/D/1V
ADC/014/D/100M
ADC/014/D/25M – -72 – dB
10 Jun. 2008 | DST/R/022 111


Common mode
rejection ratio – 60 – dB Applies within the above common mode voltage range, 0≤f ≤fc.
poles – – 2 –
poles – – – – Not applicable for FIR-type filters.
frequency).
Input resistance
each input to GND (off) 12 – – kΩ Module powered off. Measured on ANALOG(x)- input.
each input to GND (on) – 34.8 – kΩ Module powered on. Measured on ANALOG(x)- input.

Outputs – – 8 – Each output shared between two channels. Applied in groups of
four channels.
Output voltage
operating range 0 – 5.1 V Bi-polar excitation: 5V is 10V across the bridge. Allowed for
loads >700Ω. For 350Ω bridges do not exceed ±2.55V.
resolution – – 1.8 mV Bi-polar excitation: 1.8mV is 3.6mV across the bridge.
compliance – – 15 mA Per channel. Note that 30mA is shared per two channels.
short circuit current – 80 – mA
short circuit duration ∞ – – s Short on one channel affects the other channel, which uses the
same excitation driver.
DC error
error – – 0.1 %FSR With a constant 350Ω load.
noise (gain=1) – – 0.5 mVrms As measured on analog input.
noise (gain=100, 1000) – – 0.01 mVrms As measured on analog input.
112 10 Jun. 2008 | DST/R/022

Bridge adjust DC current outputs1

Outputs – – 16 – Connected internally with corresponding ANALOG(x)- input.
Output current
operating range -71 – 71 µA
resolution – 550 – nA
DC error
error – – 2 %FSR With a constant 175Ω load. The impact of this error on the
channel reading is less than 0.01%FSR (200 times lower than
the error specified here).
drift – – 0.15 µA Over temperature.
Output resistance – 34.8 – kΩ
1. The adjust line is permanently connected to ANALOG(x)- input. The line is intended for balancing strain gages, so the module
should not be used for asymmetric bridge transducers such as accelerometers or pressure transducers unless sensor re-calibra-
tion is carried out on a channel-by-channel basis.
10 Jun. 2008 | DST/R/022 113

acquisition system

Ordering options
shown below.

The following table lists the setup configurations available for the KAD/ADC/014/D/10V.
Manufacturer -
PartReference KAD/ADC/014/D/10V KAD/ADC/014/D/10V ACRA CONTROL part number
Settings - - -
Module-Analog-In-1.2 - - -
Channel
Channel(15:0)
FilterCutoff 0.25, 0.5, 1, 2, 4, 8, 16 0.25
the sampling rate.
Required excitation (in V) for the top of the bridge.
ExcitationAmplitude 0 to 5.1 0 Excitation is bipolar so entering 5V means 10V across
the bridge.
InterConnects Connection between the module channel and the sensor
No character limit Not Specified
Sensor-Channel(7:0) bridge
114 10 Jun. 2008 | DST/R/022

The following table lists all parameters that are available for the KAD/ADC/014/D/10V.
Channel(15:0)
Analog signal data
Channel(15:0)
BalanceSettings -
BalanceType CurrentShunt CurrentShunt Required shunt current (in A) for the bridge.
Applied -71e-6 to 71e-6 0 Shunt current (in A) applied to the bridge.

A data link is a connection for transmitting and receiving data. It defines both the data link and physical layers of the link.
The following are data links supported by the KAD/ADC/014/D/10V.

Name Description
Sensor-Channel(7:0) Four wire full-bridge analog I/O
"/><\.
10 Jun. 2008 | DST/R/022 115

Wiring configurations -
7 DIGITAL ←
+ ANALOG
Figures 2 to 5 show possible wiring configurations for the

ADC/014. 7
ANALOG(3)+
12 - ×
ANALOG(3)-
Buffer AAAF Digital filter Lookup
EXC_V(0)+ - + +
1 DIGITAL ← AMP- AMP-
+ ANALOG

DIGITAL ←
ANALOG
GND 35K[Radj] Vadj
51
ANALOG(0)+
3 + ANALOG Σ COUNTS KAD/ADC/014
4 - ×
ANALOG(0)-
EXC_V(0)-
2
+
AMP
-
+
AMP- Figure 5: Fourth of 16 differential ended channels

DIGITAL ←
ANALOG
34.8K Vadj
GND 51
ADC/014
As shown in Figure 5, the analog inputs can be used as
differential inputs (that is, not from a bridge). In this case, if
Figure 2: First of 16 channels on the ADC/014 the signal source is isolated with respect to the KAM-500 (for
negative input and ground (GND) should be used to provide a
-
EXC_V(0)+
1
+
DIGITAL ←
ANALOG resistors up to 10kΩ can be used. In most cases a short (0Ω)
is recommended.
ANALOG(1)+
5 + Σ
When analog inputs are used as differential inputs,
ANALOG COUNTS
6 - ×
ANALOG(1)-
setting the excitation and balance to zero improves
+ +
accuracy and reduces quiescent currents of the
EXC_V(0)-
2 AMP- AMP-
module.
DIGITAL ←
ANALOG
GND 35K[Radj] Vadj
51
KAD/ADC/014
ADC/014 shared excitations
The ADC/014 has 16 differential input channels and eight
symmetrical excitation channels that can each provide a total
Figure 3: Second of 16 ½-bridge channels of 30mA. There are more input channels than excitations, this
means that excitations must be shared across sensors if
there are more sensors than excitations.
The rules for shared excitations are:
EXC_V(1)+
7
+
AMP- DIGITAL ← 1. The same voltage must be selected for them
ANALOG
2. The total current drawn must not exceed 30mA

ANALOG(2)+
Example
ANALOG(2)-
10 -
→DIGITAL
×
→ UNITS
The following example includes two 350Ω full bridges. It will
use the ADC/014 inputs “ANALOG(0)” and “ANALOG(1)”. It
EXC_V(1)-
8
+
AMP-
+
AMP-
will share the excitation output “EXC_V(0)”.
DIGITAL ←
ANALOG
GND 35K[Radj] Vadj
51
KAD/ADC/014
Figure 4: Third of 16 potentiometer channels
Figure 6: Sample wiring of bridge sensors with shared

excitation
116 10 Jun. 2008 | DST/R/022

It is important to ensure that the current does not exceed
15mA for each bridge. If all resistors are exactly 350Ω then
there will be the current “i” down each bridge arm with the
following equation.
i = ((EXC_V+) – (EXC_V-))/(350+350)
The excitation voltage must be setup in such a way that the
current is less than 7.5mA per arm (there are four arms, two
per sensor, and 30mA available).
Therefore the limit is nominally:
((EXC_V+) – (EXC_V-)) = 750 * 0.0075
((EXC_V+) – (EXC_V-)) = 5.625
also EXC_V+= - EXC_V-
So maximum excitation in KSM should nominally be a
maximum ±2.8125V for the 350Ω bridge. Allowing 10%
tolerance, 2.5V is recommended for the bridge. An excitation
of 2.5V would be safe for the 350Ω full bridge.
Excitation setup
Excitation can contribute error to the overall measurement,
so it is recommended to use as close as possible to full-scale
excitation, to minimize the percentage error.
For optimal accuracy ensure each channel uses its
corresponding excitation. If the excitation is not used, it
should be set to 0.
Compensation for lead resistance

In bridge applications, if the lead resistance can be measured
excitation voltage. For example, for 0.5Ω leads in a 350Ω
full-bridge, where ±2.5V (5V) is desired across the bridge, the
excitation should be set to 5V + (0.5 x 5/350) = ±2.507.

⎛ 20 ⎞ 1
TD ≈ TA + ⎜19.1 − N ⎟ ⋅
⎝ 2 ⎠ 4 ⋅ fC
N = INT(15.7 − log2 (4 ⋅ f C ))
INT(x)=13.
TA (analog filter delay) ª 125µs.
10 Jun. 2008 | DST/R/022 117


1 EXC_V(0)+ Bipolar DC voltage excitation outputs Excitation to top of bridge
2 EXC_V(0)- Bipolar DC voltage excitation outputs Excitation to bottom of bridge
49 NC Not connected
50 GND KAM-500 chassis
www.acracontrol.com
118 10 Jun. 2008 | DST/R/022

KAD/ADC/105/B
8 channel D/E analog-to-digital converter with signal conditioning
C O N T R O L
DESCRIPTION
The ADC/105 is used to condition and digitize up to eight
differential ended (D/E) analog channels.
At the heart of the ADC/105 is a hard-wired state-machine
programmable cutoff frequency. This is achieved using
cascaded, half-band, decimate by 2, 15 tap,
finite-impulse-response (FIR) filters with 32-bit coefficients
followed by an 8th order Butterworth IIR filter with a default
cutoff point set at 25% of the sampling frequency.
FEATURES All signals are sampled simultaneously. Thus, when several
• Eight differential ended (D/E) input channels channels are sampled at different sampling rates, at the start
• Simultaneous 16-bit A/D for each channel of an acquisition cycle all channels will be aligned.
• High accuracy
• Programmable input range per channel
• 8th order Butterworth filter with programmable cutoff
frequency per channel
APPLICATIONS
Gain (1, 10, 100, 1000)

ANALOG(0)+ 1 + ANALOG Σ
→DIGITAL
ANALOG(0)- 2 - ×
Inst. amp. AAAF Digital filter
GND 17
ADC/105
18 Aug. 2008 | DST/U/028 119

Selection Paths
KAD/ADC/105/B 8 channel D/E analog-to-digital converter with signal conditioning
Revision History
ADC/105/B Improved format switching Recommended for new programs
Related Products
Module Details
ADC/005 8 channel D/E analog-to-digital converter with signal conditioning
Document Details
www.acracontrol.com
120 18 Aug. 2008 | DST/U/028

Specifications

Mass
– 80 – g
Power consumption
+5V 100 – 175 mA
+7V 10 – 15 mA
-7V 5 – 10 mA
+12V 45 – 65 mA
-12V 40 – 55 mA

ANALOG[7:0] 2 – 24000 sps
Input voltage
operating range (Gp=1) -10 – 10 V Primary gain=1
operating range (Gp=100) -100 – 100 mV Primary gain=100
gain=1, 10, 100 – – 0.08 %FSR
gain=2, 20, 200 – – 0.14 %FSR
gain=4, 40, 400 – – 0.25 %FSR
gain=8, 80, 800 – – 0.44 %FSR
gain=1000 – – 0.3 %FSR
gain=2000 – – 0.6 %FSR
gain=4000 – – 1.2 %FSR
gain=1, 10 13.5 – – bits fc≤ 2kHz and secondary gain of 1 (fc : filter cutoff frequency).
gain=100 11.3 – – bits fc≤ 2kHz and secondary gain of 1.
gain=1000 8 – – bits fc≤ 2kHz and secondary gain of 1.
Crosstalk
gain=1, 10, 100 – – -60 dB
gain=1000 – – -57 dB
18 Aug. 2008 | DST/U/028 121


Common mode
poles – – 4 –
Digital filter Digital filter is Butterworth.
poles – – 8 –
Input resistance
122 18 Aug. 2008 | DST/U/028

acquisition system


The following table lists the setup configurations available for the KAD/ADC/105/B.
Manufacturer -
PartReference KAD/ADC/105/B KAD/ADC/105/B ACRA CONTROL part number
Settings - - -
Channel
Channel(7:0)
FilterCutoff 0.25, 0.5, 1, 2, 4, 8, 16 0.25
the sampling rate.
The following table lists all parameters that are available for the KAD/ADC/105/B.
Channel(7:0)
Analog signal data
Channel(7:0)
18 Aug. 2008 | DST/U/028 123

Getting the most from the ADC/105 The filter delay for the ADC/105 is:
Bias current return path 1

TD ≈ TA + + TButterworth8 ( f )
If the signal source is isolated with respect to the KAM-500 fC
the negative input and ground (GND) should be used to TA (analog filter delay) ≈ 0
provide a return for bias currents and reduce common-mode fc is the filter cutoff frequency.
(0Ω) is recommended. Additional delay sources
Primary gains higher than 1 cause an additional delay from
Using high primary gains 1st order filters in the instrumentation amplifier. That
For gains above 1000, the gain-bandwidth product of the additional delay is 3μs for a gain of 10 and 13.6ms for a gain
amplifier reduces the bandwidth to 1000Hz. of 100. In applications where time correlation is more
important than suppression of aliasing, set the same cutoff
Understanding filter delays point on all channels, even if the sampling rates are different.
The KAM-500 uniquely samples all signals at the start of an Modelling an 8th order Butterworth filter with an IIR digital
acquisition cycle and at equal intervals of time thereafter. filter causes small phase and amplitude errors as shown in
Signals sampled at the same sample rate will always be Figure 3 and Figure 4.
sampled at the same time independently of how they are degrees
stored or transmitted. (This has significant advantages for 3
issues such as time correlation.) However, before signals are 2.5

2
sampling frequency, as this results in the maximum filtering of 1.5
aliasing frequencies. 1
0.5
processing techniques. Figure 2 shows a delay for an 8th
0
0.01 0.1 1
order filter where fc = 1kHz. All filters cause a delay inversely

-0.5
proportional to the filter cutoff frequency (fc), so to calculate

-1
the delay for other fc values, multiply the delay by 1kHz/ fc.
-1.5
The frequency axis then needs to be rescaled to the new fc

-2
by dividing the frequency values by 1kHz/ fc. For example, an

-2.5
-3
fin/fc
8th order Butterworth filter with an fc of 1kHz delays a 1kHz
signal by 1ms; a filter with an fc of 10Hz delays a 10Hz signal Figure 3: Delay error (ideal minus actual delay)
by 0.1s. The delay for IIR filters (for example Butterworth)
varies with the input frequency.
mdB
milliseconds 100
0
0. 01 0. 1 1
-100
-200
-300
-400 fin/fc
Figure 4: Amplitude error (ideal minus actual attenuation)

kHz
Figure 2: Filter delay for 8th order Butterworth filter where

fc = 1kHz
124 18 Aug. 2008 | DST/U/028

Connector pinout of the KAD/ADC/105/B

18 NC Not connected
19 NC Not connected
20 NC Not connected
21 NC Not connected
22 NC Not connected
23 NC Not connected
24 NC Not connected
25 NC Not connected
26 NC Not connected
27 NC Not connected
28 NC Not connected
29 NC Not connected
30 NC Not connected
31 NC Not connected
32 NC Not connected
33 NC Not connected
34 NC Not connected
35 NC Not connected
36 NC Not connected
37 NC Not connected
38 NC Not connected
39 NC Not connected
40 NC Not connected
41 NC Not connected
42 NC Not connected
43 NC Not connected
44 NC Not connected
45 NC Not connected
46 NC Not connected
47 NC Not connected
48 NC Not connected
49 NC Not connected
50 NC Not connected
51 NC Not connected
www.acracontrol.com
126 18 Aug. 2008 | DST/U/028

KAM-500 KAD/ADC/106/C
KAD/ADC/106
6-channel S/E accelerometer (ICP) analog-to-digital converter with sig. conditioning
APPLICATIONS
• Accelerometer signal conditioning and digitalization
• Suitable for ICP©, Isotron©, Piezotron© and Deltatron©
sensors
DESCRIPTION
The KAD/ADC/106 is used to condition and digitize up to
eight D/E analog channels. Six of these channels have a
constant current source and high-pass (DC-reject) filter for
use with integrated charge-amp piezoelectric (ICP)
FEATURES accelerometer devices.
• Six accelerometer input channels with DC-reject At the heart of the KAD/ADC/106 is a hard-wired
• Constant current source excitation per channel (3.6mA state-machine that oversamples all channels at a rate
typical) between 96ksps and 192ksps and digitally filters any noise
• Two differential ended (D/E) voltage input channels above the user-programmable cutoff frequency.
• Simultaneous sampling 16-bit A/D for each channel
• High accuracy This is achieved using cascaded, half-band,
• Programmable input range per channel finite-impulse-response (FIR) filters followed by an 8th order
• 8th order Butterworth filter with programmable cutoff Butterworth IIR filter with a default cutoff point set at one
frequency per channel quarter of the sampling frequency (fc=fs/4).
• Up to 24,000 samples per second per channel All signals are sampled simultaneously (isochronously).
• Up to 6kHz bandwidth Thus, when several channels are sampled at different
• Enhanced mechanical strength between motherboard and sampling rates, at the start of an acquisition cycle all
daughterboard channels will be aligned.
• High impedance per channel when powered off
3.6mA
+24V
Gain (1,10)
1µF
1
ANALOG(0)
+ ANALOG Σ COUNTS
1M →DIGITAL → UNITS
GND
- ×
2
Digital filter Lookup
Gain (1,10, 100, 1000)
+
ANALOG(6) →DIGITAL → UNITS
14 - ×
-
Inst. amp AAAF Digital filter Lookup
4th order
[email protected]
Fs>96kHz
GND 51
KAD/ADC/106
First of six accelerometer channels and first D/E channel on the KAD/ADC/106
14 Jan. 2009 | DST/U/033 127

Selection Paths
Airborne Data Acquisition → KAM-500 → Modules → Analog → Accelerometer
KAD/ADC/106/C 6-channel S/E accelerometer (ICP) analog-to-digital converter with sig. conditioning
Revision History
KAD/ADC/106/C High impedance per channel when powered off, Recommended for new programs
enhanced mechanical strength and higher compliance
voltage for current excitations
KAD/ADC/106/B Reduced power consumption on the ±7V power lines Not recommended for new programs
KAD/ADC/106 First release Not recommended for new programs
Related Products
Module Details
Document Details
www.acracontrol.com
128 14 Jan. 2009 | DST/U/033

Specifications

Mass
– 98 – g
Power consumption
+5V 100 – 200 mA
±7V 0 – 0 mA
±12V 50 – 80 mA Excludes current used by excitation. As a DC/DC converter is
used, multiply excitation current by 1.1 to calculate +12V and
-12V line currents.
AC analog inputs

ANALOG[5:0] 2 – 24,000 sps
Input voltage
AC gain error
gain=1, 2, 4, 8, 10, 20, 40, 80 – – 0.4 %FSR For fin <0.6fc and 10Hz< fin <2kHz, note that the first limitation is
mostly due to the natural attenuation of IIR digital filter. The
second limitation is due to the attenuation of analog filters in the
signal path. (fin : input signal frequency; fc : filter cutoff
frequency)
gain=1, 10 13 – – bits fc≤ 2kHz and secondary gain of 1.
Crosstalk
gain=1, 10 – -72 -60 dB The maximum crosstalk value given here represents the worst
case scenario for fin close to 6kHz; the typical value is met below
3kHz.
High pass filter
poles – – 1 –
filter cutoff -3dB – 0.16 – Hz ±15% error.
Anti aliasing filter
poles – – 4 –
14 Jan. 2009 | DST/U/033 129

AC analog inputs (continued)

poles – – 8 –
Filter delay – 0.33 – ms Where fin = fc = 6kHz. See “Understanding filter delays” on
page 134.
Input impedance
each input to GND (off) – 1 – MΩ Module powered off (measured at 3kHz).
each input to GND (on) – 250 – kΩ Module powered on (measured at 3kHz).

ANALOG [7:6] 2 – 24000 sps
Input voltage
gain=1, 10, 100 – – 0.08 %FSR
gain=2, 20, 200 – – 0.14 %FSR
gain=4, 40, 400 – – 0.25 %FSR
gain=8, 80, 800 – – 0.44 %FSR
gain=1000 – – 0.3 %FSR
gain=2000 – – 0.6 %FSR
gain=4000 – – 1.2 %FSR
Crosstalk
gain=1, 10, 100 – -72 -60 dB The maximum crosstalk value given here represents the worst
case scenario for fin close to 6kHz; the typical value is met below
3kHz. (fin : input signal frequency)
gain=1000 – – -45 dB
poles – – 4 –
130 14 Jan. 2009 | DST/U/033


poles – – 8 –
Filter delay – 0.33 – ms Where fin = fc = 6kHz. (fin : input signal frequency) See
Input resistance
between inputs (off) 1 – – GΩ Module powered off.
each input to GND (off) 1 – – GΩ Module powered off.
Single ended DC current excitation outputs

Outputs – – 6 – Applied per channel.
Output current
operating range – 3.6 – mA
compliance – – 24 V
short circuit current – – 4.9 mA
short circuit duration ∞ – – s
DC error
error – – 1.3 mA With a constant 2.2kΩ load.
noise – 3 – mVrms As measured on analog input.
14 Jan. 2009 | DST/U/033 131

Setting up the KAD/ADC/106
acquisition system

132 14 Jan. 2009 | DST/U/033

The following table lists the setup configurations available for the KAD/ADC/106/C.
Manufacturer -
PartReference KAD/ADC/106/C KAD/ADC/106/C ACRA CONTROL part number
Settings - - -
Channel
Acceleration(5:0)
FilterCutoff 0.25, 0.5, 1, 2, 4, 8, 16 0.25
the sampling rate.
Channel
Channel(1:0)
FilterCutoff 0.25, 0.5, 1, 2, 4, 8, 16 0.25
the sampling rate.
The following table lists all parameters that are available for the KAD/ADC/106/C.
Acceleration(5:0)
Acceleration signal data
Channel(1:0)
Analog signal data
Acceleration(5:0)
Channel(1:0)
"/><\.
14 Jan. 2009 | DST/U/033 133

Getting the most from the milliseconds
KAD/ADC/106
Signal return path
For channels 0 to 5, each signal is single ended so a return
(GND) for the constant current must be provided. Return path
effects are minimized if a GND pin on the module is used.
These channels are band-pass filtered (that is, the DC
component is also removed) so that when a sensor is first
connected or powered it takes about 60 seconds to settle.

kHz
For channels 6 and 7, if the signal source is isolated with
respect to the KAM-500 (for example a battery), a Figure 2: Filter delay for 8th order Butterworth filter where
common-mode resistance between the negative input and fc = 1kHz
ground (GND) should be used to provide a return for bias
currents and reduce common-mode noise pick-up. Because The filter delay for the KAD/ADC/106 is:
the bias currents are in the order of nAs, resistors up to 10kΩ
can be used. In most cases a short (0Ω) is recommended.
1
Using high primary gains fC
For gains above 1000, the gain-bandwidth product of the TA (analog filter delay) ≈ 0
amplifier reduces the bandwidth to 1000Hz.
Additional delay sources
acquisition cycle and at equal intervals of time thereafter. Primary gains higher than 1 cause an additional delay from
Signals sampled at the same sample rate will always be 1st order filters in the instrumentation amplifier. That
sampled at the same time independently of how they are additional delay is 3μs for a gain of 10 and 13.6ms for a gain
stored or transmitted. (This has significant advantages for of 100. In applications where time correlation is more
issues such as time correlation.) However, before signals are important than suppression of aliasing, set the same cutoff
sampled they are filtered to remove noise components that point on all channels, even if the sampling rates are different.
sampling frequency, as this results in the maximum filtering of Modelling an 8th order Butterworth filter with an IIR digital
aliasing frequencies. filter causes small phase and amplitude errors as shown in
Figure 3 and Figure 4.
degrees
order filter where fc = 1kHz. All filters cause a delay inversely 3
proportional to the filter cutoff frequency (fc), so to calculate 2. 5
the delay for other fc values, multiply the delay by 1kHz/ fc. 2
The frequency axis then needs to be rescaled to the new fc 1. 5
by dividing the frequency values by 1kHz/ fc. For example, an 1
0. 5
8th order Butterworth filter with an fc of 1kHz delays a 1kHz 0
signal by 1ms; a filter with an fc of 10Hz delays a 10Hz signal -0. 5

0. 01 0. 1 1
by 0.1s. The delay for IIR filters (for example Butterworth) -1
varies with the input frequency. -1. 5
-2
-2. 5
-3
fin/fc
Figure 3: Delay error (ideal minus actual delay)
134 14 Jan. 2009 | DST/U/033

mdB
100
0. 01 0. 1 1
-100
-200
-300
-400 fin/fc
Power considerations
By design, any KAM-500 chassis can be configured with any
combination of KAM-500 modules. However, there are
exceptions where total power requirements must be
considered. Refer to the relevant chassis data sheet and
TEC/NOT/016 - Power dissipation for power/current
limitations.
14 Jan. 2009 | DST/U/033 135


1 ANALOG(0) AC analog inputs Constant current output
13 ANALOG(6)+ Differential ended analog inputs
14 ANALOG(6)- Differential ended analog inputs
15 ANALOG(7)+ Differential ended analog inputs
16 ANALOG(7)- Differential ended analog inputs
18 NC Not connected
19 NC Not connected
20 NC Not connected
21 NC Not connected
22 NC Not connected
23 NC Not connected
24 NC Not connected
25 NC Not connected
26 NC Not connected
27 NC Not connected
28 NC Not connected
29 NC Not connected
30 NC Not connected
31 NC Not connected
32 NC Not connected
33 NC Not connected
34 NC Not connected
35 NC Not connected
36 NC Not connected
37 NC Not connected
38 NC Not connected
39 NC Not connected
40 NC Not connected
41 NC Not connected
42 NC Not connected
43 NC Not connected
44 NC Not connected
45 NC Not connected
46 NC Not connected
47 NC Not connected
48 NC Not connected
49 NC Not connected
50 NC Not connected
www.acracontrol.com
136 14 Jan. 2009 | DST/U/033

KAD/ADC/109/C/QB120
A C R A KAM-500 ADC/109/QB120 8-ch. A/D converter, with current exc. and sig. cond. for ¼-bridge 120Ω strain gages
C O N T R O L
APPLICATIONS
• 120Ω ¼-bridge strain gages
DESCRIPTION
The ADC/109/QB120 provides independent excitation for up
to eight channels and is intended for ¼-bridge
120Ω-strain-gage type applications. Each channel has a
separate programmable amplifier, programmable filter and
A/D converter.
At the heart of the ADC/109/QB120 is a hard-wired
FEATURES state-machine that over-samples all channels at a rate
between 96ksps and 192ksps, and digitally filters any noise
• Eight ¼-bridge (3-wire) input channels for ¼-bridge 120Ω above the user programmable cutoff frequency. This is
strain gages achieved using cascaded, half-band, decimate by 2, 15 tap,
• 16-bit A/D simultaneous sampling on all channels finite-impulse-response (FIR) filters with 32-bit coefficients
• High accuracy
• Programmable excitation and range per channel
cutoff point set at a quarter of the sampling frequency.
frequency per channel The current through the gage is programmable (up to 25mA
• Excitation shorted to ground on any channel does not in 6.35µA steps) and is kept constant. As the resistance
affect others changes, the voltage across the gage (and hence as seen by
• Excitation before instrumentation amplifier the amplifier) changes linearly.
• Up to 24,000 samples per second per channel All signals are sampled simultaneously. This means that even
• Up to 6kHz bandwidth when several channels are sampled at different sampling
• Enhanced mechanical strength between motherboard and rates, the sample at the start of the acquisition will always be
daughterboard synchronized.
-
DIGITAL ←
+ ANALOG
120 22k
EXC_I (0)+
6 Gain [1,10,100,1000]
ANALOG(0)
- ×

120Ω gage
22k
EXC_I (0)- -
3
+
GND 51
ADC/109/QB120
First of eight channels on the ADC/109/QB120
22 Aug. 2008 | DST/U/032 137

Selection Paths
KAD/ADC/109/C/QB120 8-ch. A/D converter, with current exc. and sig. cond. for ¼-bridge 120Ω strain gages
The ADC/109/QB120 uses power from the ±7V for excitation and therefore cannot be used with the CHS/04L, CHS/05F or
CHS/03F chassis.
Revision History
ADC/109/C/QB120 High impedance per channel when powered off, Recommended for new programs
enhanced mechanical strength and improved format
switching
ADC/109/B/QB120 First release Not recommended for new programs
Related Products
Module Details
ADC/109/B/QB350 8 channel A/D converter, with excitation and signal conditioning for ¼-bridge 350Ω strain gages
ADC/109/B/S1 8-channel bridge A/D converter module, with voltage excitation, external/internal balancing and
signal conditioning
ADC/109/B/S2 8-channel bridge A/D converter module, with voltage excitation, internal balancing, sense and
signal conditioning
ADC/009/QB350 The ADC/009/QB350 is an older module with slower throughput on the backplane, less accuracy
and longer filter delays. The ADC/109/B/QB350 is recommended for new programs.
Document Details
www.acracontrol.com
138 22 Aug. 2008 | DST/U/032

Specifications

Mass
– 98 – g
Power consumption
+5V 110 – 170 mA
+12V 60 – 70 mA
-12V 30 – 40 mA
Single ended analog inputs

Sampling rate Per channel.
ANALOG[7:0] 2 – 24,000 sps
Input voltage
gain=1, 10, 100 – – 0.08 %FSR
gain=2, 20, 200 – – 0.14 %FSR
gain=4, 40, 400 – – 0.25 %FSR
gain=8, 80, 800 – – 0.44 %FSR
gain=1000 – – 0.3 %FSR
gain=2000 – – 0.6 %FSR
gain=4000 – – 1.2 %FSR
Crosstalk
gain=1, 10, 100 – – -60 dB
gain=1000 – – -45 dB
poles – – 4 –
22 Aug. 2008 | DST/U/032 139

Single ended analog inputs (continued)

poles – – 8 –
Input resistance

Output current
operating range 0 – 25 mA
resolution – – 6.35 µA
DC error
140 22 Aug. 2008 | DST/U/032

Setting up the ADC/109/QB120
acquisition system


The following table lists the setup configurations available for the KAD/ADC/109/C/QB120.
Manufacturer -
PartReference KAD/ADC/109/C/QB120 KAD/ADC/109/C/QB120 ACRA CONTROL part number
InterConnects
Connection between the module channel and the sensor
Sensor-Channel(7:0) No character limit Not Specified
bridge
Settings - - -
Channel
Channel(7:0)
FilterCutoff 0.25, 0.5, 1, 2, 4, 8, 16 0.25
the sampling rate.
ExcitationAmplitude 0 to 0.025 0
the sampling rate.
The following table lists all parameters that are available for the KAD/ADC/109/C/QB120.
Channel(7:0)
Analog signal data
22 Aug. 2008 | DST/U/032 141

Channel(7:0)

following are data links supported by the KAD/ADC/109/C/QB120.

Name Description
Sensor-Channel(7:0) Three wire quarter-bridge analog I/O
"/><\.
142 22 Aug. 2008 | DST/U/032

Getting the most from the ADC/109/QB120 The filter delay for the ADC/109/QB120 is:
1
Lead error compensation TD ≈ TA + + TButterworth8 ( f )
The feedback line ANALOG(x) carries no current. Ideally it fC
should be connected close to the gage to help compensate
for lead resistances (assuming that both EXC_C(x)+ and TA (analog filter delay) ≈ 0
EXC_C(x)- lead resistances are the same). If operating with
two wires, and the ANALOG(x) and excitation lines fc is the filter cutoff frequency.
(EXC_C(x)+) are connected close to the module (not the
gage), the error introduced will be primarily an offset error Additional delay sources
(because the circuit is linear with respect to resistance) and
can be adjusted for.
1st order filters in the instrumentation amplifier. That
Use two-wire operation carefully. Estimation of cable additional delay is 3μs for a gain of 10 and 13.6ms for a gain
resistance should consider temperature drift over the of 100. In applications where time correlation is more
temperature range the cable operates (copper temperature important than suppression of aliasing, set the same cutoff
coefficient is approx. 0.4%/°C). Depending on the wire length point on all channels, even if the sampling rates are different.
and diameter, the drift may cause noticeable error of
measurement. In general, it may become an issue for thinner Modelling an 8th order Butterworth filter with an IIR digital
and longer cables. filter causes small phase and amplitude errors as shown in
Using high primary gains degrees
For gains above 1000, the gain-bandwidth product of the 3
amplifier reduces the bandwidth to 1000Hz. 2.5
Understanding filter delays 1.5
The KAM-500 uniquely samples all signals at the start of an 1
acquisition cycle and at equal intervals of time thereafter. 0.5
Signals sampled at the same sample rate will always be 0

0.01 0.1 1
sampled at the same time independently of how they are -0.5
stored or transmitted. (This has significant advantages for -1

-1.5
might alias. The recommended cutoff point is one quarter the -2
sampling frequency, as this results in the maximum filtering of -2.5
aliasing frequencies. -3
fin/fc

proportional to the filter cutoff frequency (fc), so to calculate mdB
100
0
by dividing the frequency values by 1kHz/ fc. For example, an 0. 01 0. 1 1
8th order Butterworth filter with an fc of 1kHz delays a 1kHz -100
signal by 1ms; a filter with an fc of 10Hz delays a 10Hz signal


milliseconds -300
-400 fin/fc
kHz
Figure 2: Filter delay for 8th order Butterworth filter where fc = 1kHz
22 Aug. 2008 | DST/U/032 143

Connector pinout of the KAD/ADC/109/QB120

3 EXC_I(0)- Single ended DC current excitation outputs Excitation current from gage
6 EXC_I(0)+ Single ended DC current excitation outputs Excitation current to gage
49 NC Not connected
50 NC Not connected
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144 22 Aug. 2008 | DST/U/032

KAD/ADC/109/C/QB350
A C R A KAM-500 ADC/109/QB350 8-ch. A/D converter, with current exc. and sig. cond. for ¼-bridge 350Ω strain gages
C O N T R O L
APPLICATIONS
• 350Ω ¼-bridge strain gages
DESCRIPTION
The ADC/109/QB350 provides independent excitation for up
to eight channels and is intended for ¼-bridge 350Ω strain
gage type applications. Each channel has a separate
programmable amplifier, programmable filter and A/D
converter.
At the heart of the ADC/109/QB350 is a hard-wired
FEATURES state-machine that over-samples all channels at a rate
between 96ksps and 192ksps and digitally filters any noise
• Eight ¼-bridge (3-wire) input channels for ¼-bridge 350Ω above the user programmable cutoff frequency. This is
strain gages achieved using cascaded, half-band, decimate by 2, 15 tap,
• 16-bit A/D simultaneous sampling on all channels finite-impulse-response (FIR) filters with 32-bit coefficients
• High accuracy followed by an 8th order Butterworth IIR filter with a default
• Programmable excitation and range per channel cutoff point set at a quarter of the sampling frequency.
frequency per channel The current through the gage is programmable (to
• Excitation shorted to ground on any channel does not approximately 14.5mA in 5µA steps) and is kept constant. As
affect others the resistance changes, the voltage across the gage (and
• Excitation before instrumentation amplifier hence as seen by the amplifier) changes linearly.
• Up to 24,000 samples per second per channel All signals are sampled simultaneously. This means that even
• Up to 6kHz bandwidth when several channels are sampled at different sampling
• Enhanced mechanical strength between motherboard and rates, the sample at the start of the acquisition will always be
daughterboard synchronized.
-
DIGITAL ←
+ ANALOG
349 22k
EXC_I (0)+
6 Gain [1,10,100,1000]
ANALOG(0)
4 - ANALOG Σ COUNTS
+ ×

350Ω gage
22k
EXC_I (0)- -
3
+
GND 51
ADC/109/QB350
First of 8 channels on the ADC/109/QB350
25 Feb. 2009 | DST/U/030 145

Selection Paths
KAD/ADC/109/C/QB350 8-ch. A/D converter, with current exc. and sig. cond. for ¼-bridge 350Ω strain gages
The ADC/109/QB350 uses power from the ±7V for excitation and therefore cannot be used with the CHS/04L, CHS/05F or
CHS/03F chassis.
Revision History
ADC/109/C/QB350 High impedance per channel when powered off, enhanced Recommended for new programs
mechanical strength and improved format switching
ADC/109/B/QB350 Has reduced power consumption on the ±7V power lines Not recommended for new
programs
ADC/109/QB350 First release Obsolete
Related Products
Module Details
ADC/109/B/QB120 8 channel A/D converter, with excitation and signal conditioning for ¼-bridge 120Ω strain gages
ADC/109/B/S1 8-channel bridge A/D converter module, with voltage excitation, external/internal balancing and
signal conditioning
ADC/109/B/S2 8-channel bridge A/D converter module, with voltage excitation, internal balancing, sense and
signal conditioning
ADC/009/QB350 Slower throughput on the backplane, less accuracy and longer filter delays
Document Details
www.acracontrol.com
146 25 Feb. 2009 | DST/U/030

Specifications

Mass
– 98 – g
Power consumption
+5V 110 – 170 mA
+12V 60 – 70 mA
-12V 30 – 40 mA
Three-wire quarter-bridge inputs

Sampling rate Per channel.
ANALOG[7:0] 2 – 24,000 sps
Input voltage
gain=100 – – 0.08 %FSR
gain=200 – – 0.14 %FSR
gain=400 – – 0.25 %FSR
gain=800 – – 0.44 %FSR
gain=1000 – – 0.3 %FSR
gain=2000 – – 0.6 %FSR
gain=4000 – – 1.2 %FSR
offset drift (temperature) – – 90 µε Worst case error at all gains with a current of 14mA into 350Ω.
gain=100 11.3 – – bits fc≤ 2kHz and secondary gain of 1 (fc : filter cutoff frequency).
Crosstalk
gain=100 – – -60 dB
gain=1000 – – -45 dB
25 Feb. 2009 | DST/U/030 147

Three-wire quarter-bridge inputs (continued)

poles – – 4 –
poles – – 8 –

Output current
operating range 0 – 14.5 mA
resolution – – 5 µA
DC error
148 25 Feb. 2009 | DST/U/030

Setting up the ADC/109/QB350
acquisition system


The following table lists the setup configurations available for the KAD/ADC/109/C/QB350.

Manufacturer
PartReference KAD/ADC/109/C/QB3 KAD/ADC/109/C/QB3 ACRA CONTROL part number.
50 50
SerialNumber Unique name for each module.
InterConnects No character limit Not Specified Connection between the module channel and the
Sensor-Channel(7:0) sensor bridge.
Module-Analog-In-1.2 – – –
Channel
Channel(7:0) Settings for this channel.
FilterCutoff 0.25, 0.5, 1, 2, 4, 8, 16 0.25 Required cutoff point for the filter is the chosen value
the sampling rate.
ExcitationAmplitude 0 to 0.0145 0 Required excitation (in A) for the ¼-bridge.
25 Feb. 2009 | DST/U/030 149

The following table lists all parameters that are available for the KAD/ADC/109/C/QB350.

Channel(7:0)
Analog signal data Volt OffsetBinary 16:4 R[15:0] 0000:FFFF (hex)
Channel(7:0)

RangeMinimum -10 to 10 -10 –
RangeMaximum -10 to 10 10 –

following are data links supported by the KAD/ADC/109/C/QB350.
Name Description
Sensor-Channel(7:0) Three wire quarter-bridge analog I/O
"/><\.
150 25 Feb. 2009 | DST/U/030

Getting the most from the ADC/109/QB350 The filter delay for the ADC/109/QB350 is:
1
Lead error compensation TD ≈ TA + + TButterworth8 ( f )
The feedback line ANALOG(x) carries no current. Ideally it fC
for lead resistances (assuming that both EXC_C(x)+ and TA (analog filter delay) ≈ 0
two wires, and the ANALOG(x) and excitation lines fc is the filter cutoff frequency.
gage), the error introduced will be primarily an offset error Additional delay sources
Use two-wire operation carefully. Estimation of cable additional delay is 3μs for a gain of 10 and 13.6ms for a gain
resistance should consider temperature drift over the of 100. In applications where time correlation is more
temperature range the cable operates (copper temperature important than suppression of aliasing, set the same cutoff
coefficient is approx. 0.4%/°C). Depending on the wire length point on all channels, even if the sampling rates are different.
measurement. In general, it may become an issue for thinner Modelling an 8th order Butterworth filter with an IIR digital
and longer cables. filter causes small phase and amplitude errors as shown in
Using high primary gains degrees
For gains above 1000, the gain-bandwidth product of the 3
amplifier reduces the bandwidth to 1000Hz. 2.5
Understanding filter delays 1.5
The KAM-500 uniquely samples all signals at the start of an 1
acquisition cycle and at equal intervals of time thereafter. 0.5
Signals sampled at the same sample rate will always be 0

0.01 0.1 1
sampled at the same time independently of how they are -0.5
stored or transmitted. (This has significant advantages for -1

-1.5
sampling frequency, as this results in the maximum filtering of -2.5
aliasing frequencies. -3
fin/fc

100
0


milliseconds -300
-400 fin/fc
kHz
Figure 2: Filter delay for 8th order Butterworth filter where fc = 1kHz
25 Feb. 2009 | DST/U/030 151

Connector pinout of the KAD/ADC/109/QB350

4 ANALOG(0) Three-wire quarter-bridge inputs Analog input
49 NC Not connected
50 NC Not connected
www.acracontrol.com
152 25 Feb. 2009 | DST/U/030

KAD/ADC/109/C/S1
ACRA 8-ch. bridge A/D converter module, with voltage excitation and signal conditioning
ADC/109/S1
C O N T R O L
APPLICATIONS
• Bridge sensors
DESCRIPTION
The ADC/109/S1 provides independent excitation for up to
eight channels. Each channel has a separate programmable
amplifier, programmable filter and A/D converter.
At the heart of the ADC/109/S1 is a hard-wired state-machine
FEATURES that over-samples all channels at a rate between 96ksps and
• Eight full or ½-bridge, potentiometer or differential ended programmable cutoff frequency. This is achieved using
(D/E) input channels cascaded, half-band, decimate by two, fifteen tap,
• 16-bit simultaneous sampling on all channels finite-impulse-response (FIR) filters with 32-bit coefficients
• High accuracy
• Programmable excitation, balance current and range per
cutoff point set at a quarter of the sampling frequency.
channel
• 8th order Butterworth filter with programmable cutoff All signals are sampled simultaneously. Thus, when several
frequency per channel channels are sampled at different sampling rates, at the start
• Short to ground on any channel does not affect others of an acquisition cycle all channels will be aligned.
• Bipolar excitation and balancing before instrumentation
amplifier
• Enhanced mechanical strength between motherboard and
daughterboard
EXC_V(0)+
- DIGITAL ←
2 + ANALOG
+ VREF
-
GAIN [1, 10, 100, 1000]
ANALOG(0)+
ANALOG(0)- 4 - →DIGITAL × → UNITS
2
ANALOG(0)- 1 DIGITAL FILTER
CP INST. AMP AAAF LOOKUP TABLE
-
EXC_V(0)- +
3 +
-
ADJUST(0)
1 VADJ
DIGITAL ←
6
ANALOG
34.8K [R ADJ ] ADC/109/S1
1 Optional connection for strain gage balance adjust

2 Optional Analog - connection for ease of w iring
First of 8 channels on the ADC/109/S1
22 Aug. 2008 | DST/T/097 153

Selection Paths
KAD/ADC/109/C/S1 8-ch. bridge A/D converter module, with voltage excitation and signal conditioning
The ADC/109/S1 uses power from the ±7V for excitation and therefore cannot be used with the CHS/04L, CHS/05F or CHS/03F
chassis.
Revision History
ADC/109/C/S1 High impedance per channel when powered off, Recommended for new programs
switching
ADC/109/B/S1 Reduced power consumption on the ±7V power lines Not recommended for new programs
ADC/109/S1 8 channel bridge A/D converter with excitation and signal Not recommended for new programs
conditioning
Related Products
Module Details
ADC/109/B/S2 Has two excitation sense lines for each channel to compensate for lead resistances and internal
offset-adjust
ADC/009/S1 8-ch. bridge A/D converter, with excitation and signal conditioning
Document Details
www.acracontrol.com
154 22 Aug. 2008 | DST/T/097

Specifications

Mass
– 102 – g
Height above chassis For recommended clearance requirements, see the
Power consumption
+5V 100 – 180 mA
+12V 60 – 80 mA
-12V 40 – 60 mA

ANALOG[7:0] 2 – 24,000 sps
Input voltage
gain=1, 10, 100 – – 0.08 %FSR
gain=2, 20, 200 – – 0.14 %FSR
gain=4, 40, 400 – – 0.25 %FSR
gain=8, 80, 800 – – 0.44 %FSR
gain=1000 – – 0.3 %FSR
gain=2000 – – 0.6 %FSR
gain=4000 – – 1.2 %FSR
Crosstalk
gain=1, 10, 100 – – -60 dB
gain=1000 – – -45 dB
22 Aug. 2008 | DST/T/097 155


Common mode
poles – – 4 –
poles – – 8 –
Input resistance

Output voltage
operating range 0 – 5.1 V Bi-polar excitation: 5V is 10V across the bridge.
DC error

Output current
DC error
drift – – 0.15 %FSR Over temperature.
1. The adjust line is intended for use in balancing strain gages and should not be used for asymmetric bridge transducers such as
accelerometers or pressure transducers unless sensor re-calibration is carried out on a channel-by-channel basis.
156 22 Aug. 2008 | DST/T/097

Setting up the ADC/109/S1
acquisition system


The following table lists the setup configurations available for the KAD/ADC/109/C/S1.
Manufacturer -
PartReference KAD/ADC/109/C/S1 KAD/ADC/109/C/S1 ACRA CONTROL part number
InterConnects
bridge
Sensor-Channel(7:0)
Settings -
Channel
Channel(7:0)
FilterCutoff 0.25, 0.5, 1, 2, 4, 8, 16 0.25
the sampling rate.
the bridge.
22 Aug. 2008 | DST/T/097 157

The following table lists all parameters that are available for the KAD/ADC/109/C/S1.
Channel(7:0)
Analog signal data
Channel(7:0)
BalanceSettings
-

The following are data links supported by the KAD/ADC/109/C/S1.

Name Description
"/><\.
158 22 Aug. 2008 | DST/T/097

Getting the most from the ADC/109/S1 When analog inputs are used as differential inputs,
setting the excitation and balance to zero improves
Wiring configurations accuracy and reduces quiescent currents of the
module.
Figures 2 to 4 show possible wiring configurations for the
ADC/109/S1.
Using high primary gains
EXC_V(1)+
8
-
+
DIGITAL ← For gains above 1000, the gain-bandwidth product of the
ANALOG

+ VREF
-

GAIN [1, 10, 100, 1000]
Excitation setup
ANALOG(1)+
10 - →DIGITAL × → UNITS

ANALOG(1)-
CP INST. AMP AAAF DIGITAL FILTER LOOKUP TABLE
-
EXC_V(1)- +
9 +
-
VADJ
ADJUST(1)
12
34.8K [RADJ ]
DIGITAL ←
ANALOG
ADC/109/S1
51
should be set to 0.
Figure 2: Second of 8 independent ½-bridge channels Compensation for lead resistance

EXC_V(2)+ - DIGITAL ←
14 +
+
-
ANALOG VREF

GAIN [1, 10, 100, 1000]
ANALOG(2)+
- →DIGITAL → UNITS
16 ×
ANALOG(2)-
CP INST. AMP AAAF DIGITAL FILTER LOOKUP TABLE If sense lines are required, see the ADC/109/S2.
-
EXC_V(2)- +
15 +
-
VADJ
ADJUST(2) DIGITAL ←
18 ANALOG

34.8K [RADJ ] ADC/109/S1
51

Figure 3: Third of 8 independent potentiometer channels acquisition cycle and at equal intervals of time thereafter.
-
EXC_V(3) DIGITAL ←
20 + ANALOG
+ VREF
-

GAIN [1, 10, 100, 1000]
ANALOG(3)+
ANALOG(3)-
22 - →DIGITAL ×
DIGITAL FILTER
→ UNITS
CP INST. AMP AAAF LOOKUP TABLE

-
EXC_V(3) +
21 +
-
ADJUST(3)
VADJ
DIGITAL ←
24 ANALOG
51
34.8K [RADJ ] ADC/109/S1
Figure 4: Fourth of 8 independent differential ended channels The frequency axis then needs to be rescaled to the new fc
Bias current return path 8th order Butterworth filter with an fc of 1kHz delays a 1kHz
As shown in Figure 4, the analog inputs can be used as signal by 1ms; a filter with an fc of 10Hz delays a 10Hz signal
differential inputs (that is, not from a bridge). In this case, if by 0.1s. The delay for IIR filters (for example Butterworth)
the signal source is isolated with respect to the KAM-500 (for varies with the input frequency.
pick-up. Because the bias currents are in the order of nAs,
resistors up to 10kΩ can be used. In most cases a short (0Ω)
is recommended.
22 Aug. 2008 | DST/T/097 159

milliseconds
mdB
100
0. 01 0. 1 1
-100
-200
-300
-400 fin/fc
kHz
fc = 1kHz
The filter delay for the ADC/109/S1 is:
1
fC
TA (analog filter delay) ≈ 0

additional delay is 3μs for a gain of 10 and 13.6ms for a gain
of 100. In applications where time correlation is more
point on all channels, even if the sampling rates are different.
Modelling an 8th order Butterworth filter with an IIR digital

filter causes small phase and amplitude errors as shown in
degrees
3
2.5
1.5
0.5
0
0.01 0.1 1
-0.5
-1
-1.5
-2
-2.5
-3
fin/fc
160 22 Aug. 2008 | DST/T/097

Connector pinout of the KAD/ADC/109/S1
2 EXC_V(0)+ Bipolar DC voltage excitation outputs Excitation to top of bridge for channel 0
3 EXC_V(0)- Bipolar DC voltage excitation outputs Excitation to bottom of bridge for channel 0
6 ADJUST(0) Bridge adjust DC current outputs Used to balance/calibrate bridge
49 NC Not connected
50 NC Not connected
www.acracontrol.com
162 22 Aug. 2008 | DST/T/097

KAD/ADC/109/C/S2
A C R A KAM-500 ADC/109/S2
C O N T R O L 8-ch. bridge A/D converter with voltage excitation, sense lines and signal conditioning
APPLICATIONS
• Bridge sensors
DESCRIPTION
The ADC/109/S2 has eight channels of signal conditioning
and data acquisition for differential voltages, strain gage or
channel, the ADC/109/S2 provides independent bipolar
FEATURES excitation for up to eight channels. Each D/E signal has a
separate programmable amplifier, filter and A/D converter.
• Eight full or ½-bridge, potentiometer or differential ended
D/E channels At the heart of the ADC/109/S2 is a hard-wired state-machine
• 16-bit simultaneous sampling on all channels that over-samples all channels at a rate between 96ksps and
• High accuracy 192ksps and digitally filters any noise above the user
• Programmable excitation, balance current and range per channel programmable cutoff frequency. This is achieved using
• 8th order Butterworth filter with programmable cutoff cascaded, half-band, decimate by 2, 15 tap,
frequency per channel finite-impulse-response (FIR) filters with 32-bit coefficients
• Short to ground on any channel does not affect others followed by an 8th order Butterworth IIR filter with a default
• Separate pair of sense lines for each channel cutoff point set at a quarter of the sampling frequency. All
• Bipolar excitation and balancing before instrumentation signals are sampled simultaneously. Thus, when several
amplifier channels are sampled at different sampling rates, all
• Up to 24,000 samples per second per channel channels will be aligned at the start of an acquisition cycle.
The ADC/109/S2 is intended for use with strain gages, and
• Enhanced mechanical strength between motherboard and
should not be used for asymmetric bridge transducers such
daughterboard
as accelerometers, pressure transducers unless sensor
re-calibration is carried out on a channel-by-channel basis. If
the sense lines or internal offset adjust are not required, refer
to the ADC/109/S1.
SENSE(0)+
1
2 + ANALOG
+ VREF
-
GAIN [1, 10, 100, 1000]
+
ANALOG(0)
- 4 ×
INST. AMP
-
EXC_V(0)- +
3 +
-
SENSE(0)-
6 VADJ
DIGITAL ←
ANALOG
GND 51 34.8K [R ADJ ] ADC/109/S2
First of eight channels on the ADC/109/S2
22 Aug. 2008 | DST/U/031 163

Selection Paths
KAD/ADC/109/C/S2 8-ch. bridge A/D converter with voltage excitation, sense lines and signal conditioning
The ADC/109/S2 uses power from the ±7V for excitation and therefore cannot be used with CHS/04L, CHS/05F, or CHS/03F.
Revision History
ADC/109/C/S2 High impedance per channel when powered off, Recommended for new programs
switching
ADC/109/B/S2 Reduced power consumption on the ±7V power lines Not recommended for new programs
ADC/109/S2 First release Not recommended for new programs
Related Products
Module Details
ADC/109/B/QB350 8 channel 350Ω ¼-bridge ADC module with voltage excitation
ADC/109/B/S1 8 channel bridge ADC without sense lines, offset-adjust to be carried out externally
Document Details
www.acracontrol.com
164 22 Aug. 2008 | DST/U/031

Specifications

Mass
– 102 – g
Power consumption
+5V 100 – 180 mA
+12V 60 – 80 mA
-12V 40 – 60 mA

ANALOG[7:0] 2 – 24,000 sps
Input voltage
gain=1, 10, 100 – – 0.08 %FSR
gain=2, 20, 200 – – 0.14 %FSR
gain=4, 40, 400 – – 0.25 %FSR
gain=8, 80, 800 – – 0.44 %FSR
gain=1000 – – 0.3 %FSR
gain=2000 – – 0.6 %FSR
gain=4000 – – 1.2 %FSR
Crosstalk
gain=1, 10, 100 – – -60 dB
gain=1000 – – -45 dB
22 Aug. 2008 | DST/U/031 165


Common mode
poles – – 4 –
poles – – 8 –
Input resistance
each input to GND (off) – 34.8 – kΩ Module powered off. Measured on ANALOG(x)- input.
each input to GND (on) – 34.8 – kΩ Module powered on. Measured on ANALOG(x)- input.

Output voltage
DC error

Outputs – – 8 – Applied per channel. Connected internally with corresponding
ANALOG(x)- input.
Output current
DC error
166 22 Aug. 2008 | DST/U/031

Setting up the ADC/109/S2
acquisition system


The following table lists the setup configurations available for the KAD/ADC/109/C/S2.
Manufacturer -
PartReference KAD/ADC/109/C/S2 KAD/ADC/109/C/S2 ACRA CONTROL part number
InterConnects
bridge
Settings -
Channel
Channel(7:0)
FilterCutoff 0.25, 0.5, 1, 2, 4, 8, 16 0.25
the sampling rate.
the bridge.
22 Aug. 2008 | DST/U/031 167

The following table lists all parameters that are available for the KAD/ADC/109/C/S2.
Channel(7:0)
Analog signal data
Channel(7:0)
BalanceSettings -

following are data links supported by the KAD/ADC/109/C/S2.

Name Description
"/><\.
168 22 Aug. 2008 | DST/U/031

Getting the most from the ADC/109/S2 resistors up to 10kΩ can be used. In most cases a short (0Ω)
is recommended.
Wiring configurations When analog inputs are used as differential inputs,
Figures 2 to 4 show possible wiring configurations for the setting the excitation and balance to zero improves
ADC/109/S2. accuracy and reduces quiescent currents of the
module.
SENSE(1)+
7
-
Using high primary gains
EXC_V(1)+ DIGITAL ←
8 + ANALOG
+ VREF
-
For gains above 1000, the gain-bandwidth product of the

GAIN [1, 10, 100, 1000]
ANALOG(1)+
11
10
+
-
ANALOG
→DIGITAL
Σ
×
COUNTS
→ UNITS
Excitation setup
ANALOG(1)- AAAF DIGITAL FILTER

INST. AMP LOOKUP TABLE
EXC_V(1)-
9
+
- so it is recommended to use as close as possible to full-scale
+
SENSE(1)-
12
-
VADJ
DIGITAL ←

ANALOG
51 34.8K [R ADJ ] KAD/ADC/109/S2

should be set to 0.
Figure 2: Second of 8 independent ½-bridge channels
SENSE(2)+
13
14
+
+
-
ANALOG VREF Signals sampled at the same sample rate will always be

GAIN [1, 10, 100, 1000]
ANALOG(2)+

16 ×
ANALOG(2)-

INST. AMP
EXC_V(2)- +
- sampling frequency, as this results in the maximum filtering of
15 +
SENSE(2)-
-
18 VADJ
DIGITAL ←
GND
51 34.8K [R ADJ ]
ANALOG
KAD/ADC/109/S2 The KAM-500 filters signals using over-sampling signal
Figure 3: Third of 8 independent potentiometer channels proportional to the filter cutoff frequency (fc), so to calculate
19 by dividing the frequency values by 1kHz/ fc. For example, an
-

DIGITAL ←
20 + ANALOG
+ VREF
-

GAIN [1, 10, 100, 1000] by 0.1s. The delay for IIR filters (for example Butterworth)
ANALOG(3)+
- →DIGITAL × → UNITS
22
ANALOG(3)- AAAF
INST. AMP DIGITAL FILTER LOOKUP TABLE
milliseconds
-
+
21 +
-
24
VADJ
DIGITAL ←
ANALOG
GND 34.8K [RADJ ] KAD/ADC/109/S2
51
Figure 4: Fourth of 8 independent differential ended channels

the signal source is isolated with respect to the KAM-500 (for
negative input and ground (GND) should be used to provide a kHz
pick-up. Because the bias currents are in the order of nAs Figure 5: Filter delay for 8th order Butterworth filter where
fc = 1kHz
22 Aug. 2008 | DST/U/031 169

The filter delay for the ADC/109/S2 is:
1
fC


of 100. In applications where time correlation is more

degrees
3
2.5
1.5
0.5
0
0.01 0.1 1
-0.5
-1
-1.5
-2
-2.5
-3
fin/fc
mdB
100
0. 01 0. 1 1
-100
-200
-300
-400 fin/fc
170 22 Aug. 2008 | DST/U/031

Connector pinout of the KAD/ADC/109/S2

1 SENSE(0)+ Bipolar DC voltage excitation outputs Sense line from top of bridge
4 ANALOG(0)- Differential ended analog inputs Analog input connected to internal adjust
6 SENSE(0)- Bipolar DC voltage excitation outputs Sense line from bottom of bridge
49 NC Not connected
50 NC Not connected
www.acracontrol.com
172 22 Aug. 2008 | DST/U/031

KAD/ADC/113, KAM/ADC/113
16 channel ¼-bridge A/D converter with excitation and signal conditioning for PT100
C O N T R O L
DESCRIPTION
The ADC/113 provides independent excitation for up to 16
channels and is intended for PT100 RTD type sensors. Each
channel has a separate programmable digital filter and A/D
converter. At the heart of the ADC/113 is a hard-wired
state-machine that oversamples all channels at a rate
between 48ksps and 96ksps and digitally filters any noise
above the user-programmable cutoff frequency. This is
achieved using cascaded, half-band, finite-impulse-response
(FIR) filters followed by an 8th order Butterworth IIR filter with
a default cutoff point set at one quarter of the sampling
FEATURES frequency (fc=fs/4). All signals are sampled simultaneously.
• 16 ¼-bridge (3-wire) input channels for PT100 resistance Thus, when several channels are sampled at different
temperature detector (RTD) type sensors sampling rates, at the start of an acquisition cycle all
• Simultaneous sampling 16-bit A/D for each channel channels will be aligned. The current through the RTD is
• High accuracy programmable from 1mA to 2mA in steps of 0.5µA. The
• Programmable input range and balance current per excitation current through the RTD is kept constant. As the
channel resistance changes, the voltage across the RTD (and hence
• Programmable excitation, per group of four channels as seen by the amplifier) changes linearly.
• Linear (constant current) operation A linearization table for each channel can be used to
• 8th order Butterworth filter with programmable cutoff compensate for non-linear sensors or to fine-tune gain and
frequency per channel offset.
APPLICATIONS
• Temperature measurements with RTD PT100
EXC_C(0)+
2
Inst.
amp.
ANALOG(0)
Attenuator →DIGITAL → UNITS
- ×
PT100 Gain=0.5
4th order
EXC_C(0)- AAAF
1
-7V
Programmable
current sink 1mA to
2.066mA
GND 51
DIGITAL ←
ANALOG VREF
ADC/113
28 Jul. 2008 | DST/T/055 173

Selection Paths
Airborne Data Acquisition → KAM-500 → Modules → Analog → PT100
KAD/ADC/113 CON/KAD/002/CP ADC/113 module with 52-way double-density connector
KAM/ADC/113 ACC/CON/008/04 ADC/113 module with 51-way micro-miniature connector
The ADC/113 uses power from the ±7V for excitation and therefore can not be used with CHS/04L, CHS/05F or CHS/03F. If the
maximum excitation current is drawn from each channel, then the maximum number of ADC/113s per chassis is limited to five.
Revision History
ADC/113 First release Recommended for new programs
Related Products
Module Details
ADC/013 16 channel ¼-bridge A/D converter module with excitation and signal conditioning
Document Details
TEC/NOT/023 RTDs
www.acracontrol.com
174 28 Jul. 2008 | DST/T/055

Specifications

Mass
– 92 – g
Power consumption
+5V 80 – 95 mA
+7V 25 – 30 mA
+12V 0 – 5 mA
-12V 0 – 0 mA
RTD inputs

ANALOG(x) 2 – 12000 sps
Input temperature
full scale range -200 – 660 °C
DC error Temperature averaged over 200 measurement points.
for FSR of -200°C to +660°C – – 0.27 %FSR With 1.5mA excitation current set.
for FSR of -50°C to +200°C – – 0.35 %FSR With 2mA excitation current set.
Effective number of bits 10.5 – – bits 0≤f≤0.6fc (fc: filter cutoff frequency).
Crosstalk – – -72 dB Between channels on the same module.
Analog filter cutoff
poles – – 4 –
filter cutoff -3dB – 6 – kHz
Digital filter
poles – – 8 –
filter cutoff -3dB 0.25 – 16 fs The maximum value is limited to 3kHz. (fs: sampling frequency)
Filter delay – 0.66 – fs At fc of 3kHz (See “Understanding filter delays” on page 179).
28 Jul. 2008 | DST/T/055 175


Outputs – – 16 – Applied in groups of four channels.
Output current
resolution – 0.5 – µA
compliance -5 – 5 V
short circuit current – – 2 mA Depends on user setting.
DC error
error – – 0.25 %FSR With a constant 100Ω load. Correction included within channel
reading, see DC error in “RTD inputs” table.
noise – – 0.5 °Crms Measured as subtraction of rms noise visible on read values with
and without excitation used.
176 28 Jul. 2008 | DST/T/055

acquisition system


The following table lists the setup configurations available for the KAD/ADC/113.
Manufacturer -
PartReference KAD/ADC/113 KAD/ADC/113 ACRA CONTROL part number
Settings - - -
Module-Analog-In-1.2 - - -
Channel
Settings for this channel
Temperature(15:0)
URL algorithm describing a PT100 RTD-type sensor for
Linearization No character limit Not Specified
this channel
FilterCutoff 0.25, 0.5, 1, 2, 4, 8, 16 0.25
the sampling rate.
Required excitation (in A) for the top of the bridge, in
ExcitationAmplitude 0.001 to 0.002 0.0016
2μA steps. Applied to each group of 4 channels.
The following table lists all parameters that are available for the KAD/ADC/113.
Temperature(15:0)
Celsius OffsetBinary 16:4 R[15:0] 0000:FFFF (hex)
Temperature signal data
28 Jul. 2008 | DST/T/055 177

Temperature(15:0)
An algorithm describes how data should be processed. The following are algorithms supported by the KAD/ADC/113.
Linearization
URL algorithm describing a PT100 RTD-type sensor.
PT_385.LU
PT_385_1.LU Linearization file with temperature to resistance sensor
URL PT_385.LU
PT_385_F.LU characteristics
PT_392.LU
"/><\.
178 28 Jul. 2008 | DST/T/055

Getting the most from the ADC/113 milliseconds
Lead error compensation

The feedback line ANALOG(x) carries no current. Ideally it
for lead resistances (assuming that both EXC_C(x)+ and
two wires, and the ANALOG(x) and excitation lines
gage), the error introduced will be primarily an offset error
Use two-wire operation carefully. Estimation of cable kHz
resistance should consider temperature drift over the
temperature range the cable operates (copper temperature Figure 2: Filter delay for 8th order Butterworth filter where
coefficient is approx. 0.4%/°C). Depending on the wire length fc = 1kHz
measurement. In general, it may become an issue for thinner
and longer cables.
1
Setting the range and excitation TD ≈ TA + + TButterworth8 ( f )
fC
For any temperature range required, errors can be minimized
by using as much as possible of the 0 to 500mV input range TA (analog filter delay) ≈ 0
of the A/D. For example, for a full range of -200°C to 660°C
(approximately 18Ω to 333Ω for a PT100) set the excitation to fc is the filter cutoff frequency.
1.5mA. If the current is set to a lower value this would require
bigger digital gains, with a proportional increase of Additional delay sources
measurement error.
For the best accuracy use 2mA excitation, as the card
calibration was optimized using this excitation during
manufacture. An excitation current of 2mA can be used for all
input temperature ranges within a -200°C to 400°C range, degrees
utilizing the A/D range as fully as possible.
3
2.5
Understanding filter delays 2
1.5

1
Signals sampled at the same sample rate will always be 0.5
sampled at the same time independently of how they are 0

0.01 0.1 1
stored or transmitted. (This has significant advantages for -0.5
issues such as time correlation.) However, before signals are -1
sampled they are filtered to remove noise components that -1.5

-2.5
-3
fin/fc
processing techniques. Figure 2 shows a delay for an 8th Figure 3: Delay error (ideal minus actual delay)
100
0


-300
-400 fin/fc
28 Jul. 2008 | DST/T/055 179


1 EXC_C(0)- Single ended DC current excitation outputs Excitation group 0
2 EXC_C(0)+ Single ended DC current excitation outputs Excitation group 0
3 ANALOG(0) RTD inputs
49 NC Not connected
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180 28 Jul. 2008 | DST/T/055

KAD/ADC/116/10V, KAD/ADC/116/10VNE
KAD/ADC/116/1V, KAM/ADC/116/10V
KAM/ADC/116/10VNE, KAM/ADC/116/1V
A C R A KAM-500 12-ch. accelerometer A/D converter, with current excitation and signal conditioning
ADC/116
C O N T R O L
DESCRIPTION
The ADC/116 is used to condition and digitize up to 12
accelerometer-type input channels. Each of these channels
has a constant current source and AC coupled (DC-reject)
inputs for use with integrated charge-amp piezoelectric
accelerometer devices.
that over samples all channels at a rate between 48ksps and
96ksps and digitally filters any noise above the
user-programmable cutoff frequency. This is achieved using
cascaded, half-band, finite-impulse-response (FIR) filters
FEATURES followed by an 8th order Butterworth IIR filter with a default
• 12 accelerometer input channels with DC-reject cutoff point set at one quarter of the sampling frequency
• Constant current source excitation per channel (3.6mA (fc=fs/4).
typical) All signals are sampled simultaneously. This means that even
• Simultaneous sampling 16-bit A/D for each channel when several channels are sampled at different sampling
• 0.4% FSR accuracy rates, the sample at the start of the acquisition will always be
• Programmable secondary gain and offset synchronized.
APPLICATIONS
• Accelerometer signal conditioning and digitalization
• Suitable for ICP©, Isotron©, Piezotron© and Deltatron©
sensors
• AC coupled voltage measurement
3.6mA 3.6mA
EXC(0)
36 +24V 36 +24V
1µF 1µF
ANALOG(0) 1 + ANALOG(0) 1 +
ANALOG Σ COUNTS ANALOG Σ COUNTS
1M - →DIGITAL
×
→ UNITS 1M - →DIGITAL
×
→ UNITS
GND 2 GND 2
Inst. Amp AAAF Digital filter Lookup Inst. Amp AAAF Digital filter Lookup
GAIN = 1 (ADC/116/10V) GAIN = 1
GAIN = 10 (ADC/116/1V)
GND 51 GND 51
ADC/116/10V, ADC/116/1V ADC/116/10VNE
First of 12 accelerometer channels on the ADC/116/10V, ADC/116/1V and ADC/116/10VNE
10 Jun. 2008 | DST/S/083 181

Selection Paths
Airborne Data Acquisition → KAM-500 → Modules → Analog → Accelerometer
KAD/ADC/116/10V CON/KAD/002/CP ADC/116 module ±10V input range with 52-way double-density top
connector; current excitations connected internally to analog inputs
KAD/ADC/116/10VNE CON/KAD/002/CP ADC/116 module ±10V input range with 52-way double-density top
connector; current excitations not connected internally to analog inputs but
provided on top connector as separate pin
KAD/ADC/116/1V CON/KAD/002/CP ADC/116 module ±1V input range with 52-way double-density top
KAM/ADC/116/10V ACC/CON/008/04 ADC/116 module ±10V input range with 51-way micro miniature top
KAM/ADC/116/10VNE ACC/CON/008/04 ADC/116 module ±10V input range with 51-way micro miniature top
connector; current excitations connected internally to analog inputs but
provided on top connector as separate pin
KAM/ADC/116/1V ACC/CON/008/04 ADC/116 module ±1V input range with 51-way micro miniature top
Revision History
ADC/116 First release Recommended for new programs
Related Products
Module Details
ADC/106/B 6-channel S/E accelerometer (ICP) A/D converter with signal conditioning, programmable analog
gain and up to 6kHz analog bandwidth
Document Details
TEC/NOT/012 Piezoelectric Effect and Charge Amplifiers
www.acracontrol.com
182 10 Jun. 2008 | DST/S/083

Specifications

Mass
– 87 – g
Power consumption
+5V 100 – 140 mA
±7V 0 – 0 mA
±12V 45 – 55 mA Excludes current used by excitation. As a DC/DC converter is
used, multiply excitation current by 1.1 to calculate +12V and
-12V line currents.
AC analog inputs (for ADC/116/10V and ADC/116/1V shorted internally with DC current excitation outputs)

ANALOG[11:0] 2 – 12000 sps
Input voltage
operating range -10 – 10 V ADC/116/10V, ADC/116/10VNE.
operating range -1 – 1 V ADC/116/1V.
AC gain error
gain=1 – – 0.4 %FSR For 10Hz < fin< 0.6fc.
Effective number of bits 12 – – bits For 10Hz < fin< 0.6fc.
Crosstalk – – -72 dB
Analog filters Analog filters are Butterworth.
High pass filter
poles – – 1 –
filter cutoff -3dB – 0.16 – Hz
poles – – 4 –
10 Jun. 2008 | DST/S/083 183

AC analog inputs (for ADC/116/10V and ADC/116/1V shorted internally with DC current excitation outputs)
(continued)

poles – – 8 –
Filter delay – 0.66 – ms Measured for fin = fc = 3kHz (fin: input signal frequency; fc: filter
cutoff frequency). See “Understanding filter delays” on
page 187.
Input impedance
each input to GND (off) 100 – – kΩ Module powered off (measured at 3kHz).
each input to GND (on) 100 – – kΩ Module powered on (measured at 3kHz).
Single ended DC current excitation outputs (for ADC/116/10V and ADC/116/1V shorted internally with AC
analog inputs)

Outputs – – 12 – Applied in groups of four channels.
Output current
operating range – 3.6 – mA
short circuit current – 3.6 4.9 mA
DC error
error – – 1.3 mA With a constant 2.2k load.
noise – 3 – mVrms As measured on analog input.
Output resistance – 90 – kΩ
184 10 Jun. 2008 | DST/S/083

acquisition system

Ordering options
shown below.

The following table lists the setup configurations available for the KAD/ADC/116/10V.
Manufacturer -
PartReference KAD/ADC/116/10V KAD/ADC/116/10V ACRA CONTROL part number
Settings - - -
Channel
Acceleration(11:0)
FilterCutoff 0.25, 0.5, 1, 2, 4, 8, 16 0.25
the sampling rate.
The following table lists all parameters that are available for the KAD/ADC/116/10V.
Acceleration(11:0)
Acceleration signal data
10 Jun. 2008 | DST/S/083 185

Acceleration(11:0)
"/><\.
186 10 Jun. 2008 | DST/S/083

Getting the most from the ADC/116 Understanding filter delays
Signal return path acquisition cycle and at equal intervals of time thereafter.
For channels 0 to 11 each signal is single ended so a return Signals sampled at the same sample rate will always be
(GND) for the constant current must be provided. Return path sampled at the same time independently of how they are
effects are minimized if a GND pin on the module is used. stored or transmitted. (This has significant advantages for
These channels are band-pass filtered (that is, the DC issues such as time correlation.) However, before signals are
component is also removed) so that when a sensor is first sampled they are filtered to remove noise components that
connected or powered it takes about 60 seconds to settle. might alias. The recommended cutoff point is one quarter the
Current excitation aliasing frequencies.
The ADC/116 has three ordering options; the ADC/116/10V, The KAM-500 filters signals using over-sampling signal
ADC/116/1V and ADC/116/10VNE. processing techniques. Figure 4 shows a delay for an 8th
The ADC/116/10V and ADC/116/1V have internally
connected current excitation to each ANALOG input pin as
shown in Figure 2. When internally provided current the delay for other fc values, multiply the delay by 1kHz/ fc.
excitations are to be used, the ADC/116/10V or ADC/116/1V The frequency axis then needs to be rescaled to the new fc
can reduce the number of wires inside the top-block by dividing the frequency values by 1kHz/ fc. For example, an
connector back shell. In that case EXC(x) pins are not 8th order Butterworth filter with an fc of 1kHz delays a 1kHz
connected as they are connected internally.
3.6mA
milliseconds
37 +24V
1µF
ANALOG(1) 3 +
ICP ANALOG Σ COUNTS
GND 1M - →DIGITAL
×
→ UNITS
sensor 4
Inst. Amp AAAF Digital filter Lookup
GAIN = 1 (ADC/116/10V)
GAIN = 10 (ADC/116/1V)
GND 51
ADC/116/10V, ADC/116/1V
Figure 2: Second of 12 accelerometer channels on the

ADC/116/10V and ADC/116/1V with ICP sensor connected
kHz
The ADC/116/10VNE provides current excitations, which are
not connected internally with ANALOG input pins. This allows Figure 4: Filter delay for 8th order Butterworth filter where
the use of external excitations. However, when required, fc = 1kHz
internal excitation EXC(x) are provided on the top-block, and
still can be used by connecting them to ANALOG pins as
shown in Figure 3.
1
fC
3.6mA

38 +24V
1µF
ANALOG(2)
ICP
5
1M
+ ANALOG
→DIGITAL
Σ COUNTS
→ UNITS
sensor GND 6 - ×
Inst. Amp AAAF Digital filter Lookup

GAIN = 1
GND 51
ADC/116/10VNE
Figure 3: Third of 12 accelerometer channels on the

ADC/116/10VNE with ICP sensor connected using internal
current excitation
10 Jun. 2008 | DST/S/083 187

degrees
3
2.5
1.5
0.5
0
0.01 0.1 1
-0.5
-1
-1.5
-2
-2.5
-3
fin/fc
mdB
100
0. 01 0. 1 1
-100
-200
-300
-400 fin/fc
188 10 Jun. 2008 | DST/S/083


1 ANALOG(0) AC analog inputs (connected with EXC(0) internally) EXC(0) not connected on 10VNE
18 NC Not connected
27 NC Not connected
28 NC Not connected
29 NC Not connected
30 NC Not connected
31 NC Not connected
32 NC Not connected
33 NC Not connected
34 NC Not connected
35 NC Not connected
36 EXC(0) Single ended DC current excitation outputs
48 NC Not connected
49 NC Not connected
50 NC Not connected
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190 10 Jun. 2008 | DST/S/083

KAD/ADC/117/B, KAD/ADC/117/B/E12
C O N T R O L 8 channel A/D converter with bridge signal conditioning & constant current excitation
DESCRIPTION
The ADC/117 has eight channels of signal conditioning and
data acquisition for differential voltages, strain gage and
KAD/ADC/117/B/00 PZ4274
channel, the ADC/117 provides independent constant current
excitation for up to eight channels. Each differential ended
signal has a separate programmable amplifier, filter and A/D
converter.
192ksps and digitally filters any noise above the
FEATURES user-programmable cutoff frequency. This is achieved using
• Eight full bridge or differential ended (D/E) input channels
followed by 8th order Butterworth (IIR) filter with a default
• High accuracy
cutoff point set to a quarter of the sampling frequency. All
• Programmable current excitation and input range per
signals are sampled simultaneously. Thus, when several
channel
channels are sampled at different sampling rates, at least at
the start of an acquisition cycle all channels will be aligned.
• Linear bridge operation – constant current The excitation current is programmable (0mA to 20mA in 5µA
• Short to ground on any channel does not affect others steps) and is kept constant. As the resistance changes, the
• Up to 24,000 samples per second per channel voltage across the bridge (and hence as seen by the
• Up to 6kHz bandwidth amplifier) changes linearly.
APPLICATIONS
• Bridge applications with long leads/barriers
• General purpose voltage measurement
Programmable
current source 0mA to 20mA
EXC_C(0)+
2 +10V
DIGITAL ←
ANALOG VREF
GAIN [1, 10, 100, 1000]
ANALOG(0)+
ANALOG(0)- 18 ×
INST. AMP
GND
1
GND 51
ADC/117
First of eight channels on the ADC/117
22 Aug. 2008 | DST/U/034 191

Selection Paths
KAD/ADC/117/B 8 channel A/D converter with bridge signal conditioning & constant current excitation (uses ±7V
for excitation)
KAD/ADC/117/B/E12 8 channel A/D converter with bridge signal conditioning & constant current excitation (uses ±12V
for excitation)
The ADC/117 uses power from ±7V for excitation and therefore cannot be used with the CHS/04L, CHS/05F, or CHS/03F
chassis.
ADC/117/E12 uses power from ±12V, so it can be used with the CHS/04L, CHS/05F, or CHS/03F chassis.
Revision History
ADC/117/B Improved format switching Recommended for new programs
Related Products
Module Details
ADC/118 12 channel bridge A/D converter with voltage excitation, balancing and signal conditioning
ADC/109/S1 8 channel bridge A/D converter module with voltage excitation, balancing and signal conditioning
ADC/109/S2 8 channel bridge A/D converter with voltage excitation, sense lines and signal conditioning
ADC/109/QB350 8 channel A/D converter, with voltage excitation and signal conditioning for ¼-bridge 350Ω strain
gages
Document Details
www.acracontrol.com
192 22 Aug. 2008 | DST/U/034

Specifications

Mass
– 94 – g
Power consumption ADC/117
+5V 90 – 175 mA
+7V 80 – 110 mA Excludes current used by excitation. As a DC/DC converter is
used, multiply excitation current by 2.2 to calculate +7V line
current.
-7V 0 – 0 mA
±12V 30 – 50 mA
Power consumption ADC/117/E12
+5V 90 – 175 mA
+7V 0 – 0 mA
-7V 0 – 0 mA
+12V 100 – 120 mA Excludes current used by excitation. As a DC/DC converter is
used, multiply excitation current by 1.25 to calculate +12V line
current.
-12V 30 – 50 mA

ANALOG[7:0] 2 – 24,000 sps
Input voltage
gain=1, 10, 100 – – 0.08 %FSR
gain=2, 20, 200 – – 0.14 %FSR
gain=4, 40, 400 – – 0.25 %FSR
gain=8, 80, 800 – – 0.44 %FSR
gain=1000 – – 0.3 %FSR
gain=2000 – – 0.6 %FSR
gain=4000 – – 1.2 %FSR
22 Aug. 2008 | DST/U/034 193


Crosstalk
gain=1, 10, 100 – – -60 dB
gain=1000 – – -40 dB
Common mode
poles – – 4 –
poles – – 8 –
Input resistance

Output current
resolution – 5 – µA
compliance 0 – 10 V
DC error
194 22 Aug. 2008 | DST/U/034

acquisition system

Ordering options
The PartReference is specific to each module variant. Only one variant is shown below.

The following table lists the setup configurations available for the KAD/ADC/117/B.
Manufacturer -
PartReference KAD/ADC/117/B KAD/ADC/117/B ACRA CONTROL part number
InterConnects
bridge
Settings -
Channel
Channel(7:0)
FilterCutoff 0.25, 0.5, 1, 2, 4, 8, 16 0.25
the sampling rate.
ExcitationAmplitude 0 to 0.02 0 Required excitation current (in A) for the bridge.
22 Aug. 2008 | DST/U/034 195

The following table lists all parameters that are available for the KAD/ADC/117/B.
Channel(7:0)
Analog signal data
Channel(7:0)

following are data links supported by the KAD/ADC/117/B.

Name Description
"/><\.
196 22 Aug. 2008 | DST/U/034

Getting the most from the ADC/117 milliseconds

resistors up to 10kΩ can be used. In most cases a short (0Ω)
is recommended.
kHz
Programmable
current source 0mA to 20mA
EXC_C(3)+ 8 +10V Figure 3: Filter delay for 8th order Butterworth filter where
DIGITAL ←
fc = 1kHz

ANALOG VREF
GAIN [1, 10, 100, 1000] The filter delay for the ADC/117 is:
ANALOG(3)+
24 ×
1
+ TButterworth8 ( f )
ANALOG(3)- AAAF
TD ≈ TA +
INST. AMP DIGITAL FILTER LOOKUP TABLE
GND 7
fC
GND
51 TA (analog filter delay) ≈ 0
KAD/ADC/117
Figure 2: Fourth of 8 independent differential ended channels Additional delay sources

setting the excitation to zero improves accuracy and
reduces quiescent currents of the module. of 100. In applications where time correlation is more
Using high primary gains Modelling an 8th order Butterworth filter with an IIR digital
For gains above 1000, the gain-bandwidth product of the filter causes small phase and amplitude errors as shown in
amplifier reduces the bandwidth to 1000Hz. Figure 4 and Figure 5.
degrees
Understanding filter delays 3
The KAM-500 uniquely samples all signals at the start of an 2.5
acquisition cycle and at equal intervals of time thereafter. 2
Signals sampled at the same sample rate will always be 1.5
sampled at the same time independently of how they are 1

0.5
sampled they are filtered to remove noise components that 0
0.01 0.1 1
might alias. The recommended cutoff point is one quarter the -0.5
sampling frequency, as this results in the maximum filtering of -1
aliasing frequencies. -1.5
The KAM-500 filters signals using over-sampling signal -2
processing techniques. Figure 3 shows a delay for an 8th -2.5
fin/fc
order filter where fc = 1kHz. All filters cause a delay inversely -3

22 Aug. 2008 | DST/U/034 197

mdB
100
0. 01 0. 1 1
-100
-200
-300
-400 fin/fc
198 22 Aug. 2008 | DST/U/034


2 EXC_C(0)+ Single ended DC current excitation outputs Excitation to top of bridge
17 NC Not connected
34 NC Not connected
35 NC Not connected
36 NC Not connected
37 NC Not connected
38 NC Not connected
39 NC Not connected
40 NC Not connected
41 NC Not connected
42 NC Not connected
43 NC Not connected
44 NC Not connected
45 NC Not connected
46 NC Not connected
47 NC Not connected
48 NC Not connected
49 NC Not connected
50 NC Not connected
www.acracontrol.com
200 22 Aug. 2008 | DST/U/034

KAD/ADC/118/10V, KAD/ADC/118/1V, KAD/ADC/118/100M
KAM/ADC/118/10V, KAM/ADC/118/1V, KAM/ADC/118/100M
12-ch. bridge A/D converter with voltage excitation, balancing & signal conditioning
C O N T R O L
APPLICATIONS
• High impedance bridge sensors
DESCRIPTION
The ADC/118 is used to condition and digitize up to twelve
differential-ended (D/E) analog channels. At the heart of the
ADC/118 is a hard-wired state-machine that oversamples all
channels at a rate between 48ksps and 96ksps and digitally
filters any noise above the user-programmable cutoff
FEATURES frequency.
• 12 full or ½-bridge, potentiometer or differential-ended This is achieved using cascaded, half-band,
• (D/E) input channels finite-impulse-response (FIR) filters followed by an 8th order
• Simultaneous sampling 16-bit A/D for each channel Butterworth IIR filter with a default cutoff point set at one
• High accuracy quarter of the sampling frequency (fc=fs/4). All signals are
• Programmable input range and balance current per sampled simultaneously. Thus, when several channels are
channel sampled at different sampling rates, at the start of an
• Programmable excitation per group of three channels acquisition cycle all channels will be aligned.
frequency per channel The ADC/118 is similar to the ADC/120 but includes support
• Short to ground on any channel does not affect others for channel balancing. The ADC/118 is available with three
• Up to 12,000 samples per second per channel different input ranges (±10V, ±1V, ±100mV). The input range
• Up to 3kHz bandwidth must be specified when ordering.
• Bipolar excitation and balancing before instrumentation
amplifier
EXC_V(0)+ -
1 DIGITAL ←
+ ANALOG
ANALOG(0)+
ANALOG(0)- →DIGITAL → UNITS
4 - ×
EXC_V(0)- + +
2 AMP- AMP-
DIGITAL ←
ANALOG
GND 34.8K Vadj
51
ADC/118
28 Jul. 2008 | DST/P/065 201

Selection Paths
KAD/ADC/118/10V CON/KAD/002/CP ADC/118/10V module with 52-way double density connector
KAD/ADC/118/100M CON/KAD/002/CP ADC/118/100m module with 52-way double density connector
KAM/ADC/118/10V ACC/CON/008/04 ADC/118/10V module with 51-way micro-miniature connector
KAM/ADC/118/100M ACC/CON/008/04 ADC/118/100M module with 51-way micro-miniature connector
The ADC/118 uses power from the +7V for excitation and therefore can not be used with CHS/04L, CHS/05F or CHS/03F. If the
Revision History
ADC/118/10V ADC/118 with ±10V input range Recommended for new programs
ADC/118/100M ADC/118 with ±100mV input range Recommended for new programs
Related Products
Module Details
ADC/120 12 channel bridge A/D converter module, with excitation and signal conditioning
Document Details
www.acracontrol.com
202 28 Jul. 2008 | DST/P/065

Specifications

Mass
– 92 – g
Power consumption
+5V 100 – 160 mA
+12V 30 – 50 mA
-12V 20 – 30 mA

Channel[11:0] 2 – 12000 sps
Input voltage
(ADC/118/10V)
(ADC/118/1V)
operating range -100 – 100 mV Primary gain=100
(ADC/118/100M)
gain=1 – – 0.12 %FSR
gain=2 – – 0.2 %FSR
gain=4 – – 0.3 %FSR
gain=8 – – 0.5 %FSR
ADC/118/10V, ADC/118/1V 13.5 – – bits fc≤ 1kHz and secondary gain of 1 (fc : filter cutoff frequency).
ADC/118/100M 11.3 – – bits fc≤ 1kHz and secondary gain of 1.
Crosstalk
gain=1, 10, 100 – – -72 dB
Common mode
voltage range -10 – -10 V Operational voltage range.
28 Jul. 2008 | DST/P/065 203


poles – – 4 –
poles – – 8 –
filter cutoff -3dB 0.25 – 16 fs The maximum value is limited to 3kHz.
Filter delay – 0.66 – ms Measured for fin = fc = 3kHz (fin : input signal frequency). See
Input resistance

Outputs – – 12 – Set in groups of four.
Output voltage
resolution – – 1.8 mV
DC error
noise (ADC/118/10V) – – 0.5 mVrms As measured on analog input.
noise (ADC/118/100M) – – 0.01 mVrms As measured on analog input.

Outputs – – 12 – Internally connected with corresponding ANALOG(x)- input.
Output current
DC error
204 28 Jul. 2008 | DST/P/065

acquisition system

Ordering options
shown below.

Manufacturer -
Settings -
Channel
Channel(11:0)
FilterCutoff 0.25, 0.5, 1, 2, 4, 8, 16 0.25
the sampling rate.
the bridge.
28 Jul. 2008 | DST/P/065 205

Channel(11:0)
Analog signal data
Channel(11:0)
BalanceSettings -
BalanceType CurrentShunt Not Specified Required shunt current (in A) for the bridge.

The following are data links supported by the KAD/ADC/118/10V.

Name Description
"/><\.
206 28 Jul. 2008 | DST/P/065

Getting the most from the ADC/118 resistors up to 10kΩ can be used. In most cases a short (0Ω)
is recommended.
Wiring configurations
Figures 2 to 4 show possible wiring configurations for the setting the excitation and balance to zero improves
ADC/118. accuracy and reduces quiescent currents of the
module.
EXC_V(1)+ -
Excitation setup
5 DIGITAL ←
+
ANALOG

ANALOG(1)+
ANALOG(1)- →DIGITAL → UNITS
8 - ×
Buffer AAAF Digital filter Lookup For optimal accuracy ensure each channel uses its
+ +
EXC_V(1)-
6 AMP- AMP- should be set to 0.
DIGITAL ←
GND
51
34.8K Vadj
ANALOG
KAD/ADC/118
Figure 2: Second of 12 half-bridge channels excitation voltage. For example, for 0.5Ω leads in a 350Ω
-
EXC_V(2)+
9 DIGITAL ←
+
ANALOG

ANALOG(2)+
ANALOG(2)-
12 -
→DIGITAL
×
→ UNITS
EXC_V(2)- +
AMP-
+
AMP-
10
34.8K Vadj
DIGITAL ←
ANALOG might alias. The recommended cutoff point is one quarter the
GND
51
KAD/ADC/118
Figure 3: Third of 12 potentiometer channels processing techniques. Figure 5 shows a delay for an 8th
13
-
DIGITAL ←
+ ANALOG


ANALOG(3)+
ANALOG(3)-
15
16
+
-
ANALOG
→DIGITAL
Σ
×
COUNTS
→ UNITS signal by 1ms; a filter with an fc of 10Hz delays a 10Hz signal
+ + varies with the input frequency.
14 AMP- AMP-
DIGITAL ←
ANALOG
GND 34.8K Vadj
51
KAD/ADC/118
Figure 4: Fourth of 12 differential-ended channels

28 Jul. 2008 | DST/P/065 207

milliseconds
mdB
100
0. 01 0. 1 1
-100
-200
-300
-400 fin/fc
kHz
fc = 1kHz
1
fC

degrees
3
2.5
1.5
0.5
0
0.01 0.1 1
-0.5
-1
-1.5
-2
-2.5
-3
fin/fc
208 28 Jul. 2008 | DST/P/065


4 ANALOG(0)- Differential ended analog inputs/Bridge adjust DC current outputs Analog input
17 GND KAM-500 internal ground KAM-500 internal ground
www.acracontrol.com
210 28 Jul. 2008 | DST/P/065

KAD/ADC/120/10V, KAD/ADC/120/1V, KAD/ADC/120/100M
KAM/ADC/120/10V, KAM/ADC/120/1V, KAM/ADC/120/100M
C O N T R O L 12-ch. bridge A/D converter with voltage excitation & signal conditioning
APPLICATIONS
• Strain gage signal conditioning and digitalization
DESCRIPTION
The ADC/120 is used to condition and digitize up to twelve
differential-ended (D/E) analog channels.
that oversamples all channels at a rate between 48ksps and
FEATURES 96ksps and digitally filters any noise above the
user-programmable cutoff frequency.
• 12 full or ½-bridge, potentiometer or differential-ended
(D/E) input channels This is achieved using cascaded, half-band,
• Simultaneous sampling 16-bit A/D for each channel finite-impulse-response (FIR) filters followed by an 8th order
• High accuracy Butterworth IIR filter with a default cutoff point set at one
• Programmable input range per channel quarter of the sampling frequency (fc=fs/4).
• Programmable excitation per group of three channels All signals are sampled simultaneously. Thus, when several
• 8th order Butterworth filter with programmable cutoff channels are sampled at different sampling rates, at the start
frequency per channel of an acquisition cycle all channels will be aligned.
• Up to 12,000 samples per second per channel The ADC/120 is similar to the ADC/118 but does not support
• Up to 3kHz bandwidth channel balancing. The ADC/120 is available with three
• Bipolar excitation before instrumentation amplifier different input ranges (±10V, ±1V, ±100mV). The input range
must be specified when ordering.
EXC_V(0)+ +
1 AMP
-
DIGITAL ←
ANALOG
ANALOG(0)+
4 - ×
ANALOG(0)-
EXC_V(0)- + +
2 AMP AMP-
-
GND 51
ADC/120
28 Jul. 2008 | DST/R/006 211

Selection Paths
KAD/ADC/120/100M CON/KAD/002/CP ADC/120/100M module with 52-way double density connector
KAM/ADC/120/100M ACC/CON/008/04 ADC/120/100M module with 51-way micro-miniature connector
The ADC/120 uses power from the +7V for excitation and therefore can not be used with CHS/04L, CHS/05F or CHS/3F. If the
Revision History
ADC/120/100M ADC/120 with ±100mV input range Recommended for new programs
Related Products
Module Details
ADC/118 12 channel bridge A/D converter module with voltage excitation and signal conditioning with
support for channel balancing
Document Details
www.acracontrol.com
212 28 Jul. 2008 | DST/R/006

Specifications

Mass
– 92 – g
Power consumption
+5V 100 – 160 mA
+12V 30 – 50 mA
-12V 20 – 30 mA

Channel[11:0] 2 – 12000 sps
Input voltage
(ADC/120/10V)
(ADC/120/1V)
operating range -100 – 100 mV Primary gain=100
(ADC/120/100M)
gain=1 – – 0.12 %FSR
gain=2 – – 0.2 %FSR
gain=4 – – 0.3 %FSR
gain=8 – – 0.5 %FSR
ADC/120/10V, ADC/120/1V 13.5 – – bits fc≤ 1kHz and secondary gain of 1 (fc : filter cutoff frequency).
ADC/120/100M 11.3 – – bits fc≤ 1kHz and secondary gain of 1.
Crosstalk
gain=1, 10, 100 – – -72 dB
Common mode
voltage range -10 – -10 V Operational voltage range.
28 Jul. 2008 | DST/R/006 213


poles – – 4 –
poles – – 8 –
filter cutoff -3dB 0.25 – 16 fs The maximum value is limited to 3kHz. (fs : sampling frequency)
Filter delay – 0.66 – ms Measured for fin = fc = 3kHz (fin : input signal frequency). See
Input resistance

Outputs – – 12 – Set in groups of four.
Output voltage
DC error
214 28 Jul. 2008 | DST/R/006

acquisition system

Ordering options
shown below.

Manufacturer -
Settings -
Channel
Channel(11:0)
FilterCutoff 0.25, 0.5, 1, 2, 4, 8, 16 0.25
the sampling rate.
the bridge.
28 Jul. 2008 | DST/R/006 215

Channel(11:0)
Analog signal data
Channel(11:0)

The following are data links supported by the KAD/ADC/120/10V.

Name Description
"/><\.
216 28 Jul. 2008 | DST/R/006

Getting the most from the ADC/120 resistors up to 10kΩ can be used. In most cases a short (0Ω)
is recommended.
Wiring configurations
Figures 2 to 4 show possible wiring configurations for the setting the excitation to zero improves accuracy and
ADC/120. reduces quiescent currents of the module.
Excitation setup
+
5 AMP- DIGITAL ←
ANALOG

ANALOG(1)+ excitation, to minimize the percentage error.
- ×
ANALOG(1)-
8
6
+
AMP-
+
AMP- should be set to 0.
GND
51
ADC/120
Figure 2: Second of 12 half-bridge channels

EXC_V(2)+ +
9 AMP- DIGITAL ←
ANALOG The KAM-500 uniquely samples all signals at the start of an
ANALOG(2)+
11
12
+
-
ANALOG
→DIGITAL
Σ
×
COUNTS
→ UNITS sampled at the same time independently of how they are
ANALOG(2)-
Buffer AAAF Digital filter Lookup stored or transmitted. (This has significant advantages for
+
EXC_V(2)- +
10 AMP- AMP-
GND
51
35k[Radj]
KAD/ADC/120 aliasing frequencies.
Figure 3: Third of 12 potentiometer channels processing techniques. Figure 5 shows a delay for an 8th
+ The frequency axis then needs to be rescaled to the new fc
13 AMP- DIGITAL ←

ANALOG

ANALOG(3)+
15 +
-
ANALOG
→DIGITAL
Σ
×
COUNTS
→ UNITS
16
ANALOG(3)-
+ +
14 AMP- AMP-
GND
51
ADC/120
Figure 4: Fourth of 12 differential-ended channels

28 Jul. 2008 | DST/R/006 217

milliseconds
mdB
100
0. 01 0. 1 1
-100
-200
-300
-400 fin/fc
kHz
fc = 1kHz
1
fC

degrees
3
2.5
1.5
0.5
0
0.01 0.1 1
-0.5
-1
-1.5
-2
-2.5
-3
fin/fc
218 28 Jul. 2008 | DST/R/006


www.acracontrol.com
220 28 Jul. 2008 | DST/R/006

KAD/CDC/002, KAM/CDC/002
A C R A KAM-500 CDC/002
C O N T R O L 24 channel current to digital convertor
APPLICATIONS
• Current measurements
DESCRIPTION
The CDC/002 is used to condition and digitize up to 24
differential-ended current channels.
At the heart of the CDC/002 is a hard-wired state-machine
FEATURES achieved using cascaded, half-band, decimate by 2, 15-tap,
finite-impulse-response (FIR) filters with 32-bit coefficients.
• 24 current input channels
• Simultaneous 14-bit sampling for each channel All signals are sampled simultaneously. Secondary gain and
• Input range ±20mA offset are achieved digitally according to specified range.
• Accuracy: ±0.4% for input range ±20mA
• Programmable range and filter cutoff for each channel
• For use with 4-20mA transmitters
Inst. amp. 2nd order

+ 1
+ ANALOG Σ COUNTS
ANALOG(0) 50Ω →DIGITAL → UNITS
- - ×
2
3dB=1.1kHz AAAF Fs>8.5kHz Digital filter Lookup
GND 51
CDC/002
First of 24 channels on the CDC/002
18 Oct. 2006 | DST/R/017 221

Selection Paths
Airborne Data Acquisition → KAM-500 → Modules → Analog → 4-20mA Currentloop
KAD/CDC/002 CON/KAD/002/CP CDC/002 module, with 52-way double density module top connector.
KAM/CDC/002 ACC/CON/008/04 CDC/002 module, with 51-way micro-miniature module top connector.
Revision History
CDC/002 24 channel current to digital convertor. Recommended for new programs
In this data sheet CDC/002 refers to both the KAD and KAM version of the module.
Related Products
Module Details
KSM-500 This module is supported by the KSM-500 suite of software tools.
Document Details
www.acracontrol.com
222 18 Oct. 2006 | DST/R/017

Specifications
Channels: 24
Inputs: Range: ±20mA

dc. response:±0.4% for input range ±20mA, ±1% for input range 4-20mA
ac. response:Digital filter -6dB @ quarter the sampling rate
Delay due to filter is 2.5/Fc (typ) Fc = cutoff frequency.
Passband attenuation of digital filter is ±0.2dB typ. (f<Fc/5)
AAAF second order cutoff at 1.10kHz (±15%)
RF first order cutoff at 43kHz (±20%)
Input impedance:140Ω(typical) continuous input
Overcurrent protection:±30mA max.
Sampling restrictions: Maximum sampling rate per channel:17.5kHz

Minimum sampling rate: 1Hz
Maximum aggregate sampling rate:420kHz
While the sampling rate for each channel can be individually set each must be a power of two
times any other (¼, ½, 1, 2, 4, and so on).
Name No limit to characters MySignal Range can be set to any sub-range of ±20mA wider than 10mA. Any
range narrower than 16mA may have error larger than 1% FSR.
Base Unit mA mA
maximum -20 to +20 +20
minimum -20 to +20 -20
=

Manufacturer
part reference KAD/CDC/002 KAD/CDC/002 ACRA CONTROL part number.
Settings
Getting the most from the CDC/002 of data when processing (especially in real-time) it may be
worth considering setting the same cutoff point on all
If the signal source is isolated from the KAM-500, a common- channels even if the sampling rates are different. Sensor
mode resistance between the negative input and ground used for this module must be capable of driving 150Ω, i.e. if
(GND) can be used to reduce common-mode noise pick-up. the highest current produced by sensor is 20mA, it must be
Because the bias currents are in the order of nAs, resistors capable of outputting 3V.
up to 10kΩ can be used. Digital filters, as used in the CDC/
002, cause no phase distortion. However, like all low-pass
filters they cause a delay inversely proportional to the cutoff
point (delay=2.5/Fc). However to simplify the time-correlation
18 Oct. 2006 | DST/R/017 223

Connector pinout of KAD/CDC/002

1 ANALOG(0)+ Current In Analog input
2 ANALOG(0)- Current In Analog input
www.acracontrol.com
224 18 Oct. 2006 | DST/R/017

KAM/CDC/101/6k, KAM/CDC/101/300
A C R A KAM-500 CDC/101
C O N T R O L 4-channel charge-to-digital converter for piezoelectric devices
DESCRIPTION
The CDC/101 is used to digitize signals from charge-based
sensors such as piezoelectric devices used for
accelerometers. Each is independent and consists of a
charge-to-voltage converter (charge-mode amplifier) followed
by a second order high pass filter, sixth order low pass filter,
programmable gain amplifier, a second order low pass filter
and a separate A/D as illustrated in the diagram below.
At the heart of the CDC/101 is a hard-wired state-machine
192ksps, and digitally filters any noise above the user
FEATURES programmable cutoff frequency. This is achieved using
• 4-channel charge-to-digital converter for piezoelectric
devices
• ±3% @ 3Hz - 1kHz for 6kHz version; ±3% @ 3Hz - 100Hz followed by an 8th order Butterworth IIR filter with a default
for 300Hz version (all sources over temperature) cutoff point set at a quarter of the sampling frequency.
• Programmable gains Unlike most KAM-500 modules the input connectors are SMC
• High bandwidth and programmable filters (0.5Hz to 6kHz) (10-32) sockets for each channel.
• 2nd order Butterworth high pass filter cutoff at 0.5Hz
• Standard SMC (10-32) socket for each channel
• 6th order Butterworth LPF cutoff @ 300Hz or 6kHz
APPLICATIONS
• Force and pressure measurement using piezoelectric
devices
G=1, 10
CHARGE
→ VOLTS
2ND ORDER 6 POLE LPF AAAF

HPF
ANALOG Σ COUNTS
→DIGITAL × → UNITS
CDC/101
First of four independent charge channels
10 Jun. 2008 | DST/S/032 225

Selection Paths
Airborne Products → KAM-500 → Modules → Analog → Piezo
KAM/CDC/101/6k ACC/CON/016 CDC/101 module with low-pass filter cutoff set at 6kHz; ACC/CON/016
must be ordered separately
KAM/CDC/101/300 ACC/CON/016 CDC/101 module with low-pass filter cutoff set at 300Hz; ACC/CON/016
must be ordered separately
Revision History
CDC/101 4-channel charge-to-digital converter for piezoelectric devices Recommended for new
with 2-pole high-pass filter, 6-pole low-pass filter and 2-pole programs
active anti-aliasing filter
CDC/001/C 4-channel charge-to-digital converter for piezoelectric devices Not recommended for new
with single pole high-pass filter and 2-pole active anti-aliasing programs
filter
Related Products
Module Details
ACC/CON/016 3.05m (10 ft.) cable; this part must be ordered separately
CDC/001/C 4-channel charge-to-digital converter for piezoelectric devices with single pole high-pass filter and
2-pole low-pass filter
Document Details
TEC/NOT/012 Piezoelectric effect and charge amplifiers
www.acracontrol.com
226 10 Jun. 2008 | DST/S/032

Specifications

Mass
– 66 – g
bare connector – – 2.6 mm
Power consumption
+5V 130 – 135 mA
±7V 0 – 0 mA
+12V 42 – 64 mA
-12V 30 – 50 mA
Charge converter analog inputs

ANALOG 2 – 24000 sps
Input charge
operating range (Gp=1) -10 – 10 nC Primary gain=1
operating range (Gp=10) -1 – 1 nC Primary gain=10
AC gain error
gain=1, 10 – – 3 %FSR Within 3Hz - 1kHz for 6kHz version; within 3Hz - 100Hz for
300Hz version.
300Hz version.
300Hz version.
300Hz version.
gain=1 12.5 – – bits For 10Hz<fin<fc (fin: input signal frequency, fc: filter cutoff
frequency)
gain=10 10.5 – – bits For 10Hz<fin<fc
Crosstalk
gain=1 – – -72 dB For fin<200Hz on 300Hz version; fin<1kHz on 6kHz version.
gain=10 – – -60 dB For fin<200Hz on 300Hz version; fin<1kHz on 6kHz version.
10 Jun. 2008 | DST/S/032 227

Charge converter analog inputs (continued)

High pass filter
poles – – 2 –
filter cutoff -3dB – 0.5 – Hz
Low pass filter
poles – – 6 –
filter cutoff -3dB – 300 – Hz For 300Hz version.
– 6 – kHz For 6kHz version.
poles – – 2 –
filter cutoff -3dB – 1.5 – kHz For 300Hz version.
– 24 – kHz For 6kHz version.
poles – – 8 –
Filter delay See “Understanding filter delays” on page 231.
300Hz – 22.2 – ms Where fin = fc = 100Hz for 300Hz version.
6kHz – 2.08 – ms Where fin = fc = 1kHz for 6kHz version.
Input resistance
each input to GND (off) 140 – – kΩ Module powered off.
each input to GND (on) 5 – – MΩ Module powered on.
228 10 Jun. 2008 | DST/S/032

Setting up the CDC/101
acquisition system

Ordering options
The PartReference settings are specific to each module variant. Only one variant is shown below.

The following table lists the setup configurations available for the KAM/CDC/101/300.
Manufacturer -
PartReference KAM/CDC/101/300 KAM/CDC/101/300 ACRA CONTROL part number
Settings - - -
Channel
Channel(3:0)
FilterCutoff 0.25, 0.5, 1, 2, 4, 8, 16 0.25
the sampling rate.
The following table lists all parameters that are available for the KAM/CDC/101/300.
Channel(3:0)
Coulomb OffsetBinary 16:4 R[15:0] 0000:FFFF (hex)
Charge signal data
10 Jun. 2008 | DST/S/032 229

Channel(3:0)
RangeMaximum -10e-9 to 10e-9 10e-9 -
RangeMinimum -10e-9 to 10e-9 -10e-9 -
"/><\.
230 10 Jun. 2008 | DST/S/032

Getting the most from the CDC/101 Accuracy
It is important to use the shielded coaxial cable type as Accuracy is quoted as 3% FSR from all sources over the
recommended by the sensor manufacturer. For an operating temperature range. This value includes potential
introduction to piezoelectric sensors, See “Introducing force gain error of a module (lower than ±2%) and the high pass
and pressure measurement using piezoelectric devices” and low pass analog filter roll-off characteristics within the
(TEC/NOT/012). specified bandwidth. In addition, the potential gain variations
caused by limited component accuracies were included in the
Understanding filter delays accuracy specification.
The KAM-500 uniquely samples all signals at the start of an Figure 3 and Figure 4 show possible gain characteristics
acquisition cycle and at equal intervals of time thereafter. (expressed in a gain error sense) of analog filters used on
Signals sampled at the same sample rate will always be CDC/101/300 and CDC/101/6K modules. They contain
sampled at the same time independently of how they are multiple plots, each simulated with varied component values
stored or transmitted. (This has significant advantages for within tolerance (a Monte Carlo analysis of the circuit). They
issues such as time correlation.) However, before signals are can be used to approximate potential gain error for input
sampled they are filtered to remove noise components that signals from outside the specified bandwidth.
Gain error (%)

the delay for other fc values, multiply the delay by 1kHz/fc.
by dividing the frequency values by 1kHz/fc. For example, an
Frequency (Hz)
Figure 3: Analog filters on CDC/101/300 - magnitude varia-

tions chart
milliseconds
Gain error (%)
kHz

fc = 1kHz
The filter delay for the CDC/101 is: Frequency (Hz)
Figure 4: Analog filters on CDC/101/6k - magnitude variations

1
TD ≈ TA + + TButterworth8 ( f ) chart
fC
Calibration of the module gain within the pass band is
TA (analog filter delay) ≈ 2200µs for CDC/101/300 possible, where required to achieve higher accuracy for
certain applications. Contact ACRA CONTROL for details.
TA (analog filter delay) ≈ 80µs for CDC/101/6k
10 Jun. 2008 | DST/S/032 231

Connector pinout of the CDC/101
There are four SMC (10-32) connectors, one for each channel labelled 0 to 3.
Ch 0 Ch 1 Ch 2 Ch 3
Figure 5: SMC connectors
www.acracontrol.com
232 10 Jun. 2008 | DST/S/032

KAD/LDC/101/10K, KAD/LDC/101/5K,
KAD/LDC/101/2.5K, KAM/LDC/101/10K,
KAM/LDC/101/5K, KAM/LDC/101/2.5K
LDC/101
4 channel LVDT/RVDT to digital convertor
APPLICATIONS
• LVDT/RVDT sensors
• Compatible with LVDT sensors from Schaevitz
DESCRIPTION
The LDC/101 is used for signal conditioning and digitized
data acquisition from four LVDT or RVDT devices. In addition
to the measurement channels, the LDC/101 provides
independent excitation for four channels. Each signal has
independent signal conditioning and filtering.
The LDC/101 can be used with external excitation sources
FEATURES (2kHz to 20kHz, or with the independent onboard excitation
• Four independent Linear Variable Differential Transformer outputs, which are capable of driving up to 25mA each.
(LVDT)/Rotational Variable Differential Transformer At the heart of the LDC/101 is a hard-wired state-machine
(RVDT) input channels that over-samples all channels at a rate between 96ksps and
• 16-bit simultaneous sampling on all channels 192ksps and digitally filters any noise above the user
• Accuracy: 1.25%(FSR) programmable cutoff frequency. This is achieved using
• Programmable gain and offset per channel cascaded, half-band, decimate by 2, 15 tap,
• 8th order Butterworth filter with programmable cutoff finite-impulse-response (FIR) filters with 32-bit coefficients
frequency per channel followed by an 8th order Butterworth IIR filter with a default
• Short-to-ground on any channel does not affect others cutoff point set at 25% of the sampling frequency.
• Supports ratiometric values from 0.2 to 0.8
• Ratiometric conversion compensates for variations in All signals are sampled simultaneously. This means that even
excitation. when several channels are sampled at different sampling
• Four independent excitation channels (2.5kHz x 4, 5kHz x rates, the sample at the start of the acquisition will always be
4 or 10kHz x 4@3Vrms) synchronized. Care must be taken when monitoring aircraft
• Up to 24,000 samples per second per channel control signals due to the low input impedance when
powered off.
+ 1
EXT_V(0) 2.5kHz
- 2
+
3 +
B(0)
- 4 -
A
_ ANALOG COUNTS
B
+ LPF
5 +
A(0)
- 6 -
GND 51
LDC/101
First of four channels on the LDC/101
18 Dec. 2008 | DST/P/048 233

Selection Paths
Airborne Data Acquisition → KAM-500 → Modules → Analog → LVDT/RVDT
KAD/LDC/101/10K CON/KAD/002/CP LDC/101/10K module, with 52-way double density module top connector
KAD/LDC/101/5K CON/KAD/002/CP LDC/101/5K module, with 52-way double density module top connector
KAM/LDC/101/10K ACC/CON/008/04 LDC/101/10K module, with 51-way micro-miniature module top connector
KAM/LDC/101/5K ACC/CON/008/04 LDC/101/5K module, with 51-way micro-miniature module top connector
Revision History
LDC/101/10k 4-channel LVDT/RVDT to digital convertor with 10kHz Recommended for new programs
excitation.
LDC/101/5k 4-channel LVDT/RVDT to digital convertor with 5kHz Recommended for new programs
excitation.
LDC/101/2.5k 4-channel LVDT/RVDT to digital convertor with 2.5kHz Recommended for new programs
excitation.
In this data sheet LDC/101 refers to both the KAD and KAM version of the module.
Related Products
Module Details
LDC/001 2-channel LVDT/RVDT to digital convertor
Document Details
TEC/NOT/014 Linear variable differential transformers
www.acracontrol.com
234 18 Dec. 2008 | DST/P/048

Specifications

Mass
– 96 – g
Power consumption
+5V 75 – 92 mA
±7V – – – mA
+12V 70 – 85 mA Each LDC/101 consumes 85mA on the ±12V supply. If more
-12V 62 – 75 mA than one LDC/101 is used with low impedance LVDTs, it is
possible to exceed the 1.3A limit from the ±12V supply.
Therefore, the number and choice of modules that can reside
within the same chassis as the LDC/101 may be limited.
Linear Variable Differential Transformer (LVDT) inputs

Inputs – – 4 – Pairs of units A/B.
Sampling rate While the sampling rate can be set individually, each input must
have a power of two times any other (¼, ½,...2, 4).
Channel [3:0] 0.001 – 24 ksps
Input voltage
operating range 1 – 3.5 Vrms
frequency range 2 – 20 kHz
A/B ratio 0.2 – 0.8 – Usable full scale range.
mechanical frequency – – 1 kHz Maximum measurable mechanical frequency.
overvoltage protection -10 – 10 V Voltages outside this range can damage input.
Total error (at phase) When operating in series opposed mode, where phase shift
±0o -0.5 – 0.5 %FSR between the primary winding and the secondary winding
degrade the performance. Ratiometric calculation accuracy at
±5o -0.6 – 0.6 %FSR
room temperature, with an A/B ratio of 0.8.
±7o -0.8 – 0.8 %FSR
±10o -1.25 – 1.25 %FSR
Effective number of bits 13.5 – – bits
Crosstalk -60 – – dB
Common mode
(fc : filter cutoff frequency).
Low-pass analog filter
poles – – 4 –
18 Dec. 2008 | DST/P/048 235

Linear Variable Differential Transformer (LVDT) inputs (continued)

poles – – 8 –
filter cutoff -3dB 0.25 – 16 fs The maximum value is limited to 6kHz (fs: sampling frequency)
aliasing to 0.1dB bandwidth – – -72 dB
Filter delay – 0.33 – ms Where fin = fc = 6kHz (fin: input signal frequency). See “Getting
the most from the LDC/101” on page 238.
Input resistance
between inputs (on) – 200 – kΩ Module powered off.
each input to GND (on) – 200 – kΩ Module powered off.
Bipolar AC voltage excitation outputs

Output voltage
amplitude – 3.5 – Vrms
frequency (LDC/101/2.5K) – 2.5 – kHz Frequency is set depending on ordering option and is the same
for all channels.
frequency (LDC/101/5K) – 5 – kHz
frequency (LDC/101/10K) – 10 – kHz
AC error
amplitude -10 – 10 % Measurement is accuracy; is not affected by excitation accuracy.
frequency -7.5 – 7.5 %
236 18 Dec. 2008 | DST/P/048

For LDC/101/10k, LDC/101/5k & LDC/101/2.5k channels Analog(0) to Analog(3)

Name No limit to characters MySignal
Base Unit Volt Volt
maximum -10 to +10 +10
minimum -10 to +10 -10

Manufacturer
part reference KAD/LDC/101 KAD/LDC/101 ACRA CONTROL part number.
slot 3 to N 3 DAU slot the module fits into. First module goes into slot 3, where N
is the number of user-slots +2 in the DAU.
Settings
18 Dec. 2008 | DST/P/048 237

Getting the most from the LDC/101 Schaevitz MHR250, this is 4.7 times less output than series
opposed mode.
For the four-wire configuration, it is important to use the
zero-phase frequency as specified by the LVDT/RVDT When using the LDC/101 in half-bridge mode, this reduction
manufacturer. Phase errors up to ±15° and ratio variations in useful range should be considered.
can cause gain/offset errors, so for different sensor types it is The gain can be set via the maximum and minimum range
recommended that gain and offset corrections be calculated values. If S V/V/mil is the LVDT sensitivity and ±d is the
by calibrating one of each sensor type. For half-bridge maximum deflection, the gain required is:
configuration, the phase shift is not important.
If the signals to A and B are greater than 3Vrms, they should 10
be attenuated using an external resistor divider. If possible G = ----------------------------
d • S • 12.5
both signals should be attenuated by the same amount
(because the LDC/101 calculates the ratio between them). So for d = 0.1 inc, s = 2.4 mV/V/mil and gain = 3.33
When choosing the excitation frequency, the system Offset can be used to shift the NULL voltage point of the
bandwidth and the cutoff frequency should be a maximum of
LVDT/RVDT.
1/10 the excitation frequency. For example, if the deflection
being measured has a bandwidth of Fm=200Hz, the Overall measurement accuracy depends on the
excitation frequency should be at least 2kHz and the LVDT device used. For example, Schaevitz E100
sampling rate should be approximately: has ±0.75% FSR when used at 2.5kHz, but ±1%
with Fexc=5kHz.
Fs=(Fm/0.66) x 4 = 1212Hz

+
7
EXT_V(0)
- 8
2.5kHz
External excitation
+
9 +
B(1)
- 10 - stored or transmitted. (This has significant advantages for
A
_
B
ANALOG
→DIGITAL
COUNTS
→ UNITS
A(1)
+
11 + sampled they are filtered to remove noise components that
- 12
-
GND 51
KAD/LDC/101

Figure 1: Second of four independent LVDT channels with
external reference used (½-bridge configuration)
When operating in half bridge mode the movement of the the delay for other fc values, multiply the delay by 1kHz/ fc.
core changes the inductance of the secondary coils changing The frequency axis then needs to be rescaled to the new fc
the voltage across each of them, acting as a potential divider. by dividing the frequency values by 1kHz/ fc. For example, an
milliseconds
Figure 2: Voltage seen by the LDC/101
The voltage seen by the LDC/101 is:

Va/Vb * 12.5 kHz
When the bridge is balanced, the voltage seen is 6.25V. The

LVDT’s sensitivity determines the range about this balance
fc = 1kHz
point, this can be less than ±1V. For example ±1.36V with a
238 18 Dec. 2008 | DST/P/048

The filter delay for the LDC/101 is:
1
fC
18 Dec. 2008 | DST/P/048 239

Connector pinout of KAD/LDC/101

1 EXT_V(0)+ Bipolar AC voltage excitation outputs LVDT excitation output; 1st channel
2 EXT_V(0)- Bipolar AC voltage excitation outputs LVDT excitation output; 1st channel
3 B(0)+ Linear Variable Differential Transformer (LVDT) inputs LVDT reference input; 1st channel
4 B(0)- Linear Variable Differential Transformer (LVDT) inputs LVDT reference input; 1st channel
5 A(0)+ Linear Variable Differential Transformer (LVDT) inputs LVDT input; 1st channel
6 A(0)- Linear Variable Differential Transformer (LVDT) inputs LVDT input; 1st channel
7 EXT_V(1)+ Bipolar AC voltage excitation outputs LVDT excitation output; 2nd channel
8 EXT_V(1)- Bipolar AC voltage excitation outputs LVDT excitation output; 2nd channel
9 B(1)+ Linear Variable Differential Transformer (LVDT) inputs LVDT reference input; 2nd channel
10 B(1)- Linear Variable Differential Transformer (LVDT) inputs LVDT reference input; 2nd channel
11 A(1)+ Linear Variable Differential Transformer (LVDT) inputs LVDT input; 2nd channel
12 A(1)- Linear Variable Differential Transformer (LVDT) inputs LVDT input; 2nd channel
15 EXT_V(2)+ Bipolar AC voltage excitation outputs LVDT excitation output; 3rd channel
16 EXT_V(2)- Bipolar AC voltage excitation outputs LVDT excitation output; 3rd channel
17 B(2)+ Linear Variable Differential Transformer (LVDT) inputs LVDT reference input; 3rd channel
18 B(2)- Linear Variable Differential Transformer (LVDT) inputs LVDT reference input; 3rd channel
19 A(2)+ Linear Variable Differential Transformer (LVDT) inputs LVDT input; 3rd channel
20 A(2)- Linear Variable Differential Transformer (LVDT) inputs LVDT input; 3rd channel
21 EXT_V(3)+ Bipolar AC voltage excitation outputs LVDT excitation output; 4th channel
22 EXT_V(3)- Bipolar AC voltage excitation outputs LVDT excitation output; 4th channel
23 B(3)+ Linear Variable Differential Transformer (LVDT) inputs LVDT reference input; 4th channel
24 B(3)- Linear Variable Differential Transformer (LVDT) inputs LVDT reference input; 4th channel
25 A(3)+ Linear Variable Differential Transformer (LVDT) inputs LVDT input; 4th channel
26 A(3)- Linear Variable Differential Transformer (LVDT) inputs LVDT input; 4th channel
29 NC Not connected
30 NC Not connected
31 NC Not connected
32 NC Not connected
33 NC Not connected
34 NC Not connected
35 NC Not connected
36 NC Not connected
37 NC Not connected
38 NC Not connected
39 NC Not connected
40 NC Not connected
41 NC Not connected
42 NC Not connected
43 NC Not connected
44 NC Not connected
45 NC Not connected
46 NC Not connected
47 NC Not connected
48 NC Not connected
49 NC Not connected
50 NC Not connected
www.acracontrol.com
240 18 Dec. 2008 | DST/P/048

KAD/MDC/002, KAM/MDC/002
A C R A KAM-500 MDC/002
C O N T R O L 2 x 64 channel multiplexing A/D converter, with external temperature compensation
DESCRIPTION
The MDC/002 is designed to interface two multiplexed analog
signals such as those from analog pressure scanners.
The MDC/002 has two analog inputs and two constant
current RTD inputs for differential voltages/external
temperature measurements. In addition to measurement
channels, the MDC/002 provides a 6-bit address bus for an
external multiplexer. The MDC/002 sequentially addresses
the 64 channels of an external multiplexer and measures the
voltage on the multiplexer’s outputs. The interval within all
FEATURES external channels that are addressed is programmable in the
• Two differential-ended (D/E) input channels with range of 5.12ms to 128ms.
programmable gain In a typical operation the multiplexer’s address is set to
• Two constant current RTD inputs with programmable “0000002” at the start of an acquisition cycle. 80µs later, both
excitation multiplexer’s outputs are sampled. The address is then
• Accuracy: ±0.25% (FSR) for ranges ±10V, ±5V and ±2.5V incremented to “0000012” and multiplexer outputs are
• 16-bit simultaneous sampling on both channels sampled again. After 5.12ms the address reads “1111112”
• Support for 64-channel external multiplexer with 5V or 12V
and all 128 channels from both inputs have been sampled.
CMOS logic
• Short to ground on one channel does not affect other Two four wire constant current RTD inputs are provided to
channel monitor the temperature of the external multiplexer. The
• ±12V power supply lines for pressure scanners constant current excitation for PT100 and PT500 sensors can
• Up to 12,500 samples per second per multiplexer be programmed to 0.5mA or 2.5mA.
The external temperature channels are continuously sampled
APPLICATIONS and a running average maintained. These values are used to
generate an additional gain and offset for each of 64 external
• An interface to analog pressure scanners
channels per input.
Programmable current
source 0.5 to 2.5mA
EXC(0)+
43
+
9 ANALOG
EXT_TEMP(0) →DIGITAL
- 26
44 Lookup Lookup
EXC(0)-
6
ADDR_12V[5:0]
+ Buffer
Σ X
10 ANALOG
EXT_MUX(0) →DIGITAL
27
-
Offset Gain RAM
Gain=1,2,4
GND 51
MDC/002
First of 64 channels on the MDC/002
3 Nov. 2008 | DST/N/150 241

Selection Paths
Airborne Data Acquisition → KAM-500 → Modules → Analog → Pressure Scanners
KAD/MDC/002 CON/KAD/002/CP MDC/002 module with 52-way double density module top connector
KAM/MDC/002 ACC/CON/008/04 MDC/002 module with 51-way micro-miniature module top connector
Revision History
MDC/002 2 x 64 channel multiplexing A/D converter with external Recommended for new programs
temperature compensation
In this data sheet MDC/002 refers to both the KAD and KAM version of the module.
Related Products
Module Details
MDC/001 8 x 64 channel external multiplexing A/D converter
Document Details
TEC/NOT/023 Resistance temperature detectors
www.acracontrol.com
242 3 Nov. 2008 | DST/N/150

Specifications
Channels: 2 inputs from 64-channel multiplexers

2 temperature sensors from multiplexer
2 constant current excitation outputs
Input considerations Mux input:

Range: ±10V, ±5V ±2.5V
Type: D/E
Input impedance: 1GΩ (on)/>50k (off)
Protection: ±40V
Accuracy: 0.25% total error from all sources for ranges ±10V, ±5V, ±2.5V and
secondary gain of 1
PT100, PT500 input:
Accuracy: ±1.2°C/±2.4°C, for the range -30°C to +85°C
Output considerations Mux Address out:

12V CMOS'1' 12V (5mA)
'0' 0V (-5mA)
5V CMOS'1' 5V (5mA)
'0' 0V (-5mA)
Excitation current source: 0.5mA or 2.5mA (each source is independently programmable)
Accuracy: ±5μA for 0.5mA and ±10μA for 2.5mA
Short circuit protection: Indefinite to ground
Sampling restrictions The maximum sampling rate per channel is 195Hz
3 Nov. 2008 | DST/N/150 243

For 128 parameters from EXT_MUX(0) to EXT_MUX(1) (2 x 64 channels)

Name No limit to characters MyPressure
Base Unit Pascal Pascal
maximum -4.5 to +4.5 +4.5
minimum -4.5 to +4.5 -4.5
For 2 parameters from EXT_TEMP(0) to EXT_TEMP(1)

Name No limit to characters MyTemperature
Base Unit Celsius Volt
maximum -200 to +660 +85
minimum -200 to +660 -40
For 128 parameters (2 Mux x 64 channels)

Manufacturer
part reference KAD/MDC/002 KAD/MDC/002 ACRA CONTROL part number.
Settings
maximum -55 to +125 +85
temperature
minimum -55 to +125 -40
temperature
excitation current 0.5mA 0.5
Instrument
address delay 80 to 2000 80 Address delay in µs.
mux count to float 0.00010701
voltage
conversion
Mux
calibration URL string Calibration file to be selected for Scanivalve pressure scanner.
maximum input -10 to +10 -10
volts
minimum input -10 to +10 +10
volts
temperature PT100, PT500 PT500 XidML references:
sensor PT100 RTD (degrees to mV)
PT500 RTD (degrees to mV)
244 3 Nov. 2008 | DST/N/150

Getting the most from the MDC/002
To get the best results for temperature compensation, it is
recommended not to use a wider PT100 (PT500)
temperature range than necessary.
If the external multiplexers are powered from the MDC/002,
some limitations apply. Care must be taken not to short any of
the power supply outputs together because it will stop all the
modules in the chassis working due to loss of supply on the
backplane. Also, not all the slots in all chassis have identical
current driving capability (contact ACRA CONTROL for
details).
The 5V CMOS address lines may be used with the ZOC
series from Scanivalve Corporation (contact ACRA
CONTROL for details of compatible scanners). The 5V
CMOS output may be used for changing the mode of
operation for the pressure scanner. If a 32/16/8 or 4-channel
external multiplexer is used, the MSB of the address lines
should be used to select channels as this maximizes the
settling time (for example, with 16 channels, connect the four
MSBs and read multiplexer channels 3, 7, 11, and so on to
63).
If the external multiplexers are single-ended, the negative
input of each of the analog inputs to the MDC/002 should be
connected to KAM-500 ground (GND).
ACRA CONTROL recommends that KAM-500 GND and
equipment GND be connected through a resistor in the order
of 100Ω to avoid possible common mode signal appearance.
Because sampling is sequential, all channels must be
sampled at the same rate.
3 Nov. 2008 | DST/N/150 245

Connector pinout of the KAD/MDC/002

1 ADDR_12V(0) Discrete S/E Out Channel address line (12V CMOS) LSB, active when pin 1 active
2 ADDR_12V(1) Discrete S/E Out Channel address line (12V CMOS) Active when pin 1 active
6 ADDR_12V(5) Discrete S/E Out Channel address line (12V CMOS) MSB, active when pin 1 active
7 GND KAM-500 internal ground LSB, active when pin 1 active
9 EXT_TEMP(0)+ Analog D/E In Analog input From multiplexer
10 EXT_MUX(0)+ Analog D/E In Analog input From multiplexer
11 EXT_TEMP(1)+ Analog D/E In Analog input From multiplexer
12 EXT_MUX(1)+ Analog D/E In Analog input From multiplexer
26 EXT_TEMP(0)- Analog D/E In Analog input From multiplexer
27 EXT_MUX(0)- Analog D/E In Analog input From multiplexer
28 EXT_TEMP(1)- Analog D/E In Analog input From multiplexer
29 EXT_MUX(1)- Analog D/E In Analog input From multiplexer
36 ADDR_5V(0) Discrete S/E Out Channel address line (5V CMOS) LSB, active when pin 36 active
41 ADDR_5V(5) Discrete S/E Out Channel address line (5V CMOS) MSB, active when pin 41 active
43 EXC(0)+ PT100+ excitation for sensor 0
44 EXC(0)- PT100- excitation for sensor 0
45 EXC(1)+ PT100+ excitation for sensor 1
46 EXC(1)- PT100- excitation for sensor 1
49 EXC_12+ Excitation source +12V for excitation
50 EXC_12- Excitation sink -12V for excitation
www.acracontrol.com
246 3 Nov. 2008 | DST/N/150

KAD/MDC/103, KAM/MDC/103
A C R A KAM-500 MDC/103
C O N T R O L 2 x 64 channel multiplexing A/D converter, with polynomial temperature compensation
APPLICATIONS
• Interfacing to pressure scanners e.g. ESP-16HD,
ESP-32HD, ESP-48SL or ESP-64HD from Esterline
Pressure Systems
DESCRIPTION
The MDC/103 interfaces to multiplexed analog signals such as
those from analog pressure scanners like the ESP-16HD,
ESP-32HD, ESP-48SL or ESP-64HD from Esterline. If
support for the ESP-DTC scanner series is required, contact
ACRA CONTROL.
FEATURES
The MDC/103 has two analog inputs for differential voltages
• Support for two 64-channel external multiplexers with 5V or and for external temperature measurements. In addition to
12V CMOS logic measurement channels, the MDC/103 provides a 6-bit
• Supports Esterline Pressure Systems ESP pressure address for the external multiplexer.
scanners
• Provides fourth-order polynomial correction of scanner The MDC/103 sequentially addresses up to 64 channels from
output voltage an external multiplexer and measures the voltage on the
• Two differential-ended (D/E) pressure input channels with outputs of pressure scanner multiplexers. The interval within
programmable gain which all external pressure channels are addressed is
• Two D/E temperature input channels with programmable automatically set from the range 3.2ms to 512ms. For sample
gain cycles longer than 512ms, the addressing cycle stays at the
• 16-bit simultaneous sampling maximum value.
• Up to 20,000 sps aggregate on all multiplexed channels
• ±12V power supply lines
• Calibrated 5V excitation with sense lines
SENSE_+5V(0) 23
EXC_+5V(0) -
24
+ + +5V
SENSE_AGND(0) 25
SENSE_AGND_C(0) 37
SENSE_AGND_C(0) 39
AGND 26 2 3 3 4
P=C 0+C 1•V+C 2•V +C3 •V +C 4•V
+ Inst. Amp
19 +
EXT_MUX(0) ANALOG V P
- →DIGITAL
- 20
Gain=1,2,4,8
(C0:C4)
6 6
ADDR_12V[5:0] Driver ADDRESS LOOKUP
+ Inst. Amp
21 + ANALOG Σ T
EXT_TEMP(0) →DIGITAL
22 - ×
-
Gain=5.16
EXC_+12V(0) 41
EXC_-12V(0) 42
GND 51 MDC/103
First pair of analog and temperature inputs with the multiplexer address bus
3 Sep. 2008 | DST/S/052 247

Selection Paths
Airborne Data Acquisition → KAM-500 → Modules → Analog → Pressure Scanners
KAD/MDC/103 CON/KAD/002/CP MDC/103 module with 52-way double density module top connector
KAM/MDC/103 ACC/CON/008/04 MDC/103 module with 51-way micro-miniature module top connector
Revision History
MDC/103 First release Recommended for new programs
In this data sheet MDC/103 refers to both the KAD and KAM version of the module.
Related Products
Module Details
MDC/001 8 x 64 channel external multiplexing A/D converter
MDC/002 2 x 64 channel multiplexing A/D converter, with Scanivalve support
Document Details
www.acracontrol.com
248 3 Sep. 2008 | DST/S/052

Specifications

Mass
– 72 – g
Power consumption
+5V 40 – 50 mA
-7V 40 – 50 mA
Multiplexed analog inputs

Sampling rate
EXT_MUX[1:0]± – – 20 ksps
Input voltage
primary gain=1 -10 – 10 V
primary gain=2 -5 – 5 V
primary gain=4 -2.5 – 2.5 V
primary gain=8 -1.25 – 1.25 V
Includes pressure linearization and interpolation for scanner's
temperatures between manufacturer calibration points.
gain=1, 2, 4, 8 – – 0.25 %FSR
gain=1, 2, 4, 8 13 – – bits fin < fs/4 where fs = 312.5Hz
(fin : input signal frequency; fs : sampling frequency)
Crosstalk
gain=1, 2, 4, 8 – – -80 dB fin < fs/4 where fs = 20kHz
Common mode
rejection ratio 80 – – dB fin < fs/4 where fs = 20kHz
Input resistance
3 Sep. 2008 | DST/S/052 249

Temperature inputs

Sampling rate
EXT_TEMP[1:0]± – – 312.5 sps
Input temperature
DC error -0.25 – 0.25 %FSR Temperature averaged over 200 samples. Does not include
sensor accuracy.
Effective number of bits 12 – – bits 0 ≤ f < fc (fc : filter cutoff frequency)
Crosstalk – – -60 dB Between channels on the same module.
Ripple ratio
0 ≤ f < fc – – 0.5 dB Operational voltage range.
poles – 2 – –
filter cutoff -3dB – 500 – Hz
filter delay – 450 – µs
Input resistance
Single ended DC voltage excitation outputs +5V

Outputs
EXC_+5V[1:0] – – 2 –
Output voltage
operating range – 5 – V
DC error
error -10 – 10 mV Considered only with SENSE_5V and SENSE_AGND lines used
across the load.
noise – – -84 dB
Output resistance – 0.1 – Ω Considered only with SENSE_5V and SENSE_AGND lines used
across the load.
Single ended DC voltage excitation outputs +12V

Outputs
EXC_+12V[1:0] – – 2 –
Output voltage
operating range – 12 – V
compliance – – 120 mA
short circuit current – – – mA There is no short circuit protection on this output.
short circuit duration – – 0 s
DC error
error -200 – 200 mV
250 3 Sep. 2008 | DST/S/052

Single ended DC voltage excitation outputs -12V

Outputs
EXC_-12V[1:0] – – 2 –
Output voltage
operating range – -12 – V
short circuit current – – – mA There is no short circuit protection on this output.
DC error
error -200 – 200 mV
Multiplexer address outputs 12V

Signaling rate
ADDR_12V(0) – – 10 kbps
ADDR_12V(1) – – 5 kbps
ADDR_12V(2) – – 2.5 kbps
ADDR_12V(3) – – 1.25 kbps
ADDR_12V(4) – – 0.625 kbps
ADDR_12V(5) – – 0.3125 kbps
Output voltage
logic ‘1’ 10 – – V Sourcing 1mA.
Multiplexer address outputs 5V

Signaling rate
ADDR_5V(2) – – 2.5 kbps
ADDR_5V(3) – – 1.25 kbps
ADDR_5V(4) – – 0.625 kbps
ADDR_5V(5) – – 0.3125 kbps
Output voltage
logic ‘1’ 3 – – V Sourcing 1mA.
3 Sep. 2008 | DST/S/052 251

For 2x64 parameters from EXT_MUX(0) and EXT_MUX(1)

Name No limit to characters MyPressure
Base unit Pascal Pascal
maximum No limits 82737.09 Defaults are set for ±12PSI scanner FSR.
minimum No limits -82737.09 Defaults are set for ±12PSI scanner FSR.
Data format Offset binary Offset binary
Size in bits 4 to 16 16
Offset No limits 0 Re-zero offset. See “Getting the most from the MDC/103” on
page 253.
For parameters from MUX_TEMP(0) and MUX_TEMP(1)

Base unit Celsius Volt
maximum -40 to 85 85
Size in bits 4 to 16 16
This module uses the X-Module-ExternalMultiplexer-Controller XidML schema. (See http://www.xidml.org).
For 2 x 64 parameters from EXT_MUX(0) and EXT_MUX(1)

Manufacturer
part reference KAD/MDC/103 KAD/MDC/103 ACRA CONTROL part number.
This module uses the X-Module-ExternalMultiplexer-Controller XidML schema. (See http://www.xidml.org).
For 2 x 64 parameters from EXT_MUX(0) and EXT_MUX(1)

AlgorithmSet
input No limitations Calibration.txt URL of calibration file for each pressure scanner. The URL of each
calibration file must be specified.
output No limitations Rezero.txt URL of rezero file. If not specified re-zero offset calibration won't be
applied.
252 3 Sep. 2008 | DST/S/052

Getting the most from the MDC/103 Esterline ESP family
In typical operation, the multiplexer’s address is set to 15 pin connector
SENSE_+5V(1)
“0000002” at the start of an acquisition cycle. If for example, +VS SENSE 32
14
80µs later, the multiplexer output is sampled, the address +VS EXC_+5V(1)
-
8
increments to “0000012” and the output is sampled again. SENSE_AGND(1)
33
+ + +5V
34
After 5.12ms the address reads “1111112” and all 64 channels GND SENSE SENSE_AGND_C(1)
47
13 SENSE_AGND_C(1)
have been sampled. Because sampling is sequential, all 10
GND 49
AGND
channels are sampled at the same rate. VO 35
11
A0 + Inst. Amp
Voltage input is provided to monitor the temperature output of 1
A1
EXT_MUX(1) 28 +
29 -
the external multiplexer. The external temperature channel is 2
A2
-
Gain=1,2,4,8
3
sampled with the first pressure channel and then digitally 4
A3 ADDR_12V[5:0]
A4 Driver
filtered. The temperature read from the pressure scanner 5
A5
12 +
determines the selection of a fourth order polynomial for each Vt EXT_TEMP(1)
30 +
Inst. Amp
of 64 external channels; this is used to linearize pressure 15

- 31 -
+12 VDC EXC_+12V(1) Gain=5.16
according to a calibration file provided by the manufacturer of 6
EXC_-12V(1)
45
-12 VDC
the pressure scanner. 7
GND
46
VS RTN * 51
9
Wiring
*leave not connected
The 5V voltage excitation (EXC_+5V(x)) for the scanner
bridges and temperature sensor is provided individually for
each channel. EXC_+5V(x) has a SENSE_+5V(x) line to Figure 2: Wiring the ESP pressure scanner to the second
correct for voltage drops across the excitation line. A channel of the MDC/103
SENSE_+5V(x) line must be connected to the +VS SENSE
output of the scanner. EXC_+5V(x) also contains correction Pressure scanners guarantee the best accuracy only when
for voltage drop across the AGND connection between the regular re-zero calibration of aging offset is carried out. In
module and pressure scanner. To compensate for this drop, order to compensate for this, the system can be programmed
connect the SENSE_AGND(x) line to the GNDSENSE output without re-zero files specified and readings from each
multiplexed channel treated as new re-zero offsets. Then the
of the scanner.
module can be programmed with those new values, and any
The ESP-16HD, ESP-32HD, ESP-48SL and ESP-64HD aging error will be excluded from measurement. The re-zero
pressure scanners must be used with the address lines file syntax is a multiple line file with a single floating point
ADDR_12V(x). They are to be shared if two pressure re-zero offset value per line. There are up to 64 values to be
scanners are connected. entered. The first line is related with multiplexed address 0,
the following lines contain re-zero offsets for consecutive
For the ESP family of scanners, positive input of the pressure
addresses. Offsets are to be entered in Pascals.
channel must be connected with Vo output of the scanner and
negative input with GNDSENSE output. To prevent degraded system performance, use individual
shielded cables for analog signals, excitations, and address
For the temperature channel, positive input must be lines.
connected to VT and negative to GNDSENSE. To minimize the
wiring between the pressure scanner and the module, Power consumption
connect the GND_SENSE_COPY(x) pins to EXT_MUX(x)-
and EXT_TEMP(x)- (if the scanner output voltage is In cases where high-current pressure scanners are used
referenced to GND, such as for the ESP family of scanners). (such as the ESP-64HDs), current consumption from the
MDC/103 excitation lines will exceed the value normally
Figure 2 shows a wiring example for connecting an ESP assigned to the +12V, -12V and +7V (used for EXC_+5V(x))
pressure scanner to the MDC/103. Note, VS RTN (pin 9) of the lines of the occupied slot. This is acceptable as long as the
pressure scanner must not be connected for correct total current drawn from all occupied slots does not exceed
operation of the scanner with the MDC/103. that of the KAM-500 chassis power supply.
If the maximum current of the KAM-500 chassis power supply
is exceeded, use an external ±12V and +5V power supply.
The GND of an external power supply must be connected
with the GND of the chassis. To prevent degradation of
system accuracy, it is crucial to have a stable and accurate
+5V supply.
Contact ACRA CONTROL if an external power supply will be
used.
3 Sep. 2008 | DST/S/052 253

Connector pinout of the KAD/MDC/103
1 ADDR_12V(0) Multiplexer address outputs 12V LSB of address to pressure scanner. CMOS 0 to 12
volt logic levels.
2 ADDR_12V(1) Multiplexer address outputs 12V
6 ADDR_12V(5) Multiplexer address outputs 12V MSB of address to pressure scanner. CMOS 0 to 12
volt logic levels.
9 GND KAM-500 digital ground
10 ADDR_5V(0) Multiplexer address outputs 5V LSB of address to pressure scanner. TTL 0 to 5 volt
logic levels.
15 ADDR_5V(5) Multiplexer address outputs 5V MSB of address to pressure scanner. TTL 0 to 5 volt
logic levels.
16 NC Not connected
18 NC Not connected
19 EXT_MUX(0)+ Multiplexed analog inputs From scanner pressure Mux output
20 EXT_MUX(0)-
21 EXT_TEMP(0)+ Temperature inputs From scanner temperature output
22 EXT_TEMP(0)-
23 SENSE_+5V(0) See “Getting the most from the MDC/103” on page 253.
24 EXC_ +5V(0) Single ended DC voltage excitation outputs +5V See “Getting the most from the MDC/103” on page 253.
25 SENSE_AGND(0) See “Getting the most from the MDC/103” on page 253.
26 AGND
27 NC Not connected
28 EXT_MUX(1)+ Multiplexed analog inputs From scanner pressure output
29 EXT_MUX(1)-
30 EXT_TEMP(1)+ Temperature inputs From scanner temperature output
31 EXT_TEMP(1)-
32 SENSE_+5V(1) See “Getting the most from the MDC/103” on page 253.
33 EXC_ +5V(1) Single ended DC voltage excitation outputs +5V See “Getting the most from the MDC/103” on page 253.
34 SENSE_AGND(1) See “Getting the most from the MDC/103” on page 253.
35 AGND KAM-500 analog ground
36 NC Not connected
37 SENSE_AGND_C(0) See “Getting the most from the MDC/103” on page 253.
38 NC Not connected
40 AGND Not connected
41 EXC_+12V(0) Single ended DC voltage excitation outputs +12V See “Getting the most from the MDC/103” on page 253.
42 EXC_-12V(0) Single ended DC voltage excitation outputs -12V See “Getting the most from the MDC/103” on page 253.
43 NC Not connected
44 AGND KAM-500 analog ground
45 EXC_+12V(1) Single ended DC voltage excitation outputs +12V See “Getting the most from the MDC/103” on page 253.
46 EXC_-12V(1) Single ended DC voltage excitation outputs -12V See “Getting the most from the MDC/103” on page 253.
48 NC Not connected
50 NC Not connected
52 CHASSIS
www.acracontrol.com
254 3 Sep. 2008 | DST/S/052

KAD/SDC/001, KAM/SDC/001
A C R A KAM-500 SDC/001
2-channel synchro-to-digital converter
C O N T R O L
DESCRIPTION
The SDC/001 is a dual synchro-to-digital converter module.
An electronic Scott-T is used to condition the synchro inputs.
There are four parameters available from the SDC/001: these
are the angle and the angular velocity for both channels.
The linearization table for each parameter can be used to
compensate for non-linearity or to fine tune gain and offset.
FEATURES
• Two independent synchro input channels
• Measures angle and angular velocity
• 16-bit simultaneous sampling on both channels
• Accuracy: ±5 minutes of arc
• 11.8V/400Hz inputs
APPLICATIONS
• Angle measurement (flap position)
• Compatible with synchro from Endevco
S1_SDC(0)
1
S2_SDC(0)
2
S3_SDC(0) SYNCHRO Angle COUNTS
3 → DIGITAL → UNITS
REF_SDC(0)+
6
Lookup
REF_SDC(0)-
7 tables
Velocity ANALOG COUNTS

Lookup
tables
SDC/001
First of two channels on the SDC/001
25 Sep. 2008 | DST/N/064 255

Selection Paths
Airborne Data Acquisition → KAM-500 → Modules → Analog → Synchro Converter
KAD/SDC/001 CON/KAD/002/CP SDC/001 module with 52-way double density top connector
KAM/SDC/001 ACC/CON/008/04 SDC/001 module with 51-way micro-miniature top connector
Revision History
SDC/001 2-channel synchro-to-digital converter Recommended for new programs
In this data sheet SDC/001 refers to both the KAD and KAM version of the module.
Related Products
Module Details
SDC/002/90V 90V/400Hz inputs with KAM connector
Document Details
TEC/NOT/011 Synchros
www.acracontrol.com
256 25 Sep. 2008 | DST/N/064

Specifications

Mass
– 70 – g
Power consumption
+5V 100 – 155 mA
±7V 0 – 0 mA
±12V 0 – 0 mA
Synchro inputs

Inputs – – 2 – Two channels of synchro inputs consisting of three wired
connections per channel.
Sampling rate
S1/S2/S3_SDC[1:0] – – 24000 sps
Input voltage
operating range – – 11.8 Vrms
S1/S2/S3_SDC[1:0]
S1/S2/S3_SDC[1:0]
Input angle/velocity range
angle -180 – 180 ° Angle in degrees.
angular velocity -450 – 450 °/s Angular velocity in degrees per second.
Accuracy
S1/S2/S3_SDC[1:0] -5 – 5 ‘ Angular error in arc minutes.
Input resistance
between inputs – 52 – MΩ Module powered off/on.
S1/S2/S3_SDC[1:0]
each inputs to GND – 34 – kΩ Module powered off/on.
S1/S2/S3_SDC[1:0]
25 Sep. 2008 | DST/N/064 257

Synchro reference inputs

Inputs – – 2 – Two channels of synchro reference inputs (differential ended).
Input voltage
operating range 2 – 35 Vrms Differential ended reference inputs.
REF_SDC[1:0]
REF_SDC[1:0]
Input frequency range
REF_SDC[1:0] 360 400 5000 Hz
Input resistance See Environmental Qualifications Handbook.
between inputs – 120 – MΩ Module powered off/on.
REF_SDC[1:0]
each inputs to GND – 60 – kΩ Module powered off/on.
REF_SDC[1:0]
258 25 Sep. 2008 | DST/N/064

Setting up the SDC/001
For angle channels Analog(0) to Analog(1)

Base Unit ° °
maximum -180 to +180 +180
minimum -180 to +180 -180
For angular velocity channels Analog(0) to Analog(1)

Base Unit °/s °/s
maximum -450 to +450 +450
minimum -450 to +450 -450

Manufacturer
part reference KAD/SDC/001 KAD/SDC/001 ACRA CONTROL part number.
Settings
offset value 0 to 360 0
25 Sep. 2008 | DST/N/064 259

Connector pinout of the KAD/SDC/001

1 S1_SDC(0) Synchro inputs Synchro input S1; first channel
6 REF_SDC(0)+ Synchro reference inputs Synchro reference; first channel
7 REF_SDC(0)- Synchro reference inputs Synchro reference; first channel
10 S1_SDC(1) Synchro inputs Synchro input S1; second channel
15 REF_SDC(1)+ Synchro reference inputs Synchro reference; second channel
16 REF_SDC(1)- Synchro reference inputs Synchro reference; second channel
19 NC Not connected
20 NC Not connected
21 NC Not connected
22 NC Not connected
23 NC Not connected
24 NC Not connected
25 NC Not connected
26 NC Not connected
27 NC Not connected
28 NC Not connected
29 NC Not connected
30 NC Not connected
31 NC Not connected
32 NC Not connected
33 NC Not connected
34 NC Not connected
35 NC Not connected
36 NC Not connected
37 NC Not connected
38 NC Not connected
39 NC Not connected
40 NC Not connected
41 NC Not connected
42 NC Not connected
43 NC Not connected
44 NC Not connected
45 NC Not connected
46 NC Not connected
47 NC Not connected
48 NC Not connected
49 NC Not connected
50 NC Not connected
51 NC Not connected
www.acracontrol.com
260 25 Sep. 2008 | DST/N/064

KAD/TDC/001/10K, KAD/TDC/001/2K2
A C R A KAM-500 TDC/001
16-ch. A/D converter with excitation & sig. conditioning for 2K2 & 10K thermistors
C O N T R O L
DESCRIPTION
The TDC/001 is used to digitize up to 16 thermistor channels.
At the heart of the TDC/001 is a hard-wired state-machine
achieved using cascaded, half-band, decimate by 2, 15-tap,
finite-impulse-response (FIR) filters with 32-bit coefficients.
The module provides independent excitation for up to 16
channels. The excitation is set at 5V by a precision voltage
reference. Each channel has a separate programmable
digital filter and A/D. A lookup table for each channel can be
FEATURES used to fine-tune gain and offset.
• 16 ¼-bridge (2-wire) input channels for 2.2kΩ or 10kΩ
All signals are sampled simultaneously. This means that even
thermistor type sensors when several channels are sampled at different sampling
rates, the sample at the start of the acquisition will always be
• 14-bit A/D sampling for each channel
synchronized.
• Less than 0.25% FSR error (5V)
• Programmable filter cutoff for each channel
• 5V excitation from a precision voltage reference
• Up to 1.875 kHZ bandwidth
APPLICATIONS
• Temperature measurements using thermistors
+ Voltage
reference
- (5V)
5k
ANALOG(0) +
1
+
ANALOG Σ COUNTS
Thermistor →DIGITAL → UNITS
- ×
Inst amp 2nd order Digital Lookup

G=1 filter filter tables
ANALOG(0) - 2
1.21k
GND 51
TDC/001
First of 16 independent quarter-bridge channels
15 Dec. 2008 | DST/M/056 261

Selection Paths
Airborne Data Acquisition → KAM-500 → Modules → Analog → Thermistor
KAD/TDC/001/10K CON/KAD/002/CP TDC/001 module for 10K thermistor with 52-way double density top
connector
Revision History
TDC/001/10k 16 channel A/D converter with excitation & signal Recommended for new programs
conditioning for 10K thermistors
TDC/001/2K2 16 channel A/D converter with excitation & signal Recommended for new programs
conditioning for 2K2 thermistors
Related Products
Module Details
TDC/002 15 channel thermocouple A/D converter with reference compensation
TDC/004 12 channel analog to digital converter with excitation and signal conditioning for PT100s
Document Details
www.acracontrol.com
262 15 Dec. 2008 | DST/M/056

Specifications
Channels: 16
Excitation Outputs: Excitation voltage is fixed at 5V±5mV

Short circuit protection:Indefinite to GND
Inputs Range: TDC/001/10K 285 to 121kΩ (-50°C to 125°C)

TDC/001/2K2 77Ω to 151kΩ (-50°C to 125°C)
dc. response: Total error after offset adjust: ±1°C at 25°C1
Drift: ±0.05°C per degree change in chassis temperature (total drift ±4°C)
ac. response: Digital filter -6dB @ a quarter the sampling rate
Delay due to digital filter is 2.5/Fc typ. (Fc =cutoff frequency)
Passband attenuation of digital filter is ±0.2dB typ. (f<Fc/5)
Second order anti-aliasing filter at 1800Hz ± 15%
Input impedance:10kΩ ANALOG+
50Ω ANALOG-
Overvoltage protection:±40V
RTD type 2K2 at 25°C, temperature range -50°C to +125°C

10K at 25°C, temperature range -50°C to +125°C
Mechanical: Can be placed in any user-slot in any combination
Sampling restrictions: The maximum sampling rate per channel is 26,000 samples per second
Channels must be sampled at the same rate or a binary multiple of the lowest sample rate
While the sampling rate for each channel can be individually set each must be a power of two
times any other (¼, ½, 1, 2, 4, and so on).
1. Refers to the temperature of the KAM-500 chassis.
15 Dec. 2008 | DST/M/056 263

Setting up the TDC/001

Base Unit Celsius Celsius
maximum -50 to +125 +125
minimum -50 to +125 -50
Shunt 0 to 1000 0 Long runs of cable may have a resistance measuring several ohms.
resistance This will cause a temperature measurement to have a negative
offset, which will be particularly apparent when measuring high
temperatures. Inputting the lead resistance allows this to be
removed during lookup calculation.

Manufacturer
part reference KAD/TDC/001 KAD/TDC/001 ACRA CONTROL part number.
Settings
thermistor lookup qua10k.lu qua10k.lu Lookup table for thermistors is installed to
C:\KSM\tmistor\rvt\qua10k.lu
264 15 Dec. 2008 | DST/M/056

Getting the most from the TDC/001
Digital filters, as used in the TDC/001, cause no phase
distortion. However, like all low-pass filters they cause a
delay inversely proportional to the cutoff point (delay=
2.25/Fc). The recommended cutoff point is one quarter the
sampling frequency as this means the maximum filtering of
aliasing frequencies. However to simplify the time-correlation
of data when processing (especially in real-time) it may be
worth considering setting the same cutoff point on all
channels even if the sampling rates are different.
For an excitation of ±5V the following table applies to a typical
sensor.
Temperature Rt (Ω) Vo=10V x Rt/(Rt+10k)
-50 400.600 9.756
-25 96.150 9.058
0 28.480 7.401
25 10.000 5.000
50 4.045 2.880
75 1.840 1.554
100 0.923 0.845
125 0.504 0.480
15 Dec. 2008 | DST/M/056 265

Connector pinout of the KAD/TDC/001

1 ANALOG(0)+ Thermistor inputs Analog input
2 ANALOG(0)- Thermistor inputs Analog input
33 NC Not connected
34 NC Not connected
35 NC Not connected
36 NC Not connected
37 NC Not connected
38 NC Not connected
39 NC Not connected
40 NC Not connected
41 NC Not connected
42 NC Not connected
43 NC Not connected
44 NC Not connected
45 NC Not connected
46 NC Not connected
47 NC Not connected
48 NC Not connected
49 NC Not connected
www.acracontrol.com
266 15 Dec. 2008 | DST/M/056

KAD/TDC/002/D
A C R A KAM-500 TDC/002
15 channel thermocouple analog-to-digital converter with reference compensation
C O N T R O L
DESCRIPTION
The TDC/002 is used to digitize up to 15 thermocouple
channels and the compensation block temperature. (The
compensation block refers to the double-density connector.)
The compensation block temperature is a signal indicating
the temperature of the compensation block.
This signal is digitized and put to 2 x 65536 point linearization
tables. One is used to produce a compensation value to add
or subtract from the other 15 channels (this table is T/C type
specific) and the other is used to scale the compensation
block temperature between -55°C and 125°C.
FEATURES
The compensation offset is removed from each of the T/C
• 15 thermocouple (T/C) input channels
channels. Each T/C channel is then linearized using a 65536
• ±5°C accuracy for K-type T/C point linearization table specific to the thermocouple type
• Compensation block temperature measurement
selected. Finally, all channels are scaled to the selected
• Programmable T/C type (per module)
range.
• Digital reference junction compensation
• Up to 512 samples per second per channel
• Up to 40Hz bandwidth
APPLICATIONS
• Temperature measurements
COUNTS
→ UNITS
TEMP Σ
→ DIGITAL
×
COUNTS
→ UNITS
+
2
ANALOG Σ COUNTS
ANALOG(0) →DIGITAL Σ → UNITS
×
- 3
Inst. amp.
GND 51
TDC/002
Compensation channel plus first of 15 T/C channels
28 Jul. 2008 | DST/P/059 267

Selection Paths
Airborne Data Acquisition → KAM-500 → Modules → Analog → Thermocouple
KAD/TDC/002/D CON/KAD/002/SR TDC/002/D with 52-way double density module compensation sensor
connector. Module offers wider input range (-270 to +1372ºC for K type
T/C)
Revision History
TDC/002/D Any sampling rate up to 512Hz is allowed Recommended for new programs
TDC/002/C Improved accuracy, sampling rate must be an integer Not recommended for new programs
division of 512Hz
TDC/002/B 15 channel thermocouple A/D converter with reference Not recommended for new programs
compensation, sampling rate must be an integer division
of 512Hz
Related Products
Module Details
TDC/001 16-channel A/D converter with excitation and signal conditioning for 2K2 or 10K thermistors
TDC/002/D/10M TDC/002/D/10M with 52-way double density module compensation sensor connector. Module
offers higher accuracy but narrower input range (-270 to +255ºC for K type T/C)
Document Details
TEC/NOT/010 Thermocouples
www.acracontrol.com
268 28 Jul. 2008 | DST/P/059

Specifications

Mass
– 94 – g
CON/KAD/002/SR data sheet.
Power consumption
+5V 100 – 160 mA
±7V 0 – 0 mA
±12V 10 – 60 mA
Cold junction

Inputs – – 1 – From sensor provided on top-block connector.
JUNCTION 1 – 512 sps
Input temperature
DC error – – 1.5 %FSR Temperature averaged over 200 samples.
Effective number of bits 9.5 – – bits
poles – – 1 –
filter cutoff -3dB – 0.25 – fs (fs : sampling frequency)
aliasing to fc – – -30 dB (fc : filter cutoff frequency)
28 Jul. 2008 | DST/P/059 269

Thermocouple inputs

ANALOG[14:0] 1 – 512 sps
Input temperature
full scale range K-type T/C -270 – 1372 °C
full scale range B-type T/C 0 – 1820 °C
full scale range J-type T/C -210 – 1200 °C
full scale range E-type T/C -270 – 1000 °C
full scale range R-type T/C -50 – 1767 °C
full scale range S-type T/C -50 – 1767 °C
full scale range T-type T/C -270 – 400 °C
full scale range T99-type T/C -59 – 229 °C
DC error – – 5 °C Temperature averaged over 200 samples for thermocouple
K-type measured for FSR of -270°C to 1372°C.
Effective number of bits 11 – – bits
Common mode
rejection ratio 80 – – dB Applies within the above common mode voltage range,
0≤fin<1Hz (fin : input signal frequency)
60 – – dB Applies within the above common mode voltage range, fin>1Hz
poles – – 1 –
filter cutoff -3dB – 40 – Hz ±15% error.
poles – – 1 –
filter cutoff -3dB 0.125 – 2 fs 0.125, 0.25, 0.5, 1, 2 of fs (fs : sampling frequency)
Filter delay – 7 – ms Where fin = fc = 32Hz. See “Understanding filter delays” on
page 273.
Input resistance
between inputs (off) 200 – – kΩ Module powered off. Within ±100mV input range.
between inputs (on) 1 – – MΩ Module powered on. Within ±100mV input range.
each input to GND (off) 25 – – kΩ Module powered off.
each input to GND (on) 100 – – kΩ Module powered on.
270 28 Jul. 2008 | DST/P/059

Setting up the TDC/002
For TDC/002/D channels Analog(0) to Analog(14)

maximum -270 to 1372 1372 Dependent on thermocouple type.
minimum -270 to 1372 -270 Dependent on thermocouple type.
For channel Junction

Name No limit to characters MyJunctionTemp
maximum -55 to 125 125
For channel Status

Name No limit to characters MyStatus R(15) 1 indicates the junction temperature is outside the selected
input range.
R[14:0] 1 indicates that the corresponding TC channel input is
outside the selected input range. R(14) maps onto TC15, R(0) maps
onto TC1.
Base Unit Unitless Unitless
maximum 000016 to FFFF16 1 Temperature on channel analog (0) exceeded selected input range.
minimum 000016 to FFFF16 0 Temperature on channels analog(0) to (14) and channel Junction
are within selected input range.
Data Format Bit vector Bit vector
28 Jul. 2008 | DST/P/059 271


Manufacturer
part reference KAD/TDC/002/D KAD/TDC/002/D ACRA CONTROL part number.
Settings
filter cutoff 0.125, 0.25, 0.5, 1, 2 0.25 Required cutoff point for the filter is the chosen value multiplied by
the user sampling frequency. 0.25 is recommended as any higher
linearization B, E, J, K, R, S, T, K XidML references:
T99 Type B thermo-couple (degrees to mV)
Type E thermo-couple (degrees to mV)
Type J thermo-couple (degrees to mV)
Type K thermo-couple (degrees to mV)
Type R thermo-couple (degrees to mV)
Type S thermo-couple (degrees to mV)
Type T thermo-couple (degrees to mV)
Type T99 thermo-couple (degrees to mV)
272 28 Jul. 2008 | DST/P/059

Getting the most from the TDC/002 milliseconds

The TDC/002 does not require external bias returns, and
provides the return for bias currents internally via a 100kΩ
resistor from each input to ground.
Accuracy
The accuracy of the TDC/002 is specified for K-type T/Cs. It
is also met for J and E-type T/Cs. For thermocouples with a
lower emf response (R, S and T type), 0.9% accuracy is
achieved.
kHz
Mating connector
Figure 3: Filter delay for 1st order IIR filter where fc = 1kHz
Because the compensation sensor is in the connector, only
the recommended mating connectors should be used (see The filter delay for the TDC/002 is:
“Ordering Information” on page 268).
TD ≈ TA + TFirtsorder ( f )
TA (analog filter delay) ≈ 3.1ms
Figure 2: TDC/002 module with connector

processing techniques. Figure 3 shows a delay for a 1st order
filter where fc = 1kHz. All filters cause a delay inversely
by dividing the frequency values by 1kHz/ fc. For example, a
1st order filter with an fc of 1kHz delays a 1kHz signal by
0.125ms; a filter with an fc of 10Hz delays a 10Hz signal by
12.5ms. The delay for IIR filters (for example Butterworth)
28 Jul. 2008 | DST/P/059 273

Conector pinout of the KAD/TDC/002

2 ANALOG(0)+ Thermocouple inputs
3 ANALOG(0)- Thermocouple inputs
8 NA Not available Pin replaced with sensor
274 28 Jul. 2008 | DST/P/059

KAD/VDC/001, KAM/VDC/001
A C R A KAM-500 VDC/001
2 channel CVSD voice-to-digital converter
C O N T R O L
DESCRIPTION
The VDC/001 is a dual audio-to-digital converter module.
At the core of the module is a Delta-modulator where the
Delta size depends on the rate of change. This is referred to
as Continuously Variable Slope Delta (CVSD) modulation.
This Delta-modulator outputs a serial stream to a
serial-to-parallel converter, the output of which is regularly
read over the backplane. For a detailed description of this
type of audio encoding, refer to the IRIG-106 standard,
chapter 5.
A tone output is also available that can be connected to a
FEATURES channel, for link indication or calibration/verification.
• Two differential ended (D/E) audio input channels
• Programmable sampling rates (8kbps to 64kbps)
• Fully IRIG-106 Chapter 5 compatible
• 500Hz tone output for link indication or
calibration/verification
• Programmable word length, for example 16 bits@32kbps=
2k words per second
APPLICATIONS
• Cockpit voice monitoring
10k 22pF
+
1 ANALOG SERIAL→
ANALOG(0) 100pF → SERIAL PARALLEL
- 2
22pF
Inst. amp.
TONE SERIAL→
5 ANALOG
GND 51
VDC/001
First of two independent audio channels and the tone output
25 Sep. 2008 | DST/N/065 275

Selection Paths
Airborne Data Acquisition → KAM-500 → Modules → Analog → Voice
KAD/VDC/001 CON/KAD/002/CP VDC/001 with 52-way double density top connector
KAM/VDC/001 ACC/CON/008/04 VDC/001 with 51-way micro-miniature top connector
Revision History
VDC/001 2 channel CVSD voice-to-digital converter Recommended for new programs
In this data sheet VDC/001 refers to both the KAD and KAM version of the module.
Related Products
Module Details
KSMv2 This module is supported by the KSMv2 suite of software tools
Document Details
TEC/NOT/015 CVSD Modulation of Audio Signals
www.acracontrol.com
276 25 Sep. 2008 | DST/N/065

Specifications

Mass
– 64 – g
Power consumption
+5V 80 – 140 mA
±7V 0 – 0 mA
+12V 15 – 30 mA Excludes current used by tone outputs.
-12V 10 – 20 mA Excludes current used by tone outputs.
Differential ended audio inputs

ANALOG[1:0] 8 – 64k sps
Input voltage
operating range (Gp=1) -30 – 8 dB Primary gain=1; 0dB = 489 mV
Analog filter
passband 300 3400 kHz
Input resistance
Tone outputs

Signaling rate
TONE_O 495 – 505 Hz
Output voltage
operating range 1.27 1.41 1.55 Vp-p
short circuit current – – 0 mA Tone out is capacitively coupled to the output pin.
Output impedance – 320 – Ω Coupling capacitor impedance specified for 500Hz.
25 Sep. 2008 | DST/N/065 277

Setting up the VDC/001

Name No limit to characters MySignal Serial output of CVSD modulator in parallel form. This is converted
from serial to parallel at the start of an acquisition cycle and at equal
intervals of time thereafter.
gain 1 1
Size In Bits 8 to 16 16 The rate at which data is clocked from the modulator depends on the
bits per word and the words per acquisition cycle. The VDC/001
places the CVSD data in the most significant bits of the 16-bit
VDC/001 parameter. The least significant bits are set to zero. For
example, if a 12-bit CVSD is selected, bit 15 to bit 4 of the VDC/001
parameter will contain the audio data, where bit 15 is the oldest bit;
and bits 3 to 0 will contain zeros.

Manufacturer
part reference KAD/VDC/001 KAD/VDC/001 ACRA CONTROL part number.
278 25 Sep. 2008 | DST/N/065

Getting the most from the VDC/001
Audio quality can be improved by increasing the sampling
rate. If the data is to be embedded in a PCM stream it is
recommended that the words be evenly commutated as this
simplifies ground station demodulator design. For more
information concerning ground station demodulator design
contact ACRA CONTROL.
The rate at which the card must be read depends on the word
length and the sampling rate of the modulator. Some popular
choices are:
CVSD Audio Word rate (ksps)

modulator quality
bit-rate 8 10 12 16
bits bits bits bits
32kbps Very good 4.0 3.2 ≈2.7 2.0
16kbps Good 2.0 1.6 ≈1.3 1.0
8kbps Public 1.0 0.8 ≈0.7 0.5

address
system
25 Sep. 2008 | DST/N/065 279

Connector pinout of the KAD/VDC/001

1 ANALOG(0)+ Differential ended audio inputs Voice channel
2 ANALOG(0)- Differential ended audio inputs Voice channel
3 ANALOG(1)+ Differential ended audio inputs Voice channel
4 ANALOG(1)- Differential ended audio inputs Voice channel
5 TONE Tone outputs 500Hz sine wave; 500mVrms typical
9 NC Not connected
10 NC Not connected
11 NC Not connected
12 NC Not connected
13 NC Not connected
14 NC Not connected
15 NC Not connected
16 NC Not connected
17 NC Not connected
18 NC Not connected
19 NC Not connected
20 NC Not connected
21 NC Not connected
22 NC Not connected
23 NC Not connected
24 NC Not connected
25 NC Not connected
26 NC Not connected
27 NC Not connected
28 NC Not connected
29 NC Not connected
30 NC Not connected
31 NC Not connected
32 NC Not connected
33 NC Not connected
34 NC Not connected
35 NC Not connected
36 NC Not connected
37 NC Not connected
38 NC Not connected
39 NC Not connected
40 NC Not connected
41 NC Not connected
42 NC Not connected
43 NC Not connected
44 NC Not connected
45 NC Not connected
46 NC Not connected
47 NC Not connected
48 NC Not connected
49 NC Not connected
50 NC Not connected
www.acracontrol.com
280 25 Sep. 2008 | DST/N/065

ACRA Digital modules
C O N T R O L
281
KAD/DPI/002, KAM/DPI/002
A C R A KAM-500 DPI/002
16K x 16 bit external dual-port RAM reader
C O N T R O L
DESCRIPTION
The DPI/002 provides a method of including data from
third-party manufacturers in the KAM-500 system. The card
outputs 16 address lines, a READ, and has 16 data input
lines. In a typical application, a third-party stores parameters
in a dual-port RAM or provides an I/O port that can be read
by the DPI/002.
FEATURES
• Reads up to 65,536 addresses
• 16-bit data words
• Interface to third-party equipment such as Pressure
systems S8256 or ASCB-D monitor
• Hardware compatible with the DPI/001
• All timing and read options are programmable
APPLICATIONS
• Time stamping of events
• Frequency measurement
• RPM measurement
• Data capture from a parallel bus
D[15:0]
17
DATA 32K
REGISTER CVT
32
A[15:0]
1 ADDRESS CONFIGURATION
36 REGISTER EEPROM
HARD
READ 34 + WIRE
AMP STATE
-
MESSAGE
GND 51
DPI/002
DPI/002 block diagram
22 Dec. 2008 | DST/N/067 283

Selection Paths
Airborne Data Acquisition → KAM-500 → Modules → Digital → Peripheral Interface
KAD/DPI/002 CON/KAD/002/CP DPI/002 module with 52-way double density module top connector
KAM/DPI/002 ACC/CON/008/04 DPI/002 module with 51-way micro-miniature module top connector
Revision History
DPI/002 First release Recommended for new programs
In this data sheet DPI/002 refers to both the KAD and KAM version of the module.
Related Products
Module Details
DSI/002 24-ch. discrete input module with counters and time tagging
Document Details
www.acracontrol.com
284 22 Dec. 2008 | DST/N/067

Specifications
Channels: 16 address lines + READ line+ 16-bit data
Input considerations: Type: BTTL

'1' 5V (>3V)
'0' 0V (< 0.8V)
Protection:±20V
Output considerations: Type: BTTL

'1' 5V
'0' 0V
Short circuit protection:Indefinite to ground
Address settling time:50nsec. (max.)
Sampling restrictions: The maximum sampling rate per channel is 500kHz
22 Dec. 2008 | DST/N/067 285

Setting up the DPI/002
Setup
Field Settings Scope Comment

Read interval 1μs to > 32μs in steps of 125ns Entire system Time between two Reads of an external
device
Read pulse width 250ns to 32μs in steps of 125ns Read pulse Time for which Read pulse is active
Read polarity High or Low Read pulse Determines if Read is active high or low
Address settling 250ns to > 32μs in steps of 125ns Address lines Allows for all address line to settle before
time activating the Readpulse
Data valid time 250ns to > 32μs in steps of 125ns Data lines Time for external device to respond with valid
data
All maximum time quoted are for a single event and can be extended by using more that one event for a single access.
Output Registers
The diagram below illustrates the 32,000 registers that can be read from the DPI/002.
CHASSIS # MODULE #
One of 32K CVT addresses RAM
Figure 2: Choosing a parameter to be read from the DPI/002
Register Bits Description MSB

RAM Data from external RAM
R[15:0] DATA[15:0] (data input pins) R(15)
286 22 Dec. 2008 | DST/N/067

Getting the most from the DPI/002
The DPI/002 reads the dual-port RAM or an external device
in a pre-defined sequence, which repeats exactly each
acquisition cycle. If the external writing to the RAM must be
made synchronous, the major frame pulse (MAJOR_PULSE)
from the encoder can be used.
Figure 3: Reading of external RAM waveform
22 Dec. 2008 | DST/N/067 287

Connector pinout of the KAD/DPI/002

1 ADDR(0) BTTL outputs Word select to external RAM; LSB, used if word
bigger than 16 bits
2 ADDR(1) BTTL outputs Word select to external RAM; MSB, used if word
bigger than 32 bits
3 ADDR(2) BTTL outputs Address line to external RAM; LSB
4 ADDR(3) BTTL outputs Address line to external RAM
17 DATA(0) BTTL inputs Data from RAM; LSB
18 DATA(1) BTTL inputs Data from RAM
32 DATA(15) BTTL inputs Data from RAM; MSB
34 READ BTTL outputs Makes RAM transparent when active; polarity,
pulse width are programmable
36 ADDR(15) BTTL outputs Address line to external RAM; MSB
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288 22 Dec. 2008 | DST/N/067

KAD/DSI/002, KAM/DSI/002
A C R A KAM-500 DSI/002
24 channel discrete input module with counters and time tagging
C O N T R O L
DESCRIPTION
The DSI/002 is used to monitor the status (high/low) of up to
24 D/E discrete channels. Eight of these channels have
alternate functions as programmable counters. All 24 discrete
signals are sampled simultaneously and are typically read as
two 12-bit words.
The eight counters can be programmed as period, frequency,
read, event, event_since and elapsed. The last 16 channels
can be activated as event tagging channels. The range of
each counter is programmable as is the threshold and the
sensitivity to the rising and falling edge.
FEATURES
• 24 differential-ended (D/E) discrete input channels
• 8 x 16-bit counters (period, frequency, events etc.)
• Threshold programmable in groups of 6 (0V/open,
28V/open, 0V/28V)
• Programmable falling/rising edge detect
• 16 channels with event tagging
APPLICATIONS
• Time stamping of events
• Frequency measurement
• RPM measurement
• Data capture from a parallel bus
REGISTER
24
47K
TYPE AND RANGE OF COUNTER
-5V
100K
DISCRETE(0)+
1 + COUNTS
DISCRETE(0)- → UNITS
2 -
100K COMPARATOR
(0 ) COUNTER
DIGITAL ←
47K ANALOG
(1) THRESHOLD
(2)
(3)
(4)
GND (5)
51
DSI/002
First of 24 discrete inputs and first of eight counter inputs
29 Sep. 2008 | DST/N/068 289

Selection Paths
Airborne Data Acquisition → KAM-500 → Modules → Digital → Input
KAD/DSI/002 CON/KAD/002/CP DSI/002 module with 52-way double density module top connector
KAM/DSI/002 ACC/CON/008/04 DSI/002 module with 51-way micro-miniature module top connector
Revision History
DSI/002 First release Recommended for new programs
In this data sheet DSI/002 refers to both the KAD and KAM version of the module.
Related Products
Module Details
DSI/003/B 24-channel bi-level input module with 32 bit counters
Document Details
www.acracontrol.com
290 29 Sep. 2008 | DST/N/068

Specifications

Mass
– 60 – g
Power consumption
+5V 150 – 158 mA
±7V 0 – 0 mA
+12V 31.4 – 31.7 mA
-12V 34.7 – 35.7 mA
Differential ended digital inputs

per channel 1 – 20,000 sps
Input voltage
Input signal
signal slope 50 – – V/ms
threshold -5.1 – 26.5 V
threshold steps 7.8 – – mV
29 Sep. 2008 | DST/N/068 291

Setting up the DSI/002
Setting up Parameters
<Parameters>
<ParameterTypeSet>
<ParameterType Name="MyPeriodCounterType">
<BaseUnit>Seconds</BaseUnit>
<Scale>1e-6</Scale>
<RangeMinimum>0</RangeMinimum>
<RangeMaximum>2e32</RangeMaximum>
</ParameterType>
</ParameterTypeSet>
:
<ParameterSet>
2 <Parameter Name="MyPeriodCounter">
<ParameterProperties>
<ParameterTypeReference>MyPeriodCounterType</ParameterTypeReference>
</ParameterProperties>
<Source>
<Signal>
1 <InstrumentReference>MyDSI002</InstrumentReference>
3 <VendorMap>Counter(0)</VendorMap>
</Signal>
</Source>
</Parameter>
</ParameterSet>
</Parameters>
Table2.1:
Name Type Range Default Mandatory Applies Description

to
Instrumen- Name N/A N/A Yes Each mod- Name of module from which parameter is sourced.
1
tReference ule
Parameter- Name N/A N/A Yes Each pa- The name corresponding to the channel.
2
Name rameter
VendorMap Selection 0 to 7 N/A Yes Each pa- The register (parameter) being read. For more de-
3
rameter tails, see “Output Registers” on page 294.
292 29 Sep. 2008 | DST/N/068

Setting up Instrumentation
<Instrumentation>
<InstrumentSet>
4 <X-DAU-1.0 Name="MyDAU">
<Manufacturer>
<Name>ACRA CONTROL</Name>
8 <PartReference>KAM/CHS/13U/B</PartReference>
</Manufacturer>
</X-DAU-1.0>
:
5 <X-Module-Discrete-In-1.1 Name="MyDSI002_1">
<Settings>
<Module-Discrete-In-1.1>
<Counter Index="0">
<RollOver>Yes</RollOver>
9 <ThresholdVoltageMaximum>10</ThresholdVoltageMaximum>
<ThresholdVoltageMinimum>-10</ThresholdVoltageMinimum>
6 <PeriodCounter>
7 <TriggerEdge>Rising</TriggerEdge>
</PeriodCounter>
</Counter>
:
11 <Discrete Index="8">
<ThresholdVoltageMaximum>-25</ThresholdVoltageMaximum>
10 <ThresholdVoltageMinimum>25</ThresholdVoltageMinimum>
<Event>
<Armed>No</Armed>
</Event>
</Discrete>
</Module-Discrete-In-1.1>
</Settings>
</X-Module-Discrete-In-1.1>
:
</InstrumentSet>
</Instrumentation>

to
InstrumentRe Name N/A N/A Yes Each Name of module from which parameter
5
ference module is sourced.
Type Selection PERIOD PERIOD Yes Each This mode counts the number of
6
counter defined clock periods between events.
FREQUENCY This mode counts the number of events
in a defined clock period.
EVENTS_SINCE This mode counts the number of events
between samples.
ELAPSED This mode counts the number of
defined clock periods between
samples.
COUNT This counts the number of events from
power-up updating on sample. It will
reset to 0 when the number of events is
65535.
TIMER This mode counts the total number of
defined clock periods since the last
event occurred. It is updated every
sample.
READ This mode counts the total number of
samples from power-up. It will reset to 0
when the number of events is 65535.
The count updates at the rate of the
fastest parameter sampled from the
DSI/002.
EVENT This mode counts the number of
samples between events updates upon
sample. It resets to 1 when a new event
is detected.
TriggerEdge Selection Rising, Falling, or Rising Yes Each An input event can be triggered by a
7
Both counter rising edge, falling edge or both.
29 Sep. 2008 | DST/N/068 293

to
PartRefer- Selection N/A N/A No Each ACRA CONTROL part number.
8
ence module
Threshold- Float -25V to + 25V 1.064 Yes Each The voltage at which an input is logic 1
9
VoltageMax- counter (high).
imum input
Threshold- Float -25V to + 25V 1.064 Yes Each The voltage at which an input is logic 0
10
VoltageMin- counter (low).
imum input
Discrete Info N/A N/A Yes Each The setup channels available for
11
Index parameter discretes. For more details, see “Output
Registers” on page 294.
Output Registers
The diagram below illustrates the 10 registers that can be read from the DSI/002.
CHASSIS # MODULE # TYPE
One of 8 counters COUNT

COUNTER
TAG_EVENT
STATUS STATUS_HI
STATUS_LO
Choosing a parameter to be read from the DSI/002
COUNT The value of the counter. Counters are read at the start of an acquisition cycle and
evenly spaced in time thereafter
R[15:0] BINARY The type and range of counter is specified in setup R(15)
TAG_EVENT R[47:32] Status of channels 23 to 8 after the event R(47)
R[31:16] Time_lo, seconds and centisecond time when the event occurred. BCD(00.00-59.99)s.
R[15:0] Time_Micro microsecond time when the event occurred.

BCD(0000-9999)µs.
STATUS_LO The values of the 12 discrete inputs labeled 11 down to 0. Status is read at the start of
an acquisition cycle and evenly spaced in time thereafter
R[15:4] DISCRETE[11:0] R(15)
STATUS_HI The values of the 12 discrete inputs labeled 23 down to 12. Status is read at the start of
an acquisition cycle and evenly spaced, in time, thereafter
R[15:4] DISCRETE[23:12] R(15)
294 29 Sep. 2008 | DST/N/068

Getting the most from the DSI/002
To ensure that the event tagging FIFO is never completely
filled, ensure that events are read more quickly than they
occur. The events are stored in a FIFO, which can store up to
1024 events.
For example, a square wave is input with a frequency of
500Hz (the events will occur with a frequency of 1000Hz).
The minimum frequency of reading the events must be
greater than 1000Hz to ensure that any unexpected events
do not cause the FIFO to fill up. If a burst of 1000 events
occurs every 250 seconds, then a minimum frequency of
reading of 4Hz should be used to ensure that the FIFO is
empty before the next burst arrives.
29 Sep. 2008 | DST/N/068 295

Connector pinout of the KAD/DSI/002

1 DISCRETE(0)+ Differential ended digital inputs Discrete Input; also connected to counter 0
2 DISCRETE(0)- Differential ended digital inputs Discrete Input; also connected to counter 0
17 DISCRETE(8)+ Differential ended digital inputs Discrete Input
18 DISCRETE(8)- Differential ended digital inputs Discrete Input
49 NC Not connected
50 NC Not connected
www.acracontrol.com
296 29 Sep. 2008 | DST/N/068

KAD/DSI/003/B, KAM/DSI/003/B
A C R A KAM-500 DSI/003
C O N T R O L 24 channel bi-level input module with counters and time tagging
DESCRIPTION
The DSI/003 monitors the status (high/low) of up to 24
differential-ended (D/E) discrete channels. Eight of these
have alternative functions as programmable counters, of
which four can be configured as resettable event counters.
Another 16 channels can be used to trigger time-tagged
events.
All 24 discrete signals are sampled simultaneously and can
be read as a 24-bit word (16-bit + 8-bit or 12-bit + 12-bit). The
DSI/003 uses 24 separate 14-bit A/Ds operating continuously
at 111ksps to sample each input so the threshold and
FEATURES hysteresis can be programmed separately for each channel.
• 24 differential-ended (D/E) discrete bi-level input channels The eight counters can be programmed as PERIOD,
• 8 x 32-bit counters (Period, Frequency, Events Since, FREQUENCY, EVENTS_SINCE_LAST_READ, EVENTS or
Elapsed, Read, Events, Reset, Counter) ELAPSED time. The range of each counter is programmable
• First-in-first-out (FIFO)-based time tagging as is the threshold, hysteresis sensitivity to the rising/falling
• Resettable counters edge and roll-over. If the counter uses more than 16 bits, they
• Independent channel programmability are treated as two words.
- Threshold
The 16 channels control the time tagging to the 8K FIFO. For
- Hysteresis (for a slow slew rate, high noise applications)
each input, time tagging can be triggered by a rising and
- Falling/rising edge detect falling edge or neither (when the channel is disabled). Every
time a trigger occurs, a 64-bit word is written to the FIFO
APPLICATIONS consisting of the 16 inputs (after the change) and the binary
• Data acquisition systems coded decimal (BCD) time that the event happened (up to 23
• Engine speed measurement hours 59 minutes 59.99 9999 seconds).
+ 330K
1
+ ANALOG
DISCRETE(0) AMP
2 - →DIGITAL
-
330K
330K
+5V
Register
Threshold counters
1M hysteresis time
+ 17 + ANALOG tagging
DISCRETE(8) AMP →DIGITAL
18 -
-
1M 330K
GND 51
DSI/003
First of eight counter inputs and first of sixteen discrete inputs
29 Jan. 2009 | DST/N/091 297

Selection Paths
Airborne Data Acquisition → KAM-500 → Modules → Digital → Input
KAD/DSI/003/B CON/KAD/002/CP DSI/003 module with 52-way double density module top connector
KAM/DSI/003/B ACC/CON/008/04 DSI/003 module with 51-way micro-miniature module top connector
Revision History
DSI/003/B Includes an external counter reset function Recommended for new programs
DSI/003 First release Obsolete
In this data sheet DSI/003/B refers to both the KAD and KAM version of the module.
Related Products
Module Details
DSI/002 24-channel bi-level input module with counters and time tagging
Document Details
www.acracontrol.com
298 29 Jan. 2009 | DST/N/091

Specifications

Mass
– 60 – g
Power consumption
+5V 263 – 264 mA
±7V 0 – 0 mA
+12V 14 – 18 mA
-12V 12 – 14 mA
Differential ended digital inputs

Sampling rate
per channel 1 – 20,000 sps
Input voltage
operating range -28 – 28 V Primary gain=1.
Input signal
channels 0 to 7
slew rate – 4 – V/usµs Volts per microsecond.
threshold -10 – 10 V
threshold steps – 1.22 – mV
channels 8 to 23
slew rate – 1.25 – V/usµs Volts per microsecond.
threshold -55 – 25 V
threshold steps – 4.88 – mV
29 Jan. 2009 | DST/N/091 299

Setting up the DSI/003
<Parameters>
<ParameterTypeSet>
<ParameterType Name="MyPeriodCounterType">
<BaseUnit>Seconds</BaseUnit>
<Scale>1e-6</Scale>
<RangeMinimum>0</RangeMinimum>
4 <RangeMaximum>2e32</RangeMaximum>
<SizeInBits>32</SizeInBits>
</ParameterType>
</ParameterTypeSet>
:
<ParameterSet>
2
<Parameter Name="MyPeriodCounter">
<ParameterTypeReference>MyPeriodCounterType</ParameterTypeReference>
<Source>
<Signal>
1 <InstrumentReference>MyDSI003_1</InstrumentReference>
3 <VendorMap>Counter(0)</VendorMap>
</Signal>
</Source>
</Parameter>
</ParameterSet>
</Parameters>
Name Type Range Default Mandatory Applies to Description

Instrumen- Name N/A N/A Yes Each module Name of module from which parameter is
1
tReference sourced.
Parameter- Name N/A N/A Yes Each parameter The name corresponding to the channel.
2
Name
VendorMap Selection 0 to 7 N/A Yes Each parameter The register (parameter) being read. For
3
more details, see “Output Registers” on
page 302.
SizeInBits Selection 10bit, 32bit No Each counter Counter size in bits
4
12bit,
16bit,
20bit,
24bit,
or 32bit
300 29 Jan. 2009 | DST/N/091

<Instrumentation>
<InstrumentSet>
4 <X-DAU-1.0 Name="MyDAU">
<Manufacturer>
8 <PartReference>KAM/CHS/13U/B</PartReference>
</Manufacturer>
</X-DAU-1.0>
:
5 <X-Module-Discrete-In-1.1 Name="MyDSI002_1">
<Settings>
<Module-Discrete-In-1.1>
<Counter Index="0">
<RollOver>Yes</RollOver>
9 <ThresholdVoltageMaximum>10</ThresholdVoltageMaximum>
<ThresholdVoltageMinimum>-10</ThresholdVoltageMinimum>
6 <PeriodCounter>
7 <TriggerEdge>Rising</TriggerEdge>
</PeriodCounter>
</Counter>
:
11 <Discrete Index="8">
<ThresholdVoltageMaximum>-25</ThresholdVoltageMaximum>
10 <ThresholdVoltageMinimum>25</ThresholdVoltageMinimum>
<Event>
<Armed>No</Armed>
</Event>
</Discrete>
</Module-Discrete-In-1.1>
</Settings>
</X-Module-Discrete-In-1.1>
:
</InstrumentSet>
</Instrumentation>

to
InstrumentR Name N/A N/A Yes Each Name of module from which parameter is
5
eference module sourced.
Type Selection PERIOD PERIOD Yes Each This mode counts the number of defined
6
counter clock periods between events.
FREQUENCY This mode counts the number of events
in a defined clock period.
EVENTS_SINCE This mode counts the number of events
between samples.
ELAPSED This mode counts the number of defined
clock periods between samples.
COUNT This counts the number of events from
power-up updating on sample. It will
reset to 0 when the number of events is
65535.
TIMER This mode counts the total number of
defined clock periods since the last event
occurred. It is updated every sample.
READ This mode counts the total number of
samples from power-up. It will reset to 0
when the number of events is 65535.
EVENT This mode counts the number of
samples between events updates upon
sample. It resets to 1 when a new event
is detected.
TriggerEdge Selection Rising, Falling, or Rising Yes Each An input event can be triggered by a
7
Both counter rising edge, falling edge or both.
PartReferen Selection N/A N/A No Each ACRA CONTROL part number.
8
ce module
29 Jan. 2009 | DST/N/091 301

to
ThresholdVo Float -25V to + 25V 1.064 Yes Each The voltage at which an input is logic 1
9
ltageMaximu counter (high).
m input
ThresholdVo Float -25V to + 25V 1.064 Yes Each The voltage at which an input is logic 0
10
ltageMinimu counter (low).
m input
Discrete Info N/A N/A Yes Each The setup channels available for
11
Index parameter discretes. For more details, see “Output
Registers” on page 302.
Output Registers
The diagram shows the 22 registers that can be read from the DSI/003/B.
One of 8 counters COUNTER_HI

COUNTER
COUNTER_LO
COUNTER
TAG EVENT TIME_HI

TIME_LO
TIME_MICRO
TAG_STATUS
STATUS_HI
STATUS_LO
Figure 2: Choosing a parameter to be read from the DSI/003/B
302 29 Jan. 2009 | DST/N/091

COUNTER_LO The value of the counter. Counters are read at the start of an acquisition cycle and
evenly spaced in time thereafter, depending on sampling rate.
R[15:0] COUNT[15:0] for 16 or 32-bit counter R(15)
COUNTER_HI The value of the counter. Counters are read at the start of an acquisition cycle and
evenly spaced in time thereafter, depending on sampling rate.
R[15:0] COUNT[31:16] for 32-bit counter R(15)
COUNTER R[31:0] COUNTER_HI and COUNTER_LO combine to form a 32bit register. R[31:0] COUNT, R(31)
R[15:0] for COUNTER_LO[15:0] and R[31:16] for COUNTER_HI.
STATUS_LO The values of the 12 discrete inputs labeled 11 down to 0. Status is read at the start of
an acquisition cycle and evenly spaced in time thereafter.
R[15:0] DISCRETE[15:0] when read as 16-bits R(15)
STATUS_HI The values of the 15 discrete inputs labeled 11 down to 0. Status is read at the start of
an acquisition cycle and evenly spaced in time thereafter.
TAG_STATUS The values of the 16 discrete inputs labeled 23 down to 8 after an event. When the
FIFO is empty the last values are repeated.
R[15:0] DISCRETE[23:8] R(15)
TIME_MICRO The microsecond the event happened. When the FIFO is empty the last values are
repeated.
R[15:0] BCD 0000-9999 μsec. R(15)
TIME_LO The centisecond the event happened. When the FIFO is empty the last values are
repeated.
R[15] Shows that the FIFO was overwritten R(15)
R[14:0] BCD 00.00-59.99 sec. R(14)
TIME_HI The second the event happened. When the FIFO is empty the last values are
repeated.
R[15:13] Day [2:0] R(15)
R[12:7] BCD 00-23 hours R(12)
R[6:0] BCD 00-59 minutes R(6)
MSB = Most Significant Bit

BCD = Binary Coded Decimal
29 Jan. 2009 | DST/N/091 303

Getting the most from the DSI/003
For single-ended (S/E) signals, connect to the positive input
for each channel. The negative input can be left floating but it
is recommended to tie it to ground (GND). When time tagging
events, ensure unused inputs or inputs that are not of interest
are masked such that transitions on these inputs are ignored.
This helps ensure that the FIFO does not overflow due to too
many events.
The READS counter increments every time it is read. For
example, if a 32-bit READS counter is read once per 1ms
major frame then it can act as a major frame counter that will
cycle every 49.7 days (= 232 x 1ms).
The EVENTS counter increments on events and rolls over.
For example, a 20-bit EVENTS counter connected to a 1pps
output of a time source would increment every second and
cycle every 12.1 days (=220 x 1s).
The FREQUENCY counter is used to count events over a
user defined time. For example, if a 1s time base is chosen,
then a 1kHz input will return a binary value of 11 1110 10002.
The PERIOD counter is used to measure the time between
events. For example, if an 80μs interval base is chosen, then
an input signal of 10Hz will return a binary value of 100 1110
00102.
The EVENTS_SINCE_RESET counter increments on events
and rolls over. For example, a 20-bit EVENTS counter
connected to a 1pps output of a time source would increment
every second and cycle every 12.1 days (=220 x 1s).
However, this counter can be reset by the input to the next
counter. To do this, the next counter must be set to EVENT
type and only counters 0, 2, 4 or 6 can be used as RESET
inputs.
If measuring high frequency (20kHz - 50kHz) signals with the
DSI/003, choose suitable threshold voltages, bearing in mind
that the input signal will be attenuated.
304 29 Jan. 2009 | DST/N/091

Connector pinout of the KAD/DSI/003

49 NC Not connected
www.acracontrol.com
306 29 Jan. 2009 | DST/N/091

ACRA Bus modules
C O N T R O L
307
KAD/SDI/001, KAM/SDI/001
A C R A KAM-500 SDI/001
C O N T R O L 8 channel serial data input module (clock out/data in)
APPLICATIONS
• Data acquisition systems
• General purpose serial data read from external devices
DESCRIPTION
The SDI/001 is used to read data serially from external
devices.
At the start of each acquisition cycle, the INIT line is asserted
FEATURES so as to reset each of the devices connected to the serial line.
• Eight differential ended (D/E) input channels A programmable number of output clock pulses are used to
• Eight D/E clock output channels clock data out of these devices. This can happen at intervals
• Single D/E INIT output channel spaced evenly throughout the acquisition cycle.
• Programmable word length (8 to 16 bits) per channel
• Programmable number of words (1 to 32) per channel
• Programmable number of reads (INITs) per acquisition
cycle
• 2.00, 1.00, 0.50, or 0.25MHz clock, programmable per
channel
• Data acquisition is synchronous with KAM-500 acquisition
cycle
• All input/output channels are terminated RS-422 (120Ω)
SP
+ Converter
3
+ SERIAL →
DATA(0) 120 PARALLEL
-
- 4
D/E Current
Receiver Value
Table
+ 32 Prog. Delay
+
DCLK(0) 120 -
- 33 Prog. Clock
Generator
+ 1
+
INIT 120 -
- 2
GND 51
KAD/SDI/001
INIT output and first of 8 serial channels
23 Dec. 2008 | DST/N/069 309

Selection Paths
Airborne Data Acquisition → KAM-500 → Modules → Digital → Peripheral interface
KAD/SDI/001 CON/KAD/002/CP SDI/001 module, with 52-way double density module top connector
KAM/SDI/001 ACC/CON/008/04 SDI/001 module, with 51-way micro-miniature module top connector
the Confirmation of Order unless an alternative option is specified (please see Cables data sheet).
Revision History
SDI/001 First release Recommended for new programs
In this data sheet SDI/001 refers to both the KAD and KAM version of the module.
Related Products
Module Details
KSMv2 This module is supported by KSMv2.
Document Details
www.acracontrol.com
310 23 Dec. 2008 | DST/N/069

Specifications
Channels: 8
Output drivers: Terminated RS-422 (120Ω)
Input drivers: Terminated RS-422 (120Ω)
Setup

INIT pulse width 250ns to 64μs in 250ns steps INIT pulse Time for which INIT pulse is high.
INIT polarity High or low INIT pulse Determines if INIT is active high or low.
INIT pulse interval 100μs to 2sec. in 125ns steps INIT pulse The time between INIT pulses. There must be an
integral number of INIT intervals per acquisition cycle.
Bits per word From 8 to 16 Each channel
Words per burst 1 to 32 Each channel
Bursts per INIT 1 to 32 Each channel
Clock rate 1.0, 2.0, 0.5 or 0.25MHz Each channel In other words, the clock period is 4, 2, 1 or 0.5μs.
Clock delay after INIT 10μs to 320μs in 10μs steps Each channel Time from start of INIT pulse to rising edge of clock.
Clock polarity High or low Each channel Determines if clock is active high or low.
Start of clock to data 250ns to 4000ns in 125ns steps Each channel Time from start of clock until the data is considered
valid delay valid.
Output Registers
The diagram below illustrates the 128 registers that can be read from the SDI/001.
CHASSIS # MODULE #
One of 8 Busses DATA_31
DATA_0
Choosing a parameter to be read from the SDI/001
Register Bits Description FTB
DATA Data bits clocked in
R[15:0] The number of MSBs depends on the word length specified in setup R(15)
MSB = Most Significant Bit = oldest/first bit received
Getting the most from the SDI/001

The timing diagram below shows the timing parameters that can be programmed.
INIT Interval
INIT (Polarity=1)
Pulse
Bits per word X Words per INIT width
DCLK
Clock delay after INIT Clock period
DATA
Start of clock to data valid
23 Dec. 2008 | DST/N/069 311

Connector pinout of KAD/SDI/001

1 INIT+ RS-422 Out Used to initialize external devices Internally terminated with 120Ω
2 INIT- RS-422 Out Used to initialize external devices Internally terminated with 120Ω
3 DATA(0)+ RS-422 In Data from external device First of up to 8 devices
4 DATA(0)- RS-422 In Data from external device Internally terminated with 120Ω
5 DCLK(1)+ RS-422 Out Data clock to external device Internally terminated with 120Ω
6 DCLK(1)- RS-422 Out Data clock to external device Internally terminated with 120Ω
7 NC Do not connect
8 NC Do not connect
9 DATA(1)+ RS-422 In Data from external device Internally terminated with 120Ω
32 DCLK(0)+ RS-422 Out Data clock to external device First of up to 8 devices
www.acracontrol.com
312 23 Dec. 2008 | DST/N/069

KAD/ARI/001/B, KAM/ARI/001/B
A C R A KAM-500 ARI/001
C O N T R O L 8 channel ARINC-429 bus monitor with parity option
DESCRIPTION
The ARI/001 is an ARINC-429 bus monitor combining the
capabilities of an all-pass/selected-pass monitor, a coherent
message parser and an error-detection function on a single
module.
In the discussion below "traffic" refers to words on the bus
and "tag" refers to associated information (time tags, word
count and errors).
The parser triple buffers up to 4095 words and their
associated tags (word being read, word being received and
an interim buffer). Each message has a STALE bit (word read
FEATURES before) and a SKIPPED bit (buffer overwritten).
• Monitors up to eight ARINC-429 buses
The SNARFER stores selected traffic and tags in a
• Coherently parses traffic and tags for up to 4095 words
first-in-first-out (FIFO) 16K words deep. Each word has 16
• 16K deep selective FIFO for traffic and tags (SNARFER) bits for traffic tag information and 7 bits for FIFO content
• Word counter for each bus
identification. Data selection and content identification is
• Detects seven types of errors
based on the Bus (0 to 7), Word ID (0 to 4095), tag type (time
high/low/micro and message count) and how full the FIFO is.
APPLICATIONS
The WORD count increments on receipt of a valid word. the
• ARINC-429 monitoring REPORT word has bits indicating the type of error caught
• Translation from one bus to another and the bus it occurred on.
TIMER
+
DATA(0) -
1
2
PHYSICAL LAYER WORD FINDER
TO TTL SYMBOL DETECT AND TIMING
LOCK
ID LIST
VERIFY
LOST
TRIPLE BUFFERED WORD X 1024
SEQUENCE TRACKER
TRAFFIC TAG FIFO X 16K + FILTER
GND 51
ARI/001
First of eight busses on the ARI/001
4 Sep. 2008 | DST/P/030 313

Selection Paths
Airborne Data Acquisition → KAM-500 → Modules → Bus → ARINC
KAD/ARI/001/B CON/KAD/002/CP ARI/001 module with 52-way double density module top connector
KAM/ARI/001/B ACC/CON/008/04 ARI/001 module with 51-way micro-miniature module top connector
Revision History
ARI/001/B Option to monitor parity at the start or end of received Recommended for new programs
data
ARI/001 First release Not recommended for new programs
In this data sheet ARI/001/B refers to both the KAD and KAM version of the module.
Related Products
Module Details
ARI/002 Single channel ARINC-429 transmitter module
Document Details
TEC/NOT/006 ARINC-429
TEC/NOT/007 ARINC-429 and the ARI/001
www.acracontrol.com
314 4 Sep. 2008 | DST/P/030

Specifications

Mass
– 70 – g
Power consumption
+5V 172 – 197 mA
±7V 0 – 0 mA
±12V 0 – 0 mA
ARINC-429 inputs

Signaling rate
DATA 12.5 – 100 kbps Signalling rate is either 12.5 or 100.
Input voltage
logic ‘0’ -0.8 0 2.5 V
logic ‘L’ -40 -10 -0.8 V
logic ‘H’ 2.5 10 40 V
ESD protection 8 – – kV Human Body Model.
Input resistance
4 Sep. 2008 | DST/P/030 315

Setting up the ARI/001
<Parameters>
<ParameterSet>
1 <Parameter Name="MyAnalogParameter">
<ParameterTypeReference>MyAnalogParameterType</ParameterTypeReference>
<Source>
<Signal>
<InstrumentReference>MyAnalogModule</InstrumentReference>
<VendorMap>Channel(0)</VendorMap>
</Signal>
</Source>
<Destination>
<Package>
<InstrumentReference>MyARI</InstrumentReference>
<PackageReference>MyARINC-429Message</PackageReference>
<ParameterMap>P0</ParameterMap>
</Package>
</Destination>
</Parameter>
</ParameterSet>
</Parameters>

Parameter Name N/A N/A Yes Each parameter The name corresponding to the channel.
1
Name
:
<Instrumentation>
<InstrumentSet>
2 <X-Module-ARINC-429-Monitor-1.1 Name="MyARI">
<Manufacturer>
4 <PartReference>KAD/ARI/001/B</PartReference>
</Manufacturer>
3 <Location>MyDAU</Location>
<Settings>
<Module-ARINC-429-Monitor-1.1>
<Bus Name="Bus_0">
<CheckForParity>Yes</CheckForParity>
5 </Bus>
</Module-ARINC-429-Monitor-1.1>
</Settings>
</X-Module-ARINC-429-Monitor-1.1>
</InstrumentSet>
</Instrumentation>
:

InstrumentRefer- Name N/A N/A Yes Each module Name of module.
2
ence
Location Name N/A N/A No Each DAU Name of DAU.
3
PartReference Selection N/A N/A No Each module ACRA CONTROL part number.
4
CheckForParity Selection Yes, No N/A No Each bus If checking is disabled, no parity

5
errors are reported and illegal parity
words are considered valid
316 4 Sep. 2008 | DST/P/030

Setting up Packages
:
<Packages>
<PackageSet>
6 <X-ARINC-429-Message-1.0 Name="MyARINC-429Message">
<DataLinkReference>MyARINC-429-DataLink</DataLinkReference>
<Properties>
7 <Label>1</Label>
9 <SSM>00</SSM>
8 <SDI>01</SDI>
<DataFormat>BNR</DataFormat>
10 <Parity>Odd</Parity>
</Properties>
<Content>
<Parameter Name="P0">
<NumberOfDataBits>12</NumberOfDataBits>
<Location>
<Offset_Bits>11</Offset_Bits>
</Location>
</Parameter>
</Content>
</X-ARINC-429-Message-1.0>
</PackageSet>
</Packages>
:

PackageReference Name N/A N/A Yes Each module Reference to a named package
6
definition.
Label Integer 1 to 255 N/A Yes Each package Used to determine the data type of the
7
payload section of the message.
SDI Selection 00, 01, N/A No Each package Source Destination Identifier. Allows
8
10, 11 ARINC receivers to determine if they
need to read the data, i.e. receivers
with the same SDI value will read
these messages.
SSM Selection 00, 01, N/A No Each package Sign / Status Matrix. This field
9
10, 11 contains hardware equipment
condition, operational mode, or validity
of data content.
Parity Selection Odd N/A Yes Each package The Parity bit which occupies the last
10
Even bit in the data stream (32) is intended
for error detection and correction. This
bit will constantly change as the label
and data change in order to provide
“Odd Parity”. What this means is that
at any time the 32 bit word will always
have an odd number of 1’s contained
within it.
Setting up DataLinks
<DataLinks>
<DataLinkSet>
<X-DataLink-1.1 Name="MyARINC-429-DataLink">
<Type>ARINC</Type>
<ProtocolProperties>
11 <BitRate>High</BitRate>
</ProtocolProperties>
</X-DataLink-1.1>
</DataLinkSet>
</DataLinks>

BitRate Selection High Slow Yes Each DataLink Speed of transmission of the databus can be fast
11
Low or slow corresponding to High (100kb per sec) or
Low (12.5kb per sec)
4 Sep. 2008 | DST/P/030 317

Getting the most from the ARI/001
Even if the SNARFER is not required for traffic and tags it may be worth considering setting the SNARFER filter so that only
errors are recorded. This ensures all errors and when they happened can be logged. On the ARINC-429 bus, the DATA, SDI
and SSM least significant bits (LSBs) are transmitted first. However, in the LABEL field, the LSB is transmitted last.
Error codes for the ARI/001
0 Bad bit 100 Parity error (if enabled)
1 Not enough bits in word 101-1000 Invalid label, or invalid label SDI, or invalid label SM
10 Too many bits in word 1001 Reserved for future use
11 Reserved for future use 1 0000-1111 Reserved for future use
Output Registers
The diagram below illustrates the 6155 registers that can be read from the ARI/001.
WORD COUNT One of 8 busses WORD_COUNT
TIME_HI
PARSER One of 1024 words TIME_LO
TIME_MICRO
WD_CNT
DATA_HI
DATA_LO
SNARFER SNARFER_HI
SNARFER_LO
SNARFER_HI
REPORT
WORD_COUNT Count of valid words received on each bus. In other words, WORD_COUNT increments only
when a correct label, SSM and SDI are transmitted by the ARINC bus.
R[15:0] BINARY 0000-FFFF, resets at FFFF R(15)
DATA_HI (Last)1 SSM and MSBs of DATA
R[15:14] SSM[1:0] R(15)
R[13:0] DATA[18:5] R(13)
DATA_LO (Last)1 LSBs of DATA, SDI, empty, stale, skipped and bus
R[15:11] DATA[4:0] R(15)
R[10:9] SDI[1:0] R(10)
R(8) Empty
R(7) Stale
R(6) Skipped
R[5:3] BINARY 0-7 indicates the bus the word was received on R(5)
R[2:1] Reserved for future use R(2)
R(0) Parity
DATA_HI (First)1 SSM and MSBs of DATA
R(15) Parity
R[14:13] SMM [1:0] R(14)
318 4 Sep. 2008 | DST/P/030

R[12:4] Data [18:10] R(12)
R[3:1] BINARY 0-7 indicates the bus the word was received on R(3)
DATA_LO (First)1 LSBs of DATA, SDI, empty, stale, skipped and bus
R[15:6] Data [9:0] R(15)
R[5:4] SDI [1:0] R(5)
R(3) Empty
R(2) Stale
R(1) Skipped
WD_CNT Word counter value when the word was received
R[15:0] BINARY 0000-FFFF, resets at FFFF R(15)
TIME_HI Hours and minutes time midway through first transmitted bit
R[12:7] BCD 00-23 hours R(12)
TIME_LO Seconds and centiseconds time midway through first transmitted bit
R[15:0] BCD 00.00-59.99 seconds R(15)
TIME_MICRO Microsecond time midway through first transmitted bit
R[15:0] BCD 0000-9999 microseconds R(15)
SNARFER_HI Bus number and content identifier. This together with SNARFER_LO is read from the
SNARFER_FIFO
R[15:13] BINARY 0-7 indicates the bus the word occurred on R(15)
R[11:8] BINARY 0-8 Content identifier R(11)

0 ERROR 1 SNARFER full 2 WD_CNT 3 DATA_HI
4 DATA_LO 5 TIME_MICRO 6 TIME_LO 7 TIME_HI
8 SNARFER empty 9-F Reserved for future use
SNARFER_LO SNARFER contents as indicated by content identifier. This together with SNARFER_HI is
read from the SNARFER FIFO
R[15:0] For bit definition of DATA_HI, TIME_HI, TIME_LO, TIME_MICRO and WD_CNT see above. R(15)
SNARFER empty = AAAA (hex)
SNARFER full = 5555 (hex)
ERROR = Reserved[15:7], BUS[3:0], ERROR_CODE[3:0]
DATA_LO = DATA[4:0], SDI[1:0], Reserved[0], LABEL[0:7]2
REPORT Indicates status of monitor
R(15) 1 indicates error occurred since last read
R[6:4] Indicates the bus the last error occurred on R(6)
R[3:0] Indicates the error that occurred last R(3)
1. Note that first/last is the parity option which can be chosen on the module setup.
2. Note the bit reversal of the LABEL.
4 Sep. 2008 | DST/P/030 319

Connector pinout of the KAD/ARI/001

1 DATA(0)+ ARINC-429 inputs Arinc-429 bus
2 DATA(0)- ARINC-429 inputs Arinc-429 bus
17 NC Not connected
18 NC Not connected
19 NC Not connected
20 NC Not connected
21 NC Not connected
22 NC Not connected
23 NC Not connected
24 NC Not connected
25 NC Not connected
26 NC Not connected
27 NC Not connected
28 NC Not connected
29 NC Not connected
30 NC Not connected
31 NC Not connected
32 NC Not connected
41 NC Not connected
42 NC Not connected
43 NC Not connected
44 NC Not connected
45 NC Not connected
46 NC Not connected
47 NC Not connected
48 NC Not connected
49 NC Not connected
50 NC Not connected
www.acracontrol.com
320 4 Sep. 2008 | DST/P/030

KAD/ARI/002, KAM/ARI/002
C O N T R O L Single channel ARINC-429 transmitter module
DESCRIPTION
The ARI/002 is a single channel ARINC-429 transmitter,
which takes KAM-500 parameters over the backplane and
transmits them on an ARINC-429 bus at a bit rate of 100kHz.
At the heart of the ARI/002 is a hard-wired state-machine that
reads a user defined message structure from its setup and
transmutes data read from the modules Current Value Table
(CVT) on the ARINC-429 bus.
Two message types can be sent; one where one 16 bit
KAM-500 parameter is sent in an ARINC-429 message and a
second where two 11 bit KAM-500 parameters are combined
FEATURES into one message.
• Transmits KAM-500 parameters in an ARINC-429 stream
All data transmitted is from the current KAM-500 data
• Single channel ARINC-429 compliant physical interface
acquisition cycle.
• Up to 256 unique messages can be transmitted
• Up to two parameters per message
• Programmable Label, SDI and SSM
• High throughput 100kHz bus
APPLICATIONS
• FTI, OLM and HUMS
• Data recording and storage
• Compatible with ARINC-429 data recorders
+
1 + PARALLEL ←
DATA - SERIAL
-
2
MESSAGE CVT
BUILDER
GND 51
ARI/002
ARINC-429 output on the ARI/002
3 Sep. 2008 | DST/N/071 321

Selection Paths
KAD/ARI/002 CON/KAD/002/CP ADC/109/B/S1 module with 52-way double density module top connector
KAM/ARI/002 ACC/CON/008/04 ADC/109/B/S1 module with 51-way micro-miniature module top connector
Revision History
ARI/002 First release Recommended for new programs
In this data sheet ARI/002 refers to both the KAD and KAM version of the module.
Related Products
Module Details
ARI/001/B 8 channel ARINC-429 bus monitor with parity option
ARI/103 Single-channel ARINC-573 bus monitor
Document Details
TEC/NOT/006 ARINC-429
www.acracontrol.com
322 3 Sep. 2008 | DST/N/071

Specifications

Mass
– 70 – g
Power consumption
+5V 90 – 110 mA
±7V 0 – 0 mA
±12V 0 – 0 mA
ARINC-429 outputs

Signaling rate
DATA – – 100 kbps
Output voltage
logic ‘0’ -11 -10 -9 V Sinking 0.1mA.
logic ‘1’ 9 10 11 V Sourcing 0.1mA.
short circuit duration ∞ – – s To GND. (One output at a time can be shorted to ground
indefinitely.)
3 Sep. 2008 | DST/N/071 323

Setup
Bit-rate 100kHz Bus
Label 0 to FF Each message Defines the message
Message type 1 word or 2 words Each message See “Getting the most from the ARI/002” on
page 325.
SDI 0, 1, 2, 3 Each 1 word message
SSM 0, 1, 2, 3 Each 1 word message
Fill[2:0] 0, 1, 2, 3, 4, 5, 6, 7 Each 1 word message LSBs of data word
Input registers
The input CVT is up to 512 words deep. Any parameter can go to any message(s).
www.acracontrol.com
324 3 Sep. 2008 | DST/N/071

The two types of message available are shown below.
3 Sep. 2008 | DST/N/071 325


1 DATA(0)+ ARINC-429 outputs Arinc-429 bus
2 DATA(0)- ARINC-429 outputs Arinc-429 bus
3 NC Not connected
4 NC Not connected
5 NC Not connected
6 NC Not connected
7 NC Not connected
8 NC Not connected
9 NC Not connected
10 NC Not connected
11 NC Not connected
12 NC Not connected
13 NC Not connected
14 NC Not connected
15 NC Not connected
16 NC Not connected
17 NC Not connected
18 NC Not connected
19 NC Not connected
20 NC Not connected
21 NC Not connected
22 NC Not connected
23 NC Not connected
24 NC Not connected
25 NC Not connected
26 NC Not connected
27 NC Not connected
28 NC Not connected
29 NC Not connected
30 NC Not connected
31 NC Not connected
32 NC Not connected
33 NC Not connected
34 NC Not connected
35 NC Not connected
36 NC Not connected
37 NC Not connected
38 NC Not connected
39 NC Not connected
40 NC Not connected
41 NC Not connected
42 NC Not connected
43 NC Not connected
44 NC Not connected
45 NC Not connected
46 NC Not connected
47 NC Not connected
48 NC Not connected
49 NC Not connected
50 NC Not connected
www.acracontrol.com
326 3 Sep. 2008 | DST/N/071

KAD/ARI/103, KAM/ARI/103
Single-channel ARINC-573 bus monitor
C O N T R O L
DESCRIPTION
The ARI/103 is an ARINC-573 bus monitor that supports
parsing of an ARINC-573(DFDR) bus on a major frame level
and error detection function on a single module.
In the discussion below “traffic” refers to words on the bus
and “tag” refers to associated information such as info words.
The parser triple buffers up to 2048 12-bit words (4
“sub-frames”) and their associated tags as a frame. The
status word that is buffered with each major frame indicates
whether the frame has been read before (STALE) or whether
the message was overwritten before it was read (SKIPPED),
FEATURES or whether the message has never been received (EMPTY),
• Decommutates one ARINC-573 channel as well as an error code.
• Coherently PARSEs traffic and tags for each major frame A valid frame is detected when all four sub frame sync words
• Supports a frame counter
are received, each followed by 63, 127, 255, or 511 data
• Detects Sync and Bit errors
words.
APPLICATIONS
• Monitoring of ARINC-573 DFDR bus
VERIFY T RIPLE
+ 1 SERIAL →
DAT A LOCK FRAME
- 2 PARALLEL
LOST BUFFER
SYMBOL SERIAL TO T RACKER

DET ECT PARALLEL
CONVERT OR
GND 51
ARI/103
Internal block diagram for ARI/103 module
24 Mar. 2009 | DST/R/018 327

Selection Paths
KAD/ARI/103 CON/KAD/002/CP ARI/103 module with 52-way double density module top connector
KAM/ARI/103 ACC/CON/008/04 ARI/103 module with 51-way micro-miniature module top connector
Revision History
ARI/103 First release Recommended for new programs
In this data sheet ARI/103 refers to both the KAD and KAM version of the module.
Related Products
Module Details
Document Details
www.acracontrol.com
328 24 Mar. 2009 | DST/R/018

Specifications

Mass
– 70 – g
Power consumption
+5V 73 – 74 mA
±7V 0 – 0 mA
±12V 0 – 0 mA
ARINC-573 inputs

Inputs – – 1 – ARINC-573 and ARINC-717 compatible.
Signaling rate
DATA 0.768 0.768 6.14 kbps
Physical layer
ARINC-573 and ARINC-717 – – – –
compatible
24 Mar. 2009 | DST/R/018 329

For parameter REPORT

Name REPORT REPORT
Base Unit Unitless Unitless R[15] Error received on the bus since last read
R[14] Syncword seen since list read
R[13] Bus is in lock
R[12:10]Reserved for future use
R[9:8] Error code
R[7] Stale - this frame has been read before
R[6] Skipped - this frame was overwritten at least once
R[5] Empty - no frames have been received yet
maximum
minimum
Size In Bits 16 16
For parameter FrmTimeHi

Name FrmTimeHi FrmTimeHi Hours and minutes when the last bit of the sync word from the first
minor frame was received.
Base Unit Unitless Unitless R[15:13] Reserved for future use
R[12:7] 00-23 hours
R[6:0] 00-59 minutes
maximum 11B916 005916
minimum 0
Size In Bits 16 16
For parameter FrmTimeLo

Name FrmTimeLo FrmTimeLo Seconds and centiseconds when the last bit of the sync word from
the first minor frame was received.
Base Unit Unitless Unitless R[15:0] 00.00-59.59 seconds
maximum 599916 027916
minimum 0
Size In Bits 16 16
For parameter FrmTimeMicro

Name FrmTimeMicro FrmTimeMicro Micro seconds when the last bit of the sync word from the first minor
frame was received.
maximum 999916 027916
minimum 0
Size In Bits 16 16
330 24 Mar. 2009 | DST/R/018

For parameter Data

Name Data Data ARINC 573 data word
Base Unit Unitless Unitless R[15:4] 000-FFF(16)
maximum FFF016 123016
minimum 0
Data Format OffsetBinary OffsetBinary
This module uses the X-Module-ARINC-573-Monitor-1.0. (See http://www.xidml.org).

Manufacturer
part reference KAD/ARI/103 KAD/ARI/103 ACRA CONTROL part number.
check for parity Yes or No
Setting up packages
This module uses the X-IRIG-106-Ch-4-1.1 schema. (See http://www.xidml.org).

Synchronous No No
acquisition
cycle
Data link No character limit MyARINCDataLink A named datalink, using X-ARINC-573-DataLink.
reference
Major frame
Properties
bits per minor 768, 1536, 3072, 768 Sets the number of bits in a minor frame, fixed for ARINC-573.
frame 6144
major frame
default data bits 12 12 Default number of bits per word.
per word
default most Last Last
significant bit
fill pattern AAAA16 AAAA16 hexBinary
default parity Odd, Even, None None
Synchronization
strategy
sync word 10 1110001001 Enter the sync word as hexadecimal. Synchronization bits is the
number of bits in the synchronization word.
In the XidML file the sync word pattern is binary. Minimal word length
is 4 bits for bit-rates of 8MHz and less, for higher bit-rates it is Bi-
trate[MHz]/2.
SFID
minor frame offset 10
bits
start value 0
increment 1
most significant Last
bit
24 Mar. 2009 | DST/R/018 331

For transaction channels (continued)

Modulation
PCM code DM-M Code used for bit transmission.
DCLK phase 0 or 180 0 Shifts the data clock in phase by 180°.
PCM polarity True or False True Shifts the PCM by 180°.
Content
parameter No character limit P1
number of data 12 12
bits
Fixed words can be used to generate sync words, SFID and so on. This is carried out automatically by the software.
Setting up datalinks
This module uses the X-ARINC-573-DataLink. (See http://www.xidml.org).

Data link
name MyARINC-573-DataL MyARINC-573-DataL
ink ink
rate 768, 1536, 3072, 768 Speed of transmission of the databus.
6144
Error codes for the ARI/103
002 Default - no errors 102 Syncword error
012 Bad bit 112 Reserved for future use
332 24 Mar. 2009 | DST/R/018

If parameters are super commutated, or samples of the same
parameter appear in different “sub-frames”, they will appear
in different DATA registers.
24 Mar. 2009 | DST/R/018 333


1 DATA+ ARINC-573 inputs ARINC-573 (DFDR) bus
2 DATA- ARINC-573 inputs ARINC-573 (DFDR) bus
www.acracontrol.com
334 24 Mar. 2009 | DST/R/018

KAD/CBC/101
A C R A KAM-500 CBC/101
C O N T R O L CAIS (Common Airborne Instrumentation Systems) bus controller
DESCRIPTION
The CBC/101 turns any KAM-500 chassis into a CAIS bus
controller. Each CBC/101 can be used to control up to 59
CAIS DAUs (1 of 60 DAUs is reserved for time-seeding).
In Normal (Acquire) mode, the CBC/101 retrieves samples
from all CAIS DAUs according to the selected format, and
buffers them within a CVT. From there they can be
redistributed throughout the entire acquisition system.
In Program mode, the CBC/101 translates incoming
FEATURES programming commands over the backplane into a CAIS
programming sequence. The commands are typically issued
• Allows any KAM-500 user-slot to be a CAIS bus controller from the programming system through a KAM-500 backplane
• Supports up to 8 formats controller module such as BCU/101.
• Multiple bus controllers in any chassis
Similarly, in Verify mode, the CBC/101 reads programmed
• Synchronizes KAM-500 CAIS DAUs for fully isochronous
EEPROM images from all CAIS DAUs as directed via the
operation
backplane. These images, which reside in an intermediate
• Operates with third-party CAIS DAUs
buffer, are then read via a backplane controller module out of
• Supports 12-bit and 16-bit operation
the acquisition system to the programming system.
APPLICATIONS Fully isonchronous operation throughout the entire distributed

acquisition system is provided when used in conjunction with
• Distributed data acquisition systems KAM-500 CAIS DAUs.
Timer
+ EEPROM
25
(8 formats)
RSP 75
- 26
Format
Controller
Status and report
CAIS
Encoder
and
+ Decoder
13 CVT
CMD
- 14
Buffer
GND 51 Programming
and Verification
Engine CBC/101
An internal block diagram of CBC/101
11 Nov. 2008 | DST/P/046 335

Selection Paths
Airborne Data Acquisition → KAM-500 → Modules → Bus → CAIS
KAD/CBC/101 ASD/BCU/002 CBC/101 module, with 52-way double density module top connector.
The ASD/BCU/002 mating connector must be ordered separately.
Revision History
CBC/101 First release Recommended for new programs

In this data sheet CBC/101 refers to both the KAD and KAM version of the module.
Related Products
Module Details
BCU/102 A CAIS compliant backplane controller
Document Details
www.acracontrol.com
336 11 Nov. 2008 | DST/P/046

Specifications
Inputs RSP±, D/E signal pair, CAIS compliant incoming response bus (internal 75Ω termination).
Outputs CMD±, D/E signal pair, CAIS compliant transformer coupled command bus.
Mechanical Can be placed in any user-slot in any combination.
Sampling The CBC/101 can be read over the backplane at more than 2Msps, in 16-bit mode up to 333ksps can be read
over the CAIS bus.
For register Data

Name Report DATA Data samples retrieved from CAIS bus according to the selected
format.
maximum
minimum
For register Report

Name Report REPORT
Base Unit Unitless Unitless R[15] New error observed on the response bus since last read
R[2] One DAU failed to respond during this acquisition cycle
(clears on SYNC)
R[1:0] Error code - please see table
maximum
minimum
For register STATUS(0) to STATUS(3)

Name Status STATUS_0 Status of module synchronization.
Base Unit Unitless Unitless R[15:0] ‘1’ indicates missed response from DAU, DAU[15:0]
R[15:0] ‘1’ indicates missed response from DAU, DAU[31:16]
maximum
minimum
11 Nov. 2008 | DST/P/046 337

This module uses the X-Module-CAIS-BC-1.0 XidML schema.
For transaction registers

Manufacturer
part reference KAD/CBC/101 KAD/CBC/101 ACRA CONTROL part number.
Interconnect 1 to 80 characters MyDatalink A connection to a named datalink.
Setting up packages
This module uses the X-CAIS-1.0 XidML schema.
Synchronous Yes or No Yes In asynchronous operation, the CVT of the encoder is triple-buffered
to allow the PCM transmission to be independent of the KAM-500
acquisition cycle, in synchronous operation it is dependent on the
KAM-500 acquisition cycle.
Packages per 1 1
acquisition
cycle
This module uses the X-DataLink-1.1 XidML schema.
Bits per word 10 to 16 16 Bits per data word
338 11 Nov. 2008 | DST/P/046

Error codes for the CBC/101
002 Reserved for future 102 Last bit error1

use
012 Parity 112 Reserved for future use
1. This bit is set when last bit received is too long

(>125ns).
Getting the most from the CBC/101

To enable programming via CAIS bus of connected CAIS
DAUs, the CBC/101 must be used in conjunction with the
BCU/101.
Fully isochronous operation can be achieved when used with
ACRA CONTROL CAIS DAUs.
In CONFIGURATION mode, the CBC/101 places each DAU
into a mode where its configuration can be read and CAIS
bus configuration can be determined.
In IBIT mode, the CBC/101 place all DAUs in Initiated Built-
In-Test. All DAUs capable of executing IBIT will do so. IBIT
results are stored in a specified location within the CVT.
In PROGRAM mode, the CBC/101 issues programming
commands (organized as 16-bit data words) to load
configuration data into the DAU's non-volatile memory.
In VERIFY mode, the CBC/101 reads data from the DAU's
non-volatile memory.
In NORMAL mode, the CBC/101 issues read commands on
the Command bus while DAUs operating in acquire mode
respond with data on the Response bus.
11 Nov. 2008 | DST/P/046 339

Connector pinout of KAD/CBC/101

1 NC Do not connect
2 NC Do not connect
3 NC Do not connect
4 NC Do not connect
5 NC Do not connect
6 NC Do not connect
7 NC Do not connect
8 NC Do not connect
13 CMD+ CAIS In CAIS command bus Transformer coupled
14 CMD- CAIS In CAIS command bus Transformer coupled
25 RSP+ CAIS Out CAIS response bus Transformer coupled
26 RSP- CAIS Out CAIS response bus Transformer coupled
www.acracontrol.com
340 11 Nov. 2008 | DST/P/046

KAD/CBM/101, KAM/CBM/101
A C R A KAM-500 CBM/101
C O N T R O L 4 channel cross channel data Link (CCDL) monitor
DESCRIPTION
The CBM/101 is a coherent CCDL bus monitor. It separately
parses (triple buffers) data from four independent buses.
Each channel consists of a bit finder followed by a serial to
parallel converter. After a valid preamble, 32 16-bit words
with no bit errors, and a valid postamble the message is
considered valid. Each valid message is then stored, along
with the time the first bit of the preamble appeared and the
message count for that channel. The message parser then
waits for the next message.
Errors reported include bad bit after preamble and postamble
FEATURES not correct. In the event of an error message the parser will
• Parses 4 x 2.5MHz CCDL busses immediately start looking for the next preamble.
• Coherently stores 32 traffic words per bus
• Adds stale, skipped and empty tags per message
• Adds message count and time tags per message
• Detects bit errors, and message length errors
• Features message counters on all four busses
APPLICATIONS
• CCDL bus monitoring
Message
+ 25
25 Bit-finder parser
CHANNEL(0) + Parellel
AMP
120
- →serial
- 26
26 Message and
tags triple buffered
CVT
GND 51
51
CBM/101
First of four independent CCDL parsers
5 Sep. 2008 | DST/P/064 341

Selection Paths
Airborne Data Acquisition → KAM-500 → Modules → Bus → CCDL
KAD/CBM/101 CON/KAD/002/CP CBM/101 module with 52-way double density module top connector
KAM/CBM/101 ACC/CON/008/04 CBM/101 module with 51-way micro miniature module top connector
Revision History
CBM/101 First release Recommended for new programs
Related Products
Module Details
Document Details
DOC/HBK/002 KAM-500 Environmental Qualifications Handbook
www.acracontrol.com
342 5 Sep. 2008 | DST/P/064

Specifications

Mass
– 66 – g
Power consumption
+5V 71 – 73.3 mA
+7V 0.8 – 0.8 mA
-7V 3.21 – 3.28 mA
+12V 2.6 – 2.68 mA
-12V 3.7 – 3.92 mA
RS-422 inputs

Signaling rate
DATA – – 2.5 Mbps
Input voltage
logic ‘0’ – – 0.2 V VIN+ - VIN-
logic ‘1’ 0.2 – – V VIN+ - VIN-
overvoltage protection -7.5 – 12.5 V Voltages outside of this range can damage input.
Input resistance
5 Sep. 2008 | DST/P/064 343

Setting up the CBM/101
:
<Parameters>
<ParameterTypeSet>
<ParameterType Name="MyTemperatureType">
<BaseUnit>Celsius</BaseUnit>
<RangeMaximum>500</RangeMaximum>
<RangeMaximum>-100</RangeMaximum>
</ParameterType>
</ParameterTypeSet>
<ParameterSet>
<Parameter Name="LeftWingTemperature">
<ParameterTypeReference>MyTemperatureType</ParameterTypeReference>
<Source>
<Package>
<InstrumentReference>MyCCDLModule</InstrumentReference>
<PackageReference>MyCCDLPackage</PackageReference>
1 <ParameterMap>CBM101_0_J3_D1_B0</ParameterMap>
</Package>
</Source>
:
</Parameter>
</ParameterSet>
</Parameters>
:

to
Parameter- Name N/A N/A No Each The ParameterMap element can be used to specify
1
Map module a location in a package.
For brevity, some code has been removed from the above example, code not shown is indicated by “:”
344 5 Sep. 2008 | DST/P/064

4 5
:
<Instrumentation>
<InstrumentSet>
:
<X-DAU-1.0 Name="MyDAU">
<Manufacturer>
<PartReference>KAM/CHS/13U</PartReference>
</Manufacturer>
</X-DAU-1.0>
:
2 <X-Module-CCDL-1.0 Name="MyCBM">
<Manufacturer>
5 <PartReference>KAD/CBM/101</PartReference>
</Manufacturer>
4 <SubLocation>3</SubLocation>
<Interconnect>MyCCDLPackage</Interconnect>
</X-Module-CCDL-1.0>
:
</InstrumentSet>
</Instrumentation>
:

to
Instrumen- Name N/A N/A Yes Each Name of module.
2
tReference module
3
SubLocation Number N/A N/A No Each The slot the module fits into. First user-module
4
module goes into slot 3.
5
ence module
5 Sep. 2008 | DST/P/064 345

Setting up Packages
:
<Packages>
<PackageSet>
:
<X-CCDL-1.0 Name="MyCCDLPackage">
<Synchronous>Yes</Synchronous>
<PackagesPerAcquisitionCycle>2</PackagesPerAcquisitionCycle>
<Content>
<Location>
6 <Offset_Bits>0</Offset_Bits>
</Location>
</Parameter>
:
</Content>
</X-CCDL-1.0>
:
</PackageSet>
</Packages>
:
Name Type Range Default Mandatory Applies Description Notes

to
Offset_Bits Integer N/A N/A Yes Each The location of a In the GUI this is set
6
package parameter in the package in units of 16-bit
in terms of bits from words, in XidML it is
beginning of the data set in bits.
stream
The field definition table explains the extracts shown opposite for the kSetup GUI and corresponding XidML task file for one
channel of the KAD/CBM/101.
346 5 Sep. 2008 | DST/P/064

Output registers
The diagram shows the 153 registers that can be read from the CBM/101
PARSER One of 4 busses DATA_31

DATA_0
TIME_HI
TIME_LO
TIME_MICRO
INSTANCE
INFO
MESSAGE_COUNT One of 4 busses COUNTER
REPORT

DATA_ Data word stored in PARSER. DATA_0 is first 16-bits, DATA_31 is last 16 bits.
R[15:0] Bits received (less preamble and post-amble bits), R(15) is FBR R(15)
TIME_MICRO Microsecond time at time Tst as indicated in Figure 1.1
TIME_LO Seconds and centiseconds at time Tst as indicated in Figure 1.1
R[15:0] BCD 00.00-59.99 sec. R(15)
TIME_HI Hours and minutes at time Tst as indicated in Figure 1.1
R[12:7] BCD 00-23 hours R(12)
INSTANCE The message count when message is received
INFO Stale/skipped indication for this PARSED message
R(15) 1 indicates that this parser slot is empty R(15)
R(14) 1 indicates this message was read before R(14)
R(13) 1 indicates this message overwrote another R(13)
REPORT R(15) Error on Bus 3 R(15)
R(14) Reserved for future use R(14)
R[13:12] See Error codes R(13)
R(11) Error on Bus 2 R(11)
COUNTER R[15:0] Message counter on one of the 4 busses R(15)
FBR = First Bit Received

5 Sep. 2008 | DST/P/064 347

Error codes for the CBM/101
00 Default value after power-up 10 Postamble not correct or message too long
01 Bad-bit after preamble 11 Reserved for future use
Error codes are in binary.
Getting the most from the CBM/101

Typically the report and counter words are only used for debug.
Tl
200ns 200ns 600ns 200ns
200ns 200ns 600ns 200ns
Preamble = 2.4μs Middle of preamble

Th
Preamble Data[15:0] x 32 Postamble

Data = 16 x 32 x 0.4μs = 204.8μs
200ns 600ns 200ns

200ns
200ns 600ns 200ns

200ns
Manchester 1 = 0.4μs Postamble = 2μs
Th, Tl >180ns
Inter-message gap can be one of the following:
(a) Manchester encoded 1s or 0s
(b) High always, or low always, or tri-state
Figure 2: CCDL frame structure
348 5 Sep. 2008 | DST/P/064

Connector pinout of the KAD/CBM/101

1 NC Not connected
2 NC Not connected
3 NC Not connected
4 NC Not connected
5 NC Not connected
6 NC Not connected
7 NC Not connected
8 NC Not connected
9 NC Not connected
10 NC Not connected
11 NC Not connected
12 NC Not connected
13 NC Not connected
14 NC Not connected
15 NC Not connected
16 NC Not connected
17 NC Not connected
18 NC Not connected
19 NC Not connected
20 NC Not connected
21 NC Not connected
22 NC Not connected
23 NC Not connected
24 NC Not connected
25 Channel(0)+ RS-422 inputs D/E input, internally terminated with 120Ω
26 Channel(0)- RS-422 inputs D/E input, internally terminated with 120Ω
27 NC Not connected
28 NC Not connected
29 NC Not connected
30 NC Not connected
31 NC Not connected
32 NC Not connected
33 NC Not connected
35 NC Not connected
36 NC Not connected
37 NC Not connected
38 NC Not connected
40 NC Not connected
41 NC Not connected
42 NC Not connected
43 NC Not connected
48 NC Not connected
49 NC Not connected
www.acracontrol.com
350 5 Sep. 2008 | DST/P/064

KAD/CBM/102, KAM/CBM/102
A C R A KAM-500 CBM/102 CAN bus monitor

C O N T R O L
DESCRIPTION
The CBM/102 is a CAN bus monitor which parses CAN bus
traffic and tags each message for up to four CAN bus 2.0 A/B
busses.
It combines a coherent message parser, message counter
and error detection functions in a single module. In the
following discussion, traffic refers to words on the bus (data,
error and remote) and tags refer to associated information:
microsecond time of start of frame (SOF) bit transition,
message count, response time and errors.
The PARSER buffers up to 126 complete messages per bus
FEATURES and their associated tags in triple buffers. The INFO tag
• Four controller area network (CAN) bus monitors associated with each message has a STALE bit (message
• CAN 2.0 A/B compliant with support for CAN aerospace read before) a SKIPPED bit (buffer overwritten) and an
message headers EMPTY bit (message was never received). MsgCnt
• Data, remote, error and overload frame support increments on receipt of a valid message. The REPORT
• Up to 126 complete messages per bus can be parsed word has bits indicating that an error occurred and on which
• Messages can be tagged with time and message count bus it occurred.
(they are not tagged by default in the GUI)
• Silent (monitors only, does not transmit or acknowledge)
• Programmable bit-rate per bus
APPLICATIONS
• CAN bus monitor
CANH
CANL
TIMER
+
1
DATA(0)
-
2
PHYSICAL SYMBOL DETECT AND TIMING WORD FINDER
LAYER TO TTL
Lock
Verify
TRIPLE BUFFERED MESSAGE X 504
Lost
PROTOCOL TRACKER
GND
51
CBM/102
First of four independent busses
1 May 2008 | DST/L/043 351

Selection Paths
Airborne Data Acquisition → KAM-500 → Modules → Bus → CAN
KAD/CBM/102 CON/KAD/002/CP CBM/102 module with 52-way double-density module top connector
KAM/CBM/102 ACC/CON/008/04 CBM/102 module with 51-way micro-miniature module top connector
Revision History
CBM/102 First release Recommended for new programs
In this data sheet CBM/102 refers to both the KAD and KAM version of the module.
Related Products
Module Details
Document Details
www.acracontrol.com
352 1 May 2008 | DST/L/043

Specifications

Mass
– 66 – g
Power consumption
+5V 75 – 105 mA
±7V 0 – 0 mA
±12V 0 – 0 mA
total power 375 – 525 W
CAN bus interface

Inputs – – 4 – CAN bus 2.0 A/B compatible.
Sampling rate
DATA[3:0]± – – 1 Msps
Physical layer
CAN bus 2.0 0.05 – 1 Msps
Supported baud rates 10 – 1000 kbps 10, 20, 100, 125, 250, 500, 1000
1 May 2008 | DST/L/043 353

For register MsgCnt
Name MsgCnt CBM102_MsgCnt The current value of the message count for each bus.
Base Unit Unitless Unitless R[15:0] 000016-FFFF16, resets at FFFF16.
maximum FFFF16 FFFF16
minimum 000016 0
Data Format Hexadecimal Hexadecimal
Size In Bits 16 16
For register MsgExtIdHi

Name MsgExtIdHi CBM102_ The MSBs of the extended identifier.
MsgExtIdHi
Base Unit Unitless Unitless R[15:0] EID [17:2].
minimum 000016 0
Size In Bits 16 16
For register MsgExtIdLo

Name MsgExtIdLo CBM102_ The LSBs of the extended identifier.
MsgExtIdLo
Base Unit Unitless Unitless R[15:13] EID [2:0].
minimum 000016 0
Size In Bits 16 16
For MsgInfo
Name MsgInfo MsgInfo Stale/skipped indication for this PARSED message
Base Unit Unitless Unitless R(15) ID is empty (no message received).
R(14) 1 indicates this message was read before.
R(13) 1 indicates this message overwrote another.
maximum E00016 000216
minimum 0 0
Size In Bits 16 16
For register MsgStdId

Name MsgStdId CBM102_MsgStdId The standard identifier.
Base Unit Unitless Unitless R[15:5] ID [10:0].
R(4) SRR Standard frame remote transmit request bit.
R(3) IDE Extended identifier flag.
minimum 000016 0
Size In Bits 16 16
354 1 May 2008 | DST/L/043

For register MsgDLC
Name MsgDLC CBM102_MsgDLC DLC.
Base Unit Unitless Unitless R[15:12] Data length code.
minimum 000016 0
Size In Bits 16 16
For register MsgTimeMicro

Name MsgTimeMicro CBM102_ Microsecond time midway through message start bit.
MsgTimeMicro
Base Unit Unitless Unitless R[15:0] 0000 to 9999 microseconds.
minimum 000016 0
Size In Bits 16 16
For register MsgTimeLo

Name MsgTimeLo CBM102_ Seconds and centiseconds time midway through message start bit.
MsgTimeLo
Base Unit Unitless Unitless 00.00 to 59.99 seconds.
minimum 000016 0
For register MsgTimeHi

Name MsgTimeHi CBM102_ Hours and minutes time midway through message start bit.
MsgTimeHi
Base Unit Unitless Unitless R[15:13] Reserved for future use.
R[12:7] 00 to 23 hours.
R[6:0] 00 to 59 minutes.
maximum 11D916 11D916
minimum 000016 0
For register PackageData

Name PackageData CBM102_
PackageData
Base Unit Unitless Unitless D[15:8] First 8-bit word
D(15) is MSB.
D[7:0] Second 8-bit word (if present)
D(7) is MSB.
minimum 000016 0
1 May 2008 | DST/L/043 355

For register REPORT
Name REPORT CBM102_REPORT Indicates status of monitor.
Base Unit Unitless Unitless R(15) 1 indicates error occured since last read.
R[3:0] Indicates the bus the error occurred on.
maximum 800F16 800F16
minimum 000016 0
This module uses the X-Module-Pcm-Out-1.1 schema.
Manufacturer
part reference KAD/CBM/102 KAD/CBM/102 ACRA CONTROL part number.
InterConnect 0 or 1 Port 1 InterConnect associates a named datalink with a named datalink.
356 1 May 2008 | DST/L/043

Connector pinout of the KAD/CBM/102

1 DATA(0)+ CAN bus interface High level CAN bus (receive only)
2 DATA(0)- CAN bus interface Low level CAN bus (receive only)
www.acracontrol.com
358 1 May 2008 | DST/L/043

KAD/DEC/003, KAM/DEC/003
A C R A KAM-500 DEC/003
2 channel IRIG-106 PCM decoder/merger
C O N T R O L
DESCRIPTION
The DEC/003 is a dual PCM decommutator that can accept
two independent PCM streams. Data from each stream is
individually parsed into minor frame buffer from which it can
be read coherently over the backplane.
The DEC/003 is ideally suited to merge two PCM streams in
a distributed acquisition systems with a star configuration.
In a typical distributed acquisition system where each
KAM-500 is operated synchronously, the DEC/003 runs in
synchronous mode. Data is decommutated by the decoder
before it is read over the backplane. In this mode there is no
FEATURES need for stale or skipped indication.
• Decommutates two IRIG-106 PCM streams
When decommutating data from an encoder running
• Accepts BIØ-L or NRZ-L codes asynchronously, data is parsed into coherent buffer. All
• Up to 20Mbps for NRZ-L and 8Mbps for BIØ-L
parameters read are guaranteed to be from the same minor
• Up to 4k words per minor frame
frame. If data us read slower than it is received, minor frames
• Programmable word length (4-64) per word are skipped occasionally. If data is read faster than it is
• Programmable parity (odd/even/none) per word
received, minor frames are repeated (stale) occasionally. In
• Programmable word orientation per word
asynchronous mode it is recommended that the stale and
• Operates in synchronous mode with other KAM-500s skipped indication be read.
• Operates in asynchronous mode with third-party PCM
encoders
APPLICATIONS
• Distributed data acquisition systems
• PCM decoders/mergers
+ 1
DATA(0) +
- LOCK
2
- SERIAL →
3 PARALLEL VERIFY
+ +
LOST
DCLK(0) -
4
-
GND 11
DEC/003
DCLK IS NOT NEEDED FOR BIΦ -L
First of two independent PCM decommutators
27 Nov. 2008 | DST/N/039 359

Selection Paths
Airborne Data Acquisition → KAM-500 → Modules → Bus → IRIG-106
KAD/DEC/003 CON/KAD/002/CP DEC/003 module with 52-way double density module top connector
KAM/DEC/003 ACC/CON/008/04 DEC/003 module with 51-way micro-miniature module top connector
Revision History
DEC/003 Max. data rate increased from 2Mbps to 20Mbps for NRZ-L Recommended for new programs
DEC/002 First release Obsolete
In this data sheet DEC/003 refers to both the KAD and KAM version of the module.
Related Products
Module Details
BCU/101 KAM-500 backplane controller with IRIG-106 PCM encoder
ENC/005 IRIG-106 PCM encoder
Document Details
www.acracontrol.com
360 27 Nov. 2008 | DST/N/039

Specifications

Mass
– 60 – g
Power consumption
+5V 320 – 360 mA
RS-422 inputs

Signalling rate
Data 0 – 20 Mbps NRZ-L (8 Mbps for BIO-L).
Input voltage
operating range -7.5 – 12.5 V Do not exceed operating range.
logic ‘0’ – – 0.2 V (50mv hysteresis) VIN+ - VIN-
logic ‘1’ 0.2 – – V (50mv hysteresis) VIN+ - VIN-
overvoltage protection -7.5 – 12.5 V Voltage in excess of these values can damage input.
ESD protection – 8 – kV Human Body Model.
Input resistance
between inputs – – – MΩ Module powered on.
between inputs 12 19 – kΩ Module powered off.
between inputs – 120 – Ω Module powered on and inputs terminated.
between inputs – 120 – Ω Module powered off and inputs terminated.
each input to GND – 1.22 – MΩ Module powered on.
each input to GND – 11.7 – kΩ Module powered off.
27 Nov. 2008 | DST/N/039 361

Setting up the DEC/003
<Parameters>
<ParameterTypeSet>
<ParameterType Name="MyStatusType">
<BaseUnit>BitVector</BaseUnit>
</ParameterType>
</ParameterTypeSet>
<ParameterSet>
1 <Parameter Name="DEC3_STATUS">
<ParameterTypeReference>MyStatusType</ParameterTypeReference>
<Source>
<Signal>
<InstrumentReference>MyDEC</InstrumentReference>
2
<VendorMap>STATUS</VendorMap>
</Signal>
</Source>
:
</Parameter>
</ParameterSet>
</Parameters>

to
Parameter Name N/A N/A Yes Each The name corresponding to the channel
1
Name parameter
VendorMap Selection N/A N/A Yes Each Selection of registers, please see Module Regis-
2
parameter ters for more details
<Instrumentation>
3 <X-Module-Pcm-In-1.1 Name="MyDEC">
<Manufacturer>
6 <PartReference>KAD/DEC/003</PartReference>
</Manufacturer>
4
<Location>MyDAU</Location>
5
<SubLocation>3</SubLocation>
<Interconnect>MyTTL_PCMDataLink</Interconnect>
<Settings>
<Module-Pcm-In-1.1>
<Bus Index="0">
<SyncWordMask>FFFFFFFF</SyncWordMask>
</Bus>
</Module-Pcm-In-1.1>
</Settings>
</X-Module-Pcm-In-1.1>
</Instrumentation>

to
InstrumentReference Name N/A N/A Yes Each Name of module from which parameter
3
module is sourced.
4
362 27 Nov. 2008 | DST/N/039

to
SubLocation Number N/A N/A No Each The slot the module fits into. First
5
module user-module goes into slot 3.
PartReference Selection N/A N/A No Each ACRA CONTROL part number.
6
module
The number of necessary synchronization words to consider frame lock, and errors to cause a frame loss, is fixed. For more
information, see “Getting the most from the DEC/003” on page 364.
Output Registers
The diagram below illustrates the 8,194 registers that can be read from the DEC/003.
DATA DATA
One of 2 busses One of 4096 data words
STATUS BUS_STS
One of 2 busses
Figure 2: Choosing a parameter to be read from the KAD/DEC/003
DATA Serial bits received
R[15:0] The number of MSBs and the orientation depends on the word length and received R(15)
MSB first/last specified in setup
STATUS Status of the bus
R(15) Error received on the bus since last read
R(14) Sync word since last read
R(13) The bus is in lock
R[9:8] Error code R(9)
R(7) Stale, this frame has been read before (asynchronous mode only)
R(6) Skipped, one or more frames has been skipped (asynchronous mode only)
R(5) Empty, no frames have been received
Error codes for the DEC/003
0 Bit error 10 Sync word error
1 Parity error 11 Reserved for future use
27 Nov. 2008 | DST/N/039 363

Getting the most from the DEC/003
Frame lock and loss
The number of necessary synchronization words to consider
frame lock, and errors to cause a frame loss, is fixed, and
therefore cannot be reprogrammed.
The DEC/003 is considered to be locked when two
consecutive synchronization words are received correctly at
the expected location and no other bit errors have been
detected.
The DEC/003 will miss a frame immediately after detecting a
bit error (illegal bit), parity or syncword error.
In summary, two synchronization words will cause a frame
lock and more than one bit error will cause a frame loss.
Asynchronous mode
In asynchronous mode, if the data is read slightly faster (for
example, 1% faster) than it is being received, data will never
be missed. However, it will sometimes be repeated (1 in 100
frames in that case).
Frame structure
The DEC/003 is a minor-frame decoder only and therefore
the default number of minor-frames per major-frame is one.
364 27 Nov. 2008 | DST/N/039

Connector pinout of the KAD/DEC/003

1 DATA(0)+ RS-422 inputs PCM data; first bus
2 DATA(0)- RS-422 inputs PCM data; first bus
3 DCLK(0)+ RS-422 inputs PCM data clock; first bus
4 DCLK(0)- RS-422 inputs PCM data clock; first bus
5 DATA(1)+ RS-422 inputs PCM data
6 DATA(1)- RS-422 inputs PCM data
7 DCLK(1)+ RS-422 inputs PCM data clock
8 DCLK(1)- RS-422 inputs PCM data clock
29 NC Not connected
30 NC Not connected
31 NC Not connected
32 NC Not connected
33 NC Not connected
34 NC Not connected
35 NC Not connected
36 NC Not connected
37 NC Not connected
38 NC Not connected
39 NC Not connected
40 NC Not connected
41 NC Not connected
42 NC Not connected
43 NC Not connected
44 NC Not connected
45 NC Not connected
46 NC Not connected
47 NC Not connected
48 NC Not connected
www.acracontrol.com
366 27 Nov. 2008 | DST/N/039

KAD/EBM/101, KAM/EBM/101
A C R A KAM-500 EBM/101 Ethernet bus monitor

C O N T R O L
• Detection of system failures and performance problems
• Filters network management traffic and non-IP packets
• AFDX monitoring
DESCRIPTION
The EBM/101 is designed to accept Fast Ethernet
(100BaseTX) or Ethernet (10BaseT) traffic, parse it, and
distribute it to other KAM-500 modules.
Ethernet traffic is parsed on the IP layer. The EBM/101 can
classify traffic using 8 x 16-bit frame fields such as MAC
addresses, IP addresses, IP length, protocol type
FEATURES (UDP/TCP), UDP or TCP port numbers. Up to 254 unique
• IEEE 802.3u (100BaseTX) and 802.3i (10BaseT) flows can be identified, where a flow represents a stream of
information from a specific source to a specific destination.
standards compatible Ethernet interface
• Monitors single network link The identification is based on the classification parameters
• Parses (triple buffers) and classifies Internet Protocol (IP) with optional masking. All other traffic, excluding network
management traffic such as ARP and ICMP-PING, is
packets
• Identifies and monitors 254 different flows plus one catchall optionally discarded or else monitored via Parser Slot-ID 254.
• Supports flow identification on selected frame fields (8 x ARP-Requests and ICMP-PING-Requests are replied to.
Flows are tagged with timestamps and packet count. The
16-bit fields) such as Ethernet MAC addresses, IP
addresses, and Layer 3 (UDP/TCP) ports EBM/101 can optionally operate in a promiscuous mode,
• Can be programmed to operate in promiscuous mode which allows it to observe all traffic on the link, not only
packets that are addressed to it.
• Features ‘valid’ and ‘error’ frame counters and error
detection on Ethernet and IP layers
APPLICATIONS
• Monitoring, recording, diagnosis and troubleshooting of
Ethernet network traffic
RX+ 1
Packet
RX- 2
Physical interface classification, Packet

and MAC error detection and buffer
TX+ 18
filter
TX- 19
Triple buffered
Flow
message
identification
memory
GND 51
EBM/101
Single Ethernet link frame parser
25 Mar. 2009 | DST/R/049 367

Selection Paths
Airborne Data Acquisition → KAM-500 → Modules → Ethernet
KAD/EBM/101 CON/KAD/002/CP EBM/101 module with 52-way double density module top connector
KAM/EBM/101 ACC/CON/008/04 EBM/101 module with 51-way micro miniature module top connector
Revision History
EBM/101 First release Recommended for new programs
Related Products
Module Details
Document Details
www.acracontrol.com
368 25 Mar. 2009 | DST/R/049

Specifications

Mass
– 74 – g
Power consumption
+5V 197 – 365 mA
±7V 0 – 0 mA
±12V 0 – 0 mA
Ethernet interface

Inputs/outputs – – 1 – IEEE 802.3 compatible.
25 Mar. 2009 | DST/R/049 369

Setting up the EBM/101
All module setup can be defined in XML using XidML schemas (see www.xidml.org).
The following treeview provides an overview of setup configurations available for the EBM/101:
XidML Legend
DAU: Data Acquisition Unit
Instrument: Any component or module

used in a data acquisition system.
DataLink: Connection for transmitting or

receiving (defines both the data link and the
physical layer).
Package: Used to describe how data is

transmitted or stored.
Parameter: Any register that can be read

from an instrument.
370 25 Mar. 2009 | DST/R/049

Setting up the Module
The following table lists the setup configurations available for the EBM/101:

Manufacturer
Name ACRA CONTROL ACRA CONTROL
PartReference KAD/EBM/101 KAD/EBM/101 ACRA CONTROL part number
SerialNumber FE1234 Fixed 6 characters
Connections
ETHERNET-IN No character limit MyEthernetDataIn Ethernet data input
Module-Ethernet-Monitor-1.0
MessageBuffers
MessageBuffer - Parser(254) Parser slot for unclassified packages
(excluding network management traffic)
MessageReference No character limit MyUnclassifiedPackage References an unclassified package
monitor definition
MessageBuffer - Parser[253:0] Parser slots for classified packages
MessageReference No character limit MyClassifiedPackage References a package classification
definition
OperatingMode Non-promiscuous Promiscuous Promiscuous mode allows monitoring of
Promiscuous all network traffic. Non-promiscuous
mode filters out traffic other than that
addressed to the module's network
MAC address including broadcast
traffic.
NetworkMode Static Static
NetworkManagementDiscard Enabled Disabled Disabling allows processing of received
Disabled ARP-/PING- requests and generation of
appropriate response packets. Also all
ARP-/PING- requests will be rooted to
parser slot 254. If set to Enabled all
ARP-/PING- requests will be discarded.
VLANSupport Enabled Disabled Enabling allows slot parser to skip over
Disabled VLAN packet headers, if present, to
classify traffic on basis of IP and
UDP/TCP packet header fields.
DiscardMode Enabled Disabled Enabling imposes discard of all traffic
Disabled not specifically classified into parser
slots 0 to 253. Disabling causes routing
of all such traffic to parser slot 254.
NetworkConnections
Connection - Port(0)
IPAddress 192.168.1.1 IP address of module; required to
generate ARP / PING - response, that
is, if NetworkManagementDiscard is
Disabled.
MACAddress 00-0C-4D-1A-1B-1C Ethernet address of module; required to
generate ARP / PING - response, that
is, if NetworkManagementDiscard is
Disabled. Also required if
OperatingMode is NonPromiscuous.
25 Mar. 2009 | DST/R/049 371

Parameter Definitions
The following table lists the parameters that are available from the EBM/101:

Report Unitless BitVector 16 R[15:1] Reserved for future use
Reports status of module operation R(0) Error Code: 0 indicates link is not
connected; 1indicates no error
FrameCount Count OffsetBinary 16 R[15:0] 0000:FFFF
Frame count on the network link
MessageSize Unitless OffsetBinary 16 R[10:0] 0040:05EE
Received frame size in bytes
MessageCount Count OffsetBinary 16 R[15:0] 0000:FFFF
Received frame count in the parser slot
MessageTimeHi Unitless BitVector 16 R[15:13] Reserved for future use
Hours and minutes of the 44 bit time R[12:7] Time[43:38] BCD hours 00:23
register. Time at start of first received bit R[6:0] Time[37:31] BCD minutes
00:59
MessageTimeLo Second BCD 16 R(15) Reserved for future use
Seconds and centiseconds of the 44 bit R[14:8] Time[30:24] Seconds 00:59
time register. Time at start of first received R[7:0] Time[23:16] Centiseconds
bit 00:99
MessageTimeMicro Second BCD 16 R[15:0] Time[15:0] Microseconds
Microseconds of the 44 bit time register. 0000:9999
Time at start of first received bit
MessageInfo Unitless BitVector 16 R(15) 1 indicates that there is no
Information about parsed message message stored (EMPTY)
R(14) 1 indicates this message was
read before (STALE)
R(13) 1 indicates this message
overwrote another (SKIPPED)
MessageStatus Unitless BitVector 16 R[15:3] Reserved for future use
Status of IP packets parsed R(2) 1 indicates a bad IP Header
Checksum
R(1) 1 indicates IP version is not Ipv4
MessageData Unitless BitVector 16 R[15:0] 0000:FFFF
Data captured from Ethernet frames
A datalink is a connection for transmitting and receiving data. It defines both the datalink and physical layers of the link.
The following table lists the datalinks supported by the KAD/EBM/101:
ETHERNET-IN
Ethernet data connection

ProtocolProperties
BitRate 100E6 100E6 Set according to the bit-rate of the
10E6 network to be monitored
372 25 Mar. 2009 | DST/R/049

Setting up Packages
UnclassifiedNetworkPackages
Defines package for monitoring of unclassified traffic

DataLink Reference No character limit MyEthernetDataIn References a datalink carrying Ethernet
data
Content
Parameter
Location
Offset_Bytes 1517:0 1024 Offset of desired data in the filtered
package
ClassifiedNetworkPackages
Defines package classification using masking

DataLinkReference No character limit MyEthernetDataIn References a datalink carrying Ethernet
data
Properties
HashBinary HashBinary is used to specify values to
be found at the 8 classification offsets.
Each package can have up to 8
HashBinary elements for the 8 offsets.
Value This is a 16 bit binary value used for
packet classification. Its context is
defined by its sibling
OffsetIndex_Words. For example, if
OffsetIndex_Words was set to 13 (and
VLAN support was disabled), this would
mean that the 16 bit value would
represent the first two octets of the
source IP address in the IP packet
header. So if this value was set to
1100000010101000, it would mean that
you are interested in data being sent
from a host whose IP address begins
with 192.168.
OffsetIndex_Words 29:0 Not Specified This element sets the context for packet
classification. Think of it as a window to
slots of 16 bit data. For example, if you
set it to 0 you will see the first 16 bits of
a Destination MAC address; or if you set
it to 5 you will see the last 16 bits of a
Source MAC address. This is used in
conjunction with its sibling, Value, to
classify packets.
Content
Parameter
Location
Offset_Bytes 1517:0 1024 Offset of desired data in the filtered
package
25 Mar. 2009 | DST/R/049 373

Getting the most from the EBM/101 Monitoring unfiltered traffic via a hub
The EBM/101 can be used to parse and classify IP packets, The EBM/101 monitors unfiltered traffic at the common star
which are transported over an Ethernet network link. Ethernet point established by the hub. Ethernet packets cannot be
traffic rates up to 100Mbps bandwidth are supported. delayed or filtered in the hub. However, hubs should not be
used to monitor full-duplex Ethernet links, as operation is
100BaseTX physical layer medium is defined as 100Ω CAT5
restricted to half-duplex mode only, thus making hubs
UTP cable. Link auto-negotiation is supported to establish
susceptible to collisions, which will result in frames with
10/100Mbps full-/half-duplex modes.
errors.
Monitoring network traffic via a passive
network tap
Node C (PC)
The EBM/101 monitors true full-duplex traffic per link in
real-time. Port 3
100Mb/s
Port 4 Hub Port 2 EBM/101
Port 0 Port 1
Node D (PC)
Switch
Port A Port B
Full-duplex link
(2 x 100Mb/s)
EBM/101
Port X 100Mb/s
Full-duplex link
(2 x 100Mb/s) Half-duplex link Half-duplex link
TAP (100Mb/s) (100Mb/s)
100Mb/s
Port Y
EBM/101
Node A (PC) Node B (PC) Node A (PC) Node B (PC)
Figure 2: Ethernet monitoring via tap Figure 4: Ethernet monitoring via hub
Monitoring network traffic via a switch EBM/101 limitations

The EBM/101 can monitor filtered traffic as managed by the ARP and PING packets addressed to the EBM/101 will be
switch. Ethernet packets can be delayed, reordered, or even replied to only if the EBM/101 is connected to the network via
lost in the switch. a switch or hub, but not via a tap.
The EBM/101 does not reply to a PING if the PING

buffer size is not 32 bytes (Windows default size).
Node C (PC)
Non-Windows operating systems, for example
Linux and UNIX, may have a default size which is
Port 3
Switch Port 2 100Mb/s not 32 bytes, in which case the EBM/101 does not
Port 4 EBM/101
Port 0 Port 1
reply. To ensure the EBM/101 can reply to a PING,
the PING buffer size must be set to 32 bytes using
Node D (PC) the PING command switch “-I 32”.
The EBM/101 might not be able to reply to a PING

from a UNIX workstation. The EBM/101 is
Full-duplex link Full-duplex link expecting the "Target MAC Address" field in the
(2 x 100Mb/s) (2 x 100Mb/s) ARP-Request frame to contain 00-00-00-00-00-00.
The ARP-Request from UNIX may set this field to
FF-FF-FF-FF-FF-FF, such that the EBM/101
rejects the ARP-Request and does not reply.
Without successful ARP it is impossible for PING to
Node A (PC) Node B (PC)
work.
Figure 3: Ethernet monitoring via switch A combination of high data rate (more than 85Mbps) and
small packets (less than 112 bytes) can lead to packet loss
A managed switch can be used to filter traffic to the switch (0.5%) due to a hardware FIFO overflow. Lower average data
port connecting to the EBM/101. rates may also experience packet loss if the peak burst rate
exceeds 85Mbps. Packet loss can be reduced by setting up
Unmanaged switches may require the switch port connecting the instrumentation such that packets of no interest to the
to the EBM/101 to be stimulated via PING request/reply user, (that is, which are not classified to user-specified
packets to prevent the switch port from dropping an "inactive parser-slots) are discarded rather than being classified to the
link". Unmanaged switches may not forward all traffic to the catchall parser-slot.
switch port connecting to the EBM/101.
374 25 Mar. 2009 | DST/R/049

Packet classification example: In this case, five Ethernet frame fields (Fields-11/13/14/15/16)
are classified as follows:
IP Packets can be classified into any of 254 unique parser
slots on the basis of frame/packet header field values and/or • xx11/C0A8/0137/xxxx/xxxx => route to parser slot 0
data. Eight fields may be specified within the Ethernet frame, • xx11/xxxx/xxxx/C0A8/0137 => route to parser slot 0
where each field has 16-bit size and granularity. • xx06/C0A8/0137/xxxx/xxxx => route to parser slot 1
• xx06/xxxx/xxxx/C0A8/0137 => route to parser slot 1
• The EBM/101 is being used to monitor packets using a
switch, where the switch has been set up to forward all IP This is a simple example classifying data packets using only
packets received on ports A/B/C/D to the EBM/101 via port five of the eight available fields. More complicated
L, but not traffic received on ports E/F/G. Thus the switch is classification is possible, using for example the Ethernet
performing a very coarse filtering of data. MAC addresses in the case where IP addresses are not
• The traffic to be monitored is dialog involving Node-A predetermined (in a network where a server allocates IP
(connected to port A) and the other nodes connected to addresses using the DHCP protocol), or using fields to
ports B/C/D. distinguish between higher-layer protocol packets such as
• TCP and UDP traffic will be monitored. HTTP (web browser traffic) or FTP (file transfer).
• The network is configured with static IP addresses, that is
Values of OffsetIndex_Words
the IP address is predetermined and known (as opposed to
dynamic IP addressing where a server allocates addresses Field name Offset if Offset if
to the network nodes using Dynamic Host Configuration VLAN VLAN
Protocol [DHCP]). The IP address of Node-A is disabled enabled
192.168.1.55 (on a Windows PC the IP address can be
determined from DOS shell using the command Destination MAC address, word 0 0 0
"ipconfig /all"). Destination MAC address, word 1 1 1
• It is not essential to know the Ethernet MAC address (or
"Physical address") of Node-A or any of the nodes with Destination MAC address, word 2 2 2
which it is communicating, as the IP address is a unique
identifier for the node on the network. Source MAC address, word 0 3 3
Source MAC address, word 1 4 4

In this example:
Source MAC address, word 2 5 5
The EBM/101 is set up to filter packets sent by Node-A, and
packets destined to Node-A. Frame type 6 8
• Packets sent by Node-A will have the field "IP Source VLAN priority/ID N/A 7
address" = 192.168.1.55.
• Packets destined to Node-A will have the field "IP IP version/IHL/ToS 7 9
Destination address" = 192.168.1.55.
IP packet size 8 10
• 192.168.1.55 is a 32-bit number represented in hex
notation as C0A8013716. IP ID 9 11
• The IP Source address field is located within an Ethernet
frame in 16-bit fields 13 and 14. IP flags and fragment offset 10 12
• The IP Destination address field is located within an IP TTL and protocol 11 13
Ethernet frame in 16-bit fields 15 and 16.
• TCP traffic is distinguished by the 8-bit "IP Protocol Field" = IP header checksum 12 14
0616.
Source IP address, word 0 13 15
• UDP traffic is distinguished by the 8-bit "IP Protocol Field"
= 1116. Source IP address, word 1 14 16
• The IP Protocol field is located within an Ethernet frame in
Destination IP address, word 0 15 17
the lower byte of 16-bit field 11.
Thus the EBM/101 may be configured as follows: Destination IP address, word 1 16 18
• UDP traffic sent from Node-A will be routed to parser slot 0. Source port no. 17 19
• UDP traffic sent to Node-A will be routed to parser slot 1.
Destination port no. 18 20
• TCP traffic sent from Node-A will be routed to parser slot 2.
• TCP traffic sent to Node-A will be routed to parser slot 3. UDP Length; TCP seq word 0 19 21
In this case, five Ethernet frame fields (Fields-11/13/14/15/16) UDP CSum; TCP seq word 1 20 22
are classified as follows:
IENA key; TCP Ack word 0 21 23
• xx11/C0A8/0137/xxxx/xxxx => route to parser slot 0
• xx11/xxxx/xxxx/C0A8/0137 => route to parser slot 1 IENA size; TCP Ack word 1 22 24
• xx06/C0A8/0137/xxxx/xxxx => route to parser slot 2
• xx06/xxxx/xxxx/C0A8/0137 => route to parser slot 3 IENA date 0; TCP offset/flags 23 25
Or, alternatively, the EBM/101 may be configured as follows: IENA date 1; TCP window 24 26
• UDP traffic sent to or from Node-A will be routed to parser IENA date 2; TCP Csum 25 27
slot 0.
• TCP traffic sent to or from Node-A will be routed to parser IENA status; TCP urgent Ptr 26 28
slot 1.
25 Mar. 2009 | DST/R/049 375

Values of OffsetIndex_Words (continued)
Field name Offset if Offset if

VLAN VLAN
disabled enabled
IENA Seq; TCP Options (or TCP 27 29

Data 0)
AFDX monitoring
Avionics Full Duplex Switched (AFDX) is part of the
ARINC-664 specification that extends Ethernet so as to
provide deterministic timing and redundancy. Because the
EBM/101 is an Ethernet packet parser, care must be taken
using the EBM/101 as an AFDX destination end-system. In
particular with two EBM/101s (for redundancy), both packets
would be stored, no sequencing checks would be carried out
and addresses must be specified for each packet at the
bit-location level.
376 25 Mar. 2009 | DST/R/049

Connector pinout of the KAD/EBM/101
1 RX+ Ethernet interface
2 RX- Ethernet interface
3 NC Not connected
4 NC Not connected
11 NC Not connected
12 NC Not connected
13 NC Not connected
14 NC Not connected
15 NC Not connected
18 TX+ Ethernet interface
19 TX- Ethernet interface
20 NC Not connected
21 NC Not connected
22 NC Not connected
23 NC Not connected
24 NC Not connected
25 NC Not connected
26 NC Not connected
27 NC Not connected
28 NC Not connected
29 NC Not connected
30 NC Not connected
31 NC Not connected
32 NC Not connected
35 NC Not connected
36 NC Not connected
37 NC Not connected
38 NC Not connected
41 NC Not connected
42 NC Not connected
43 NC Not connected
44 NC Not connected
45 NC Not connected
46 NC Not connected
47 NC Not connected
48 NC Not connected
49 NC Not connected
50 NC Not connected
www.acracontrol.com
378 25 Mar. 2009 | DST/R/049

KAD/ENC/005/B, KAM/ENC/005/B
A C R A KAM-500 ENC/005
IRIG-106 PCM encoder
C O N T R O L
DESCRIPTION
The ENC/005 is used to encode data from any KAM-500
module in an IRIG-106 Ch.4 PCM stream. Frame
configuration is versatile and fully IRIG-106 compliant.
Parameters to be transmitted are stored in predefined
locations in RAM. Each parameter has a word definition that
includes the location in RAM, bits per word, MSB sent
first/last and parity. This definition controls the RAM reader
and the parallel-to-serial converter.
The ENC/005 has differential ended (D/E RS-422) outputs for
data and clock along with buffered TTL outputs for NRZ-L
FEATURES and the four bit/word/minor-frame/major-frame pulses.
• 100% IRIG-106 compliant
Multiple ENC/005 modules can be included in a KAM-500
• Fully software programmable system and parameters can be sent to some or all of the
• Up to 14 PCM codes at up to 16Mbps
encoders. For example, a system can have two encoders
• 2 to 32K words per major frame
using different codes, data rates, word lengths and frame
• 1 to 8K words per minor frame lengths. The only restriction is that an integral number of
• 4 to 64 bits per word (programmable word by word)
major frames be transmitted per acquisition cycle.
• Odd, even or no parity (programmable word by word)
• Supports any sync. word and sub-frame strategy
APPLICATIONS
• Encode data in IRIG-106 Ch.4 PCM stream
DATA + 15
+
120
-
DATA - 16
DCLK + 17
PARALLEL ←
RAM
+ SERIAL
120
-
DCLK - 18
DATA 22
NRZ-L 24 CONTROL
DCLK 23
TTL BUFFER
WORD_PULSE 19
MINOR_PULSE 20
MAJOR_PULSE 21
GND 12 ENC/005
ENC/005 block diagram
3 Nov. 2008 | DST/P/005 379

Selection Paths
Airborne Data Acquisition → KAM-500 → Modules → PCM encoder
KAD/ENC/005/B CON/KAD/002/CP ENC/005/B module with 52-way double density module top connector
KAM/ENC/005/B ACC/CON/008/04 ENC/005/B module with 51-way micro-miniature module top connector
Revision History
ENC/005/B Allows asynchronous operation Recommended for new programs
ENC/005 First release Not recommended for new programs
In this data sheet ENC/005/B refers to both the KAD and KAM version of the module.
Related Products
Module Details
BCU/001/B KAM-500 backplane controller with IRIG-106 PCM encoder
ENC/004 IRIG-106 PCM encoder with KAM-500 Controller
Document Details
TEC/NOT/035 Rules of PCM placement
TEC/NOT/036 Capturing asynchronous IRIG-106 PCM streams
www.acracontrol.com
380 3 Nov. 2008 | DST/P/005

General

Mass
– 60 – g
Power consumption
+5V 320 – 400 mA
±7V 0 – 0 mA
±12V 0 – 0 mA
total power 1.6 – 2 W
RS-422 outputs

Signaling rate
DATA+ – – 16 Mbps
DCLK+ – – 16 MHz
Output voltage
absolute operating range -14 – 14 V Absolute voltage of the operating signal must stay within this
range.
logic ‘0’ – – -2 V V0+ - V0- ; RLOAD = 100Ω
logic ‘1’ 2 – – V V0+ - V0- ; RLOAD = 100Ω
common mode voltage – – 3 V
3 Nov. 2008 | DST/P/005 381

BTTL outputs

Signaling rate
WORD PULSE – – 4 MHz
MINOR PULSE – – 4 MHz
MAJOR PULSE – – 2 MHz
DCLK – – 16 MHz
NRZ-L – – 16 Mbps
Output voltage
logic ‘0’ – – 0.55 V Sinking 0.1mA.
logic ‘1’ 3 – – V Sourcing 0.1mA.
short circuit current – – 50 mA To GND.
short circuit duration ∞ – – s To GND. Only one output may be shorted at a time.
For fixed data

Name Fixed Data FIXED_DATA
maximum FFFF16 AAAA16
minimum 0 0
Data Format Binary Binary
"/><\.
This module uses the X-Module-Pcm-Out-1.1 schema. (See http://www.xidml.org).

Manufacturer
part reference KAD/ENC/005/B KAD/ENC/005/B ACRA CONTROL part number.
InterConnect No character limit TTL_PCMDataLink InterConnect associates a named datalink with a physical IRIG PCM
stream.
382 3 Nov. 2008 | DST/P/005

Setting up packages
This module uses the X-IRIG-106-Ch-4-1.1 schema. (See http://www.xidml.org).

Synchronous Sync, Async In asynchronous operation, the CVT of the encoder is triple-buffered
to enable the PCM transmission to be independent of the KAM-500
acquisition cycle. In synchronous operation, it is dependent on the
KAM-500 acquisition cycle.
acquisition
cycle
Data link No character limit TTL_PCMDataLink A named datalink.
reference
Major frame
Properties
default parity Odd, Even, None None Parity can be changed for particular words.
default data bits 4 to 64k 4 Default number of bits per word can be changed for particular words
per word later on.
major frame
bits per minor 1 to 65535 Shows the first bit index of the first occurrence of this parameter in
frame the frame. It is set when the parameter is placed.
Synchronization
strategy
sync word 4 to 64 bits 1111.1110.0110.1011 Enter the sync word as hexadecimal. Synchronization bits is the num-
0010.1000.0100.0000 ber of bits in the synchronization word. In the XidML file the sync word
pattern is binary.
Minimal word length is 4 bits for bit-rates of 8MHz and less, for higher
bit-rates it is Bitrate[MHz]/2. For example, 32bit sync word
FE6B28406
Modulation
PCM code NRZ-L, RZ, BIØ-L, Code used for bit transmission, the options are dependent on the
NRZ-S, NRZ-M, modules used.
BIØ-M, BIØ-S,
RNRZ-L(15)
DCLK phase 0/1 Shifts the data clock in phase by 180°.
PCM polarity True/False Shifts the PCM by 180°.
sync word 27 choices Hexadecimal pattern that is the sync word, this can be any pattern
with a trailing 'h', and enters Synchronization bits which is the number
of bits in the synchronization word. In the XidML file the sync word
pattern is binary.
Content
parameter no character limit P1
number
minor frame offset
words
occurrences
bit
3 Nov. 2008 | DST/P/005 383

Getting the most from the ENC/005 Input registers
The table below displays the bit-rates available between The ENC/005 has a 16-bit wide transmission buffer of 32K
16Mbps and 2Mbps. There are over one million lower registers in synchronous mode and 8K registers in
frequencies available, and, at 1Mbps, the granularity is better asynchronous mode. The encoder can concatenate multiple
than 2%. registers to form words up to 64 bits long. However, if a
register is transmitted, at least 4 bits from that register must
16.0000 14.0000 13.3333 12.8000 12.0000 11.2000 be sent.
10.6667 10.0000 9.6000 9.3333 9.1429 8.0000 In synchronous operation, a single register can be used for
multiple parameters or multiple instances of the same
7.1111 7.0000 6.8571 6.6667 6.4000 6.2222 parameter. In asynchronous operation, the PCM frame can
6.0000 5.8182 5.7143 5.6000 5.3333 5.0909 be transmitted as soon as the transmission buffer is ready.
5.0000 4.9231 4.8000 4.6667 4.5714 4.4444 The origin of each word must be specified in the PCM
stream, with fill data used for unspecified locations. The
4.3636 4.3077 4.2667 4.0000 3.7647 3.7333
location of the parameter in the buffer is transparent to the
3.6923 3.6364 3.5556 3.5000 3.4286 3.3684 user.
3.3333 3.2941 3.2000 3.1111 3.0769 3.0476
3.0000 2.9474 2.9091 2.8571 2.8235 2.8000
2.7826 2.6667 2.5600 2.5455 2.5263 2.5000
2.4615 2.4348 2.4000 2.3704 2.3529 2.3333
2.2857 2.2400 2.2222 2.2069 2.1818 2.1538

2.1333 2.1053 2.0870 2.0741 2.0645 2.0000
Figure 2 shows the timing for the various

outputs.
1 0 0 1 1 1 0 0 0 0 1 1
NRZ-L
PCM (BIØ-L)
DCLK
WORD
MINOR Last word of minor frame
MAJOR Last word of major frame
Figure 2: Output timing
Even though the ENC/005 allows varied word lengths and

non-standard commutation (that is, samples of a specific
parameter not evenly spaced in the PCM frame), many
third-party decommutators do not. ACRA CONTROL
recommends using a default word length (for example, 16
bits) and evenly spaced commutation.
The acquisition cycle and asynchronous PCM frames are
fully independent. Therefore, if an asynchronous frame has a
transmission time less than the acquisition cycle there will be
a repeat of parameters. Similarly, if the asynchronous
transmission is longer than the acquisition cycle, some
acquisition cycles will occasionally be skipped.
The asynchronous frame has full flexibility over the number of
minor frames in a major frame. Coherency applies only to the
major frame.
384 3 Nov. 2008 | DST/P/005

Connector pinout of KAD/ENC/005/B
15 DATA+ RS-422 outputs PCM output; internally terminated with 120Ω
16 DATA- RS-422 outputs PCM output; internally terminated with 120Ω
17 DCLK+ RS-422 outputs Bit clock for PCM; internally terminated with 120Ω
18 DCLK- RS-422 outputs Bit clock for PCM; high for last half of bit
19 WORD_PULSE BTTL outputs Indicates end of word; high for last bit of word
20 MINOR_PULSE BTTL outputs Indicates end of minor frame; high for last word of
minor frame
21 MAJOR_PULSE BTTL outputs Indicates end of major frame; high for last word of
major frame
22 DATA BTTL outputs PCM output
23 DCLK BTTL outputs Bit clock for PCM; high for last half of bit
24 NRZ_L BTTL outputs Non-return to zero (level) data
www.acracontrol.com
386 3 Nov. 2008 | DST/P/005

KAD/ENC/106, KAM/ENC/106
A C R A KAM-500 ENC/106
IRIG-106 PCM encoder with premodulation filter (PMF) output
C O N T R O L
APPLICATIONS
• RF transmission of PCM streams
• Encode data in IRIG-106 Ch.4 PCM stream
DESCRIPTION
The ENC/106 is used to encode data from any KAM-500
module in an IRIG-106 Ch.4 PCM stream.
Multiple ENC/106 modules can be included in a KAM-500
system and parameters can be sent to some or all encoders.
In particular, a system can have four encoders at different
FEATURES codes, data rates, word lengths and frame lengths. The only
restriction is that an integral number of major frames be
• Sixth order linear phase (Bessel) premodulation filter transmitted per acquisition cycle.
(PMF)
• Programmable PMF cutoff from 175kHz to 6MHz Parameters to be transmitted are stored in predefined
• Programmable PMF output voltage from ±0.5Vp to ±5Vp locations in RAM. Each parameter has a word definition
which includes the location in RAM, bits per word, MSB sent
• RS-422 and TTL outputs
first/last and parity. This definition controls the RAM reader
• 100% IRIG-106 compliant
and the parallel-to-serial converter.
• Programmable bit rate
• Up to 15 PCM codes at up to 20Mbps The ENC/106 has differential-ended (D/E) RS-422 outputs for
• 2 to 64K words per major frame data and clock along with buffered TTL outputs for NRZ-L,
• 4 to 8K words per minor frame DATA, DCLK, word, minor-frame and major-frame pulses.
• 5 to 64 bits per word (programmable word-by-word)
The ENC/106 also has a programmable premodulation
• Odd, even or no parity (programmable word-by-word)
filtered analog output which is suitable for use with a linear
• Supports any sync. word and sub-frame strategy
FM transmitter for telemetry. The cutoff frequency and
amplitude can be changed to suit the bit rate and transmitters
deviation sensitivity.
+
15 +
DATA(0)
- 16 -
+ PARALLEL ←
17 + SERIAL RAM
DCLK(0)
- 18 -
WORD_PULSE
19
MINOR_PULSE
20
MAJOR_PULSE
21
DATA TTL BUFFER CONTROL
22
DCLK
23
NRZ-L
24
PMF_A + Σ
29
- ×
PMF_B +
4
-
GND
51
ENC/106
ENC/106 block diagram
10 Nov. 2008 | DST/S/092 387

Selection Paths
Airborne Products → KAM-500 → Modules → PCM encoders
KAD/ENC/106 CON/KAD/002/CP IRIG-106 PCM encoder with PMF output and KAD connector
KAM/ENC/106 ACC/CON/008/04 IRIG-106 PCM encoder with PMF output and KAM connector
Revision History
ENC/106 First release Recommended for new programs
In this data sheet ENC/106 refers to both the KAM and KAD version of the module.
Related Products
Module Details
Document Details
TEC/NOT/024 Evolution of Pulse Code Modulation
TEC/NOT/035 Rules for PCM Placement
TEC/NOT/036 Capturing Asynchronous IRIG 106 PCM Streams
www.acracontrol.com
388 10 Nov. 2008 | DST/S/092

Specifications

Mass
– 68 – g
bare connector – 11 – mm
bare connector – 0.43 – in. Design metric is millimeters.
Throughput
aggregate – – 2 Msps
Power consumption
+5V 231 – 284 mA
±7V 0 – 0 mA
+12V 53 – 54 mA
-12V 49 – 49 mA
RS-422 outputs

Signalling rate
DATA[1:0] – – 20 Mbps RZ, NRZ-L/M/S, RNRZ-L 11/13/15/17
DATA[1:0] – – 8 Mbps BiØ-L/M/S, DBIØ-M/S, DM-M/S.
DCLK[1:0] – – 20 MHz
Output voltage
logic ‘0’ – – -2 V V0+ - V0- ; RLOAD = 100Ω
logic ‘1’ 2 – – V V0+ - V0- ; RLOAD = 100Ω
ESD protection – – 5 kV Human Body Model.
10 Nov. 2008 | DST/S/092 389

BTTL outputs

Signalling rate
DCLK – – 16 MHz
NRZ_L – – 16 Mbps
WORD – – 16 MHz High for last bit of any word.
MINOR – – 4 MHz High for last word of minor frame.
MAJOR – – 4 MHz High for last word of major frame.
Output voltage
short circuit protection – – 50 mA Indefinite to GND.
Output resistance – 100 – Ω 100Ω in series with standard TTL.
Premodulation filter outputs

Amplitude
PMF_A ±0.5 – ±2 Vp PMF_A will drive a 50Ω load; setting the output voltage to 2Vp
will result in 1Vp as the output impedance is 50Ω.
PMF_B ±2 – ±5 Vp PMF_B is not designed to drive loads lower than 1KΩ;
connecting a 50Ω load to it will result in excessive power
dissipation.
Filter cutoff 175 – 6000 kHz The filter cutoff is defaulted to 0.7 times the bit rate for non return
to zero codes and to 1.4 times for bi-phase codes. This is in
accordance with the IRIG Telemetry Application Handbook
recommendations.
Signalling rate
RNRZ-L 11/13/15/17, 250 – 8000 kbps
NRZ-L/M/S
BiØ-L/M/S 125 – 4000 kbps
Total harmonic distortion
PMF_A – 40 – dBc
PMF_B – 40 – dBc
Current output
short circuit protection – 40 – mA Indefinite to GND.
PMF_A
short circuit protection – 100 – mA Indefinite to GND.
PMF_B
Output resistance – 50 – Ω 50Ω in series with the output driver.
Filter type – – – – Bessel (linear phase).
Restrictions – – – – PCM code must be the same as the PCM digital output.
390 10 Nov. 2008 | DST/S/092

For fixed data

Name Fixed Data FIXED_DATA
Base unit Unitless Unitless
maximum FFFF16 AAAA16
minimum 0 0
Data format Binary Binary
Size In bits 1 to 16 16
This module uses the X-Module-Pcm-Out schema. (See http://www.xidml.org).

Manufacturer
part reference KAD/ENC/106 KAD/ENC/106 ACRA CONTROL part number.
Inter connect No character limit PCMDataLink InterConnect associates a named datalink with a physical IRIG PCM
stream.
Premodulation
filter
Enabled Yes or No Yes Turns on or off the premodulation filter saving 315mW (typical) from
+5V and 240mW from ±12V supplies.
Amplitude 0.5 to 5 1 Peak amplitude of the premodulation filter output; setting to 1V with
an offset of 0V will result in a ±1V signal (2Vp-p).
Offset -1 to 1 0 Measured in volts.
Type Bessel Bessel
Setting up packages
This module uses the X-IRIG-106-Ch-4 schema. (See http://www.xidml.org).

Referenced to Yes or No Yes Used only when the package is built, transmitted or stored as a
absolute time function of absolute time. Yes means that data in the package is
sampled at the start of a second and at equal intervals thereafter.
acquisition
cycle
Data link No character limit PCMDataLink A named datalink.
reference
Major frame
properties
default parity Odd, Even, None None Parity can be changed for particular words.
default data bits 5 to 64 5 Default number of bits per word can be changed for particular
per word words.
major frame
bits per minor 1 to 65535 Shows the first bit index of the first occurrence of this parameter in
frame the frame. It is set when the parameter is placed.
10 Nov. 2008 | DST/S/092 391


Synchronization
strategy
sync word 5 to 64 bits 1111.1110.0110.1011 Enter the sync word as hexadecimal. Synchronization bits is the
0010.1000.0100.0000 number of bits in the synchronization word. In the XidML file the
sync word pattern is binary.
Minimal word length is 5 bits for bit rates of 8MHz and less; for
higher bit rates it is Bitrate[MHz]/2. For example, 32bit sync word
FE6B284016.
Modulation
PCM code BIØ-L/M/S, DM-M/S, Code used for bit transmission; the options are dependent on the
DBIØ-M/S, modules used. Not all codes are available when PMF is used, see
NRZ-L/M/S, Table , “Premodulation filter outputs,”.
RNRZ-L11/13/15/17,
RZ
DCLK phase 0/1 Shifts the data clock in phase by 180°.
PCM polarity True/False Shifts the PCM by 180°.
sync word 27 choices The sync word is a hexadecimal pattern, that is any pattern with a
trailing 'h', and contains synchronization bits, which is the number of
bits in the synchronization word. In the XidML file the sync word
pattern is binary.
Content
number
minor frame offset 0 to 8191 0
words
occurrences
bit
392 10 Nov. 2008 | DST/S/092

Getting the most from the ENC/106
DATA (BiøL)
The ENC/106 has a transmission buffer of 32K registers in
synchronous mode. The transmission buffer is 16 bits wide. DATA (NRZL)
The encoder can concatenate multiple registers to form
words up to 64 bits long. If a register is transmitted, at least DATA+ (NRZL)
four bits from that register must be sent. Because data
transmission is synchronous with backplane operation, a
single register can be used for multiple parameters or DATA- (NRZL)
multiple instances of a parameter when operating in
DCLK
synchronous mode.
The origin of each word in the PCM stream must be DCLK+
specified; fill data is used for unspecified locations. The
location of the parameter in the buffer is transparent.
When transmitting PCM data over an RF link using bi-phase DCLK-
codes there are two dominant frequencies in the data signal;
at the bit rate and at half the bit rate. When using non return WORD_PULSE
to zero codes, the highest frequency is at half the bit rate but
long chains of 1's or 0's can introduce frequencies down to MINOR_PULSE
DC. Using random codes such as RNRZ-L/13 makes good
use of the available bandwidth whilst breaking up long chains
MAJOR_PULSE
of constant bits.
PCM encoder outputs Figure 2: Timing for outputs

The ENC/106 has the following PCM encoder outputs:
The ENC/106 allows variable word lengths and non-standard
commutation (that is, samples of a specific parameter not
DATA[1:0]±
evenly spaced in the PCM frame). However, ACRA
D/E RS-422 output. Differential PCM coded data output. CONTROL recommends using a default word length (for
example, 16 bits) and evenly spaced commutation.
DCLK[1:0]±
D/E RS-422 output. Differential data clock, consists of a Premodulation filter outputs
transition at the start and centre of each bit transmitted. The ENC/106 has two premodulation filter outputs (PMF_A,
pin 29 and PMF_B, pin 4) for interfacing to FM transmitters.
DATA The filter is a programmable sixth order Bessel (linear phase)
S/E BTTL output with 100Ω resistor in series. which is generated digitally and reconstructed using a
communications DAC.
DCLK The filter cutoff is set at 0.35 times the bit-rate for non-return
S/E BTTL clock output with 100Ω resistor in series. to zero codes and to 1.4 times the bit-rate for bi-phase code.
The amplitude is user-defined, and should be set to allow for
WORD_PULSE the FM transmitter's deviation sensitivity.
S/E BTTL output with 100Ω resistor in series. High for the last In order to give the widest possible output voltage range to
bit of each word. Its falling edge is aligned to the end of the match as many transmitters as possible, while keeping
last bit of each word. quantization steps in the DAC from having a negative effect
on the outputs, there are two outputs:
MINOR_PULSE
• PMF_A covers +/- 0.5V to +/- 2V.
S/E BTTL output with 100Ω resistor in series. High for the last • PMF_B follows PMF_A and has an analog gain of 2.5,
word of each minor frame. Its falling edge is aligned to the making it ideal for driving transmitters requiring between
end of the last bit of each minor frame. +/- 2V to +/-5V.
MAJOR_PULSE
S/E BTTL output with 100Ω resistor in series. High for the last
word of each major frame. Its falling edge is aligned to the
end of the last bit of each major frame.
Timing, bit-rates and commutation

Figure 2 shows examples of timing for NRZL and Bi-Phase L
(BIØ-L). For maximum bit-rates and supported PCM
transmission See “Specifications” on page 389.
10 Nov. 2008 | DST/S/092 393

Connector pinout of the KAD/ENC/106
4 PMF_B Premodulation filter output ±2 to ±5V
14 NC Not connected
15 DATA(0)+ RS-422 outputs PCM output 0; not internally terminated
16 DATA(0)- RS-422 outputs PCM output 0; not internally terminated
17 DCLK(0)+ RS-422 outputs Bit clock for PCM output 0; not internally terminated
18 DCLK(0)- RS-422 outputs Bit clock for PCM output 0; not internally terminated
19 WORD_PULSE BTTL outputs High for last bit of word
20 MINOR_PULSE BTTL outputs High for last word of minor frame
21 MAJOR_PULSE BTTL outputs High for last word of major frame
22 DATA BTTL outputs PCM output
23 DCLK BTTL outputs Bit clock for PCM; internally terminated with 100Ω
24 NRZ_L BTTL outputs Uncoded PCM output
29 PMF_A Premodulation filter output ±0.5 to ±2V
34 DATA(1)+ RS-422 outputs PCM output 1; not internally terminated
39 DATA(1)- RS-422 outputs PCM output 1; not internally terminated
40 DCLK(1)+ RS-422 outputs Bit clock for PCM output 1; not internally terminated
41 DCLK(1)- RS-422 outputs Bit clock for PCM output 1; not internally terminated
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394 10 Nov. 2008 | DST/S/092

KAM/FBM/001/B
A C R A KAM-500 FBM/001
C O N T R O L Single EF-2000 FCS bus monitor module
DESCRIPTION
The FBM/001 monitors data on an FCS bus and stores data.
This module uses a single receiver of the type used in the
dual-redundant STANAG-3910 monitor SBM/001. In
particular it assumes the physical layer of the FCS is identical
to a single non-redundant STANAG 3910.
The transport/protocol layer of the FCS is identical to
STANAG-3910 (PR/SD/FC/PA/DA/WC/INFO/CRC/ED)
except that all but the INFO and CRC is fixed. The INFO has
15 address/data pairs.
FEATURES
Each message is stored in a temporary buffer (32 x 16 bits
• Parses traffic and tags for up to 1024 data words wide) until the complete message is received. If the message
• LED indication for traffic and errors is received correctly, the message count (MES_CNT) is
• Supports continuous preamble updated and the DATA, MES_CNT, LOW and MICRO time
tags, can be written, for up to 8192 parameters, determined
APPLICATIONS by the address. Up to 8192 data words can be parsed.
• FCS bus monitoring To facilitate continuous preamble the receivers are reset after
the end-delimiter for 2µs.
Timer
Word Finder
Optic
Symbol Detect
-Fiber to
and Timing
TTL
SBI +
LOGIC
10 Protocol
Tracker
Address List
FBM /001
FBM/001/B
27 Nov. 2008 | DST/N/027 395

Selection Paths
Airborne Data Acquisition → KAM-500 → Modules → Bus → EFAbus
KAM/FBM/001/B Not Supplied Single EF-2000 FCS bus monitor

The FBM/001 uses two user-slots.
Revision History
FBM/001/B Support for continuous pre-amble added Recommended for new programs
FBM/001 First release Not recommended for new programs
Related Products
Module Details
Document Details
www.acracontrol.com
27 Nov. 2008 | DST/N/027

Specifications
Busses: 1
Input considerations: Optic fibre

-12dBm to -35.5dBm in line with SP-J-402-E-1039
Sampling restrictions: The maximum sampling rate from the module is 500ksps
Physical restrictions: The unit occupies two user-module slots
Output registers
The diagram shows the 32,768 words that can be read from FBM/001.
PARSER One of 8192 words DATA

TIME_LO
TIME_MICRO
MSG_CNT
MESSAGE_COUNT MESSAGE_COUNT
REPORT
MESSAGE_COUNT Count of valid messages received on this bus
R[15:0] BINARY 0000-FFFF (hex), resets at FFFF R(15)
DATA_ 16 data bits
R[15:0] D(15) is first transmitted bit R(15)
MSG_CNT Value of MESSAGE_COUNT when message was received on this

bus
INFO Stale/skipped indication
R(15) 1 indicates the tags and data associated with this message was read
before
R(14) 1 indicates the tags and data associated with this message
overwrote others
TIME_MICRO Microsecond time midway through first transmitted bit
TIME_LO Seconds and centiseconds time midway through first transmitted bit
R[15:0] BCD 00.00-59.99 seconds R(15)
R(15) 1 indicates an error occurred since last read
27 Nov. 2008 | DST/N/027 397

R[3:0] Indicates the error that occurred last (see “Error codes for the FBM/ R(3)
001” on page 398)
Error codes for the FBM/001
016 Reserved for future use 416 Incorrect bits in WC
116 Incorrect CRC 516 ED not correct
216 Bad bit 616 Reserved for future use
316 Incorrect FC 7-F16 Reserved for future use
Error codes are in hexadecimal.
CONNECTOR
Traffic Errors
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398 27 Nov. 2008 | DST/N/027

KAD/FBM/102, KAM/FBM/102
C O N T R O L FireWire bus monitor
DESCRIPTION
The FBM/102 is designed to monitor IEEE 1394 (FireWire)
traffic, parse and tag packets, and distribute the monitored
packet contents to other KAM-500 modules. The FBM/102
acts as a leaf in the FireWire bus topology. To all other nodes
on the bus the link layer and transaction layer appear to be
deactivated.
The bus monitor triple buffers up to 64 isochronous channels
or asynchronous stream packets, with associated tags, i.e.
the attributes which the bus monitor associates with each
FEATURES parsed packet (time, count, status and information words).
• IEEE 1394 compliant Each buffer contains up to 1036 16-bit words, i.e. 1030 words
• Monitors IEEE 1394a and 1394b at signaling rates of of packet content, 3 words of timestamp, 1 word containing
100Mbps, 200Mbps and 400Mbps transaction number, 1 word containing information tag
• Coherent parsing of traffic (INFO), and 1 word containing packet size. Triple buffering
• Transaction level tagging (time, count, status, info) supports concurrent access to the packet being read, packet
• Maximum payload size of 2kByte per packet being received, and an interim packet. The INFO word tag
• Triple buffering of parsed packets associated with each packet is used to indicate whether the
• Discards bus configuration packets and PHY packets packet is STALE (buffer has been read before) or SKIPPED
• Provides transaction counters and error detection (buffer has been overwritten).
Data selection and content is based on a 64-bit filter mask,
APPLICATIONS which allows the selection of each individual isochronous
• FireWire bus monitoring channel for parsing. Only traffic with transaction code 0xA is
recognized. Bus configuration traffic, PHY packets, and
asynchronous transactions are ignored. The FBM/102 is
available only with a 52-way double density connector.
Timer
-
25
TPB
23
+ Packet Parser
Triple
reception (classification
PHY buffered
CRC check protocol
- CVT
21 1st level filter tracking)
TPA
19
+
Setup
EEPROM
Filter Mask (63:0)
VG 2
FBM /102
FireWire interface of the FBM/102
10 Nov. 2008 | DST/P/052 399

Selection Paths
Airborne Data Acquisition → KAM-500 → Modules → Bus → Firewire
KAD/FBM/102 CON/KAD/002/CP FBM/102 module, with 52-way double density module top connector
Revision History
FBM/102 FireWire bus monitor, operates in bilingual mode Recommended for new programs
In this data sheet FBM/102 refers to both the KAD and KAM version of the module.
Related Products
Module Details
KSM-2 This module is supported by KSM-2 software.
Document Details
www.acracontrol.com
400 10 Nov. 2008 | DST/P/052

Specifications
I/O considerations: Self-powered single IEEE 1394 bilingual port. Chassis and signal ground are fully isolated on
this module (please see IEEE Std. 1384b-2002, 4.2.1B.5.1.)
Sampling restrictions: Supports transfer rates up to 2Msps
Module setup
<Parameters>
<ParameterTypeSet>
:
<ParameterType Name="MyCounterType">
<BaseUnit>Count</BaseUnit>
<DataType>BinaryCodedDecimal</DataType>
</ParameterType>
:
</ParameterTypeSet>
<ParameterSet>
:
2 <Parameter Name="MyTransactionCounter">
<ParameterTypeReference>MyCounterType</ParameterTypeReference>
<Source>
<Signal>
1 <InstrumentReference>MyFBM102</InstrumentReference>
3 <VendorMap>TRANSACTION_COUNT</VendorMap>
</Signal>
</Source>
:
</Parameter>
:
</ParameterSet>
</Parameters>

to
InstrumentRe Name N/A N/A Yes Each Name of module.
1
ference module
ParameterNam Name N/A N/A No Each pa- The name assigned to this module.
2
e rameter
VendorMap Selection N/A N/A Yes Each pa- Selection of registers (please see Output Registers
3
rameter for more details).
10 Nov. 2008 | DST/P/052 401

<Instrumentation>
<InstrumentSet>
:
<X-DAU Name="MyDAU">
<Manufacturer>
</Manufacturer>
</X-DAU>
:
<X-Module-Firewire-Monitor-1.0 Name="MyFBM102">
<Manufacturer>
<PartReference>KAD/FBM/102</PartReference>
5
</Manufacturer>
4
<Settings>
<Module-Firewire-Monitor-1.0>
<FillValue>1023</FillValue>
7
<Channel Index="0">
<Ignore>No</Ignore>
6
</Channel>
</Module-Firewire-Monitor-1.0>
</Settings>
</X-Module-Firewire-Monitor-1.0>
:
</InstrumentSet>
:
</Instrumentation>

Location Name N/A N/A Yes Each DAU Name of DAU.
4
ParameterNam Name N/A N/A No Each parameter The name assigned to this module.
5
e
Ignore Boolean Yes, No Yes Yes Each isochronous Ignores the selected isochronous transac-
6
transaction chan- tion channel.
nel
FillValue 16-bit 0 to 1023 Yes Each module Value used to fill empty parser slot.
7
value FFFF
402 10 Nov. 2008 | DST/P/052

Setting up Packages
<Packages>
<PackageSet>
:
8 <X-Firewire-1.0 Name="MyFirewirePackage">
<Source>
9
<ChannelNumber>0</ChannelNumber>
</Source>
<Properties>
<NumberOfWords>8</NumberOfWords>
</Properties>
<Content>
<Location>
<Offset_Words>1</Offset_Words>
</Location>
</Parameter>
</Content>
</X-Firewire-1.0>
:
</PackageSet>
</Packages>

PackageRefer Name N/A N/A Yes Each package Reference to a named package definition.
8
ence
ChannelNumbe Number 0 to 63 N/A No Each module Firewire isochronous transaction channel.
9
r
10 Nov. 2008 | DST/P/052 403

Output registers
The diagram shows the 64K registers that can be read from the FBM/102.
PARSER_SLOT_ID TIME_HI
TIME_LO
TIME_MICRO
INFO
PKT_DATA_0
REPORT
PKT_DATA_1029
TA_COUNT TA_NO
PKT_SIZE
1394_STATUS
Choosing a parameter to be read from the FBM/102
TIME_MICRO Microsecond time at start of first received bit
TIME_LO Seconds and centiseconds time at start of first received bit
R[15:0] BCD 00.00-59.99 seconds R(15)
TIME_HI Hours and minutes time at start of first received bit
R[12:7] BCD 00-23 hours R(12)
INFO Information tag for this PARSED transaction
R(14) 1 indicates this message was read before (STALE)
R(13) 1 indicates this message overwrote another (SKIPPED)
PKT_DATA_ R[15:0] IEEE 1394 packet. PKT_DATA_0 is first word received. R(15)
TA_NO R[15:0] Transaction number R(15)
REPORT R(15) Error occurred since last read
TA_COUNT R[15:0] Transaction counter, counts all fully parsed transactions R(15)
1394_STATUS R[15:8] Reserved for future use
R[7:2] PHY_ID R(7)
R(0) Link is connected R(0)
404 10 Nov. 2008 | DST/P/052

016 Reserved for future use
0xF Default startup value; not an error
116 CRC error in header or payload was detected
216 FIFO overflow. This indicates that the amount of

incoming traffic that needs to be parsed exceeds
the processing capability of the module. Filtering
must be tightened
416 Length mismatch. The in the header given

payload does not match the actual received
amount of data
5-716 Reserved for future use
816 Packet too big. a packet was received that

exceeds the maximum payload of 2048 bytes
9-D16 Reserved for future use
E16 Reserved for future use
Getting the most from the FBM/102

Ground loops can be encountered when a single KAM-500
chassis is populated with two or more FBM/102s that monitor
the same IEEE1394 bus, as standard FireWire cables carry
signal ground either separately and/or through one or both of
the inner shields. It is recommended that only one IEEE1394
bus ground be connected to the KAM-500 chassis.
TPB signal pair
TPA signal pair
GND
IEEE1394 device
Port 1
GND loop
Port 0
FBM/102
FBM/102
KAM-500
10 Nov. 2008 | DST/P/052 405

Connector pinout of KAD/FBM/102

2 VG Cable ground
19 TPA+ D/E signal Data on receive, strobe on transmit (differential pair) TPA in IEEE convention
21 TPA- D/E signal Data on receive, strobe on transmit (differential pair) TPA* in IEEE convention
23 TPB+ D/E signal Strobe on receive, data on transmit (differential pair) TPB in IEEE convention
25 TPB- D/E signal Strobe on receive, data on transmit (differential pair) TPB* in IEEE convention
36 TPA(R) Twisted pair A ground reference Isolates the TPA(R) from other GNDs as
required when connecting to beta capable
nodes
52 CHASSI KAM-500 chassis
S
www.acracontrol.com
406 10 Nov. 2008 | DST/P/052

KAD/FBM/103/B
S200 beta mode FireWire bus monitor
C O N T R O L
DESCRIPTION
The FBM/103 monitors FireWire (IEEE 1394b) traffic. It acts
as a leaf in the FireWire bus topology and to all other nodes
on the bus, the link layer and transaction layer appear to be
deactivated.
The FBM/103 parses isochronous or asynchronous stream
packets. All other traffic is ignored (configuration traffic, PHY
packets and asynchronous transactions). Selected packets
and associated tag information are stored in one of 65
triple-buffered parser slots. Each parser slot contains up to
1036 16-bit words: 1030 words of packet content; three
FEATURES words of timestamp information; one word containing the
transaction number; one word containing the packet size; and
• IEEE 1394b compatible
one word containing buffer information.
• Physical layer has a transformer coupled interface
• Monitors IEEE 1394b at a signal rate of 200Mbps (S200b) FireWire packets are parsed in two stages. First, packets are
• Coherent parsing of isochronous and asynchronous filtered to accept only isochronous and asynchronous stream
stream packets by channel ID/message ID packets (traffic with transaction code A16). Then the channel
• Transaction level tagging (time, count, status, info) ID and message ID (third quadlet in the FireWire packet) are
• Maximum data payload size of 2KB per packet used to classify the packet and determine which of the 65
• Triple-buffering of parsed packets parser slots the packet is written to. Unique channel ID and
• Discards other asynchronous, bus configuration and PHY message ID combinations can be targeted to any of the 64
packets available parser slots.
• Provides transaction counters and error detection
Parser slot 0 may be configured to operate as a "catch all"
slot where any channel and message IDs not mapped to
APPLICATIONS specific parser slots will be routed.
• FireWire beta mode bus monitoring
TIMER
PHY WITH
TRANSFORMER
PARSER
+ 19 (Hash Table TRIPLE
TPA BUFFERED CVT
Classifier)
- 21
+ 23
TPB PACKET
- 25 RECEPTION
(CRC/Length Check
Filtering)
SETUP
EEPROM
GND
51
FBM/103
Filtering and parsing in the FBM/103
5 Feb. 2008 | DST/T/085 407

Selection Paths
Airborne Data Acquisition → KAM-500 → Modules → Bus → FireWire
KAD/FBM/103/B CON/KAD/002/CP FBM/103/B module with 52-way double density module top connector
Revision History
Transformer coupled FireWire bus monitor with enhanced Recommended for new programs
FBM/103/B
parsing
First release Not recommended for new

FBM/103
programs
Related Products
Module Details
FBM/102 FireWire bus monitor, operates in bilingual mode up to S400 signalling
Document Details
www.acracontrol.com
408 5 Feb. 2008 | DST/T/085

Specifications

Mass
– 74 – g
Power consumption
+5V 195 – 324 mA
FireWire bus interface

Inputs – – 1 – IEEE 1394b compatible.
Sampling rate
TPA – – 2 Msps
TPB – – 2 Msps
Voltage 200 – 800 mV 1394b differential input voltage.
Data rate 100 – 200 Mbps FireWire S200B and S100B rates.
5 Feb. 2008 | DST/T/085 409

For parameter Report

Name Report FBM103_Report Received transactions error report.
Base Unit Unitless Unitless R(15) Error occurred since last read.
R[3:0] Error code.
maximum 800816 800116 CRC error occurred since last read.
minimum 000116 000F16
For parameter Sts1394

Name Sts1394 FBM103_Sts_1394 IEEE 1394b port status.
Base Unit Unitless Unitless R[15:8] Reserved for future use.
R[7:2] PHY_ID.
R(1) Reserved for future use.
R(0) Link is connected.
maximum 00FD16 000116 Link is connected. Node has an ID of 0.
minimum 0 0 Nothing is connected to the port.
For parameter TotalTrnCnt

Name TrnCnt FBM103_Trns_Cnt Transaction counter, counts all fully parsed transactions, counter
can overflow.
maximum FFFF16 000216 2 packets were parsed.
minimum 0 0 0 packets were parsed.
For parameter PackageData

Name PackageData FBM103_TrnData IEEE 1394b packet. Pkt_Data_0 is first word received. The first word
received is the packet header. 16 MSB bits.
minimum 0 0
For parameter TrnInfo

Name TrnInfo FBM103_TrnInfo Information tag for this parsed transaction. This is a non-zero value.
Base Unit Unitless Unitless R(15) 1 indicates that there is no message stored (EMPTY)
R(14) 1 indicates this message was read before (STALE)
R(13) 1 indicates this message overwrote another (SKIPPED)
R[12:0] Reserved for future use, may be non-zero value.
maximum 800016 800016 Parser slot empty, nothing parsed since power-up.
minimum 0 0 New message parsed, no messages skipped.
410 5 Feb. 2008 | DST/T/085

For parameter TrnTimeHi
Name TrnTimeHi FBM103_TrnTimeHi Hours and minutes time of start of transaction.
Base Unit Unitless Unitless [12:11] Tens of Hours
D[10:7] Hours
D[6:4] Tens of Minutes
D[3:0] Minutes
maximum 11D916 000216 Message was received when TimeHi was 0 hours, 2 minutes.
minimum 0 0
For parameter TrnTimeLo

Name TrnTimeLo FBM103_TrnTimeLo Seconds and centiseconds time of the start of transaction.
Base Unit Second Second R[14:12] Tens of seconds
maximum 599916 000216 Message was received when TimeLo was 0.02 seconds.
minimum 0 0
For parameter TrnTimeMicro

Name TrnMicroTime FBM103_TrnMicroTime Microsecond time of the start of the acquisition cycle.
Base Unit Second Second
maximum 999916 000216 Message was received when TimeMicro was 2µs.
minimum 0 0
For parameter TrnCnt

Name TrnCnt FBM103_TrnCnt Transaction number.
maximum FFFF16 000216 Message was the 2nd parsed packet.
minimum 0 0
For parameter TrnSize

Name TrnSize FBM103_TrnSize Packet size in quadlets, with header, header CRC, data, and data
CRC.
maximum 020316 010316 Message has a 1024B data payload (total packet size is 1036B).
minimum 4 4 Message has a 4Byte data payload (total packet size us 16B).
5 Feb. 2008 | DST/T/085 411

This module uses the X-Module-Firewire-Monitor-1.1 XidML schema. (See http://www.xidml.org).
For messages
Manufacturer
part reference KAD/FBM/103 KAD/FBM/103 ACRA CONTROL part number.
Settings
MessageBuffer Parser(0) to Parser Parser(0) This element is used to store the name of messages that are
(64) buffered together.
Name Message Name Msg_0_J5_0 This element is used to store the name of a message.
fill value 0 to FFFF16 1023 Value used to fill empty parser slots. This is the default value for all
parameters beginning with Trn, except TrnInfo which is 800016
when nothing is parsed. Also all PackageData are filled with this
value when nothing is parsed.
Setting up packages
This module uses the X-Firewire-1.1 XidML schema. (See http://www.xidml.org).

Synchronous No No
Packages per 1 1
acquisition
cycle
Properties
number of words 0 to 1029 4
HashBinaryValue 1,0,X Up to 32 bits 1,000000000000000 The channel, Message High and Message Low ID are stored in a
00000000000000000 hashbinary. If the OffsetIndex_Bits is 8, the value contains the
channel. If the OffsetIndex_Bits is 64, the value is the Message High
and Message Low ID's.
OffsetIndex_Bits 8, 64 Specifies the offset in bits of the location containing the specified
value.
Content
offset words 0 to 1029 0
016 Reserved for future use.
116 CRC error in header or payload was detected.
216 FIFO overflow. This indicates that the amount of incoming traffic that needs to be parsed exceeds the processing capability of the
module. Filtering must be tightened.
416 Length mismatch. The length defined in the header does not match the actual received amount of data.
516-716 Reserved for future use.
816 Packet too big. A packet was received that exceeds the maximum payload of 2048 bytes.
916-D16 Reserved for future use.
E16 Reserved for future use.
F16 Default value after power up.
412 5 Feb. 2008 | DST/T/085

Getting the most from the FBM/103/B drop the packet is based on three fields of information from
each packet: the 6-bit Channel ID; the upper 16 bits of the
Triple Buffering Message ID; and the lower 16 bits of the Message ID
(Message ID is the third quadlet in the packet). An explicit
Triple buffering supports concurrent access to the packet data value or a special wildcard value “ALL” can be specified
being read, packet being received, and an interim packet. for each of these fields. The combination of these three fields
The transaction information (TrnInfo) word associated with plus a destination parser slot is defined as a rule. Up to 255
each packet is used to indicate whether the packet is ‘stale’ rules can be specified. Rules can allow for multiple packets to
(buffer has been read before) or ‘skipped’ (buffer has been be stored in a single parser slot. And rules may overlap. The
overwritten). compiler sorts and processes rules in a deterministic order.
The following table is an example set of rules that can be
Packet Classification
defined. Rules may be entered in any order. The compiler
FireWire isochronous (or asynchronous stream) packets can sorts the rules as shown in this table. Rules for a channel are
be stored in one of 65 parser slots or dropped (not stored). grouped together and then within this group explicit rules are
The decision on which parser slot to store the packet or to processed first, followed by wildcard rules.
Example classification names

Rule Parser Slot Channel ID Message Hi Message Lo Order Rules Description
ID ID Processed
0 1 1 ALL ALL 1 All packets with a Channel ID of 1 will be routed
to parser slot 1.
1 2 2 ALL CAFE 2 All packets with a Channel ID of 2 and the
Message Lo ID of CAFE will be routed to parser
slot 2.
2 3 3 0 0 3 Packets with a Channel ID of 3, a Message Hi ID
of 0 and a Message Lo ID of 0 will be routed to
parser slot 3.
3 4 3 0 ALL 4 Packets that match this pattern, excluding
packets that match rule 2, will be routed to parser
slot 4.
4 5 3 ALL 0 5 Packets that match this pattern, excluding
packets that match rule 2 & 3, will be routed to
parser slot 5.
5 6 3 ALL ALL 6 Packets that match this pattern, excluding
packets that match rule 2 & 3 & 4, will be routed
to parser slot 6.
6 62 ALL DEAD DEAD 7 Packets that match this pattern will be routed to
parser slot 62.
For Channel ID 1, this rule will have no effect.
For Channel ID 2, this rule will affect all packets
not covered by rule 1.
For Channel ID 3, this rule will have no effect.
The reason is that rules 3-6 have higher priority
than this rule.
7 63 ALL BODE ALL 8 Packets that match this pattern will be routed to
parser slot 63.
Rules 0 to 6 have higher priority than this rule.
8 64 ALL ALL ABBA 9 Packets that match this pattern will be routed to
parser slot 64.
This rule has the lowest priority.
5 Feb. 2008 | DST/T/085 413

Connector pinout of the KAD/FBM/103
17 NC No connection
18 NC No connection
19 TPA+ FireWire bus interface Receive Data+ (IEEE convention uses TPA)
20 NC No connection
21 TPA- FireWire bus interface Receive Data- (IEEE convention uses TPA*)
22 NC No connection
23 TPB+ FireWire bus interface Transmit Data+ (IEEE convention uses TPB)
24 NC No connection
25 TPB- FireWire bus interface Transmit Data- (IEEE convention uses TPB*)
26 NC No connection
28 NC No connection
29 NC No connection
30 NC No connection
31 NC No connection
32 NC No connection
33 NC No connection
34 NC No connection
35 NC No connection
37 NC No connection
46 NC No connection
47 NC No connection
48 NC No connection
49 NC No connection
51 GND
52 CHASSIS
www.acracontrol.com
414 5 Feb. 2008 | DST/T/085

KAD/MBI/001/B, KAM/MBI/001/B
MBI/001
A MIL-STD-1553 remote terminal
DESCRIPTION
The MBI/001 turns any KAM-500 chassis into a
MIL-STD-1553 remote terminal (RT). The RT address is
hardwired to 10 by default. Contact ACRA CONTROL for
other RT addresses.
Any traffic received by the MBI/001 will be confirmed with a
status reply. Furthermore, response to the following mode
codes is supported: mode codes 1, 2, 3, 4, 8, 17, 19.
Additionally, the MBI/001 features message counters on both
busses, as well as a report register that indicates observed
error conditions.
FEATURES
• Turns any KAM-500 chassis into a MIL-STD-1553 remote
terminal
• Supports mode codes 1, 2, 3, 4, 8, 17, 19
• Full dual redundant operation
• Transformer-coupled interface
• More than one module per chassis
APPLICATIONS
• MIL-STD-1553 remote terminal
+
7
+
DATA_T - Encoder/decoder MSG_COUNT
- 41
1553 message
procesor
REPORT
RESPONSE TIME
MIL-STD-1553
Tx/Rx Setup
EEPROM
GND 51
MBI/001
Primary channel of MBI/001
18 Dec. 2008 | DST/P/019 415

Selection Paths
Airborne Data Acquisition → KAM-500 → Modules → Bus → MIL-STD-1553
KAD/MBI/001/B ASD/MSB/001/TC 52-way double density module top connector to MIL-STD-1553

(transformer coupled)
KAM/MBI/001/B ACC/CON/029 51-way micro-miniature module top connector to MIL-STD-1553

Revision History
MBI/001/B Additional protection against illegal response times and Recommended for new programs
corrupted EEPROM images
MBI/001 First release Obsolete
In this data sheet MBI/001/B refers to both the KAD and KAM version of the module.
Related Products
Module Details
KSMv2 This module is compatible with KSMv2 software
Document Details
TEC/NOT/004 MIL-STD-1553 and the KAM/MSB/001
www.acracontrol.com
416 18 Dec. 2008 | DST/P/019

Specifications

Mass
– 70 – g
– 2.47 – oz
bare connector – – 0.43 in.
Power consumption
+5V 120 – 190 mA
±7V – – – mA
±12V – – – mA
MIL-STD-1553 dual redundant bus

Channels – – 1 Pair Dual redundant. MIL-STD-1553-B compatible.
Signaling rate
– – 1 Mbps Maximum data rate of MIL-STD-1553 is 36kwps.
Connection methods
Transformer coupled – – – –
direct coupled – – – –
18 Dec. 2008 | DST/P/019 417

Setting up the MBI/001/B
Response time 12 to 128μs For each module The MIL-STD-1553 protocol tracker, that monitors all dialogs on the
bus, reports status replies that are observed later than the specified
"Response time" as time-out errors in the report register. For details,
see “Error codes for the MBI/001/B” on page 419.
The default value is set to 12μs.
Output Registers
The diagram shows the 2 registers that can be read from the MBI/001.
CHASSIS # MODULE #
MESSAGE COUNT Primary/secondary bus MSG_COUNT
REPORT
Choosing a parameter to be read from the MBI/001/B
Register Bits Bit Definition MSB
MSG_COUNT R[15:0] Per channel message counter1 R(15)
REPORT R[15:0] Errors reported R(15)
R(15) Error occurred since last read
R[4:0] Error codes R(4)
1. Resets to 0 on internal resets or mode code 8
418 18 Dec. 2008 | DST/P/019

Error codes for the MBI/001/B 2716 Reserved for future use
2816 Expected Tx cmd. of RT to RT(s) had invalid RT

016 Debug error 1 (contact ACRA CONTROL)
2916 Expected Tx cmd. of RT to RT(s) had invalid SA
116 Data word did not have enough bits
2a16 Expected Tx cmd. of RT to RT(s) had invalid number of
words
216 Data word had bit error
2b16 Expected Tx cmd. of RT to RT(s) had different number of
316 Data word had parity error
words than Rx cmd.
416 Non-data word did not have enough bits
2c16 Expected Tx cmd. of RT to RT(s) had same RT as Rx
516 Non-data word had bit error cmd.
616 Non-data word had parity error 2d16 Expected Tx cmd. of RT to RT(s) had contiguous traffic
716 Reserved for future use 2e16 Expected Tx cmd. of RT to RT(s) was not a Tx cmd.
816 Expected data word was non-data word 2f16 Reserved for future use
916 Expected data word did not have contiguous word 3016 Reserved for future use
a16 Expected last data word was not last 3116 Reserved for future use
b16 Expected mode data word was non-data word 3216 Reserved for future use
c16 Expected mode data word has contiguous traffic 3316 Reserved for future use
d16 Reserved for future use 3416 Reserved for future use
e16 Reserved for future use 3516 Reserved for future use
f16 Reserved for future use 3616 Reserved for future use
1016 Expected first cmd. was data word 3716 Reserved for future use
1116 Expected first cmd. had invalid RT 3816 Reserved for future use
1216 Expected first cmd. had invalid SA 3916 Reserved for future use
1316 Expected first cmd. had invalid number of words 3a16 Reserved for future use
1416 Expected first cmd. was invalid mode 3b16 Reserved for future use
1516 Expected first cmd. had contiguous traffic 3c16 Reserved for future use
1616 Expected first cmd. was Rx with no contig, data word 3d16 Reserved for future use
1716 Expected first cmd. was Mode with no contig. data 3e16 Reserved for future use
1816 Expected second sts. of RT to RT was data word 3f16 Reset occurred since last read
1916 Expected second sts. of RT to RT had incorrect RT

Exp. = Expected Tx = Transmit Contig = Con-
1a16 Expected second sts. of RT to RT had contiguous traffic tiguous
1b16 Expected second sts. of RT to RT timed out Getting the most from the MBI/001/B
1c16 Reserved for future use This module is for use in test instrumentation applications
only and should not be used in support of mission critical
1d16 Reserved for future use
applications. Thus, the MBI/001/B should only be connected
1e16 Reserved for future use to instrumentation busses, and not flight-critical control
busses. Contact ACRA CONTROL for mission critical
1f16 Reserved for future use applications.
2016 Expected sts. was data word
2116 Expected sts. was invalid
2216 Expected sts. had incorrect RT
2316 Expected sts. had contiguous traffic
2416 Expected sts. timed out
2516 Expected sts. had no contiguous data word
18 Dec. 2008 | DST/P/019 419

Connector pinout of MBI/001/B
1 NC Not connected
2 NC Not connected
3 NC Not connected
4 NC Not connected
5 NC Not connected
6 NC Not connected
7 DATAT(0)+ MIL-STD-1553 dual redundant bus Transformer coupled; primary bus (by convention)
8 NC Not connected
9 NC Not connected
10 NC Not connected
11 NC Not connected
12 DATAT(1)+ MIL-STD-1553 dual redundant bus Transformer coupled; secondary bus (by
convention)
13 NC Not connected
14 NC Not connected
15 NC Not connected
16 NC Not connected
17 NC Not connected
18 NC Not connected
19 NC Not connected
20 NC Not connected
21 NC Not connected
23 NC Not connected
24 NC Not connected
25 NC Not connected
26 NC Not connected
27 NC Not connected
28 NC Not connected
29 NC Not connected
30 NC Not connected
31 NC Not connected
33 NC Not connected
34 NC Not connected
35 NC Not connected
36 NC Not connected
37 NC Not connected
38 NC Not connected
39 NC Not connected
40 NC Not connected
41 DATAT(0)- MIL-STD-1553 dual redundant bus Transformer coupled; primary bus (by convention)
42 NC Not connected
43 NC Not connected
44 NC Not connected
45 NC Not connected
46 DATAT(1)- MIL-STD-1553 dual redundant bus Transformer coupled; secondary bus (by
convention)
47 NC Not connected
48 NC Not connected
49 NC Not connected
50 NC KAM-500 chassis
www.acracontrol.com
420 18 Dec. 2008 | DST/P/019

KAD/MSB/001/B, KAM/MSB/001/B
A C R A KAM-500 MSB/001
C O N T R O L Dual redundant MIL-STD-1553 bus monitor with D/C and T/C inputs
DESCRIPTION
The MSB/001 is a MIL-STD-1553 dual redundant bus
monitor. It combines the capabilities of an all-pass/selected-
pass monitor (for example IRIG-106 Ch. 8), a coherent
message parser and a range of utility and error detection
functions all on a single module. In the following discussion,
traffic refers to words on the bus (command, status and data)
and tags refer to associated information (microsecond time of
sync. bit transition, message count, response time and
errors).
FEATURES The parser triple buffers up to 512 complete messages and
• Coherently PARSEs traffic and tags from up to 512 their associated tags in buffers up to 41 words wide and three
messages messages deep (message being read, message being
received on each bus and a buffer). The INFO tag associated
• 16K deep selective FIFO for traffic and tags (SNARFER)
• Handles all mode codes (including user defined) with each message has a STALE bit (message read before)
• 2 x Utilization counts (one for each bus) and a SKIPPED bit (buffer overwritten).
• 2 x Message counts (one for each bus) The SNARFER stores selected traffic and tags in a FIFO 16K
• Detects over 35 different errors words deep. Each word has 16 bits for traffic/tag information
• Protocol tracker does not rely on instrumentation bit and 8 bits for FIFO content identification. Data selection and
• Direct coupled or transformer coupled operation content identification is based on the bus (primary/
secondary), message ID (up to 512), traffic type (command,
APPLICATIONS status, data), tag type (High/Low/Micro/Response time,
message count) and how full the FIFO is. The UTILISATION
• Monitoring MIL-STD-1553 traffic counts reflect the true level of bus activity over the previous
200ms (00.00 to 99.99%). The MESSAGE count increments
on receipt of a valid message. The ERROR word has bits
indicating the type of error caught in the form of a 6-bit code
and the bus on which it occurred.
+ Timer
2
DATAD(0)
Word Finder
- 37 Symbol Detect
and Timing
Physical Layer to TTL
Lock Triple Buffered Mess. x512

Verify
Trigger List
Lost
Protocol
Tracker
Traffic tag FIFO x 16K + Filter M SB/001
Each bus has a seperate word finder and protocol tracker
Primary bus monitor on the MSB/001/B
11 Nov. 2008 | DST/N/079 421

Selection Paths
KAD/MSB/001/B ASD/MSB/001/TC MSB/001/B module with 52-way double-density mating connector with
flying leads (transformer coupled).
KAD/MSB/001/B ASD/MSB/001/DC MSB/001/B module with 52-way double-density mating connector with
flying leads (direct coupled).
KAM/MSB/001/B ACC/CON/009 MSB/001/B module with 51-way micro-miniature to MIL-STD-1553 (direct

coupled).
KAM/MSB/001/B ACC/CON/029 MSB/001/B module with 51-way micro-miniature to MIL-STD-1553

(transformer coupled).
the Confirmation of Order unless an alternative option is specified (see Cables data sheet). Please contact ACRA CONTROL
for details of the version of this module with mode-code-17 support.
Revision History
MSB/001/B Supports both D/C (direct coupled) input or T/C Recommended for new programs
(transformer coupled) input.
MSB/001 -- Not recommended for new programs
In this data sheet MSB/001 refers to both the KAD and KAM version of the module.
Related Products
Module Details
MSB/103 Handles all mode codes (including user defined), optional recording of messages with timed
out status reply.
MSB/003/B Improved power regulator circuitry reduce the inrush currents on power-up; up to 1024 parser
slots; full mode-code-17 support; optional store on time-out; supports interleaved message
reading; supports multiple RT to RT sources and sinks, BDMA support.
MSB/002/B Up to 800 parser slots; supports last mode-code-17 only; message must be read before switching
to next message; single RT to RT.
Document Details
TEC/NOT/004 MIL-STD-1553
www.acracontrol.com
422 11 Nov. 2008 | DST/N/079

Specifications
Input considerations: Direct coupled or Transformer coupled. The input resistors, transformers and transceivers have
all been specified by their suppliers for MIL-STD-1553 operation.
The MSB/001 handles traffic at rates above 100% on both busses simultaneously.
Sampling restrictions: The maximum sampling rate from the module is 500ksps.
Setup
ID 0 to 1FF(hex) Each bus The 17 bits of the bus (primary/secondary) and the
Each 16-bit command word can be mapped on to an 9-bit ID (0-FF
command word hex).
Message All mode codes (including user Each ID

definition defined) and all message
types
Filter All, some or none Each ID Any of the command, status, data, time tags (5) or the
Each FIFO ¼ message count for each ID can be excluded from entering
the SNARFER FIFO depending on FIFO fullness (1st,
2nd, 3rd or 4th quarter). Error reports and tags always
enter the SNARFER.
11 Nov. 2008 | DST/N/079 423

Output Registers
The diagram illustrates up to 10,503 registers that can be read from the MSB/001.
MESSAGE COUNT Primary/secondary bus MES_COUNT
UTILISATION Primary/secondary bus UTILISATION
PARSER One of 512 Message IDs COMMAND

STATUS
TIME_HI
TIME_LO
TIME_MICRO
RESPONSE
TIME_LAST
INFO
MES_CNT
DATA_31
DATA_0
SNARFER SNARFER_HI
SNARFER_LO
REPORT
Choosing a parameter to be read from the MSB/001/B
MES_COUNT Count of valid messages received on this bus
R[15:0] BCD 0000-9999, resets at 9999 R(15)
UTILISATION Reflects the percentage utilization on this bus
R[15:0] BCD 00.00-99.99% R(15)
COMMAND Command word stored in parser
R[15:0] Bits received (less synchronization and parity bits), R(15) is FTB R(15)
STATUS Status word stored in PARSER
DATA_ Data word stored in PARSER
TIME_MICRO Microsecond time midway through command sync. bit
TIME_LO Seconds and centiseconds time midway through command sync. bit
R[15:0] BCD 00.00-59.99 sec. R(15)
TIME_HI Hours and minutes time midway through command sync. bit
R[12:7] BCD 00-23 hours R(12)
RESPONSE Binary count in microseconds of response time (see MIL-STD-1553B)
424 11 Nov. 2008 | DST/N/079

R[15:0] BINARY 000016-FFFF16 Stops at FFFF16 R(15)
TIME_LAST Microsecond time midway through last data word sync. bit
MES_CNT Message counter value when this message was PARSED
R[15:0] BCD 0000-9999, Resets at 9999 R(15)
R(14) 1 Indicates this message was read before
R(13) 1 Indicates this message overwrote another
SNARFER FIFO
R(15) 1 indicates an even number of ones in the bus identifier, content identifier and content
R[14:12] BINARY 0-7, Bus identifier as defined in setup R(14)
R[11:8] BINARY 016-F16, Content identifier (see also IRIG-106 Ch.8) R(11)
F Command on primary bus 7 TIME_HI
E Status on primary bus 6 TIME_LO
D Data on primary bus 5 TIME_MICRO
C Non-data on primary bus 4 RESPONSE
B Command on secondary bus 3 MES_CNT
A Status on secondary bus 2 ERROR
9 Data on secondary bus 1 SNARFER empty
8 Non-data on secondary bus 0 SNARFER full
SNARFER_LO SNARFER contents as indicated by content identifier. This and SNARFER_HI are read
from the SNARFER FIFO
R[15:0] The contents of the SNARFER R(15)

For bit definition of COMMAND, STATUS, DATA, TIME_HI, TIME_LO, TIME_MICRO,
RESPONSE, and MES_CNT see earlier.
The contents for SNARFER empty are AAAA16
The contents for SNARFER full are 555516
The contents for NON-DATA are the command/status bits if not enough information is
available to distinguish between them (this can only happen when recovering from an error
condition)
The R[15:7] for ERROR are reserved, R(6) = 1 indicates the error was on the secondary
bus, R[5:0] is the Error codes as below
R(15) 1 Indicates error occurred since last read
R(9) 1 indicates the last error occurred on secondary bus
R[5:0] Indicates the error that occurred last (see below) R(5)
R[5:0] Indicates the error that occurred last (Please see Error codes) R(5)

FTB = First Bit Transmitted (received)
11 Nov. 2008 | DST/N/079 425

Getting the most from the MSB/001
Even if the SNARFER is not required for traffic and tags it
may be worth considering setting the SNARFER filter so that
only errors are recorded. This ensures that all errors and
when they happen can be logged.
426 11 Nov. 2008 | DST/N/079

Error codes for the MSB/001/B 2716 Reserved for future use.
2816 Exp. Tx cmd. of RT to RT(s) had invalid RT.

016 Debug error 1 (contact ACRA CONTROL).
2916 Exp. Tx cmd. of RT to RT(s) had invalid SA.
116 Data word did not have enough bits.
2A16 Exp. Tx cmd. of RT to RT(s) had invalid number of
216 Data word had bit error. words.
316 Data word had parity error. 2B16 Exp. Tx cmd. of RT to RT(s) had different number of
words than Rx cmd.
416 Non-data word did not have enough bits.
2C16 Exp. Tx cmd. of RT to RT(s) had same RT as Rx cmd.
516 Non-data word had bit error.
2D16 Exp. Tx cmd. of RT to RT(s) had contiguous traffic.
616 Non-data word had parity error.
2E16 Exp. Tx cmd. of RT to RT(s) was not a Tx cmd.
2F16 Reserved for future use.
816 Exp. data word was non-data word.
30-3E16 Reserved for future use.
916 Exp. data word did not have contiguous word.
3F16 Reset occurred since last read.
A16 Exp. last data word was not last.
B16 Exp. mode data word was non-data word. Exp. = Expected Tx = Transmit Contig = Con-
tiguous
C16 Exp. mode data word has contiguous traffic. Error codes are in hexadecimal.
D16 Reserved for future use.
F16 Reserved for future use.
1016 Exp. first cmd. was data word.
1116 Exp. first cmd. had invalid RT.
1216 Exp. first cmd. had invalid SA.
1316 Exp. first cmd. had invalid number of words.
1416 Exp. first cmd. was invalid mode.
1516 Exp. first cmd. had contiguous traffic.
1616 Exp. first cmd. was Rx with no contig, data word.
1716 Exp. first cmd. was Mode with no contig. data.
1816 Exp. second sts. of RT to RT was data word.
1916 Exp. second sts. of RT to RT had incorrect RT.
1A16 Exp. second sts. of RT to RT had contiguous traffic.
1B16 Exp. second sts. of RT to RT timed out.
1C16 Reserved for future use.
1D16 Reserved for future use.
1E16 Reserved for future use.
2016 Exp. sts. was data word.
2116 Exp. sts. was invalid.
2216 Exp. sts. had incorrect RT.
2316 Exp. sts. had contiguous traffic.
2416 Exp. sts. timed out.
2516 Exp. sts. had no contiguous data word.
11 Nov. 2008 | DST/N/079 427

Connector pinout of KAD/MSB/001/B

1 NC Do not connect
2 DATAD(0)+ MIL-STD-1553 Direct coupled Primary bus (by convention only)
3 NC Do not connect
4 NC Do not connect
5 NC Do not connect
6 NC Do not connect
7 DATAT(0)+ MIL-STD-1553 Transformer coupled Primary bus (by convention only)
8 NC Do not connect
9 NC Do not connect
12 DATAT(1)+ MIL-STD-1553 Transformer coupled Secondary bus (by convention only)
17 DATAD(1)+ MIL-STD-1553 Direct coupled Secondary bus (by convention only)
37 DATAD(0)- MIL-STD-1553 Direct coupled Primary bus (by convention only)
41 DATAT(0)- MIL-STD-1553 Transformer coupled Primary bus (by convention only)
46 DATAT(1)- MIL-STD-1553 Transformer coupled Secondary bus (by convention only)
50 DATAD(1)- MIL-STD-1553 Direct coupled Secondary bus (by convention only)
www.acracontrol.com
428 11 Nov. 2008 | DST/N/079

KAD/MSB/103/B, KAM/MSB/103/B
A C R A KAM-500 MSB/103
Dual redundant MIL-STD-1553 bus monitor with Mode Code 17 support
C O N T R O L
DESCRIPTION
The MSB/103 is a MIL-STD-1553 dual redundant bus monitor
which combines the capabilities of a SNARFER, coherent
message parser, message counter, and error detection
functions on a single module. Traffic refers to words on the
bus (command, status and data) and tags refer to associated
information (microsecond time of sync. bit transition,
message count, response time and errors). When used in
parser mode, the MSB/103 triple buffers up to 1023 complete
messages and their associated tags in buffers up to 43 words
wide. The INFO tag associated with each message has a
FEATURES STALE bit (message read before), a SKIPPED bit (buffer
• 3K deep selective FIFO for traffic and tags (SNARFER) overwritten) and an EMPTY bit (message was never
• FIFO formatted with IRIG-106 Ch. 8 acquisition formatting received), as well as an indication on which bus the message
standard was received. The MESSAGE count increments on receipt of
• Coherently parses traffic and adds tags from up to 1023 a valid message. The ERROR word has bits indicating the
messages type of error caught in the form of a 6-bit code and the bus on
• ID based on all 16 bits of command, bus (A or B) which it occurred.
• ID based on the last Mode Code 17 sub-address map The MSB/103 records Mode Code 17, sub-address map
number received for the involved remote terminals numbers for each remote terminal separately. With that it can
• Handles all mode codes (including user-defined) monitor the full expanded sub-address space for up to 31
• Supports one message counter for each bus remote terminals. The SNARFER stores selected traffic and
• Detects 64 different errors tags in a FIFO 3K words deep. Each word has 16 bits for
• Protocol tracker does not rely on instrumentation bit traffic/tag information and 8 bits for FIFO content
• Direct coupled or transformer coupled operation identification. Data selection and content identification is
• Optional recording of messages with timed out status reply based on the bus (primary/secondary), traffic type
(command, status, data), tag type (high/low/micro/response
APPLICATIONS time, message count) and how full the FIFO is.
• MIL-STD-1553 traffic monitor
DATAD(0)+
2
DATAT(0)+
7
DATAT(0)-
41
DATAD(0)-
37 SYMBOL DETECT
AND TIMING
PHYSICAL LAYER TO TTL WORD FINDER
Lock
TRIGGER LIST
Verify
Lost
MESSAGE FILTER
PROTOCOL
TRACKER
TRAFFIC/TAG SNARFER MSB/103
Primary bus monitor on the MSB/103
25 Mar. 2009 | DST/S/053 429

Selection Paths
KAD/MSB/103/B ASD/MSB/001/TC 52-way double-density mating connector with flying leads (transformer
coupled)
KAD/MSB/103/B ASD/MSB/001/DC 52-way double-density mating connector with flying leads (direct
coupled)
KAM/MSB/103/B ACC/CON/009 51-way micro-miniature to MIL-STD-1553 (direct coupled)
KAM/MSB/103/B ACC/CON/029 51-way micro-miniature to MIL-STD-1553 (transformer coupled)
Contact ACRA CONTROL for details of the version of this module with Mode Code 17 support.
Revision History
MSB/103/B Dual redundant MIL-STD-1553 bus monitor with Mode Recommended for new programs
Code 17 support and 3K deep selective FIFO for traffic
and tags (SNARFER)
MSB/103 First release Not recommended for new programs
In this data sheet MSB/103 refers to both the KAD and KAM version of the module.
Related Products
Module Details
MSB/003/B Dual redundant MIL-STD-1553 bus monitor with Mode Code 17 support
Document Details
TEC/NOT/004 MIL-STD-1553
www.acracontrol.com
430 25 Mar. 2009 | DST/S/053

Specifications

Mass
– 76 – g
Power consumption
+5V 106 – 147 mA
+7V 0 – 0 mA
-7V 0 – 0 mA
+12V 0 – 0 mA
-12V 0 – 0 mA
MIL-STD-1553

Inputs – – 1 – Dual redundant. MIL-STD-1553-B compatible.
Sampling rate
– – 2 Msps Maximum data rate of MIL-STD-1553 is 36kwps.
Input voltage
operating range 1.3 – 20 Vp-p Applies to both transformer and direct coupled connection
methods.
Connection methods
transformer coupled – – – –
direct coupled – – – –
25 Mar. 2009 | DST/S/053 431

Setting up the MSB/103
For parameter CntBusA
Set-up data Default Choices Notes
Name CntBusA Count of valid messages received on the primary bus.
Base unit Unitless
Size in bits 16 16
For parameter CntBusB

Name CntBusB Count of valid messages received on the secondary bus.
Base unit Unitless
Size in bits 16 16
For parameter Report

Name Report Indicates status of monitor.
Base unit R(15) 1 Indicates an error occurred since last read.
R(14) 1 Indicates error occurred on secondary bus.
R[5:0] Indicates the error that occurred last (see “Error codes for the
MSB/103” on page 435).
Data format Bit vector Any
Size in bits 16 4 to 16
For parameter PackageData

Name PackageData Parser Slot Data.
Size in bits 16 16
For parameter MsgTxCmd

Name MsgTxCmd Parser slot TX Command Word.
Size in bits 16 16
For parameter MsgTxSts

Name MsgTxSts Parser slot TX Status Word.
Size in bits 16 16
For parameter MsgTxRespTime

Name MsgTxRespTime Parser slot Tx Response Time.
Base unit Seconds
Scale 1e-6
Size in bits 16 16
432 25 Mar. 2009 | DST/S/053

For parameter MsgRxCmd

Name MsgRxCmd Parser slot RX Command Word.
Size in bits 16 16
For parameter MsgRxSts

Name MsgRxSts Parser slot RX Status Word.
Size in bits 16 16
For parameter MsgRxRespTime

Name MsgRxRespTime Parser slot Rx Response Time.
Base unit Seconds
Scale 1e-6
Size in bits 16 16
For parameter MsgTimeHi

Name MsgTimeHi Parser slot Time Hi.
Base unit Unitless
Data format Bit vector Bit vector
Size in bits 16 16
For parameter MsgTimeLo

Name MsgTimeLo Parser slot Time Lo.
Base unit Seconds
Scale 1e-2
Data format BCD BCD
Size in bits 16 16
For parameter MsgTimeMicro

Name MsgTimeMicro Parser slot Time Micro.
Base unit Seconds
Scale 1e-6
Data format BCD BCD
Size in bits 16 16
For parameter MsgCnt

Name MsgCnt Parser slot Message Count.
Base unit Unitless
Size in bits 16 16
25 Mar. 2009 | DST/S/053 433

For parameter MsgInfo

Name Msginfo Info for parser slot.
Base unit R(15) 1 Indicates this message was never received before (empty).
R(14) 1 Indicates this message was read before.
R[(13) 1 Indicates overwrote another.
R(12) 1 Indicates message was received on the secondary bus. 0 indicates
message was received on the primary bus.
Size in bits 16 16
Snarfer high parameters

Name Snarfer_Hi Bus number and content identifier. This together with SNARFER_LO is read
from the SNARFER FIFO.
Base unit R(15) 1 Indicates an even number of ones in the bus identifier, content
identifier and content.
R[14:12] Bus identifier as defined in setup.
R[11:8] Content identifier, (See “Snarfer low parameters” on page 434.).
Size in bits 16 16
Snarfer low parameters

Name Snarfer_Lo SNARFER contents as indicated by content identifier. This and
SNARFER_HI are read from the SNARFER FIFO.
Base unit R[15:0] The contents of the SNARFER.
See “Setting up parameters” on page 432., for bit definition of COMMAND,
STATUS, DATA, TIME_HI, TIME_LO, TIME_MICRO, RESPONSE, and
MES_CNT.
The contents for SNARFER empty are AAAA16.
The contents for SNARFER full are 555516.
The contents for NON-DATA are the command/status bits if not enough
information is available to distinguish between them (this can only happen
when recovering from an error condition).
The R[15:7] for ERROR are reserved.
R(6) = 1 indicates the error was on the secondary bus.
R[5:0] See “Error codes for the MSB/103” on page 435.
Data format Data format is dependent on the corresponding Snarfer High contents
Size in bits 16 16
434 25 Mar. 2009 | DST/S/053

Error codes for the MSB/103 (continued)
Content IDs for MSB/103 SNARFER FIFO 2716 Reserved for future use.
016 Buffer overflow 2816 Expected Tx cmd. of RT to RT(s) had invalid RT.
116 Fill word 2916 Expected Tx cmd. of RT to RT(s) had invalid SA.
216 Non-data B (in case of error event) 2A16 Expected Tx cmd. of RT to RT(s) had invalid number of
316 Non-data A (in case of error event) words.
416 Time - Response 2B16 Expected Tx cmd. of RT to RT(s) had different number
of words than Rx cmd.
516 Time - Microsecond
2C16 Expected Tx cmd. of RT to RT(s) had same RT as Rx
616 Time - Low
cmd.
716 Time - High
2D16 Expected Tx cmd. of RT to RT(s) had contiguous traffic.
816 Error B
2E16 Expected Tx cmd. of RT to RT(s) was not a Tx cmd.
916 Data B
A16 Status B
B16 Command B
C16 Error A
D16 Data A
E16 Status A
F16 Command A
Error codes for the MSB/103
016 Reserved for future use. 3916 Reserved for future use.
116 Data word did not have enough bits. 3A16 Reserved for future use.
216 Data word had bit error. 3B16 Reserved for future use.
316 Data word had parity error. 3C16 Reserved for future use.
416 Non-data word did not have enough bits. 3D16 Reserved for future use.
516 Non-data word had bit error. 3E16 Reserved for future use.
616 Non-data word had parity error. 3F16 Reset occurred since last read.
816 Expected data word was non-data word. Tx = Transmit; sts = status; cmd = command.
916 Expected data word did not have contiguous word.
A16 Expected last data word was not last.
B16 Expected mode data word was non-data word.
C16 Expected mode data word has contiguous traffic.
D16 Reserved for future use.
F16 Reserved for future use.
1016 Expected first cmd. was data word.
1116 Expected first cmd. had invalid RT.
1216 Expected first cmd. had invalid SA.
1316 Expected first cmd. had invalid number of words.
1416 Expected first cmd. was invalid mode.
1516 Expected first cmd. had contiguous traffic.
1616 Expected first cmd. was Rx with no contiguous data
word.
1716 Expected first cmd. was Mode with no contiguous data.
1816 Expected second sts. of RT to RT was data word.
1916 Expected second sts. of RT to RT had incorrect RT.
1A16 Expected second sts. of RT to RT had contiguous traffic.
1B16 Expected second sts. of RT to RT timed out.
1C16 Received invalid 2nd status in RT to RT.
1D16 Reserved for future use.
1E16 Reserved for future use.
2016 Expected sts. was data word.
2116 Expected sts. was invalid.
2216 Expected sts. had incorrect RT.
2316 Expected sts. had contiguous traffic.
2416 Expected sts. timed out.
2516 Expected sts. had no contiguous data word.
25 Mar. 2009 | DST/S/053 435

The MSB/103 uses the X-Module-1553-Monitor XidML schema. See http://www.XidML.org.
Snarfer filter settings

SNARFER_FILTER0to25 All tags All_Tags, Selects what content is stored into the SNARFER FIFO when it is
FIFO_LEVEL_0_25 Traffic, Header, 0 to 25% full.
Error
SNARFER_FILTER26to50 Traffic All_Tags, Selects what content is stored into the SNARFER FIFO when it is
Error
SNARFER_FILTER51to75 Header All_Tags, Selects what content is stored into the SNARFER FIFO when it is
Error
SNARFER_FILTER76to100 Error All_Tags, Selects what content is stored into the SNARFER FIFO when it is
Error
AcceptMessageWithNoStatus Yes Yes or No
BusIdentifier 0 0 to 7 Specifies to which 1553 bus the module is monitoring. Used as
part of data written to the Snarfer.
Mode Code 17 settings

DefaultMapOnPowerUp None 16 bit hex
value
LoadMapFrom None SSA or cycle
BroadcastOnly None Yes or No
IgnoreFreshBit None Yes or No
IgnoreTimeBit None Yes or No
For each message buffer on the MSB/103

MessageBuffer Name of a 1553 message.
name None Any Each buffer must have a unique name.
MessageReference None Any A reference to a named 1553 message.
index None Any Index values must be unique.
Setting up packages
The MSB/103 uses the X-MIL-STD-1553-Message XidML schema to define messages. There are 10 types of 1553 message.
See http://www.XidML.org.
Messages between bus controller and remote terminal

Set-up data Notes
Message Type
Bus ControllerTo RemoteTerminal This element defines a message from a bus controller to a remote terminal.
RemoteTerminalToBusController This element defines a message from a remote terminal to a bus controller.
RemoteTerminalToRemoteTerminal This element defines a message from a remote terminal to a remote terminal.
BusControllerToAllRemoteTerminals This element defines a broadcast message from a bus controller to all remote terminals.
RemoteTerminalToAllRemoteTerminals This element defines a broadcast message from a remote terminal to all other remote terminals.
ModeNoData This element defines a mode message with no data to a remote terminal.
ModeTransmitData This element defines a mode message with data from a remote terminal.
ModeReceiveData This element defines a mode message with data to a remote terminal.
BroadcastModeNoData This element defines a broadcast mode message with no data.
BroadcastModeReceiveData This element defines a broadcast mode message with data.
436 25 Mar. 2009 | DST/S/053

Non-mode code message package properties
NumberOfDataWords None Any This value allows the bus monitor to distinguish between
messages on the basis of their length. If this value is not set
then all word lengths are covered.
Mode Code message package properties

ModeCode None 0-31 This is the Mode Code number.
1553 message source section

RemoteTerminal None 0-30 This is the Mode Code number.
SubAddress Any or an The transmitting remote terminal's ID. The absence of this
address between value indicates that the message is defined for any transmitting
0 and 31 remote terminal.
SubAddressMap Any or a Map A sub-sub-address on the remote terminal.
between 1 and
128
This section only applies to the RemoteTerminalToBusController, RemoteTerminalToRemoteTerminal,

RemoteTerminalToAllRemoteTerminals and ModeTransmitData message types.
1553 message destination section

RemoteTerminal None 0-30 This is the Mode Code number.
SubAddress Any or an The transmitting remote terminal's ID. The absence of this
address between value indicates that the message is defined for any
0 and 31 transmitting remote terminal.
SubAddressMap Any or a Map A sub-sub-address on the remote terminal.
between 1 and
128
This section does not apply to the RemoteTerminalToBusController, ModeNoData and ModeTransmitData message types.
For each parameter in the 1553 message content section

NumberOfDataBits 16 1-512 The transmitting remote terminal's ID. The absence of this
value indicates that the message is defined for any transmitting
remote terminal.
Location A parameter can be placed in up to 32 locations.
Offset_Words/ Offset_Bits None Between 1 and A location can be specified using either Word or Bit offsets.
128 Both offset values start at 0.
Occurrences None Any The number of times that a parameter occurs in a package. If
this value is greater than one then it is presumed that each
occurrence of a parameter is placed at equally spaced intervals
in the package.
This section does not apply to the ModeNoData and BroadcastModeNoData message types.
25 Mar. 2009 | DST/S/053 437

The MSB/103 uses the X-1553-DataLink-1.0 XidML schema. See http://www.XidML.org.

MaximumResponseTime 12 16-bit value in When a status reply hasn’t been observed within the maximum
units of 1ms response time, the module will indicate a timeout error.
Getting the most from the MSB/103 may belong to that message as a status word. This may
cause issues parsing the next message. If the response time
The following section describes how to configure the is set too low then the MSB/103 may consider that a valid
MSB/103 for specific data acquisition requirements. message has timed out due to no response. The status of this
message will appear as the next command. This may cause
Handling remote terminals that are off-line issues parsing the next message and so on.
In many flight test applications it is desirable to acquire data
from off-line MIL-STD-1553 remote terminals. In this situation Parser sample rate
the MIL-STD-1553 message will not have a response word, The MSB/103 parser is triple buffered. If there is a burst of
and the configuration option is “Accept message with no more than three messages between parser sampling
status”1. If this option is enabled then the MSB/103 parser will intervals, the triple buffer can be saturated. Therefore if it is
capture messages with no status response. Otherwise these necessary that all messages get captured, the parser data
partial messages will not be stored. It is recommended that must be sampled at the speed of the burst if this is above the
“Accept message with no status” is set if there are aggregate rate.
MIL-STD-1553 remote terminals off-line during acquisition.
Variable sized messages
Detecting messages where the remote terminal
By default the MSB/103 is configured to parse any number of
is off-line
data words for a particular message. It is also possible to
If “Accept message with no status” is set, the relevant parse messages of particular sizes.
STATUS and RESPONSE time is set to FFFF16. This detects
In cases where there are variable sized messages and when
whether a remote terminal is off-line or not. word count is set to “all”, care must be taken when
When the transmission remote terminal is off-line, ensure processing the data. The parser will only update the data
only the transmission command appears on the bus and this words that appear on the MIL-STD-1553 bus. The other
is the only valid part of the message stored in the parser. For words will not be valid. This means that the ground station or
a remote terminal-to-remote terminal message, only the Tx post processing must use the number of data words indicated
and Rx commands will be stored. It is important that the in the command word to identify which data words are valid.
ground station or postprocessing does not consider data from The other option is to parse particular message sizes
messages where the Tx remote terminal is off-line since individually.
these words will be invalid. The first status will always be
FFFF16 in these cases. SNARFER sampling rate
The SNARFER sample rate should be set according to the
Response time expected aggregate bus traffic. A 100% utilized bus will have
One feature of the MSB/103 is the ability to program the MIL-STD-1553 traffic appearing at 50kHz. This can be used
response timeout. This value should reflect the actual as a guideline for configuring the SNARFER sample rate. For
response timeout on the MIL-STD-1553 bus. Under normal 100% utilization, sample at 50kHz; for 50% utilization, sample
circumstances a remote terminal will respond within 4 to 12 at 25kHz and so on.
microseconds. However a remote terminal should wait a If the FIFO overflows MIL-STD-1553 traffic will be lost.
minimum of 14 microseconds before considering that the Therefore it is important to set the SNARFER filter settings
remote terminal has timed out. Some implementations of appropriately.
MIL-STD-1553 have deviated from the standard and have
their own response times. For this reason the expected
response time is configurable on the MSB/103.
The reason why it is important for the MSB/103 to have the
response time configured correctly is that there may be
confusion over which MIL-STD-1553 messages certain
control words belong to. In MIL-STD-1553 the command
word and status word have the same signature.
For example if the response time is set too high and if there is
no response from a particular RT the next command word
1. This option was previously called “Store on timeout” in

KSMv2 and KSM-500
438 25 Mar. 2009 | DST/S/053

Connector pinout of the KAD/MSB/103

2 DATAD(0)+ MIL-STD-1553 Direct coupled primary bus
7 DATAT(0)+ MIL-STD-1553 Transformer coupled primary bus
12 DATAT(1)+ MIL-STD-1553 Transformer coupled secondary bus
17 DATAD(1)+ MIL-STD-1553 Direct coupled secondary bus
37 DATAD(0)- MIL-STD-1553 Direct coupled primary bus
41 DATAT(0)- MIL-STD-1553 Transformer coupled primary bus
46 DATAT(1)- MIL-STD-1553 Transformer coupled secondary bus
50 DATAD(1)- MIL-STD-1553 Direct coupled secondary bus
51 GND KAM-500 internal ground Do not connect
www.acracontrol.com
440 25 Mar. 2009 | DST/S/053

KAD/PBM/001, KAM/PBM/001
A C R A KAM-500 PBM/001
C O N T R O L 8 channel Panavia bus monitor
DESCRIPTION
The PBM/001 is a Panavia bus monitor. It combines the
capabilities of an all-pass/selected-pass monitor, a coherent
message parser and a range of error detection functions all
on a single module.
In the discussion below, traffic refers to words on the bus and
tags refers to associated information (time tags, word count,
and errors).
The PARSER triple buffers up to 256 words and their
FEATURES associated tags in buffers (word being read, word being
received on each bus and a buffer). The INFO tag associated
• Monitors up to 8 busses with each message has a STALE bit (word read before) and a
• Coherently PARSEs traffic and tags up to 256 words SKIPPED bit (buffer overwritten).
• 16K deep selective FIFO for traffic and tags (SNARFER)
The SNARFER stores selected traffic and tags in a FIFO 16K
• Word counter for each bus
words deep. Each word has 16 bits for traffic/ tag information
• Detects 8 types of errors
and 8 bits for FIFO content identification. Data selection and
content identification is based on the Bus (0 to 7), Word ID (0
APPLICATIONS to 31), tag type (High/Low/Micro, message count) and how
• Panavia bus monitoring full the FIFO is.
The WORD count increments on receipt of a valid word. The
REPORT word has bits indicating the type of error caught
and the bus it occurred on.
+ 1
Timer
DATA(0)
2
-
Word Finder
+
3 Symbol Detect
DCLK(0) and Timing

4
-
Physical Layer to TTL
Triple buffered Word x 256

Lock
Verify
ID List
Lost
Sequence
GND 51 Tracker
Traffic tag FIFO x 16K + Filter PBM/001
First of eight independent Panavian busses
10 Nov. 2008 | DST/N/074 441

Selection Paths
Airborne Data Acquisition → KAM-500 → Modules → Bus → Panavia
KAD/PBM/001 CON/KAD/002/CP PBM/001 module, with 52-way double density module top connector
KAM/PBM/001 ACC/CON/008/04 PBM/001 module, with 51-way micro-miniature module top connector
Revision History
PBM/001 First release Recommended for new programs
In this data sheet PBM/001 refers to both the KAD and KAM version of the module.
Related Products
Module Details
KSMv2 This product is supported by KSMv2 software (command line only); this product is supported by
kProgram (version 1.5 upwards)
Document Details
TEC-NOT-008 Panavia
TEC-NOT-009 Panavia and the KAD/PBM/001
www.acracontrol.com
442 10 Nov. 2008 | DST/N/074

Specifications
Input considerations:
Sampling restrictions: The maximum sampling rate from the module is 500kHz.
Setup
Sequence ON or OFF Each bus If sequence checking is enabled the complete sequence of tags must
checking be specified.
Filter All, some or Each bus Any of the data words, time tags (3) or the word count for each bus
none Each tag and tag can be excluded from entering the SNARFER FIFO depending
Each FIFO 1/4 on the FIFO fullness (1st, 2nd, 3rd or 4th quarter). Error reports and
tags always enter the SNARFER.
Output Registers
The diagram below illustrates the 1547 registers that can be read from the PBM/001.
SNARFER SNARFER_HI
SNARFER_LO
PARSER One of 8 busses One of 32 tags TIME_HI

TIME_LO
TIME_MICRO
WD CNT
DATA_HI
DATA_LO
WORD COUNT One of 8 busses WORD_COUNT
REPORT
Choosing a parameter to be read from the PBM/001
10 Nov. 2008 | DST/N/074 443

WORD_COUNT Count of all valid words received on this bus
DATA_LO 16 data bits
R[15:0] DATA[15:0] R(15)
DATA_HI Empty, stale, skipped, bus and TAG
R(15) EMPTY
R(14) STALE
R(13) SKIPPED
R[7:5] BUS[2:0] R(7)
R[4:0] TAG[4:0] R(4)
WD_CNT Word counter value when word was received
R[15:0] Binary 0000-FFFF (hex), resets at FFFF R(15)
TIME_MICRO Microseconds time midway through last transmitted bit
TIME_LO Seconds and centiseconds midway through last transmitted bit
R[15:0] BCD 00.00-99.99 seconds R(15)
TIME_HI Hours and minutes midway through last transmitted bit
R[12:7] BCD 00-23 hours R(12)
SNARFER_FIFO
R[15:13] BINARY 0-7 indicates the bus the word occurred on R(15)
R[11:8] BINARY 0-F content identifier R(11)
0 ERROR 1 SNARFER full 2 WD_CNT 3 DATA_LO
4 DATA_HI 5 TIME_MICRO 6 TIME_LO 7 TIME_HI
8 SNARFER EMPTY 9-F Reserved for future use
SNARFER_LO Snarfer content as indicated by content identifier. This together with SNARFER_HI is read
from the SNARFER_FIFO.
R[15:0] For bit definition of DATA_LO,TIME_HI,TIME_LO, TIME_MICRO and WD_CNT see above R(15)
SNARFER_EMPTY = 5555 (hex)
SNARFER_FULL = AAAA (hex)
ERROR = “000000000000”,ERR_CODE[3:0]
DATA_HI = DATA[15:0]
DATA_LO = "000000",Reserved[1:0],"000",TAG[4:0]
R[6:4] Indicates the bus the last error occurred on R(6)
R[3:0] Indicates the error that occurred last (Please see Error codes) R(3)

LTB = Last Transmitted Bit
444 10 Nov. 2008 | DST/N/074

Getting the most from the PBM/001
Even if the SNARFER is not required for traffic and tags it
may be worth considering setting the SNARFER filter so that
only errors are recorded. This ensures that all errors and
when they happened can be logged.
Error codes for the PBM/001
016 Bad bit
116 Not enough bits
216 Too many bits
316 Spare bit error
416 Parity error
516 Invalid tag
616 Sequence error (if enabled)
716 Control error
916-F16 Reserved for future use
10 Nov. 2008 | DST/N/074 445

Connector pinout of KAD/PBM/001
1 DATA(0)+ Panavia In Panavia bus (data) First bus
2 DATA(0)- Panavia In Panavia bus (data) First bus
3 DCLK(0)+ Panavia In Panavia bus (data clock) First bus
4 DCLK(0)- Panavia In Panavia bus (data clock) First bus
5 DATA(1)+ Panavia In Panavia bus (data)
6 DATA(1)- Panavia In Panavia bus (data)
7 DCLK(1)+ Panavia In Panavia bus (data clock)
8 DCLK(1)- Panavia In Panavia bus (data clock)
29 DATA(7)+ Panavia In Panavia bus (data) Last bus
30 DATA(7)- Panavia In Panavia bus (data) Last bus
31 DCLK(7)+ Panavia In Panavia bus (data clock) Last bus
32 DCLK(7)- Panavia In Panavia bus (data clock) Last bus
www.acracontrol.com
446 10 Nov. 2008 | DST/N/074

KAD/PBM/002, KAM/PBM/002
A C R A KAM-500 PBM/002
C O N T R O L A parser for the MC (and ENMC) link
DESCRIPTION
The PBM/002 is used to parse words from an MC (or ENMC)
link. Each word is parsed according to its word number and
minor-frame number allowing normal, super or sub
commutation of parameters in the incoming stream.
Parameters in frozen frames or repeat frames are not
updated.
When in lock the PBM/002 writes each parameter to a
specific location in the Current Value Table (CVT). The
location to write to is returned from a lookup table whose
FEATURES inputs are the minor-frame count, word number and whether
• Parses up to 1024 parameters or not the frame is a repeat or frozen.
• Ignores frozen frames The PBM/002 remains in lock until a bad bit occurs, or a
• Ignores repeat frames syncword is not where it is expected, or the SFID jumps by
• Corrects bit reversal of data more than one. It remains out of lock until two consecutive
• Handles MC and enhanced MC (ENMC) format syncwords are found.
The PBM/002 is available with two connector options:
APPLICATIONS KAM/PBM/002 has a 51-way micro-miniature connector and
• MC link monitoring KAD/PBM/002 has a 52-way double density connector.
+
1
DATA
- 2
+
3 16
DCLK
- 4
Lock
WORD
SERIAL → FRAME 12
Verify
SWITCH PARALLEL FROZEN
Lost REPEAT
WORD
STALE
FINDER LOOKUP 1-DEEP
PROTOCOL CVT
TRACKER
DATA
22
DCLK
23
BIT FINDER
PBM/002
Key elements of PBM/002
18 Oct. 2006 | DST/N/126 447

Selection Paths
Airborne Data Acquisition → KAM-500 → Modules → Bus → Panavia
KAD/PBM/002 CON/KAD/002/CP PBM/002 module, with 52-way double density module top connector.
KAM/PBM/002 ACC/CON/008/04 PBM/002 module, with 51-way micro-miniature module top connector.
Revision History
PBM/002 A parser for the MC (and ENMC) link. Recommended for new programs
In this data sheet PBM/002 refers to both the KAD and KAM version of the module.
Related Products
Module Details
PBM/001 8 Channel Panavia bus monitor.
Document Details
TEC/NOT/008 Panavia
www.acracontrol.com
448 18 Oct. 2006 | DST/N/126

Specifications
Busses 1
Input considerations TTL-buffered inputs. Clock set to 64kHz.

RS-422 (differential-ended). Clock set to 64kHz.
Setup
Assign a parameter name to each word of each minor-frame and whether to parse it when frozen or repeated.
Output Registers
The diagram below illustrates the 1024 registers that can be read from the PBM/002.
CHASSIS # MODULE #
DATA
One of 1024 parameters
REPORT
Choosing a parameter to be read from the PBM/002
DATA Data bits extracted from the link
R[15:0] See figure 1 below, D15 is LRB. R[15:0] = D[15:0] R(15)
REPORT R(15) New error occurred
R(14) Syncword occurred since last read
LRB = Last received bit
18 Oct. 2006 | DST/N/126 449

Error codes for the PBM/002
016 Parity error in word
116 Bad clock bit
216 Bad data bit
416 Fixed bit in data word not correct
516 SFID count changed by more than +1
616 No syncword where expected
816-E16 Reserved for future use
F16 No errors
Error codes are in hexadecimal
450 18 Oct. 2006 | DST/N/126

Getting the most from the PBM/002
The complete structure of the major frame received is as outlined in See “Figure 1. Complete structure of the major frame
received”. There is no stale or skipped indication with this bus monitor. The PBM/002 has two modes of operation. In MC mode
the frozen bit indicators and frame counter as shown in the first SFID definition are used, for the ENMC mode the frame counter
and frozen bits as shown in the second SFID definition are used.
Figure 1. Complete structure of the major frame received
18 Oct. 2006 | DST/N/126 451

Connector pinout of KAD/PBM/002

1 DATA+ RS-422 In PCM data Internally terminated with 120Ω
2 DATA- RS-422 In PCM data Internally terminated with 120Ω
3 DCLK+ RS-422 In PCM data clock Internally terminated with 120Ω
4 DCLK- RS-422 In PCM data clock Internally terminated with 120Ω
5 NC Do not connect
6 NC Do not connect
7 NC Do not connect
8 NC Do not connect
9 NC Do not connect
22 DATA BTTL In PCM data
23 DCLK BTTL In PCM data clock
www.acracontrol.com
452 18 Oct. 2006 | DST/N/126

KAM/SBM/001
SBM/001 Stanag-3910 bus monitor
DESCRIPTION
The SBM/001 is a bus monitor for use with STANAG-3910
dual-redundant avionics busses.
The SBM/001 monitors both primary and secondary busses
simultaneously, and coherently parses up to 254 different bus
messages (up to 8192 words in total). Each message is given
a unique 8-bit ID, based on the destination address (DA) and
physical address (PA) of the message. As an option, each
occurrence of each message can be time-tagged.
The SBM/001 maintains a message count for both primary
and secondary busses, and reports errors which occur on
FEATURES both busses. Thus, the SBM/001 has four LEDs: two per bus
• Parses one Stanag-3910 dual-redundant avionics bus indicating traffic (green) and errors (red). In the event that a
• Coherently stores traffic and tags for up to 254 different 4-bit preamble (PR) and start delimiter (SD) is received, the
messages green LED for each bus lights for 100 to 200ms. If an error is
• Adds stale, skipped and empty tags per message detected the red LED will light for 100 to 200ms. The module
• Adds message count and time tags per message assumes that data arrives on only one bus at a time
• LED indication on module top block for traffic (green) and
The SBM/001 keeps a message count, and stale and skipped
errors (red) for each bus
indication for each of the 254 parsed messages.
• Detects CRC/FC/WC and invalid PA/DA errors
The SBM/001 is two KAM-500 user-slots wide.
APPLICATIONS
• Stanag-3910 avionics bus monitoring
Timer
A Word
finder
Optic-fiber to TTL
Symbol detect and timing
10 LOCK
Trigger VERIFY
LOST
list Triple buffered
mess. X 255
Protocol tracker
SBM/001
Primary bus (secondary bus not shown)
18 Dec. 2008 | DST/J/059 453

Selection Paths
Airborne Data Acquisition → KAM-500 → Modules → Bus → STANAG-3910
KAM/SBM/001 Dual redundant Stanag-3910 bus monitor
The SBM/001 module is supplied without a mating connector. For details of the recommended mating connector, consult the
Stanag-3910 standard.
Revision History
SBM/001 First release Recommended for new programs
Related Products
Module Details
KSM-500 This module is supported by the KSM-500 suite of software tools; this product is supported by
kProgram (version 1.6 upwards)
KSMv2 This module is supported by KSMv2 software
Document Details
18 Dec. 2008 | DST/J/059 454

Specifications

Slots – – 2 – This unit occupies two user-slots. Due to the high power
consumption, if using more than two SBM/001 modules per
chassis, contact ACRA CONTROL.
Mass
– 225 – g
Power consumption
+5V 600 – 875 mA
±7V – – – mA
±12V – – – mA
STANAG3910 optical inputs

Inputs – – 2 – Optical STANAG 3910 inputs JN1055 (HA) style receptacle;
type N (normal) keyways.
Signaling rate
Data – – 20 Mbps
Input signal
operating range -35 – -12 dBm
overload protection – – +7 dBm
18 Dec. 2008 | DST/J/059 455

Setting up the SBM/001
ID 1 to FE (hex) Each PA, DA The 20 bits associated with PA and DA are mapped to an 8-bit ID
Output registers
The diagram below illustrates the registers that can be read from the SBM/001.
MESSAGE COUNT Primary/secondary bus MESSAGE_COUNT
PARSER One of 256 Message IDs

HI_TAG
LO_TAG
MICRO_TAG
INFO
MSG_COUNT
REPORT DATA_4095
DATA_0
Choosing a parameter to be read from the SBM/001
MESSAGE_COUNT Count of valid messages received on this bus
R[15:0] BINARY 0000-FFFF (hex), Resets at FFFF R(15)
DATA_ 16 data bits
R[15:0] D(15) is first transmitted bit R(15)
MSG_COUNT Value of MESSAGE_COUNT when message was received on this bus
INFO Stale/skipped indication
R(15) 1 indicates the tags and data associated with this message was read before
R(14) 1 indicates the tags and data associated with this message overwrote others
R(13) Bus 0=A, 1=B
MICRO_TAG Microsecond time midway through first transmitted bit
LO_TAG Seconds and centiseconds time midway through first transmitted bit
R[15:0] BCD 00.00-59.99 seconds R(15)
HI_TAG Hours and minutes time midway through first transmitted bit
R[12:7] BCD 00-23 hours R(12)
18 Dec. 2008 | DST/J/059 456

R[3:0] Indicates the error that occurred last (for details see “Error codes for the SBM/001” on R(3)
page 457)
Error codes for the SBM/001
016 Invalid PA/DA
116 Incorrect CRC
216 Bad bit
316 Incorrect FC
416 Incorrect bits in WC
516 ED not correct
616 SD on other bus
716-F16 Reserved for future use
18 Dec. 2008 | DST/J/059 457

Connector
Primary Secondary
Errors on secondary
Traffic on secondary
Errors on primary
Traffic on primary
www.acracontrol.com
458 18 Dec. 2008 | DST/J/059

KAM-500 KAD/SDI/103
KAD/SDI/103 Serial data bus parser
DESCRIPTION
The KAD/SDI/103 is used to read data serially from external
devices and store the data in a coherent frame buffer.
Synchronization is done via a Data clock, a Word clock and a
Frame clock.
FEATURES
• Frame data is time-tagged using standard 3 x 16 timer to
1µs resolution
• Decommutates one serial stream in RS-422 format
• Accepts NRZ-L, Bit clock, Word clock and Frame clock
• 100kbps, 200kbps, 300kbps, 500kbps, 800kbps, 1Mbps
baud rates supported
• Supports 4, 8, 16, 32, 64, 128, 256, 512, 1024, 2048, 4096
words per frame
• Programmable word length (12 or 16-bit)
• No supercommutation
• All inputs have option for termination
• NRZ-L and Bit clock can be triggered on rising or falling
edge
APPLICATIONS
• Data acquisition systems
• General purpose serial data read from external devices
DATA+ 1 +
120
DATA_TRM+ 34
34
- LOCK CVT
DATA- 2
SERIAL →
PARALLEL VERIFY
LOST
DCLK+ 3 +
120
DCLK_TRM+ 36
DCLK- 4 -
WORD_CLOCK+ 5 +
120
WORD_CLOCK_TRM+ 38
38
WORD_CLOCK- 6 -
FRAME_CLOCK+ 7 +
120
FRAME_CLOCK_TRM+ 40
FRAME_CLOCK- 8 -
GND 51
KAD/SDI/103
KAD/SDI/103 block diagram
20 Jan. 2009 | DST/U/015 459

Selection Paths
Airborne Data Acquisition → KAM-500 → Modules → Bus → RS-232/422/485
KAD/SDI/103 Serial data bus parser
Revision History
KAD/SDI/103 First release Recommended for new programs
Related Products
Module Details
Document Details
www.acracontrol.com
460 20 Jan. 2009 | DST/U/015

Specifications

Mass
– 64 – g
Power consumption
+5V 80 – 105 mA
±7V 0 – 0 mA
±12V 0 – 0 mA
RS-422 inputs

Signaling rate
DATA – – 1 Mbps
Input voltage
logic ‘0’ – – 0.2 V VIN+ - VIN-
logic ‘1’ 0.2 – – V VIN+ - VIN-
overvoltage protection -7.5 – 12.5 V Voltages outside of this range can damage input.
Input resistance
20 Jan. 2009 | DST/U/015 461

Setting up the KAD/SDI/103
acquisition system

462 20 Jan. 2009 | DST/U/015

The following table lists the setup configurations available for the KAD/SDI/103.

Manufacturer
PartReference KAD/SDI/103 KAD/SDI/103 ACRA CONTROL part number.
SerialNumber – – Unique number for each module.
InterConnects
SERIAL-DATA-IN No character limit Not Specified Externally clocked serial input.
Module-Parser-1.0 – – –
PackageBuffers – – –
PackageBuffer
Parser – – Serial frame content and tags.
PackageReference No character limit MySDIFrame –
The following table lists all parameters that are available for the KAD/SDI/103.

MessageTimeHi
Hours and minutes of the 44-bit Unitless BitVector 16 R[15:13] Reserved for future use.
time register when first bit of the R[12:7] Time[43:38] BCD Hours 0 to 23.
frame was received. R[6:0] Time[37:31] BCD Minutes 0 to 59.
MessageTimeLo
Seconds and centiseconds of the Second BCD 16 R(15) Reserved for future use.
44-bit time register when first bit R[14:8] Time[30:24] Seconds 0 to 59 .
of the frame was received. R[7:0] Time[23:16] Centiseconds 0 to 99.
MessageTimeMicro
Microseconds of the 44-bit time Second BCD 16 R[15:0] Time[15:0] Microseconds 0 to 9999.
register when first bit of the
frame was received.
Counter
Number of frames received since Count OffsetBinary 16 R[15:0] 0000:FFFF.
power-up
MessageCounter
Value of frame counter when Count OffsetBinary 16 R[15:0] 0000:FFFF.
frame was parsed
MessageInfo
Status of serial data channel – BitVector 16 R(15) Error received on the bus since last read.
R(11) Buffer is empty.
R(10) Data has been read before.
R(9) Data has been overwritten.
R(2) Frame clock error.
R(1) Word clock error.
R(0) Bit clock error.
PackageData
Serial frame data – BitVector 12 12 R[11:0] is data, with R[15:12]='0'.
16 16 R[15:0].
20 Jan. 2009 | DST/U/015 463

PackageData

SizeInBits 12 Not Specified R[15:0].
16
ParameterTypeReference – – –

following are data links supported by the KAD/SDI/103.
SERIAL-DATA-IN
Externally clocked serial link (RS-422) with word and frame pulse.

ProtocolProperties
BitRate 1,000,000 Not Specified –
800,000
500,000
300,000
200,000
100,000
Setting up packages
SDI-PACKAGE
SDI frame definition.

ReferencedToAbsoluteTime No No Data can only be received asynchronously.
DataLinkReference No character Not Specified –
limit
Properties – – –
MajorFrameProperties – – –
BitsPerMinorFrame 65536:48 512 65536 when using a 16-bit word size and 4K words
per frame.
MinorFramesPerMajorFrame 1 1 –
DefaultDataBitsPerWord 12 16 Bit per word.
16
DefaultMostSignificantBit First First –
FillPattern – – –
DefaultParity None None –
SynchronizationStrategy
SyncWord – – –
SubframeSynchronizationStrategy – – –
Modulation
PCMCode – – –
DclkPhase 0 0 –
180
PCMPolarity True True –
False
Content – – –
Parameter – –
NumberOfDataBits 12 Not Specified –
16
MostSignificantBit First First –
464 20 Jan. 2009 | DST/U/015

Location
MinorFrameNumber 1 1 There can only ever be 1 minor frame per package.
Offset_Words 4096:1 1 –
Offset_Bits 65520:12 16 –
Occurrences 4096:1 1 Number of occurrences of this parameter per
frame.
"/><\.
Getting the most from the Power considerations

KAD/SDI/103 By design, any KAM-500 chassis can be configured with any
combination of KAM-500 modules. However, there are
Serial lines waveform exceptions where total power requirements must be
Figure 2 illustrates serial data timing. Word identification is considered. Refer to the relevant chassis data sheet and
done via a Data clock (DCLK) and a Word clock. The Frame TEC/NOT/016 - Power dissipation for power/current
clock occurrence can be identified by a unique flag or by a limitations.
time word in the PCM frame. This is identified and checked
against the expected frame sync. location as defined by the
programmed baud rate, word length and frame length.
1 0 1 1 0
Data
DCLK
Word clock
Frame clock
Frame N Frame N+1
Figure 2: Serial data timing
Interpreting MessageInfo words

The MessageInfo word D(15) indicates when a new error is
received. Although D(15) clears after it has been read, the
lower three bits do not clear on read; these three bits toggle
whenever a new error of that type is detected.
To determine which error was detected, compare the current
MessageInfo word—which will have D(15) set—with the
previous MessageInfo word.
The toggles of the lower MessageInfo bits indicate the error
type.
Loss of frame sync

Data is assembled into frames using the Frame clock, and
stored in a triple buffer. The frames can be read in received
order. If data is read again before a new frame arrives, the
STALE flag is set; if data arrives and no buffer is available,
the SKIPPED flag is set.
20 Jan. 2009 | DST/U/015 465

Connector pinout of the KAD/SDI/103
1 DATA+ RS-422 inputs Data input; not internally terminated
2 DATA- RS-422 inputs Data input; not internally terminated
3 DCLK+ RS-422 inputs Data clock input; not internally terminated
4 DCLK- RS-422 inputs Data clock input; not internally terminated
5 WORD_CLOCK+ RS-422 inputs Word pulse input; not internally terminated
6 WORD_CLOCK- RS-422 inputs Word pulse input; not internally terminated
7 FRAME_CLOCK+ RS-422 inputs Frame pulse input; not internally terminated
8 FRAME_CLOCK- RS-422 inputs Frame pulse input; not internally terminated
34 DATA_TRM+ RS-422 inputs
36 DCLK_TRM+ RS-422 inputs
38 WORD_CLOCK_TRM+ RS-422 inputs
40 FRAME_CLOCK_TR+ RS-422 inputs
www.acracontrol.com
466 20 Jan. 2009 | DST/U/015

KAD/TCG/001/C, KAM/TCG/001/C
TCG/001
IRIG-B time code reader and generator with external battery
DESCRIPTION
The TCG/001 is used to seed the timers in other modules
used for time-tagging. It contains three blocks: reader, timer
and generator. The reader block is essentially a serial to
parallel converter. It checks each bit has the correct number
of 3X and 1X waveforms (analog) or has the correct Pulse
Width Modulation (PWM) shape (digital). Furthermore, it
verifies that each word has the correct number and type of
bits and that each frame starts with two reference bits. If the
SBS or CF bits are not used they must be zero. The counter
adds any delay caused by the block before loading the timer.
The timer block is a 4x16 bit BCD counter with microsecond
FEATURES
resolution. To illustrate, the time one microsecond before
• Acts as reader or generator or both midnight on Tuesday 1 March 2000 is as follows: 2000 03:01
• Reads IRIG-B123 (1kHz analog with SBS and CF) and 23:59.99 9999
IRIG-B-003
If a valid frame (that is, no errors over 101 bits) is read by the
• Generates IRIG-B123 and IRIG-B003 (AM and PWM)
time code reader all 64 bits are updated. While no errors are
• Counter has 1µsec. resolution
being received the reader supplies a 1msec. (carrier-wave
• Outputs a 1kHz tone
zero crossing) beat to the timer to keep the count
• Outputs 1 and 10pps pulses
synchronous. The timer continues counting with less than
• Less than 4.5ppm drift when acting as a generator
4.5ppm drift when the IRIG-B input signals are removed.
• Can connect external battery to maintain time during power
down
APPLICATIONS
• Time tagging with an external IRIG time
VBAT 46 TCO RTC
Regulator
+ Status
1 + ANALOG CF
TIME_AN_IN - →DIGITAL
READER
- 2 SBS
Buffer Time 1000pps
TIME_DIG_IN 21
Time
2xD/A
TONE 19 Time
DIGITAL ←
ANALOG
TIME_AN_OUT 3
CF
1 AND 10 PPS PULSE 2 Generator
TIME_DIG_OUT 18
GND 22 KAD/TCG/001/C
Internal block diagram of TCG/001/C
19 Dec. 2008 | DST/P/033 467

Selection Paths
Airborne Data Acquisition → KAM-500 → Modules → Bus → Time
KAD/TCG/001/C CON/KAD/002/CP KAD/TCG/001/C module with 52-way double density mating connector
KAM/TCG/001/C ACC/CON/008/04 KAM/TCG/001/C module with 51-way double density mating connector
Revision History
TCG/001/C Offers an additional real-time clock that can be driven by Recommended for new programs
an external battery (to maintain time during power down)
TCG/001/B Added BTTL digital IRIG time input Not recommended for new programs
TCG/001 First release Not recommended for new programs
In this data sheet TCG/001/C refers to both the KAD and KAM version of the module.
Related Products
Module Details
kSeedtime Time seeding software utility for real-time modules within KAM-500 system
KSMv2 This module is supported by the KSMv2 software
Document Details
19 Dec. 2008 | DST/P/033 468

Specifications
Channels: One IRIG-B123 (analog) input, one IRIG-B0003 digital input

8 discrete inputs
One IRIG-B123 (analog) output
One IRIG-B003 (digital) output
1pps and 10pps digital outputs
Input considerations: Analog:
Range: X = 100mVp-p min. to 10Vp-p max.
Type: D/E
Impedance:1GΩ(on)/20kΩ (off)
Protection: ±40V
Digital (BTTL):
'1' >2V '0' < 0.8V
Type: S/E
Protection: ±40V
Battery:
Input Voltage: 4.5V to 12V
Input Current: <20μA
Output considerations: Analog:
Tone Amplitude: 4Vp-p
Time Amplitude: 3X = 12Vp-p (X = 4Vp-p)
Digital (BTTL):
Type: S/E
Drift:
4.5ppm when chassis powered on
<10ppm when chassis not powered and battery connected
19 Dec. 2008 | DST/P/033 469

Setting up the TCG/001
<Parameters>
<ParameterTypeSet>
<ParameterType Name="MyMicroTimeType">
<BaseUnit>BitVector</BaseUnit>
<DataFormat>BinaryCodedDecimal</DataFormat>
</ParameterType>
</ParameterTypeSet>
:
<ParameterSet>
2 <Parameter Name="MyMicroTime">
<Source>
<Signal>
1 <InstrumentReference>MyTCG001</InstrumentReference>
3 <VendorMap>TimeMicro</VendorMap>
</Signal>
</Source>
</Parameter>
</ParameterSet>
</Parameters>
:

to
1
tReference module
Parameter- Name N/A N/A No Each pa- The name corresponding to the channel.
2
Name rameter
VendorMap Info N/A N/A No Each pa- The register (parameter) being read. For more de-
3
rameter tails, see “Output Registers” on page 472.
19 Dec. 2008 | DST/P/033 470

<Instrumentation>
<X-IRIGTimeInOut-1.1 Name="MyTCG001">
<Manufacturer>
6 <PartReference>KAD/TCG/001/C</PartReference>
</Manufacturer>
<Settings>
<IRIGTimeInOut-1.1>
11 <LeapYear>Yes</LeapYear>
<InputCode>
9 <Code>B120</Code>
10 <Polarity>No</Polarity>
</InputCode>
<ToneOutput>
7 <Frequency>1000</Frequency>
8 <Amplitude>4.0</Amplitude>
</ToneOutput>
<Channel Index="0">
<OutputCodes>
<IRIGTimePackageReference>MyPackage</IRIGTimePackageReference>
</OutputCodes>
</Channel>
</IRIGTimeInOut-1.1>
</Settings>
</X-IRIGTimeInOut-1.1>
</Instrumentation>

Location Name N/A N/A Yes Each DAU Name of DAU.
4
SubLocation Number N/A N/A Yes Each module The slot the module fits into. First us-
5
er-module goes into slot 3.
PartRefer- Selection N/A N/A Yes Each module ACRA CONTROL part number.
6
ence
Frequency Selection 500Hz, 1000Hz No Tone output The frequency of the output tone.
7
1000Hz,
1500Hz,
and
2000Hz
Amplitude Integer 10mV to 4.0 No Tone output The amplitude of the output tone.
8
10V
Code Selection B123 Analog No Analog input or The IRIG time input (analog or digital).
9
(which is digital input The user can choose which IRIG time in-
analog) or put to use.
B003
(which is
digital)
Polarity Boolean True, Normal No Analog input or The analog input circuitry assumes that a
10
False digital input positive-going zero crossing indicates the
time marker as defined in IRIG-B. Some
third-party time sources do not follow this
convention. Selecting to invert the input
will correct this.
LeapYear Boolean Yes, No N/A No Analog input or If Yes then the counter resets at 366, if No
11
digital input it resets at 365.
19 Dec. 2008 | DST/P/033 471

Output Registers
The diagram below illustrates the 8 registers that can be read from the TCG/001.
CF_HI
DISCRETE CF_LO
SBS
STATUS
TIME TIME_DOY
TIME_HI
TIME_LO
TIME_MICRO
Figure 2: Choosing a parameter to be read from the TCG/001
SBS1 LSBs of straight binary seconds received
R[15:0] SBS[15:0] The LSBs of the straight binary seconds received R(15)
STATUS Bus status, MSB of SBS and discrete inputs received
R(15) 0 indicates an error in the incoming IRIG-B stream
R(14) SBS(16) The MSB of the straight binary seconds received
R[13:6] DISCRETE[7:0] The values of the 8 discrete inputs R(13)
R(0) Battery (backed timer) error, 0 when no errors detected, 1 when power on test fails (battery
voltage is not present or the oscillator was not running).
CF_LO Control function bits received
R[15:5] CF[10:0] The LSBs of the control function bits received R(15)
CF_HI Control function bits received
R[15:0] CF[26:11] The MSBs of the control function bits received R(15)
TIME_MICRO Microsecond time of the start of the acquisition cycle
TIME_LO Seconds and centiseconds time of the start of the acquisition cycle
R[15:0] BCD 00.00-59.99 seconds R(15)
TIME_HI Hours and minutes time of the start of the acquisition cycle
R[12:11] BCD 10’s of hours R(12)
R[10:7] BCD hours R(10)
R[6:4] BCD 10’s of minutes R(6)
R[3:0] BCD minutes R(3)
TIME_DOY Day of year
R[9:0] BCD 001-366 days R(9)
1. The SBS read register is loaded with the SBS of the last valid IRIG frame received and therefore will be up to 1.25 seconds behind the TIME
registers.
CF = Control Function Bits SBS = Straight Binary Seconds 00000-1517F (hex)

LSB = Least Significant Bit BCD = Binary Coded Decimal
19 Dec. 2008 | DST/P/033 472

Getting the most from the TCG/001/C
The generator block transmits two IRIG-B codes
(pulse-width-code and 1kHz carrier), a 1kHz tone output and
two pulses (1 and 10pps). CF bits in the IRIG-B codes can be
taken from the reader or from any parameter on the
backplane. The generator subtracts the delay caused by the
block before generating the stream.
It is important to ground (GND) the source of the IRIG-B
stream. If the time source is single-ended, the GND should
also be connected to the negative IRIG-B input TIME_AN_IN.
It is also important that the input connection is not inverted as
this may not synchronize. The SBS read register is loaded
with the SBS of the last valid IRIG frame received. Therefore,
it will be up to 1.25 seconds behind the TIME registers.
If the TCG/001 is powered on without an external battery
connected, its timer resets to its default value. It will display
1:00:00:00:00:0000 and count from there onwards.
When a valid IRIG frame is received, the TCG/001's timer is
updated, which in turn updates the battery backed timer. The
KAM-500 can then be left without power, and the time will be
maintained by the battery backed timer (if a battery is
connected). When power is reapplied, the TCG/001 will
display a valid time one second after power up (if the battery
has remained connected).
On power-up, if the battery backed timer is valid (the battery
is present and the oscillator is running) then on the next
update of the seconds (maximum one second from
power-up) the state machine reads the time from the battery
backed timer and updates the TCG/001's timer.
19 Dec. 2008 | DST/P/033 473

Connector pinout of the TCG/001
1 TIME_AN_IN+ Analog IRIG time inputs Analog IRIG-B time in (AM/PWM); 1kHz carrier
2 TIME_AN_IN- Analog IRIG time inputs Analog IRIG-B time in (AM/PWM); 1kHz carrier
3 TIME_AN_OUT Analog IRIG time outputs Analog IRIG-B time out (AM/PWM); 1kHz carrier
5 DISCRETE(0) BTTL inputs Discrete input; LSB
6 DISCRETE(1) BTTL inputs Discrete input
12 DISCRETE(7) BTTL inputs Discrete input; MSB
13 NC Not connected
14 NC Not connected
16 10PPS_PULSE BTTL outputs Pulses 10 times per second; high for 10msec.
17 1PPS_PULSE BTTL outputs Pulses once per second; high for 100msec.
18 TIME_DIG BTTL outputs Digital IRIG-B time out (PWM)
19 TONE Tone outputs 1kHz sine wave, ±4Vp-p
21 TIME_DIG_IN BTTL inputs Digital IRIG-B time in (PWM)
23 NC Not connected
24 NC Not connected
25 NC Not connected
27 NC Not connected
28 NC Not connected
29 NC Not connected
30 NC Not connected
31 NC Not connected
32 NC Not connected
33 NC Not connected
34 NC Not connected
35 NC Not connected
36 NC Not connected
37 NC Not connected
38 NC Not connected
39 NC Not connected
40 NC Not connected
41 NC Not connected
42 NC Not connected
43 NC Not connected
44 NC Not connected
45 NC Not connected
46 VBAT Positive input from battery
www.acracontrol.com
474 19 Dec. 2008 | DST/P/033

KAD/UAR/001, KAM/UAR/001
A C R A KAM-500 UAR/001
C O N T R O L 8 channel RS-232 or RS-422/485 universal asynchronous receiver
DESCRIPTION
The UAR/001 is used to store serial data in a FIFO for up to 8
channels. Data for each channel is stored in a separate FIFO
2K words deep.
Because the UAR/001 does not parse data, the major frame
pulse from the encoder or BCU module can be used to
synchronize data transmission. However, all traffic must be
read and care must be taken to have an additional “dummy”
read so as to empty the FIFO in the event of a glitch. Finally,
it is important to ground (GND) each source of RS-232 or RS-
FEATURES 422/485 serial data.
• Up to 8 separate input channels The signal type, RS-232 or RS-422/485, bit-rate, bits per
• Each channel can be RS-232 or RS-422/485 word, parity and stop bits can be programmed individually for
• Bit-rates from 300 to 38,400 bps each channel.
• 7/8 bits per word
The maximum sampling rate from the module is 500kHz.
• Odd/even or no parity
• 1 or 2 stop bits The UAR/001 is available with two different connector options
• 2K FIFO per channel – the KAM/UAR/001 has a 51-way micro-miniature connector
and the KAD/UAR/001 has a 52-way double density
APPLICATIONS connector.
• General purpose serial data receiver for FTI
+ 1 +
DATA(0) 120
2
AMP
-
-
RS-422/485 Serial
FIFO
x 2K
Parallel
DATA(0) 33
RS-232
GND 51
UAR/001
First of eight channels of the UAR/001
10 Nov. 2008 | DST/N/076 475

Selection Paths
Airborne Data Acquisition → KAM-500 → Modules → Bus → RS-422/485
KAD/UAR/001 CON/KAD/002/CP UAR/001 module, with 52-way double density module top connector
KAM/UAR/001 ACC/CON/008/04 UAR/001 module, with 51-way micro-miniature module top connector
In this data sheet UAR/001 refers to both the KAD and KAM version of the module.
Revision History
UAR/001 First release Recommended for new programs
Related Products
Module Details
UAR/102 4 channel RS-232, RS-422 or RS-485 universal asynchronous parser and snarfer
UAR/003 A 2-channel RS-422 (sync-bit=address) parser
UAR/002/C 4 channel RS-232 or RS-422/485 universal asynchronous parser
Document Details
www.acracontrol.com
476 10 Nov. 2008 | DST/N/076

Specifications
Busses: 8
Inputs: D/E RS-422/485 (internal 120Ω termination)

S/E RS-232
Sampling restrictions: The maximum sampling rate from the module is 500kHz
Setup
Type RS-422/485 or RS-232 Each channel
Rate 300 to 38,400 (8 choices) Each channel Choices are 300, 600, 1200, 2400, 4800, 9600, 19,200, 38,400bps
Bits 7/8 Each channel
Parity Odd, even or none Each channel
Stop bits 1 or 2 Each channel
Output registers
The diagram below illustrates the 8 registers that can be read from the UAR/001.
CHASSIS # MODULE #
One of 8 busses SNARFER
Choosing a parameter to be read from the UAR/001
SNARFER Data received and FIFO empty and full indication
R[15:8] The 8/7 bits received. R(15) is the LBT R(15)
R(7) 1 indicates the FIFO is empty R[15:8] = 55 hex
R(6) 1 indicates the FIFO is full
LBT = Last Bit Transmitted (received)

Getting the most from the UAR/001

It is important to ground (GND) each source of the RS-422,
RS-485 or RS-232 data stream.
Because the UAR/001 does not PARSE data, a popular
method is to use the major frame pulse from the encoder or
BCU module to synchronize data transmission. However all
traffic must be read and care must be taken to have an
additional "dummy" read so as to empty the FIFO in the event
of a glitch.
10 Nov. 2008 | DST/N/076 477

Connector pinout of KAD/UAR/001
1 DATA(0)+ RS-422 in Data in D/E alternative to pin 33
2 DATA(0)- RS-422 in Data in Internally terminated with 120Ω
3 NC Do not connect
4 NC Do not connect
7 NC Do not connect
8 NC Do not connect
33 DATA(0) RS-422 in Data in S/E alternative to pins 1 and 2
47 DATA(7) RS-422 in S/E alternative to pins 29 and 30
www.acracontrol.com
478 10 Nov. 2008 | DST/N/076

KAD/UAR/002/C, KAM/UAR/002/C
A C R A KAM-500 UAR/002
4 channel RS-232 or RS-422/485 universal asynchronous parser
C O N T R O L
DESCRIPTION
The UAR/002 is used to parse, coherently extract specific
bytes, up to 4 x RS-422/485/232 channels. In total up to 126
complete messages are triple buffered so that stale indication
is message wide.
Each message can be up to 511 characters, byte, long, each
message is also time tagged to ±100μs.
A message is considered found when up to eight specific
bytes are received. The stop sequence must determine the
number of words or else a user-defined stop character.
A message is not updated if the start sequence, any word, or
FEATURES stop sequence (if any) is not correct.
• Four independent input channels
• Bitrates from 300bps to 115kbps
• Seven/eight bits per word
• Odd/even or no parity
• Programmable start sequence, (one to eight characters)
• Programmable stop sequence, (one character or by fixed
length)
• Up to 126 strings, messages, per module
• Up to 511 characters, bytes, per message
• Time tagging ±100μs
• Message-wide stale, new, indication
APPLICATIONS
• Receiving data from GPS module or onboard computer.
DATA(0)+ 1
12Ohm +
DATA(0)- 2
AMP
-
Word finder
DATA(0) 33
Lock
Verify Parser
3 X 126 X 511
GND 51 Lost
UAR/102
First of 4 independent channels
22 Dec. 2008 | DST/N/133 479

Selection Paths
KAD/UAR/002/C CON/KAD/002/CP 4-Channel RS-422/485/232 parser module, with 52-way double density
top connector
KAM/UAR/002/C ACC/CON/008/04 4-Channel RS-422/485/232 parser module, with 51-way micro-miniature

top connector
Revision History
UAR/002/C Supports a strategy of lock on large gap Recommended for new programs
UAR/002/B First release Not recommended for new programs
In this data sheet UAR/002/C refers to both the KAD and KAM version of the module.
Related Products
Module Details
Document Details
www.acracontrol.com
480 22 Dec. 2008 | DST/N/133

Specifications
Busses: 4
Inputs: D/E RS-422/485 (internal 120Ω termination) or RS-232
Sampling restrictions: The maximum sampling rate from the module is 500kHz
22 Dec. 2008 | DST/N/133 481

Setting up the UAR/002
<Parameters>
<ParameterTypeSet>
:
<ParameterType Name="MyDegreesCelsius">
<BaseUnit>Celsius</BaseUnit>
<RangeMinimum>-200</RangeMinimum>
</ParameterType>
:
</ParameterTypeSet>
<ParameterSet>
<Parameter Name="LeftWingTemperature">
1
<ParameterTypeReference>MyDegreesCelsius</ParameterTypeReference>
<DataFormat>Format</DataFormat>
<SizeInBits>Integer</SizeInBits>
:
<Source>
<Signal>
2 <InstrumentReference>MyRS232Module</InstrumentReference>
<PackageReference>MyRS232DataStream</PackageReference>
<VendorMap>P1</VendorMap>
</Signal>
</Source>
</Parameter>
:
</ParameterSet>
</Parameters>
ParameterName Name N/A N/A Yes Each The name corresponding to the
1
parameter channel.
PackageReference Name N/A N/A Yes Each module Reference to a named package
2
definition.
482 22 Dec. 2008 | DST/N/133

<Instrumentation>
<InstrumentSet>
:
2 <X-DAU Name="MyDAU">
<Manufacturer>
</Manufacturer>
</X-DAU>
:
1 <X-Module-RS-232-Monitor-1.1 Name="MyUAR002C">
<Manufacturer>
4 <PartReference>UAR/002/C</PartReference>
</Manufacturer>
<Interconnect>MyRS232DataLink</Interconnect>
</X-Module-RS-232-Monitor-1.1 >
:
</InstrumentSet>
</Instrumentation>

to
InstrumentReference Name N/A N/A Yes Each Name of module from which
1
module parameter is sourced.
Location Name N/A N/A No Each Name of DAU.
2
DAU
SubLocation Number N/A N/A No Each The slot the module fits into. First
3
module user-module goes into slot 3.
PartReference Selection N/A N/A No Each ACRA CONTROL part number.
4
module
<DataLinks>
<DataLinkSet>
<X-RS-232-DataLink-1.0 Name="DL_KAD/UAR/002/C_4_Channel_0">
<Type>RS-422</Type>
<BitRate_Hz>9600</BitRate_Hz>
<DataBitPerWord>8</DataBitPerWord>
<Parity>None</Parity>
</X-RS-232-DataLink-1.0>
<X-RS232-DataLink-1.0 Name="MyRS232DataLink">
5 <Type>RS-232</Type>
6 <BitRate_Hz>10e6</BitRate_Hz>
7 <DataBitPerWord>8</DataBitPerWord>
8 <Parity>None</Parity>
<StartBits>8</StartBits>
<StopBits>8</StopBits>
<Handshaking>Full</Handshaking>
<FirstTransmittedBit>MSB</FirstTransmittedBit>
<MostSignificantBit>First</MostSignificantBit>
</X-RS232-DataLink-1.0>
</DataLinkSet>
</DataLinks>
22 Dec. 2008 | DST/N/133 483

Type Selection RS-232, RS-422 Yes Each Type of data stream.
5
RS-422, DataLink
RS-485
BitRate_Hz Selection 600, 9600 Yes Each The speed of the data stream.
6
1200, DataLink
2400,
4800,
9600,
19200,
38400,
57600,
76800,
115200
DataBitPerWord Selection 7/8 per 8 No Each Bits per word.
7
character channel
Parity Selection Odd, None Yes Each Parity of word.
8
Even, channel
None
Setting up Packages
:
<Packages>
<Packages>
<PackageSet>
.
<X-RS-232-Basic-1.1 Name="MyRS232DataStream">
<Properties>
<MessageIdentification>
<StartPattern>
9 <String>SEQ</String>
</StartPattern>
</MessageIdentification>
</Properties>
<Content>
<Location>
<Offset_Words>1</Offset_Words>
</Location>
</Parameter>
</Content>
</X-RS-232-Basic-1.1>
.
</PackageSet>
</Packages>

StartPattern Text Max. 8 SEQ Yes Each The start sequence indicates the start
9
characters channel of the message.
The field definition table explains the XidML task file for one channel of the UAR/002/C.
484 22 Dec. 2008 | DST/N/133

Output registers
The diagram below illustrates the 64628 registers that can be read from the UAR/002/C.
CHASSIS # MODULE #
ID COUNTER
BYTE COUNTER
One of 126 messages INFO
TIME_HI
TIME_LO
TIME_MICRO
DATA_511
DATA_0
One of 4 busses REPORT
Figure 2: Choosing a parameter to be read from the UAR/002/C
DATA N (ODD) R[15:8] The 7/8 bits of byte N in serial stream. R(15) is the LBT R(15)
R[7:0] The 7/8 bits of byte N-1 in serial stream. R(15) is the LBT R(7)
DATA N (EVEN) R[15:8] The 7/8 bits of byte N in serial stream. R(15) is the LBT R(15)
R[7:0] The 7/8 bits of byte N+1 in serial stream (if applicable). R(15) is the LBT R(7)
R(15) ID is empty (no message received)
R(14) 1 indicates this message was read before
R(13) 1 indicates this message overwrote another
TIME_HI Hours and minutes time of the last character in message
R[12:7] BCD 00-23 hours R(12)
R[6:0] BCD 00-5999 minutes R(6)
TIME_LO Seconds and centiseconds time of the start of the last character in message
R[15:0] BCD 00.00-59.99 seconds R(15)
TIME_MICRO Microsecond time of the start of the last character in message
R[14:13] The bus the error occurred on R(14)
R[3:0] Indicates the error that occurred last (for details, see “Error codes for the UAR/002” on R(3)
page 486)
ID_COUNTER R[15:0] Number of messages received for current ID R(15)
BYTE_COUNTER R[15:14] Bus R(15)
R[8:0] Number of received bytes (including start bytes), for example 0+8 = nine bytes R(8)
22 Dec. 2008 | DST/N/133 485

LBT = Last Bit Transmitted (received) MSB = Most Significant Bit

It is important to ground (GND) each source of the RS-422 or
RS-485 data stream.
Error codes for the UAR/002
00116 Parity error
01016 Bad stop bit
10016 Too many data words
486 22 Dec. 2008 | DST/N/133

Connector pinout of the KAD/UAR/002

1 DATA(0)+ RS-422 inputs Data in; internally terminated with 120Ω
2 DATA(0)- RS-422 inputs Data in; internally terminated with 120Ω
3 NC Not connected
4 NC Not connected
6 DATA(1)- RS-422 inputs Data in; nternally terminated with 120Ω
7 NC Not connected
8 NC Not connected
11 NC Not connected
12 NC Not connected
15 NC Not connected
16 NC Not connected
17 NC Not connected
18 NC Not connected
19 NC Not connected
20 NC Not connected
21 NC Not connected
22 NC Not connected
23 NC Not connected
24 NC Not connected
25 NC Not connected
26 NC Not connected
27 NC Not connected
28 NC Not connected
29 NC Not connected
30 NC Not connected
31 NC Not connected
32 NC Not connected
33 DATA(0) RS-232 inputs Data in; S/E alternative to pins 1 and 2
34 NC Not connected
36 NC Not connected
38 NC Not connected
40 NC Not connected
41 NC Not connected
42 NC Not connected
43 NC Not connected
44 NC Not connected
45 NC Not connected
46 NC Not connected
47 NC Not connected
48 NC Not connected
www.acracontrol.com
488 22 Dec. 2008 | DST/N/133

KAD/UAR/102, KAM/UAR/102, MKM/UAR/102
UAR/102
4 channel RS-232, RS-422 or RS-485 universal asynchronous parser and snarfer
DESCRIPTION
The UAR/102 is used to parse (coherently extract specific
bytes) and snarf (send all data to a FIFO) up to 4
RS-232/422/485 channels. The module is able to parse and
snarf each channel at the same time.
The signal type (RS-232/422/485), bits per word and parity
are programmable on a channel-by-channel basis. The
bit-rates must be binary multiples of each other.
In the parser, a total of up to 126 complete messages are
triple buffered so that the ‘stale’ indication is a message wide.
Each message can be up to 512 characters (bytes) long
FEATURES (including start and stop characters). Each message is
• 4 independent input channels tagged to 0.1ms resolution; a message is considered found
• Bit-rates from 300bps to 1,000,000bps when up to eight specific bytes are received. The end of
• 7/8 bits per word with odd/even or no parity message byte is determined by a user-defined stop character
• Programmable start sequence (1 to 8 characters) or specific number of words. A message is not updated if any
• Programmable stop sequence (1 character or by fixed sequence is incorrect. The snarfer stores all data from each
length) bus in a separate FIFO 2K words deep.
• Locks on idle time
• Parses up to 126 strings (messages) per module
• Up to 512 characters (bytes) per message
• Time tagging (±0.1ms)
• Message wide stale (skipped) indication
• FIFO is 2K words deep per channel
• 2-bits for FIFO full/empty
APPLICATIONS
• Receiving data from GPS module or onboard computer
DATA(0)+ 1
120Ohm +
TERM(0)
DATA(0)-
34
2
AMP
-
FIFO
X 2K
Snarfer
Word
finder
DATA(0) 33
Lock
Verify Parser
Lost
3 X 126 X 512
GND 51
UAR/102
First of four channels of the UAR/102
2 Feb. 2009 | DST/R/004 489

Selection Paths
KAD/UAR/102 CON/KAD/002/CP KAM-500 4 channel RS-232/422/485 parser with 52-way double density
top connector
KAM/UAR/102 ACC/CON/008/04 KAM-500 4 channel RS-232/422/485 parser with 51-way micro-miniature

top connector
MKM/UAR/102 ACC/CON/008/04 MicroKAM 4 channel RS-232/422/485 parser with 51-way micro-miniature

top connector
Revision History
UAR/102 First release Recommended for new programs
In this data sheet UAR/102 refers to the KAD, KAM and MKM version of the module.
Related Products
Module Details
UAR/002 4 busses, maximum data rate of 115.2k, 126 parser messages x 512 words. Not pin compatible
with the UAR/102
UAR/001 8 busses, maximum data rate of 38.4k, 2k snarfer depth per channel
Document Details
www.acracontrol.com
490 2 Feb. 2009 | DST/R/004

Specifications
Slots 1 – Can be placed in any user-slot in any combination.
Mass
69 70 71 g
2.43 2.49 2.50 oz
bare connector — — 11 mm
bare connector — — 0.43 in
Throughput
aggregate — 2 — Msps
Power consumption
+5V 150 155 164.9 mA Unloaded.
+7V — 0 — mA Unloaded.
-7V — 0 — mA Unloaded.
+12V — 0 — mA Unloaded.
-12V — 0 — mA Unloaded.
total power 750 775 824.5 W Unloaded.
+5V — — — mA Loaded.
-7V — — — mA Loaded.
-12V — — — mA Loaded.
total power — — — W Loaded.
Environmental ratings1
operating temperature -40 — +85 °C Chassis base/side plate temperature.
storage temperature -55 — +105 °C
1. Refer to Environmental Qualifications Handbook for details of environmental specifications.
RS-422 inputs
Inputs –
Signalling rate
Data 0.0003 — 1 Mbps
Input voltage
operating range -7.5 — +12.5 V Do not exceed operating range.
logic ‘0’ — — 0.2 V (50mv hysteresis) VIN+ - VIN-
logic ‘1’ 0.2 — — V (50mv hysteresis) VIN+ - VIN-
common mode voltage -7 — +12 V
overvoltage protection -7.5 — +12.5 V Voltage in excess of these values can damage input.
ESD protection — 8 — kV Human Body Model.
Input resistance
between inputs — — — MΩ Module powered on.
between inputs 12 19 — kΩ Module powered off.
between inputs — 120 — Ω Module powered on and inputs terminated.
between inputs — 120 — Ω Module powered off and inputs terminated.
each input to GND — — — MΩ Module powered on.
each input to GND — — — kΩ Module powered off.
2 Feb. 2009 | DST/R/004 491

Setting up the UAR/102
For TimeMicro

Name TimeMicro TIME_MICRO Microsecond time of the start of the acquisition cycle.
Base unit Second Second
maximum 999916 000216
minimum 0 0
Data format BinaryCodedDecimal BinaryCodedDecimal
Size in bits 16 16
For TimeHi

Name TimeHi TIME_HI Hours and minutes time of the start of the acquisition cycle.
Base unit Unitless Unitless R[12:11] Tens of hours
R[10:7] Hours
R[6:4] Tens of minutes
R[3:0] Minutes
maximum 11D916 005916
minimum 0 0
Data format BitVector BitVector
Size in bits 16 16
For TimeLo

Name TimeLo TIME_LO Seconds and centiseconds time of the start of the acquisition
cycle.
Base unit Unitless Unitless R[14:12] Tens of seconds
maximum 599916 000216
minimum 0 0
Data format BinaryCodedDecimal BinaryCodedDecimal
Size in bits 16 16
For MsgInfo

Name MsgInfo MSG_INFO Stale/skipped indication for this PARSED message
Base unit Unitless Unitless R(15) ID is empty (no message received)
R(14) 1 indicates this message was read before
maximum E00016 000216
minimum 0 0
Size in bits 16 16
For Report

Name Report REPORT Indicates status of monitor.
Base unit Unitless Unitless R(15) 1 indicates an error occurred since last read
R[14:13] The bus the error occurred on
R[3:0] Indicates the error that occurred last (See “Error codes” on
page 496.)
492 2 Feb. 2009 | DST/R/004

For Report

maximum 800716 000216
minimum 0 0
Size in bits 16 16
For Data N (odd) to Data N (even)

Name Parser Data_n_odd Data received and FIFO empty and full indication.
Base unit Unitless Unitless Data N (odd) R[15:8] The 7/8 bits of byte M in serial stream. R(15)
is the LBT.
Data N (odd) R[7:0] The 7/8 bits of byte M-1 in serial stream. R(15)
is the LBT.
Data N (even) R[15:8] The 7/8 bits of byte M in serial stream.
R(15) is the LBT.
Data N (even) R[7:0] The 7/8 bits of byte M+1 in serial stream.
R(15) is the LBT.
minimum 0 0
Size in bits 16 16
For ID counter

Name Parser Id_counter Number of messages received for current ID.
Base unit Unitless Unitless R[15:0]
minimum 0 0
Size in bits 16 16
For MSGByteCount

Name Parser Id_counter
Base unit Unitless Unitless R[15:14] Bus
R[8:0] Number of received bytes (including start bytes), for
example 0+8 = nine bytes
maximum C1FF16 000216
minimum 0 0
Size in bits 16 16
2 Feb. 2009 | DST/R/004 493

For Snarfer

Name Snarfer SNARFER Data received and FIFO empty and full indication.
Base unit Unitless Unitless R[15:8] The 8/7 bits received. R(15) is the First Bit Transmitted
R(7) 1 indicates the FIFO is empty
R[15:8] = 5516
R(6) 1 indicates the FIFO was full
R[5:0] Reserved for future useR(5)
maximum FF0016 000216
minimum 0 0
Size in bits 16 16
This module uses the X-Module-RS-232-Monitor XidML schema. (See http://www.xidml.org).
Setting up RS-232 monitor

Manufacturer
part reference KAD/UAR/102 KAD/UAR/102 ACRA CONTROL part number.
Setting up packages
This module uses the X-RS-232-Basic-1.1 and X-Snarfer 1.0 schema. (See http://www.xidml.org).
Setting up RS-232 packages

Package No character limit Reference to a named package definition.
reference
bytes per 9 to 512 The number of bytes in the RS-232 package is used to determine
package when a message ends.
start pattern max 8 characters SEQ The start sequence indicates the start of the message.
idle time steps 2 to 64 msec. Idle time required to lock on message.
This module uses the X-RS-232-DataLink-1.0 schema. (See http://www.xidml.org).
Setting up RS-232 datalinks

Type RS-232, RS-422, RS-422 Type of data stream.
RS-485
Bit rate Hz 1000000, 500000, 9600 The speed of the data stream. See “Getting the most from the
360000, 352500, UAR/102” on page 496.
312500, 208300,
115200, 76800,
62500, 57600,
38400, 19200,
14400, 9600, 4800,
2400, 1200, 600, 300
Data bits per 7/8 per character 8 Bits per word.
word
Parity Odd, Even, None None Parity of word.
494 2 Feb. 2009 | DST/R/004

Setting up RS-232 datalinks

Sync idle time 2 to 63 ms Time between consecutive characters required before starting new
range message.
2 Feb. 2009 | DST/R/004 495

It is important to ground (GND) each source of RS-232,
RS-422 or RS-485. Figure 2 shows how to optionally
terminate the RS-422 receivers by using the third pin (called
TERM). STAR grounding provides optimal noise rejection.
DATA(0)+
TERM(0)
DATA(0)-
UNTERMINATED
DATA(0)+
TERM(0)
DATA(0)-
TERMINATED
Figure 2: Optional RS-422 third pin termination
Maximum message length

The maximum message length is 512 bytes. This length
includes the bytes used for the start pattern and the end byte
(if an end byte is used).
Rules for baud rate availability

A channel can use a baud rate between 300 baud and
1Mbaud,
1000000, 500000, 360000, 352500, 312500, 208300,
115200, 76800, 62500, 57600, 38400, 19200, 14400, 9600,
4800, 2400, 1200, 600, 300
A channel can also use a non-standard baud rate. You can
define non-standard baud rates (tolerance of ±2%) provided
the relationship between the highest non-standard baud rate,
f1, and the other non-standard baud rate, fNS, obeys the
following:
fNS = f1
where N is an integer greater than or equal to 2 and less than

4095.
Error codes
116 Parity error
216 Bad stop bit
416 Last character not found in 512 characters
816 Bad bit error
016, 316, Reserved for future use

516, 616,
716
496 2 Feb. 2009 | DST/R/004

Connector pinout of the KAD/UAR/102

1 DATA(0)+ RS-422 inputs Data in; D/E alternative to Pin 33
2 DATA(0)- RS-422 inputs Data in; connect to pin 34 for 120Ω termination
33 DATA(0) RS-232 inputs Data in; S/E alternative to pin 1
34 TERM(0) RS-422 inputs Connect to pin 2 for 120Ω termination
51 GND
52 CHASSIS DD connector only
www.acracontrol.com
498 2 Feb. 2009 | DST/R/004

KAD/UAT/101, KAM/UAT/101
A C R A KAM-500 UAT/101
C O N T R O L 4-channel RS-232 and 4-channel RS-422 universal asynchronous transmitter
APPLICATIONS
Periodically transmit messages to modules
DESCRIPTION
The UAT/101 is a universal asynchronous transmitter
supporting up to four RS-232 channels and four RS-422
channels. Each of the eight channels is configured
independently for the bit rate, the number of bits per word, the
parity generation, and the number of stop bits.
Each channel supports messages with a maximum length of
FEATURES 8184 characters. Messages are programmed in the
MsgBuffer of the EEPROM before transmission is enabled.
• Four independent single-ended (S/E) RS-232 output
Transmission of messages is enabled when the module
channels
enters acquisition mode. Messages are transmitted
• Four independent differential-ended (D/E) RS-422 output periodically. A message can be sent synchronous to the
channels
acquisition cycle, that is, at the start of the cycle a message is
• Bit-rates from 600bps to 1,000,000bps
transmitted. Messages can also be sent asynchronous to the
• Seven/eight bits per character with odd/even or no parity acquisition cycle, in that the cycle rate of the message can be
• Programmable one or two stop bits
programmed with a minimum period of 1ms up to a maximum
• Maximum message length of 8184 characters
• Messages periodically transmitted either synchronously or period of 65.536 seconds (1ms x 216).
asynchronously to the acquisition cycle
DATA(4)+ 15 Buffer
RS-422 Channel 0 Tx Msg

Channel Construction
DATA(4)- 16
Msg
CycleRate
Buffer
Tx Msg
RS-232 Channel 0 DATA(0) 41 Channel Construction
Msg
CycleRate
GND 51
MsgBuffers
EEPROM
UAT/101
First RS-422 and first RS-232 channel of the UAT/101
4 Oct. 2007 | DST/T/071 499

Selection Paths
KAD/UAT/101 CON/KAD/002/CP KAM-500 4-channel RS-232 and 4-channel RS-422 transmitter with
52-way double density top connector.
KAM/UAT/101 ACC/CON/008/04 KAM-500 4-channel RS-232 and 4-channel RS-422 transmitter with
51-way micro-miniature top connector.
Revision History
UAT/101 Issued first release of data sheet. Recommended for new programs
In this data sheet UAT/101 refers to both the KAD and KAM version of the module.
Related Products
Module Details
UAR/102 4-channel RS-232, RS-422 or RS-485 universal asynchronous receiver.
Document Details
www.acracontrol.com
500 4 Oct. 2007 | DST/T/071

Specifications

Mass
– 66 – g
– 2.33 – oz
bare connector – – 11 mm CON/KAD/002/CP data sheet for KAD modules, and see the
ACC/CON/008/04 data sheet for microKAM and KAM modules.
bare connector – – 0.43 in
Power consumption
+5V – – 130 mA Unloaded.
±7V – – 0 mA Unloaded.
±12V – – 0 mA Unloaded.
total power – – 0.65 W Unloaded (chassis with 30W load).
+5V – – 175 mA Loaded.
±7V – – 0 mA Loaded.
±12V – – 0 mA Loaded.
total power – – 0.875 W Loaded (chassis with 30W load).
RS-422 outputs

Signaling rate
maximum data rate 0.6 – 1000 kbps
Output voltage
absolute operating range -7 – 12 V For correct operation the voltage on the signal pins must remain
within these limits.
logic ‘0’ – – -2 V V0+ - V0- ; RLOAD = 100Ω
logic ‘1’ 2 – – V V0+ - V0- ; RLOAD = 100Ω
short circuit current – – ±250 mA
ESD protection – ±8 – kV Human Body Model.
Output resistance – 5 – Ω
RS-232 outputs

Signaling rate
maximum data rate 0.6 – 1000 kbps
Output voltage
absolute operating range -25 – 25 V For correct operation the voltage on the signal pins must remain
within these limits.
logic ‘0’ 5 – – V RLOAD = 3kΩ
logic ‘1’ – – -5 V RLOAD = 3kΩ
short circuit current – – ±60 mA
Output resistance – 500 – Ω
4 Oct. 2007 | DST/T/071 501

For MsgCounter
Name MsgCounter(0) to MsgCounter(0) Number of times a message is sent on each channel.
MsgCounter(7)
Base unit Unitless Unitless R[15:0] = MsgCounter.
Note: The register is not reset when read.
minimum 0 0
Size in bits 16 16
This module uses the X-Module-RS-232-Monitor XidML schema. (See http://www.xidml.org).

Manufacturer
part reference KAD/UAT/101 KAD/UAT/101 ACRA CONTROL part number.
Setting up packages
This module uses the X-RS-232-Basic-1.2 Package schema. (See http://www.xidml.org).

DataLinkReference Package Reference MySerialDataLink Reference to a DataLink defined in “Setting up datalinks”
on page 503.
Properties N/A N/A N/A
Content
Parameter
FillValue 00-FF16 4116 Fill value
Location
Offset_Words 0-8183 0 The word offset for data words being transmitted in the
package.
502 4 Oct. 2007 | DST/T/071

This module uses the X-DataLink-1.3 Datalink schema. (See http://www.xidml.org).
Datalink definition for Channel(0) to Channel(3)
Type RS-232 RS-232 Type of serial stream.
ProtocolProperties
BitRate 1000000, 9600 The speed of the data stream.
512000, 500000,
360000, 352500,
312500, 208300,
115200, 76800,
62500, 57600,
38400, 28800,
19200, 14400,
9600, 4800, 2400,
1200, 600
DataBitsPerWord 7, 8 8 Data bits per word.
StopBits 1, 2 1 Stop bits.
PackageSequences
ReferencedToAbsoluteTime Yes, No Yes Yes – Synchronous mode
No – Asynchronous Mode
SequencePeriod 1-65536 2000 The time in milliseconds for the message buffers on the
module to transmit all data.
Package
PackageReference Package MyRS232Package References a package defined in “Setting up packages” on
Reference page 502.
Datalink definition for Channel(4) to Channel(7)

Type RS-422 RS-422 Type of serial stream.
ProtocolProperties
BitRate 1000000, 9600 The speed of the data stream.
512000, 500000,
360000, 352500,
312500, 208300,
115200, 76800,
62500, 57600,
38400, 28800,
19200, 14400,
9600, 4800, 2400,
1200, 600
DataBitsPerWord 7, 8 8 Data bits per word.
StopBits 1, 2 1 Stop bits.
PackageSequences
ReferencedToAbsoluteTime Yes, No Yes Yes – Synchronous mode
No – Asynchronous Mode
SequencePeriod 1-65536 2000 The time in milliseconds for the message buffers on the
module to transmit all data.
Package
PackageReference Package MyRS422Package References a package defined in “Setting up packages” on
Reference page 502.
4 Oct. 2007 | DST/T/071 503

Getting the most from the UAT/101 Synchronous mode
Each character in the 8184 word MsgBuffer is framed Figure 2 illustrates the transmission of a message on a
according to the channel parameters. The channel channel that has been configured in synchronous mode. The
parameters define the character size (seven/eight bits), the transmission of all messages is synchronous to the
parity generation, and the number of stop bits. acquisition cycle. Note the offset from the start of the
acquisition cycle to when the message is sent.
Each channel provides a count of the number of times a
message has been transmitted, using the MsgCounter
S yn c c yc le ra te
parameter.
M sg 0 M sg 0
On power-up, the UAT/101 will not initiate transmission of TX channel
P rog P L L a n d
messages until the module is in acquisition mode and the w a it lo c k A c q u is tio n c yc le
PLLs are locked. The PLLs take 10ms to lock. The first SYN C T im e
acquisition cycle after the PLLs are locked will initiate 0
F O R M A T (0 ) F O R M A T (0 ) F O R M A T (0 )
message transmission. The UAT/101 will select one of the 15
formats (as specified by the controller module) that are stored
in the EEPROM.
Figure 2: Transmission of a message on a single channel in
If the UAT/101 is transmitting a message and a new format is synchronous mode
selected at the start of the acquisition cycle, the current
message will be transmitted to completion before
transmission of a message for the new format commences.
The PLLs must not be re-programmed with a different value
when changing format.
If the module is switched from acquisition mode to
programming mode, transmission of messages is terminated
immediately.
The UAT/101 transmits pre-defined fixed content

messages that are stored in EEPROM during
programming of the module. Parameters cannot be
transmitted from the KAM-500 backplane through
the UAT/101.
Maximum message length

The maximum message length is 8184 words. The
acquisition cycle (synchronous mode) or the cycle rate
(asynchronous mode) must be long enough to support
transmitting the message with the specified bit rate and line
parameters.
Bit rate availability

A channel can use any of the following standard bit rates:
1000000, 512000, 500000, 360000, 352500, 312500,
208300, 115200, 76800, 62500, 57600, 38400, 28800,
19200, 14400, 9600, 4800, 2400, 1200, 600.
Asynchronous mode
Figure 1 illustrates the transmission of a message on a
channel that has been configured in asynchronous mode.
The first transmission of the message is aligned to the
acquisition cycle (with an offset). Thereafter it is aligned to the
cycle rate of the channel.
Async cycle rate
Msg 0 Msg 0
TX channel
Prog PLL and
Wait Lock Acquisition cycle
SYNC Time
0
FORMAT(0) FORMAT(0) FORMAT(0) FORMAT(0)
Figure 1: Transmission of a message on a single channel in

asynchronous mode
504 4 Oct. 2007 | DST/T/071

Connector pinout of the KAD/UAT/101
Pin Pin See specifications table Comment

1 NC Not connected
2 NC Not connected
3 NC Not connected
4 NC Not connected
5 NC Not connected
6 NC Not connected
7 NC Not connected
8 NC Not connected
14 NC Not connected
15 Data(4)+ RS-422 outputs D/E
16 Data(4)- RS-422 outputs D/E
19 NC Not connected
20 NC Not connected
21 NC Not connected
22 NC Not connected
23 NC Not connected
24 NC Not connected
31 NC Not connected
32 NC Not connected
33 NC Not connected
34 NC Not connected
35 NC Not connected
36 NC Not connected
37 NC Not connected
38 NC Not connected
39 NC Not connected
40 NC Not connected
41 Data(0) RS-232 outputs S/E
49 NC Not connected
www.acracontrol.com
506 4 Oct. 2007 | DST/T/071

ACRA Other user-modules
C O N T R O L
507
KAD/BIT/101, KAM/BIT/101
A C R A KAM-500 BIT/101
Built-in self test module
C O N T R O L
DESCRIPTION
The BIT/101 is a continuous built-in test module (CBIT) which
checks the KAM-500 backplane to verify correct system
operation.
The BIT/101 measures the precise value of the ±12V, ±7V
and +5V power lines to ensure they are within specifications.
Temperature sensors are located at the top block and the
center of the module to allow the measurement of both the
chassis top block temperature and the chassis internal
temperature.
The BIT/101 checks that the current acquisition cycle is a
FEATURES valid format, measures the duration of each acquisition cycle
• Provides up to 120 window functions (e.g. limit checking) and performs a checksum of all addresses transferred on the
• Up to 32 parameters can be sent to each window function backplane to ensure the correct operation of the current
• Includes voltage and temperature monitors format.
• Monitors format running and address checksum
The BIT/101 module can be used to check both analog signal
• Monitors status from MEM modules and bus monitors conditioning modules and bus monitor modules in a chassis.
• Counts number of power-ons and total time powered on
Channels on analog signal conditioning modules are checked
• 4 x 3 types of STATUS output (TTL, LED and ‘Dolls eye’)
that the signal stays within a minimum and maximum value.
• Selected errors stored in FIFO with optional time tag The BIT/101 can check the STATUS register from each bus
• Selected errors transmitted via RS-422
monitor module in the chassis to indicate when an error
occurs.
APPLICATIONS
• System monitoring
OPTO
- Opto isolated ±12V
28 ISOLATED POWER
RS422_OUT RS422 EEPROM Pow er ±7V
+ 29 RS422 EEPROM MONITOR
driver monitor
DRIVER SECURITY +5V
circuitry
TTL
T TL
TTL(0) 1 Buffer
BUFFER
120
Control logic
CONTROL LOGIC
LED(0) 8 LED
LED
240 Buffer
125mA
+12V 26 Dolls eye
+12V
indicator
COM 31 T emperature
T EMPERAT URE
drivers
DOLLS EYE Signal
SIGNAL
DE_SET(0) 35 INDICAT OR TOP BLOCK Conditioning
CONDITIONING
DRIVERS TEMPERATURE
DE_RESET(0) 37 SENSOR
Error
ERROR
FIFO
51 CHASSIS
INTERNAL
TEMPERATURE
SENSOR BIT/101
First of each of the four STATUS outputs for BIT/101
30 Sep. 2008 | DST/R/015 509

Selection Paths
Airborne Data Acquisition → KAM-500 → Modules → Utility
KAD/BIT/101 CON/KAD/002/CP BIT/101 module with 52-way double density module top connector
KAM/BIT/101 ACC/CON/008/04 BIT/101 module with 51-way micro-miniature module top connector
Revision History
BIT/101 First release Recommended for new programs
In this data sheet BIT/101 refers to both the KAD and KAM version of the module.
Related Products
Module Details
Document Details
www.acracontrol.com
30 Sep. 2008 | DST/R/015

Specifications

Mass
– 68 – g
ACC/CON/008/04 data sheet for microKAM and KAM modules.
Power consumption
+5V 85 – 140 mA Excludes current used by TTL, LED and RS-422 outputs.
±7V 0 – 0 mA
+12V 5 – 20 mA Excludes current sourced from +12V excitation for ‘Dolls eye’
indicators.
-12V 5 – 10 mA
BTTL outputs (TTL)

Signaling rate
TTL(x) – – 5 Hz
Output voltage
logic ‘1’ 4.4 – – V Sourcing 0.1mA.
short circuit current – – 50 mA Only one output may be shorted at a time.
BTTL outputs (LED)

Signaling rate
LED(x) – – 5 Hz
Output voltage
short circuit current – – 50 mA Only one output may be shorted at a time.
30 Sep. 2008 | DST/R/015 511

RS-422 outputs

Signaling rate
RS-422 OUT 9,600 – 115,200 bps
Output voltage
absolute operating range -5 – 5 V Absolute voltage of the operating signal must stay within this
range.
logic ‘0’ – – -3 V V0+ - V0- ; RLOAD = 100Ω
logic ‘1’ 3 – – V V0+ - V0- ; RLOAD = 100Ω
common mode voltage 2.2 – 3.3 V
Open collector outputs

Outputs – – 4 – Four pairs of DE_SET(x) and DE_RESET(x).
Signaling rate
DE_SET(x) – – 2 Hz
DE_RESET(x) – – 2 Hz
Output voltage
logic ‘0’ – 0.9 – V Sinking 100mA.
logic ‘1’ N/A – – V High impedance (open collector).
Output resistance – 2 – Ω Equivalent dynamic resistance when sinking 100mA.
Single ended DC voltage excitation outputs

Output voltage
operating range – 12 – V Connected via 125mA fast-acting fuse from internal +12V
chassis line.
short circuit current – – 1,000 mA Drawing this current causes the fuse to blow within 1ms.
short circuit duration – – 0 s Short of this output causes protection fuse to blow. As the fuse is
soldered on the PCB, the module must be returned to ACRA
CONTROL for fuse replacement.
512 30 Sep. 2008 | DST/R/015

Setting up the BIT/101
Error codes Analog alarm Window Fixed

Digital alarm functions Power line voltage levels
The BIT/101 measures the precise value of the +12V, -12V, +7V, -7V, +5V
power lines at greater than 1% accuracy.
Chassis temperature
The BIT/101 measures chassis and chassis internal temperatures at greater
than ±6°C accuracy.
KAM-500 operation
The BIT/101 ensures the operation of the acquisition cycle by checking the
selected formats address checksum and the number of clock cycles.
Parameters
Any parameters in KAM-500 can be monitored. Examples are:
Memory module status
The BIT/101 can report the status of a MEM/00x module as follows: FULL
/EMPTY/ PARTIALLY FULL.
Bus monitor module operation
The BIT/101 checks the STATUS register of each bus monitor module to
verify correct operation of each bus monitor module.
Analog channel behavior
The BIT/101 can check any analog channel that the signal is within a
minimum and maximum value.
RS-422 9600, 115200 RS-422 Baudrate of RS-422 data stream.

baudrate Total message length is 20 ASCII characters.
Message format is:
“$E<ERR_COUNT>, <PARAMETER-ID>, <WINDOW_FCT-ID>,
<STS_OUT>, <SKIPPED> <CR><LF>”
where:
<ERR_COUNT>: BCD Count which increments every error. 5 characters.
<PARAMETER-ID>: BCD ID number of parameter. 2 characters.
<WINDOW_FCT-ID>: BCD ID number of window function. 3 characters.
<STS_OUT>: Error status output. 1 character
<SKIPPED>: is an ASCII “O” when an overflow occurred, otherwise a “N”. 1
character
<CR>: is an ASCII carriage return
<LF>: is an ASCII line feed
TTL LOW, HIGH TTL Active level of TTL outputs.

outputs
LED LOW, HIGH LED Active level of LED outputs.

outputs
‘Dolls eye’ SET, RESET ‘Dolls eye’ Active position of Dolls eye.
output
FIFO NONE, MICRO ERROR Time Tag stored in FIFO with ERROR_CODE.
TIME_TAG ONLY, ALL FIFO
By default, the module will monitor the KAM-500 power lines and format operation. The module may be configured via KSM-500
to monitor the memory logging modules, analog signal conditioning modules and bus monitoring modules.
30 Sep. 2008 | DST/R/015 513

<Parameters>
<ParameterTypeSet>
:
1
<ParameterType Name="MyAnalogParameterType">
<BaseUnit>Volt</BaseUnit>
</ParameterType>
<ParameterType Name="MyBooleanType">
<BaseUnit>Boolean</BaseUnit>
<DataFormat>BitVector</DataFormat>
</ParameterType>
<ParameterType Name="MyRegisterType">
<BaseUnit>Unitless</BaseUnit>
<DataFormat>BitVector</DataFormat>
</ParameterType>
</ParameterTypeSet>
<ParameterSet>
<Parameter Name="MyAnalogParameter1">
<ParameterTypeReference>
MyAnalogParameterType
</ParameterTypeReference>
<Source>
<Signal>
<InstrumentReference>MyADCModule</InstrumentReference>
</Signal>
</Source>
2
<Destination>
<Algorithm>
<InstrumentReference>MyBITModule</InstrumentReference>
<AlgorithmReference>MyWindowFunction1</AlgorithmReference>
</Algorithm>
</Destination>
</Parameter>
<Parameter Name="MyBusMonitorReport">
<ParameterTypeReference>MyRegisterType</ParameterTypeReference>
<Source>
<Signal>
<InstrumentReference>MyBusMonitor</InstrumentReference>
<VendorMap>REPORT</VendorMap>
</Signal>
</Source>
<Destination>
<Algorithm>
<InstrumentReference>MyBITModule</InstrumentReference>
<AlgorithmReference>MyBitwiseTest1</AlgorithmReference>
</Algorithm>
</Destination>
</Parameter>
</ParameterSet>
</Parameters>

to
Parameter- Name N/A N/A No Each pa- The name corresponding to the channel.
1
Name rameter
VendorMap Selection N/A N/A Yes Each pa- Selection of registers (see “Output Registers” on
2
rameter page 517 for details).
514 30 Sep. 2008 | DST/R/015

<Instrumentation>
<InstrumentSet>
:
<DataLinks>
<X-RS-232-DataLink-1.0 Name="MyRS-422DataLink">
<Type>RS-422</Type>
<BitRate_Hz>9600</BitRate_Hz>
<Parity>None</Parity>
</X-RS-232-DataLink-1.0>
</DataLinks>
:
<X-Module-Built-In-Test-1.0 Name="MyBITModule">
3 <Manufacturer>
<Name>BITRUS</Name>
<PartReference>BIT-101</PartReference>
</Manufacturer>
6
4 <Settings>
5
<Module-Built-In-Test-1.1>
<IndicatorMappings>
<Indicator Index="0">
<OR>
<AlgorithmReference>MyWindowFunction1</AlgorithmReference>
</OR>
</Indicator>
<Indicator Index="1">
<OR>
<AlgorithmReference>MyBitwiseTest1</AlgorithmReference>
</OR>
</Indicator>
</InidcatorMappings>
<EventTag>"High,Low,MicroTime"</EventTag>
</Module-Built-In-Test-1.1>
</Settings>
</X-Module-Built-In-Test-1.0>
</InstrumentSet>
</Instrumentation>

to
3
tReference module
4
SubLocation Number N/A N/A No Each The slot the module fits into. First user-module
5
module goes into slot 3.
6
ence module
30 Sep. 2008 | DST/R/015 515

Setting up Window functions
<Algorithms>
7 <AlgorithmSet>
<X-Alarm-1.0 Name="MyWindowFunction1">
<Output>
<ParameterTypeReference>MyBooleanType</ParameterTypeReference>
</Output>
<Window>
<OKMaximum>5</OKMaximum>
8 <OKMinimum>2</OKMinimum>
9 </Window>
</X-Alarm-1.0>
<X-Boolean-Simple-1.0 Name="MyBitwiseTest1">
<Output>
<ParameterTypeReference>MyBooleanType</ParameterTypeReference>
</Output>
<OR>
<Input>
<BitIndex>0</BitIndex>
</Input>
10 <Input>
<BitIndex>1</BitIndex>
</Input>
</OR>
</X-Boolean-Simple-1.0>
</AlgorithmSet>
</Algorithms>

Algorithm- Name N/A N/A Yes Each algorithm Reference to a named algorithm defini-
7
Reference tion.
OkMaximum Selection 0 to N/A Yes Each algorithm Maximum value allowed.
8
65535
OKMinimum Selection 0 to N/A Yes Each algorithm Minimum value allowed.
9
65535
BitIndex Selection 0 to 15 N/A No Each algorithm Bit to examine.
10
516 30 Sep. 2008 | DST/R/015

Output Registers
The diagram below shows the registers that can be read from the BIT/101
FIFO ERROR_CODE
ERROR_TIME_HI
ERROR_TIME_LO
ERROR_TIME_MICRO
POWER +12V
-12V
+7V
-7V
+5V
TEMPERATURE CH_TEMP
INT_TEMP
STATUS
POWER_ON POWER_ON_HI
POWER_ON_LO
TIME_ON_HI
TIME_ON
TIME_ON_LO
TICKS_HI
TICKS
TICKS_LO
ERROR_COUNT
+12V R[15:0] 16-bit value of +12V power line on chassis backplane. To calculate voltage = R(15)
(R[15:0] * 20/65536 -10) * 2.
-12V R[15:0] 16-bit value of -12V power line on chassis backplane. To calculate voltage = R(15)
(R[15:0] * 20/65536 -10) * 2.
+7V R[15:0] 16-bit value of +7V power line on chassis backplane. To calculate voltage = R(15)
R[15:0] * 20/65536 -10.
-7V R[15:0] 16-bit value of -7V power line on chassis backplane. To calculate voltage = R(15)
R[15:0] * 20/65536 -10.
5V R[15:0] 16-bit value of +5V power line on chassis backplane. To calculate voltage = R(15)
R[15:0] * 20/65536 -10.
CH_TEMP R[15:0] Chassis temperature BCD ratio, measured at top block. R(15)
See “Getting the most from the BIT/101” on page 519 to calculate
temperature.
INT_TEMP R[15:0] Internal chassis temperature BCD ratio. See “Getting the most from the R(15)
BIT/101” on page 519 to calculate temperature.
STATUS R[15:0] R[15:12] = Reserved for future use R(15)

R(11) = Error accessing EEPROM
R[10:4] = Reserved for future use R(10)
R[3:0] = Error status(3:0) R(3)
ERROR_CODE Error code from Error FIFO

R(13) FIFO FULL
R(12) FIFO EMPTY
R[11:7] PARAMETER ID R(11)
R[6:0] WINDOW FUNCTION ID R(6)
30 Sep. 2008 | DST/R/015 517

ERROR_TIME_HI Hours and minutes time of when error occurred and was stored in the Error
FIFO
R[12:7] BCD 00-23 hours R(12)
ERROR_TIME_LO R[15:0] Seconds and centiseconds time of when error occurred and was stored in R(15)
the Error FIFO
BCD 00.00-59.99 seconds
ERROR_TIME_MICRO R[15:0] Microsecond time of when error occurred and was stored in the Error FIFO R(15)
BCD 0000-9999 microseconds
ERROR_COUNT R[15:0] The number of errors occurred during module checks R(15)
POWER_ON_LO R[15:0] Power_On[15:0] The LSBs of the number of times the module has been R(15)
powered on. This value is non-volatile.
POWER_ON_HI R[15:0] Power_On[31:15] The MSBs of the number of times the module has been R(15)
TIME_ON_LO R[15:0] Time_On[15:0] The LSBs of the total amount of 5 minute intervals that the R(15)
module has been powered on, and the number of times the module has been
TIME_ON_HI R[15:0] Time_On[31:15] The MSBs of the total amount of 5 minute intervals that the R(15)
module has been powered on, and the number of times the module has been
TICKS_LO R[15:0] TICKS[15:0] The LSBs of the number of clock ticks in previous cycle R(15)
TICKS_HI R[15:0] TICKS[31:15] The MSBs of the number of clock ticks in previous cycle R(15)
518 30 Sep. 2008 | DST/R/015

Getting the most from the BIT/101 Window Function 1
Parameter
The BIT/101 is a continuous built-in test module that monitors BIT/101 Value
Output(3:0)
Internal
the KAM-500 system using window functions to ensure that it Power 0 0001 Window Function 1
is operating correctly. A window function is a table with an Parameter 1 0001 Output
2 0001
entry for every possible value of a parameter with a 2
3 0000
0001
corresponding output entry. Up to 120 window functions can - -

be configured, each window function can check up to 32 65534 0000
65535 0000
parameter inputs with an output of four-bits. The outputs of all Window function 1 is defined as Window Function
of the window functions are OR’d together to produce a four output 0001 when the BIT/101 Power Outputs(3:0)
bit result. The BIT/101 has six methods to indicate the results
Parameter is over 2 else output 0000
OR 0011
of the window functions, shown in Figure 2. Window Function 120

Parameter
Output(3:0)
Value
0 0010 Window Function 120
Parameter from
1 0010 Output
Other Module
Window WINDOW FUNCTION OUTPUTS(3:0) 2 0010
TTL(3:0) 65534 0010
Functions 3 0010
- -
LED(3:0) 65534 0010
DE_SET(3:0) 65535 0000
Dolls Eye
Driver Window function 120 is defined as
DE_RESET(3:0) output 0010 when the input
parameter is not 65535 else output 0000
RS422_Out+ Figure 3: Example of two window functions

RS422
Transmitter
RS422_Out-
The POWER_ON and TIME_ON counters are stored in an
EEPROM, which has an approximate life of ten years. The
Error
FIFO
STATUS register contains a bit which indicates when the
module must be returned to ACRA CONTROL for a
replacement EEPROM.
STATUS
Register
The TIME_ON counter takes up to 250ms to be updated and
can be updated asynchronously from the acquisition cycle.
When the module is power-cycled there may be an extra
Figure 2: Six methods to indicate window functions character transmitted on the RS-422 serial output.
The LED and TTL outputs are updated for 200ms or the
The BIT/101 accepts internal parameters and parameters
length of the acquisition cycle, whichever is longer. If the
from other modules as inputs for window functions. There are
acquisition cycle is longer than 200ms the LED and TTL
window functions that can be configured to monitor the
outputs are updated at the start of the cycle and remain the
BIT/101 internal parameters to check power, temperature and
same for the cycle. Otherwise if the acquisition cycle is
KAM-500 backplane operation. Other window functions can
shorter than 200ms the LED and TTL outputs have an output
be configured to monitor parameters from other modules to
period of 200ms. If the error condition is met again during an
ensure they are operating correctly.
output active period, then the period will be extended.
An example of two window functions is in Figure 3. The first
The BIT/101 powers up to four dual-coil ‘Dolls eye’ indicators.
window function is used to check one of the internal power
The BIT/101 SET and RESET outputs are energized with a
parameters of the BIT/101. The output of the window function
40ms pulse to select the display state of the ‘Dolls eye’
is 0001 because the value of the input parameter is not above
indicator. The outputs that drive the four ‘Dolls eye’ are
2. The second window is used to check a parameter from
sequenced with a 10ms gap, these outputs are updated
another module. The output of the window function is 0010
asynchronously from the acquisition cycle and update every
because the value of the input parameter is not equal to
500ms.
65535.
The BIT/101 outputs a +12V supply which can be used to
power the ‘Dolls eye’ indicators, or an external source can be
used. It is required that the BIT/101 COM input is connected
to the +12V supply. The COM input is connected to the ‘Dolls
eye’ driver within the BIT/101 and protects drivers against
damage when switching ‘Dolls eye’ indicators. It is not
recommended that the ‘Dolls eye’ be used to monitor the
supply rails.
The circuitry for voltage monitoring on all of the supply rails
are measured using the +12V supply. Any changes on the
+12V supply will affect all voltages measured. When the
format of the current acquisition cycle is changed then the
Error Counter and FIFO in the BIT/101 are reset.
The BIT/101 contains two non-volatile counters. The first
counter increments each time the chassis containing the
module has been powered on, the second counter
30 Sep. 2008 | DST/R/015 519

increments when the module is powered on and every five If the temperature is more than 50°C then this formula can be
minutes after. approximated using,
The BIT/101 has four status bits which indicate when an error Temperature °C = (425 x (Ratio10/1000010)) – 273
occurs, these can be configured for each error condition. The
status bits drive four TTL outputs, four LED outputs and four When viewing this parameter care must be taken to
‘Dolls eye’ Indicators on the top block of the module. The treat it as BCD and not as hex or offset binary.
fourth status bit is also used to specify that a code
corresponding to the error will be written to the Error FIFO
and transmitted via the RS-422 output stream.
The ERROR_CODE is stored in the Error FIFO with optional
time-tags, the Error FIFO can store a maximum of 4096
errors or tags, if ERROR_TIME_MICRO tag is also stored
then the FIFO can hold 2048 and with all three time tags
stored then the FIFO can hold 1024 errors. The RS-422
output stream transmits the error code in a 20 character
message. This message also contains the error number and
an overflow indicator. The transmission bit rate can be either
9.6kbps or 115.2kbps.
If using the BIT/101 in a CHS/13U, CHS/13U/B, or
CHS/13U/C, two BIT/101 modules are required to monitor the
+12V supply of all slots. The +12V supply is split between two
supply rails, the first rail supplies the first four module slots
while the second rail supplies the last nine slots.
Figure 4 shows an example of the operation of the window
functions outputs when the acquisition cycle is less than
200ms.
WINDOW
FUNCTION
STATUS
OUTPUT(0)
STATUS
OUTPUT(1) 100ms
TTL(0)
LED(0)
DE 100ms 200ms
RESET(0)
DE 500ms
SET(0)
DE
RESET(1)
DE
SET(1) 40ms 10ms
Acqusition LED/TTL outputs Dolls Eyes updated

Cycle updated asynchronously asynchronously from
<200ms from acquisition cycle acquisition cycle
Figure 4: Example of the operation of window function out-

puts when the acquisition cycle is less than 200ms
Additional functionality on the BIT/101 checks the status of

the MEM/003 and MEM/004 modules to determine whether
the:
• CompactFlash® card in the module is empty
• CompactFlash card in the module has stored data over a
specified threshold
• CompactFlash card in the module is full
Measuring the temperature of the chassis

The BIT/101 has two temperature sensors that measure the
chassis top block and internal temperature. The
temperatures measured can be inputs to window functions
and/or can be read as parameters. The temperature
parameter is a four digit BCD value with a range from 000010
to 999910. To calculate the temperature measured, use the
following formulae:
Temperature °C = -200 x (0.85 – (Ratio10/1000010))3 + (425 x

(Ratio10/1000010)) – 273
520 30 Sep. 2008 | DST/R/015

Connector pinout of the KAD/BIT/101

1 TTL(0) BTTL outputs (TTL) STATUS TTL output
4 TTL GND Ground for TTL outputs
6 NC Not connected
7 NC Not connected
8 LED(0) BTTL outputs (LED) STATUS LED output
9 LED GND Ground for LED outputs
16 NC Not connected
18 NC Not connected
19 NC Not connected
20 NC Not connected
25 NC Not connected
26 +12V Out +12V to ‘Dolls eye’ indicators
27 NC Not connected
28 RS-422_OUT- RS-422 outputs
29 RS-422_OUT+ RS-422 outputs
30 NC Not connected
31 COM ‘Dolls eye’ Driver; supply voltage
32 NC Not connected
34 NC Not connected
35 DE_SET(0) Open collector outputs ‘Dolls eye’ indicator set
36 NC Not connected
37 DE_RESET(0) Open collector outputs ‘Dolls eye’ indicator reset
38 NC Not connected
40 NC Not connected
42 NC Not connected
44 NC Not connected
46 NC Not connected
48 NC Not connected
50 NC Not connected
www.acracontrol.com
522 30 Sep. 2008 | DST/R/015

KAD/DAC/001, KAM/DAC/001
A C R A KAM-500 DAC/001
C O N T R O L 8 channel analog outputs, with 16 channel discrete outputs
DESCRIPTION
The DAC/001 can be used to output up to eight single ended
waveforms, and provide up to sixteen discrete output
indications.
The module is able to take any parameter from the backplane
and, using a user-defined lookup table, map that parameter
into the output voltage range of the analog output channel. A
different map can be used for each of the eight analog
channels.
Each of the discrete outputs can be set to a logic high or low
based on a combination of input words. The input words are
FEATURES passed through a user-defined mapping function, which
• Eight single ended (S/E) analog output channels (±10V) produces a single bit output. A typical example would be a
• 0.25% (FSR) total error from all sources for analog output max-min. window function to determine if a parameter lies in
• Lookup tables to map input parameter to analog output a defined range.
• 16 S/E discrete output channel (Buffered TTL)
The outputs from the mapping functions can be either
• Combinatorial logic can be used to map multiple
logically ANDed or ORed together, and inverted if required, in
parameters to a single discrete output order to control the discrete output.
• Outputs are short-circuit protected (indefinite to ground)
APPLICATIONS
• Output a voltage waveform based on backplane
parameters, e.g. for a strip recorder
• Provide discrete outputs based on backplane parameters,
for example memory status
DIGITAL ← UNITS ←
ANALOG (0) 1 ANALOG COUNTS
12 16
AGND 9
DISCRETE [15:0]
Buffered TTL drivers Combinatorial logic Transfer tables
GND 26
DAC/001
First of 8 analog channels and the 16 discrete channels of the DAC/001
3 Sep. 2008 | DST/N/077 523

Selection Paths
Airborne Data Acquisition → KAM-500 → Modules → Utility
KAD/DAC/001 CON/KAD/002/CP DAC/001 module with 52-way double density module top connector
KAM/DAC/001 ACC/CON/008/04 DAC/001 module with 51-way micro-miniature module top connector
Revision History
DAC/001 First release Recommended for new programs
In this data sheet DAC/001 refers to both the KAD and KAM version of the module.
Related Products
Module Details
Document Details
www.acracontrol.com
524 3 Sep. 2008 | DST/N/077

Specifications

Mass
– 66 – g
Power consumption
+5V 108 – 115 mA
±7V 0 – 0 mA
+12V 10 – 11 mA
-12V 10 – 10 mA
Single ended DC voltage outputs

Output voltage
short circuit duration 0 – – s To GND.
DC error -40 – 40 mV
Output resistance – – 3.9 kΩ
BTTL outputs

Signaling rate
DIGITAL – – 10 kbps
Output voltage
3 Sep. 2008 | DST/N/077 525

Setting up the DAC/001
<Parameters>
<ParameterTypeSet>
<ParameterType Name="MyAnalogParameterType">
<BaseUnit>Volt</BaseUnit>
2
3
4 <RangeMinimum>-10</RangeMinimum>
</ParameterType>
</ParameterTypeSet>
<ParameterSet>
1 <Parameter Name="MyAnalogParameter">
<ParameterTypeReference>MyAnalogParameterType</ParameterTypeReference>
<Source>
<Signal>
<InstrumentReference>MyAnalogModule</InstrumentReference>
</Signal>
</Source>
<Destination>
<Signal>
<InstrumentReference>MyDAC</InstrumentReference>
</Signal>
</Destination>
</Parameter>
</ParameterSet>
</Parameters>

Parameter Name N/A N/A Yes Each The name corresponding to the
1
Name parameter channel
SizeInBits Selection N/A 16 No Each The size in bits of the source pa-
2
parameter rameter.
RangeMaximum Float -10V to +10V 10 Yes Each Maximum voltage output from the
3
parameter module.
RangeMinimum Float -10V to +10V -10 Yes Each Minimum voltage output from the
4
parameter module.
526 3 Sep. 2008 | DST/N/077

<Instrumentation>
<InstrumentSet>
<X-Module-Analog-Out-1.1 Name="MyDAC">
5
<Manufacturer>
<PartReference>KAD/DAC/001</PartReference>
8
</Manufacturer>
<Settings>
<Module-Analog-Out-1.1>
<Channel Index="0">
<Linearisation>MyPiecewiseLinearAlgorithm</Linearisation>
</Channel>
</Module-Analog-Out-1.1>
</Settings>
</X-Module-Analog-Out-1.1>
</InstrumentSet>
</Instrumentation>

InstrumentRef Name N/A N/A Yes Each module Name of module from which parameter is
5
erence sourced.
6
SubLocation Number N/A N/A No Each module The slot the module fits into. First
7
user-module goes into slot 3.
PartReference Selection N/A N/A No Each module ACRA CONTROL part number.
8
Input registers
The DAC/001 has nine input registers.
ANALOG The voltage to the D/A updated at the start of each acquisition cycle
R[15:0] OFFSET BINARY (0000-FFFF) for the range specified in Module Setup R(15)
DISCRETE Level of discretes updated at the speed of the fastest output rate
R[15:0] D[15:0] R(15)
The origin of each parameter must be specified, except the memory and bus monitor status.
3 Sep. 2008 | DST/N/077 527

Getting the most from the DAC/001
Each of the outputs is single ended. AGND and GND are
connected internally on the module. However, it is
recommended to use AGND for the analog output returns
and GND for the discrete output returns.
An example of discrete outputs may be defined as follows
when the appropriate modules are present:
D(15)1 Power-down glitch during last fastest output period
D(14) EEPROM memory is full
D(13) EEPROM memory is empty
D(12) EEPROM memory is logging
D(11) IRIG-B time is connected with no receive errors this

acquisition cycle
D(10) There has been no errors on any bus being monitored

this acquisition cycle
D(9) Parameter A is within the defined window
D(8) Parameter B is within the defined window
D[7:0] TBD
1. D(15) can not be pre-configured.
The DAC/001 GUI does not support discrete output setup.

However, settings can be configured via low level file
management from the command line. To request instructions
for configuring discrete output - TSR_U_029, contact ACRA
CONTROL.
528 3 Sep. 2008 | DST/N/077

Connector pinout of the KAD/DAC/001

1 ANALOG(0) Single ended DC voltage outputs Analog output
10 DISCRETE(0) BTTL outputs Discrete output
25 DISCRETE(15) BTTL outputs Discrete output; MSB, indicates power-down glitch
during fastest rate period
27 NC Not connected
28 NC Not connected
29 NC Not connected
30 NC Not connected
31 NC Not connected
32 NC Not connected
33 NC Not connected
34 NC Not connected
35 NC Not connected
36 NC Not connected
37 NC Not connected
38 NC Not connected
39 NC Not connected
40 NC Not connected
41 NC Not connected
42 NC Not connected
43 NC Not connected
44 NC Not connected
45 NC Not connected
46 NC Not connected
47 NC Not connected
48 NC Not connected
49 NC Not connected
50 NC Not connected
51 NC Not connected
www.acracontrol.com
530 3 Sep. 2008 | DST/N/077

KAD/ETH/101, KAM/ETH/101
A C R A KAM-500 ETH/101
2.5Msample/sec data acquisition and programming over Ethernet
C O N T R O L
DESCRIPTION
The ETH/101 is a full-duplex, fast Ethernet (100Mbps)
module that can be used to program a KAM-500 system or
transmit data from a KAM-500 system.
In acquisition mode, some or all acquired data is transferred
from the backplane to the on-board CVT. On-board it is
packetized into a user-defined structure. Once full, the packet
is transmitted via UDP.
Any number of user-defined packet structures can be
handled simultaneously. Different packet identifiers, packet
sizes and destination IP addresses can be individually
FEATURES programmed for each packet type. Destination IP addresses
• Programming and verification of up to 64 KAM-500 chassis can be unicast, multicast or broadcast.
• Bi-directional, full-duplex, fast Ethernet (100BaseTx) Upon reception of a programming packet, the module
connection
immediately exits acquisition mode and switches to
• Fixed user-assigned internet protocol (IP) address
program/verify mode. In program/verify mode it can read or
• Two separately buffered Ethernet outputs write data blocks to or from any module in any chassis within
• User Datagram Protocol (UDP) support for packets up to
a distributed KAM-500 system.
64kbyte (32ksamples) via IP fragmentation
• Current value table (CVT) of up to 1Msample The ETH/101 supports IPv4 networks with fixed IP address
• IPv4 and IENA protocols supported allocation, including user-assignment of the module's own IP
• Replies to address resolution protocol (ARP) & PING address. The module is factory-programmed with a unique
requests from other nodes on the network Ethernet MAC address.
APPLICATIONS
• Ethernet based data acquisition systems
+
18 PACKETISER
TX_A
- 19 ←
MAC/PHY
+ →
RX_A
1
- DEPACKETISER CVT 1Msample depth
2
COMMAND
EXCHANGE
+
PROG_A
6 STANDARD
-
7 KAM-500
PROGRAMMING
INTERFACE
GND
51
ETH/101
One of two Ethernet links and programming links
2 Mar. 2009 | DST/T/052 531

Selection Paths
Airborne Data Acquisition → KAM-500 → Modules → Ethernet
KAD/ETH/101 CON/KAD/002/CP ETH/101 module with 52-way double density module top connector
KAM/ETH/101 ACC/CON/008/04 ETH/101 module with 51-way micro-miniature module top connector
Revision History
ETH/101 First release Recommended for new programs
In this data sheet ETH/101 refers to both the KAD and KAM version of the module.
Related Products
Module Details
ETH/001 A 100 base Tx Ethernet interface for programming and data acquisition
OBE/ESW/001 8-port rugged Ethernet switch
KSM/STE/001 This module is supported by the KSM-500 suite of software tools
Document Details
TEC/NOT/032 Using Ethernet for data acquisition
TEC/NOT/034 Ethernet data acquisition networking
www.acracontrol.com
532 2 Mar. 2009 | DST/T/052

Specifications

Mass
– 74 – g Design metric is grams.
– 2.6 – oz
bare connector – – 11 mm Design metric is millimeters.
bare connector – – 0.43 in.
Power consumption
+5V 523 – 526 mA
±7V 0 – 0 mA
±12V 0 – 0 mA
Ethernet interface

Inputs/outputs – – 1 – IEEE 802.3 compatible.
RS-485

Signaling rate
PROG_A – – 1 Mbps
PROG_B – – 1 Mbps
Input voltage
logic ‘0’ – – -0.2 V VIN+ - VIN-
logic ‘1’ 0.2 – – V VIN+ - VIN-
Output voltage
logic ‘0’ – – -2 V V0+ - V0- ; RLOAD = 100Ω
logic ‘1’ 2 – – V V0+ - V0- ; RLOAD = 100Ω
Input resistance
2 Mar. 2009 | DST/T/052 533

For DATA

Name DATA DATA Data is written to the CVT in acquisition order. Re-ordering of data
can occur during composition of data packets.
Base unit Unitless Unitless R[15:0] Data is stored MSB justified.
maximum
minimum
Size in bits 16 16
For REPORT

Name REPORT REPORT
Base unit Unitless Unitless R(15) Error since last read.
R[3:0] Error code.
016: Primary network link not established.
116: Secondary network link not established when enabled.
216: Secondary network link transmit frame contained errors.
316: Primary network link receive frame contained errors.
416: CVT overflow.
516: Module is in configuration mode.
616: Housekeeping not successfully loaded from serial EEPROM &
Flash.
716: Module reset.
816: SRAM access contention.
916: Module is in Programming Mode.
A16: Framing-engine TxOffset configuration setting is greater than
actual acquisition cycle.
B16: Primary network link receive frame dropped from FIFO.
Size in bits 16-bits 16
534 2 Mar. 2009 | DST/T/052

This module uses the Module-Ethernet-Settings-1.1 and Module-Ethernet-Monitor-Settings-1.0 schemas. (See
http://www.xidml.org.)

Manufacturer
part reference KAD/ETH/101 KAD/ETH/101 ACRA CONTROL part number.
MAC address Fixed 12 hex 00 0C 4D 98 76 54 Unique Ethernet MAC address for each module. The upper six hex
characters characters 00 0C 4D are allocated by IEEE as the organizationally
unique identifier (OUI) for ACRA CONTROL network equipment.
The lower six hex characters are factory programmed to a unique
number for each ETH/101 module.
Connections
Link_A No character limit MyLink_A Ethernet network link A.
Link_B No character limit MyLink_B Ethernet network link B. (Duplicate of Ethernet network link A.)
PROG_A No character limit MyPROG_A Programming link A.
PROG_B No character limit MyPROG_B Programming link B. (Independent of programming link A.)
Settings
IP address Four decimal values, 192.168.1.1 User-assigned IP address of module.
0 to 255 for each
value
port number Hex value C00016 to C12316 UDP private port number used for programming.
FFFF16
Setting up packages
The ETH/101 uses the X-IENA-Ethernet-UDP-Basic-1.2 XidML schema to define transmitted Ethernet packets.

Packages per 1 The number of data packets per acquisition cycle.
acquisition
cycle
Data link No character limit NwLink_A A named datalink.
reference
Properties
Key No character limit IENAPacket_0 Unique identifier for the packet.
Status HexBinary
NumberOfWords UnsignedInt Total number of words in the IENA packet including header
information and data.
EndWord HexBinary Pattern that identifies the end of the IENA packet.
TimeToLive UnsignedInt 255 Maximum number of network links the packet is allowed to traverse.
Required to prevent packets circling on the network forever.
ContentIdentifier Optional. Each content identifier tag immediately precedes the data
in the package. NOTE: If this element is used it is presumed that all
parameters in the packet are tagged.
NumberOfBitsIn UnsignedInt 16 Number of bits in content identifier tag. Number of bits in each
ContentIdentifier content identifier tag is identical.
DefaultNumberOf UnsignedInt 16 Default number of bits that makes up the data section of a
DataBits parameter.
Source Source of the data packet.
IPaddress Four decimal values, 192.168.1.1 IP address of packet’s source. This is typically the ETH/101 module
0 to 255 for each IP address, or a multicast IP address corresponding to a multicast
value group of which the source network node is a member.
Port Hex value 000016 to 456716 UDP port number of packet’s source.
FFFF16
MACaddress Fixed 12 hex 00 0C 4D 98 76 54 Ethernet MAC of packet’s source. Typically the ETH/101 module
characters MAC address.
2 Mar. 2009 | DST/T/052 535

Destination
IPaddress Four decimal values, 192.168.1.20 IP address of packet’s destination. Can be unicast or multicast.
0 to 255 for each
value
Port Hex value 000016 to 456716 UDP port number of packet’s destination.
FFFF16
MACaddress Fixed 12 hex 00 13 20 77 AE F0 Ethernet MAC of packet’s destination. Can be unicast, multicast or
characters broadcast.
Content
Parameter
ID HexBinary
Delay String Yes / No
Tag HexBinary 0123 Specifies the value that is used to identify the parameter. If this
element is included then the 'ContentIdentifier' element must be
defined in the 'Properties' section. NOTE: It is presumed that data
immediately follows this tag.
NumOfDataBits UnsignedInt 16 Total number of data bits in the word. Need only be specified if
different to 'DefaultNumberOfDataBits'. NOTE: The total number of
bits is the sum of the number of bits occupied by the tag and the
number of bits containing data.
Location Location(s) of the parameter in the package. NOTE: If more than
one location is specified then it is an error to have an Occurrences
value greater than one.
Offset_Words UnsignedInt 10 Location of the parameter in terms of the number of words.
Offset_Bits UnsignedInt 160 Location of the parameter in terms of the number of bits.
Occurances UnsignedInt 1 Number of times that the parameter occurs in the package. If this
value is greater than one then it is presumed that each occurrence
of the parameter is placed at equally spaced intervals within the
package.
This module uses the X-DataLink XidML-1.2 XidML schema. (See http://www.xidml.org.) The module can reference a data link
that describes physical attributes of the connection.

Type No character limit IENA Reference to a named package definition.
Protocol
Properties
BitRate double 10000000 / The bit rate of the datalink; 10Mb/sec or 100Mb/sec for Ethernet.
100000000
PhysicalLayer
LayerType No character limit Ethernet Type of physical layer of the datalink.
NumberOfWires UnsignedInt 4 Number of wires that comprise the physical connection.
Coupling Direct/Transformer Transformer Ethernet is transformer coupled.
536 2 Mar. 2009 | DST/T/052

Getting the most from the ETH/101 The ETH/101 module is then released from IP address
configuration mode by removing GND from top-block pin#39.
The Ethernet cabling standard (EIA/TIA-568-B) recommends
the use of Category 5 cable. Only one module on the network should be set to
IP Address Configuration Mode. This prevents
Differences between Ethernet link A and other ETH/101 modules from simultaneously
processing the configuration packets and thus
Ethernet link B mistakenly acquiring the same user-assigned IP
Although packet transmission on Ethernet link B is a copy of address.
Ethernet link A, and performs in a similar manner to that
illustrated in Figure 2, packet reception is not supported on Packet fragmentation
Ethernet link B. Also, ARP/PING are implemented via
Ethernet link A only. Ethernet packet sizes range between 64 bytes and 1518
bytes. Packets larger than 1518 bytes (known as giants) can
ETH/101 and programming be transmitted directly over Ethernet by high level protocols
such as Internet Protocol (IP). When being transmitted over
As indicated in Figure 2, incoming programming packets from Ethernet, giant IP packets are fragmented (split into smaller
the programming PC are processed by the ETH/101 and pieces). Fragmented packets must then be reassembled by
translated into a programming sequence that is transmitted the receiving device to recreate the original IP packet.
out over ACRA CONTROL’s proprietary programming link
(PROG_A, PROG_B). Similarly, acknowledgements and data Packet fragmentation is undesirable for the following
replies that are received on one of these programming links reasons:
are packetized and forwarded to the PC via the Ethernet • Fragments may arrive out of order and complicate
link A. reassembly of the data.
• Fragments may be lost, rendering all other fragments of
the frame useless.
• The process of fragmenting and reassembling the data is
time-consuming.
Switches and routers which support IEEE 802.1Q

VLAN tagging support Ethernet packets of up to
1522 bytes, including the 4-byte IEEE 802.1Q
VLAN tag.
Figure 2: Programming over Ethernet
User-assignment of ETH/101 IP address

Unlike its ETH/001 predecessor, the ETH/101 does not have
a 32-bit top-block pin-out, which allowed the module's IP
address to be hard-wired. Instead, the KSM-500 software is
used to configure the module with a user-assigned IP
address. The mechanism works as follows:
A top-block pin (pin#39 = IP_ASSIGN) is connected to GND
to put the module into IP Address Configuration Mode. When
in this mode, the module will assume a default hard-wired IP
address. The IP address 224.0.0.3 is used, as it is an
unassigned IP multicast address (defined by IETF
RFC-3171), within the local network control block of
addresses. It can be used to transmit packets to a network
element using a multicast Ethernet MAC address
(01-00-5E-00-00-03), and is limited to the local network, such
that it will not be forwarded by a router.
An IP address configuration packet is transmitted to the
module for the purpose of configuring the module with a
user-assigned IP address. The user-assigned IP address is
stored in serial EEPROM on the module for subsequent
reference.
2 Mar. 2009 | DST/T/052 537

Connector pinout for the KAD/ETH/101
1 RX_A+ Ethernet interface
2 RX_A- Ethernet interface
3 NC Not connected
4 NC Not connected
6 PROG_A+ RS-485 Internally terminated with 120Ω
7 PROG_A- RS-485 Internally terminated with 120Ω
8 PROG_B+ RS-485 Internally terminated with 120Ω
9 PROG_B- RS-485 Internally terminated with 120Ω
11 NC Not connected
12 NC Not connected
13 NC Not connected
14 NC Not connected
15 NC Not connected
16 RX_B+ Ethernet interface Ethernet interface B
17 RX_B- Ethernet interface Ethernet interface B
18 TX_A+ Ethernet interface Ethernet interface A
19 TX_A- Ethernet interface Ethernet interface A
20 NC Not connected
21 NC Not connected
22 NC Not connected
23 NC Not connected
24 NC Not connected
25 NC Not connected
26 NC Not connected
27 NC Not connected
28 NC Not connected
29 NC Not connected
30 NC Not connected
31 NC Not connected
32 NC Not connected
33 TX_B+ Ethernet interface Electrical copy of pin 18
34 TX_B- Ethernet interface Electrical copy of pin 19
35 NC Not connected
36 NC Not connected
37 NC Not connected
38 NC Not connected
39 IP_ASSIGN User-assigned IP address; internally pulled to 1 if open
41 NC Not connected
42 NC Not connected
43 NC Not connected
44 NC Not connected
45 NC Not connected
46 NC Not connected
47 NC Not connected
48 NC Not connected
49 NC Not connected
50 NC Not connected
www.acracontrol.com
538 2 Mar. 2009 | DST/T/052

KAM/MEM/003/E
A C R A KAM-500 MEM/003
KAM-500 high speed CompactFlash® memory module
C O N T R O L
DESCRIPTION
The MEM/003 is a memory card interface which supports
logging to CompactFlash removable memory cards.
The MEM/003 is designed to be used with a wide range of
CompactFlash cards. As higher density CompactFlash cards
become available, they will be approved by ACRA
CONTROL for use with this module. Approved cards are
listed in the DRE/CFM/002 data sheet.
The MEM/003 can store data in a CompactFlash Card from
any combination of data sources in a KAM-500 system. Data
storage can be triggered by a combination of discrete bits
FEATURES and analog signal levels. To read or erase the data, remove
• Supports removable solid-state memory cards the card and read it using a standard off-the-shelf
• Removable CompactFlash media (supports Type I & II) CompactFlash card reader. Software tools are available from
• CompactFlash media: can be read with USB card-reader ACRA CONTROL and third party vendors to read and view
or PCMCIA adapter recorded data.
• Programmable event size The MEM/003 is designed for applications where stand-alone
• Supports high speed CompactFlash cards up to 128GB
logging of data is required, that is, without the need for a
separate data recorder. A status register is available to be
APPLICATIONS transmitted via an output module, to monitor errors, logging
• Standalone data logging conditions and capacity remaining. This can be useful as a
pre-test checkout capability.
The MEM/003 has a knurled head captive screw for
fastening/unfastening the DAU lid by hand or with tools.
CompactFlash CompactFlash card

BUFFER
card interface
MEM/003
MEM/003 functional diagram
5 Jan. 2009 | DST/T/087 539

Selection Paths
Airborne Data Acquisition → KAM-500 → Modules → Bus → Storage
KAM/MEM/003/E MEM/003/E module with knurled head captive screw
Only one MEM/003 can be installed in a KAM-500 chassis.
Revision History
MEM/003/E Added knurled head captive screw Recommended for new programs
MEM/003/D Supports CompactFlash cards up to 128GB in size Not recommended for new programs
MEM/003/C Supports CompactFlash cards up to 8GB in size Not recommended for new programs
MEM/003/B Supports high capacity CompactFlash cards Not recommended for new programs
MEM/003 First release Not recommended for new programs
Related Products
Module Details
DRE/CFM/002 MEM/003 compatible CompactFlash® cards
GTS/MCI/001 CompactFlash® card reader with USB interface
kFlashcard Initializes CompactFlash® cards and extracts logged data
Document Details
TEC/NOT/33 CompactFlash® Application Notes
TEC/NOT/39 Using the KAM/MEM/003/B
www.acracontrol.com
540 5 Jan. 2009 | DST/T/087

Specifications

Slots – – 1 – Software supports only one MEM/003 card per system. Can be
placed in any user-slot.
Mass
– 86 – g
bare connector – – 19.5 mm
Power consumption
+5V 109 – 132 mA
±7V 0 – 0 mA
±12V 0 – 0 mA
total power 0.545 – 0.66 W CompactFlash card fitted.
CompactFlash interface

Memory size – – 128 GB ACRA CONTROL can only guarantee correct operation of the
CompactFlash cards validated and approved for use with the
MEM/003. See the DRE/CFM/002 data sheet.
Recording rate – – 2 Msps Depends on the CompactFlash card (see the DRE/CFM/002
data sheet). The MEM/003 supports sampling rates of up to
2Msps.
Format select restrictions – – – – The MEM/003 supports format select 0 only.
Tightening torque – – – – 0.6Nm for all captive screws on the product.
5 Jan. 2009 | DST/T/087 541

Setting up the MEM/003
acquisition system

542 5 Jan. 2009 | DST/T/087

The following table lists the setup configurations available for the KAM/MEM/003/E.
Manufacturer -
PartReference KAM/MEM/003/E KAM/MEM/003/E ACRA CONTROL part number
InterConnects
No character limit Not Specified Connection for writes to CompactFlash
LOGGED-DATA
Settings - - -
Module-Recorder-1.3 -
The number of bytes that must be logged when a
EventLogSize_Bytes 4294967296:131072 131072 logging event is triggered, this must be a minimum of
131072 and an integer multiple of 65536 bytes.
Triggers
-
Trigger(1:0)
TriggerAlgorithmReference No character limit Not Specified -
Addendum -
StrategyFile -
The StrategyFile defines the order in which samples are
recorded onto the CompactFlash card and is used by
Url strategy.txt
the KSM-500 suite of tools to extract data from the
CompactFlash card.
Yes Indicates if the StrategyFile should be over written each
AlwaysOverwrite No
No time
The following table lists all parameters that are available for the KAM/MEM/003/E.
R[15:9] Binary 0 - 7F hex shows how full the
CompactFlash card is
R(8) 1 when card is full
Report
Unitless BitVector 16 R(7) 1 while logging
Status of CompactFlash Card
R(6) 1 if logging or logged at least once
R[5:0] Error code. See “Error codes for the MEM/003”
on page 545.

The following are data links supported by the KAM/MEM/003/E.

Name Description
LOGGED-DATA CompactFlash card interface
5 Jan. 2009 | DST/T/087 543

Setting up packages
MEMORY-PACKAGE
User defined data package
ReferencedToAbsoluteTime Yes Yes -
PackageRate 1 -
DataLinkReference No character limit Not Specified -
Properties -
0000
InitializationPattern 0000 -
FFFF
Header -
Value FFFF:0000 0000 -
Content - - -
Parameter - - -
Location -
Occurrences - - -
Offset_Address - - -
An algorithm describes how data should be processed.The following are algorithms supported by the KAM/MEM/003/E.
TRIGGER-ALARM-ALGORITHM
This algorithm is used to define trigger conditions when the required trigger condition is a counter/bit vector value or range of
values.
Window -
OKMaximum 0 to 65535 Not Specified -
OKMinimum 0 to 65535 Not Specified -
TRIGGER-BOOLEAN-ALGORITHM
This algorithm is used to define trigger conditions when the required trigger condition is a bit or combination of bit values. The bit
value combinations can be logically ANDed or ORed together to create complex triggering scenarios.
OR - - -
Input -
BitIndex 15:0 Not Specified -
Yes
Invert No -
No
AND - - -
Input -
Yes
Invert No -
No
"/><\.
544 5 Jan. 2009 | DST/T/087

Error codes for the MEM/003 CompactFlash card. Successful writing of the first samples to
the CompactFlash card is indicated by the status word error
code changing from 3F16 to 0016.
0016 Log mode + ok
MEM/003 must be used with kFlashcard to initialize the
0116 Reserved for future use CompactFlash card and extract data from the CompactFlash
0216 Reserved for future use card. kFlashcard supports Windows 2000 and Windows XP
platforms only.
0316 Logging too fast
When a filled CompactFlash card is fitted in a MEM/003, this
0416 CompactFlash memory card fault or no information will be indicated by R[8] of the status word being
CompactFlash card present set to 1. R[15:9] will indicate 0016. R[8] has precedence over
R[15:9].
0616-3E16 Reserved for future use
3F16 CompactFlash card detected and initialization

complete
Getting the most from the MEM/003

Any subset of the
parameters available over
the backplane can be stored
in the MEM/003. Up to two
parameters can be used to
specify the start (or trigger)
conditions. For example, an
analog signal is within a
certain window and certain
discrete bits in another
parameter can be set.
Event sizes are specified
ultimately in terms of
acquisition cycles, but they
are presented via the graphical user interface in terms of
seconds.
The status word will indicate overflow (logging too fast). See
“Error codes for the MEM/003”. This status information is also
recorded with the logged data. Overflow occurs when the
CompactFlash card fitted/installed cannot log continuously at
the configured sampling rate.
The minimum number of blocks to be logged for a given
trigger condition can be configured. This is the minimum
number of blocks that will be recorded for an event where the
trigger conditions are met for a single sample. This condition
can be met when both trigger conditions have been met,
even if one is valid for a single sample. The maximum
number of blocks that can be recorded from this type of event
is 65536 blocks, the minimum is two blocks. If the trigger is
maintained for more than the specified minimum number of
blocks to log, data will be logged until the trigger condition is
removed, so if the trigger is maintained valid for a sufficient
number of acquisition cycles the CompactFlash card can be
filled with data from a single event.
When logging data from analog modules with digital filtering
(for example the ADC/014) after power up, the digital filtering
must be given time to settle before data is logged to the
MEM/003. In this case it is recommended to use time or
discrete data as the B trigger input, with the A trigger as the
selected analog parameter value range.
When logging at low sample rates (<1000sps) it can take
several minutes for the data to be written into the
5 Jan. 2009 | DST/T/087 545

Removing the CompactFlash card
To eject the CompactFlash card, unscrew the captive lid locking screw and hinge the lid away from the card. Press the eject
button and remove the card. The hinged lid restrains the card while in use. The hinged lid opens out 95°, in an arc of radius
63mm (2.5 inch).
80.00
65.50
16.00
9.25 60.25
67.75 CAPTIVE SCREW: ACM/SCW/001/01
Radius 63.25
Open Lid Position: Angle 95°
19.50
8.00
3.00 3.00
46.50
5.00 7.00
27.00
24.00
17.00 15.00
10.00
73.00
4 off Drill & Tap to suit M2

BLK/006/03
NOTE ON FINISH:
3rd ANGLE PROJECTION ACRA CONTROL
6082-T6 (Din No: AlMgSi1) Electroless nickel plated
with top surface painted:
TITLE: Plan and Elevations of
TOLERANCES: REINORANGE RAL2004. ACC/MEM/003/E/01/OPEN
DOC Nº: Date:28 Apr '08
1 Decimal places= ±0.02mm ACC/MEM/003/E/01/OPEN
2 Decimal places= ±0.01mm Sheet: 1 of 1
Figure 2: MEM/003 hinged lid
Connector pinout of the KAM/MEM/003

There is no connector pinout for the KAM/MEM/003.
www.acracontrol.com
546 5 Jan. 2009 | DST/T/087

KAD/MEM/004/B/4G, KAM/MEM/004/B/4G
C O N T R O L A CompactFlash® memory module with data extraction via Fast Ethernet
DESCRIPTION
The MEM/004 is a memory module which supports logging of
KAM-500 data to solid-state memory. The data can be
sourced from any module within a distributed KAM-500
system. Logged data can then be extracted via a Fast
Ethernet interface.
The MEM/004 is designed for applications where stand-alone
logging of data is required, without the need for a separate
data recorder, and where access to the unit is restricted. If
removal of the CompactFlash card is preferred, the MEM/003
is recommended.
FEATURES The MEM/004 is available with two connector options: the
• Supports logging of data into solid-state memory KAM (51-way micro-miniature) and KAD (52-way double
• High data transfer rate density). Each connector option is available with three
• Data extraction via Fast Ethernet (100 Base TX) CompactFlash card sizes, 4GB, 6GB or 12GB. For example,
• Programmable event sizes and data triggers the KAM/MEM/004/B/4G has a 51-way micro-miniature
connector and comes with a 4GB CompactFlash card,
APPLICATIONS whereas the KAD/MEM/004/B/6G has a 52-way double
density connector and comes with a 6GB CompactFlash
• Standalone data logging card.
• Restricted unit access
Trigger
logic
Solid state memory

Memory
Data
interface
buffer
Data
buffer
RX+ 1
RX- 2 100 MAC/PHY Ethernet
interface
TX+ 18
TX- 19
GND 51
MEM/004
Inputs and outputs on the MEM/004
15 Jul. 2008 | DST/T/054 547

Selection Paths
Airborne Data Acquisition → KAM-500 → Modules → Storage
KAD/MEM/004/B/4G CON/KAD/002/CP Module with a 4GB CF card and a 52-way double density top connector
KAM/MEM/004/B/4G ACC/CON/008/04 Module with a 4GB CF card and a 51-way micro-miniature top connector
Revision History
MEM/004/B/xG Corrects problems with capacity reporting at power up Recommended for new programs
and initialization at high temperature
MEM/004/xG Memory module with a xGB CompactFlash card Not recommended for new programs
In this data sheet MEM/004 refers to both the KAD and KAM version of the module.
Related Products
Module Details
MEM/003/C Supports removable CompactFlash cards
DRE/CFM/002/4GB 4GB Type I CompactFlash card
DRE/CFM/002/6GB 6GB Type II CompactFlash card
DRE/CFM/002/12GB 12GB Type II CompactFlash card
kFlashCardXID Utility to extract data form the CompactFlash card
Document Details
www.acracontrol.com
548 15 Jul. 2008 | DST/T/054

Specifications

Slots – – 1 – Only one MEM/004 module is allowed per KAM-500 system; it
must be in the master.
Mass
– 88 – g
Power consumption
+5V 350 – 440 mA
Ethernet interface

Inputs/outputs – – 1 – IEEE 802.3 compatible; 100BaseTX only.
15 Jul. 2008 | DST/T/054 549

acquisition system

Ordering options
The PartReference settings are specific to each module variant. Only one variant is shown below.
550 15 Jul. 2008 | DST/T/054

The following table lists the setup configurations available for the KAD/MEM/004/B/12G.
Manufacturer -
PartReference KAD/MEM/004/B/12G KAD/MEM/004/B/12G ACRA CONTROL part number
InterConnects
No character limit Not Specified Connection for writes to CompactFlash
LOGGED-DATA
Data can be extracted from the CompactFlash over Fast
ETHERNET-DATA No character limit Not Specified
Ethernet
Settings - - -
Module-Recorder-1.3 -
The number of bytes that must be logged when a
EventLogSize_Bytes 4294967296:131072 131072 logging event is triggered, this must be a minimum of
Triggers
-
Trigger(1:0)
TriggerAlgorithmReference No character limit Not Specified -
Module-Ethernet-1.1 Ethernet Interface for extracting data
IP Address of the Module. The standard decimal dot
IPAddress 0.0.0.0
notation must be used, 192.168.1.111.
MAC Address of the Module. The standard hexadecimal
MACAddress 00-00-00-00-00-00
notation must be used, 00-0E-2E-DB-88-08.
Addendum -
StrategyFile -
The StrategyFile defines the order in which samples are
recorded onto the CompactFlash card and is used by
Url strategy.txt
the KSM-500 suite of tools to extract data from the
CompactFlash card.
Yes Indicates if the StrategyFile should be over written each
AlwaysOverwrite No
No time
The following table lists all parameters that are available for the KAD/MEM/004/B/12G.
R[15:9] Binary 0 - 7F hex shows how full the
CompactFlash card is
R(8) 1 when card is full
Report
Unitless BitVector 16 R(7) 1 while logging
Status of CompactFlash Card
R(6) 1 if logging or logged at least once
R[5:0] Error code. See “Error codes for the MEM/004”
on page 553.

The following are data links supported by the KAD/MEM/004/B/12G.

Name Description
ETHERNET-DATA IEEE 802.3 compatible data link
15 Jul. 2008 | DST/T/054 551

Setting up packages
MEMORY-PACKAGE
User defined data package
ReferencedToAbsoluteTime Yes Yes -
PackageRate 0 1 -
DataLinkReference No character limit Not Specified -
Properties -
0000
InitializationPattern 0000 -
FFFF
Header - - -
Value FFFF:0000 0000 -
Content - - -
Parameter - - -
Location -
Occurrences - - -
Offset_Address - - -
An algorithm describes how data should be processed. The following are algorithms supported by the KAD/MEM/004/B/12G.
values.
Window -
OKMaximum 0 to 65535 Not Specified -
OKMinimum 0 to 65535 Not Specified -
OR - - -
Input -
Yes
Invert No -
No
AND - - -
Input -
Yes
Invert No -
No
"/><\.
552 15 Jul. 2008 | DST/T/054

Error codes for the MEM/004 IP and MAC addresses
The IP (Internet Protocol) and MAC (Media Access Control)
016 Log mode + ok of the MEM/004 are stored in EPROM and must be
configured before the MEM/004 will be detected over an
116 Reserved for future use Ethernet network. The MEM/004 should be power cycled
216 Card is being initialized or data is being extracted after reprogramming the IP or MAC address.
316 Too fast data logging
416 CompactFlash memory card fault or no

CompactFlash card present
516 - 3E16 Reserved for future use

complete

When recording to the MEM/004, data is organized into
individual ‘events’. Each event is a continuous stream of data
recorded to the memory card. This continuous data stream is
written to the media from onboard RAM buffers in the form of
individual ‘blocks’, each of which is 32ksamples in length.
When the MEM/004 is configured to use a trigger as a start
condition, there are several options for defining a stop
condition. The first option is to log for a user-configurable
number of 32ksample blocks—from two up to 65536 blocks.
In this scenario, when the trigger condition is TRUE, an event
is started and data is recorded to the card for the
user-specified number of 32ksample blocks. When the
specified number of data blocks has been written to the card,
one of two things happens. If by this time the trigger condition
has become FALSE, data logging is stopped and the event
finished. However, if the trigger condition is still TRUE after
the specified number of blocks has been written, data
continues to be logged to the card until the trigger condition
becomes FALSE or the card is completely filled. In this way
the card can be filled by one single event.
When configured to continuously log, blocks of data are
written to the memory card whenever the system is powered
on. The number of events created on a card will be
determined by the number of times that system power is
cycled.
(such as the ADC/109), after power up the digital filters must
be given time to settle before ‘good’ data is recorded to the
card. If using one of these analog parameters as a trigger, it
is recommended that a second trigger be used, with either
time or discrete data as the start condition. This prevents
erroneous events from being created on the card due to any
analog data spikes that may occur as the digital filters settle.
The CompactFlash card cannot be initialized at the same
time as programming, as during programming MEM/004
access to the CompactFlash card is disabled. While media is
not removable, the CompactFlash card can be upgraded by
ACRA CONTROL.
Network protocol support

When connected to an Ethernet network the MEM/004 will
appear as a network node. It supports the ARP and PING
protocols for network address resolution and network debug.
15 Jul. 2008 | DST/T/054 553

Connector pinout of the KAD/MEM/004

1 RX+ Ethernet interface Ethernet in
2 RX− Ethernet interface Ethernet in
3 NC Not connected
4 NC Not connected
5 NC Not connected
6 NC Not connected
7 NC Not connected
8 NC Not connected
9 NC Not connected
10 NC Not connected
11 NC Not connected
12 NC Not connected
13 NC Not connected
14 NC Not connected
15 NC Not connected
16 NC Not connected
17 NC Not connected
18 TX+ Ethernet interface Ethernet out
19 TX− Ethernet interface Ethernet out
20 NC Not connected
21 NC Not connected
22 NC Not connected
23 NC Not connected
24 NC Not connected
25 NC Not connected
26 NC Not connected
27 NC Not connected
28 NC Not connected
29 NC Not connected
30 NC Not connected
31 NC Not connected
32 NC Not connected
33 NC Not connected
34 NC Not connected
35 NC Not connected
36 NC Not connected
37 NC Not connected
38 NC Not connected
39 NC Not connected
40 NC Not connected
41 NC Not connected
42 NC Not connected
43 NC Not connected
44 NC Not connected
45 NC Not connected
46 NC Not connected
47 NC Not connected
48 NC Not connected
49 NC Not connected
50 NC Not connected
www.acracontrol.com
554 15 Jul. 2008 | DST/T/054

KAM/MEM/103
KAM-500 series 100 CompactFlash® memory module
C O N T R O L
DESCRIPTION
The MEM/103 is a memory card interface which supports
logging to CompactFlash removable memory cards.
The MEM/103 is designed to be used with a wide range of
CompactFlash cards. As higher density CompactFlash cards
become available, they will be approved by ACRA
CONTROL for use with this module. Approved cards are
listed in the DRE/CFM/002 data sheet.
The MEM/103 can store data in a CompactFlash Card from
any combination of data sources in a KAM-500 system. Data
storage can be triggered by a combination of discrete bits
FEATURES and analog signal levels. To read or erase the data, remove
• Supports removable solid-state memory cards the card and read it using a standard off-the-shelf
• Removable CompactFlash media (supports Type I & II) CompactFlash card reader. Software tools are available from
• CompactFlash media: can be read with USB card-reader ACRA CONTROL and third party vendors to read and view
or PCMCIA adapter recorded data.
• Programmable event size The MEM/103 is designed for applications where stand-alone
• Designed to support high-speed CompactFlash cards up to
logging of data is required, that is, without the need for a
128GB
separate data recorder. A status register is available to be
• Logs data at up to 2Msps transmitted via an output module, to monitor errors, logging
conditions and capacity remaining. This can be useful as a
APPLICATIONS pre-test checkout capability.
• Standalone data logging The MEM/103 has a knurled head captive screw for
fastening/unfastening the DAU lid by hand or with tools.
CompactFlash CompactFlash card

BUFFER
card interface
MEM/103
MEM/103 functional diagram
6 Jan. 2009 | DST/U/016 555

Selection Paths
Airborne Data Acquisition → KAM-500 → Modules → Bus → Storage
KAM/MEM/103 KAM-500 series 100 CompactFlash® memory module
Only one MEM/103 can be installed in a KAM-500 chassis.
Revision History
MEM/103 First release Recommended for new programs
Related Products
Module Details
DRE/CFM/002 MEM/103 compatible CompactFlash® cards
kFlashcard Initializes CompactFlash® cards and extracts logged data
Document Details
www.acracontrol.com
556 6 Jan. 2009 | DST/U/016

Specifications

Slots – – 1 – Software supports only one MEM/103 card per system. Can be
placed in any user-slot in any combination.
Mass
– 86 – g
Height above chassis For clearance requirements for the hinged lid, see
measurements in Figure 2 on page 562.
Power consumption
+5V 70 – 135 mA
±7V 0 – 0 mA
±12V 0 – 0 mA
total power 0.35 – 0.675 W CompactFlash card fitted.
CompactFlash interface

Memory size – – 24 GB ACRA CONTROL can only guarantee correct operation of the
CompactFlash cards validated and approved for use with the
MEM/103. For details of approved CompactFlash cards, see the
DRE/CFM/002 data sheet.
The MEM/103 has been designed to work with CompactFlash
cards up to 128GB in size; at the time of writing, the MEM/103 is
compatible with CompactFlash cards of up to 24GB in size.
Recording rate – – 2 Msps Depends on the CompactFlash card (see DRE/CFM/002 data
sheet). The MEM/103 supports sampling rates of up to 2Msps.
Format select restrictions – – – – The MEM/103 supports format select 0 only.
Tightening torque – – – – 0.6Nm for all captive screws on the product.
6 Jan. 2009 | DST/U/016 557

acquisition system


The following table lists the setup configurations available for the KAM/MEM/103.

Manufacturer
PartReference KAM/MEM/103 KAM/MEM/103 ACRA CONTROL part number.
SerialNumber – – Unique name for each module.
InterConnects No character limit Not Specified Connection for writes to CompactFlash.
LOGGED-DATA
Module-Recorder-1.3
EventLogSize_Bytes 4294967296:131072 131072 The number of bytes that must be logged when a
logging event is triggered, this must be a minimum of
Triggers
Trigger(1:0)
TriggerAlgorithmReference No character limit Not Specified –
Addendum – – –
558 6 Jan. 2009 | DST/U/016

StrategyFile
Url – strategy.txt The StrategyFile defines the order in which samples
are recorded onto the CompactFlash card and is used
by the KSM-500 suite of tools to extract data from the
CompactFlash card.
AlwaysOverwrite Yes No Indicates if the strategy file should be overwritten each
No time.
The following table lists all parameters that are available for the KAM/MEM/103.

Report
Status of CompactFlash Card Unitless BitVector 16 R[15:9] Binary 0 - 7F hex shows how full the
CompactFlash card is.
R(8) 1 when card is full.
R(7) 1 while logging.
R(6) 1 if logging or logged at least once.
R[5:0] Error code.

following are data links supported by the KAM/MEM/103.
Name Description
Setting up packages
MEMORY-PACKAGE
User defined data package.

ReferencedToAbsoluteTime Yes Yes –
PackageRate – 1 –
DataLinkReference No character limit Not Specified –
Properties
InitializationPattern 0000 0000 –
FFFF
Header
Value 0000 0000 –
to
FFFF
Content – – –
Parameter – – –
Location
Occurrences – – –
Offset_Address – – –
6 Jan. 2009 | DST/U/016 559

An algorithm describes how data should be processed. The following are algorithms supported by the KAM/MEM/103.
values.

Window
OKMaximum 0 to 65535 Not Specified –
OKMinimum 0 to 65535 Not Specified –

OR – – –
Input
BitIndex 15:0 Not Specified –
Invert Yes No –
No
AND – – –
Input
BitIndex 15:0 Not Specified –
Invert Yes No –
No
"/><\.
560 6 Jan. 2009 | DST/U/016

Error codes for the MEM/103 the CompactFlash card is indicated by the status word error
code changing from 3F16 to 0016.
MEM/103 must be used with kFlashcard to initialize the
0016 Log mode + ok CompactFlash card and extract data from the CompactFlash
card. kFlashcard supports Windows 2000 and Windows XP
platforms only.
When a filled CompactFlash card is fitted in a MEM/103, this
0316 Logging too fast information will be indicated by R(8) of the status word being
set to 1. R[15:9] will indicate 0016. R(8) has precedence over
0416 CompactFlash memory card fault or no R[15:9].
CompactFlash card present
0616-3E16 Reserved for future use

complete

Any subset of the
parameters available over
the backplane can be stored
in the MEM/103. Up to two
parameters can be used to
specify the start (trigger)
conditions. For example, an
analog signal is within a
certain window and certain
discrete bits in another
parameter can be set.
Event sizes are specified
ultimately in terms of
acquisition cycles, but they
are presented via the graphical user interface in terms of
seconds.
The status word will indicate overflow (logging too fast). See
“Error codes for the MEM/103”. This status information is also
recorded with the logged data. Overflow occurs when the
CompactFlash card fitted/installed cannot log continuously at
the configured sampling rate.
The minimum number of blocks to be logged for a given
trigger condition can be configured. This is the minimum
number of blocks that will be recorded for an event where the
trigger conditions are met for a single sample. This condition
can be met when both trigger conditions have been met,
even if one is valid for a single sample. The maximum
number of blocks that can be recorded from this type of event
is 65536 blocks, the minimum is two blocks. If the trigger is
maintained for more than the specified minimum number of
blocks to log, data will be logged until the trigger condition is
removed, so if the trigger is maintained valid for a sufficient
number of acquisition cycles the CompactFlash card can be
filled with data from a single event.
(for example, ADC/014) after power up, the digital filtering
must be given time to settle before data is logged to the
MEM/103. In this case it is recommended to use time or
discrete data as the B trigger input, with the A trigger as the
selected analog parameter value range.
When logging at low sample rates (1000sps) it can take
several minutes for the data to be written into the
CompactFlash card. Successful writing of the first samples to
6 Jan. 2009 | DST/U/016 561

Removing the CompactFlash card
To eject the CompactFlash card, unscrew the captive lid locking screw and hinge the lid away from the card (see Figure 2).
Press the eject button and remove the card. The hinged lid restrains the card while in use. The hinged lid opens out 95°, in an
arc of radius 63mm (2.5 inch).
80.00
65.50
16.00
9.25 60.25
67.75 CAPTIVE SCREW: ACM/SCW/001/01
Radius 63.25
Open Lid Position: Angle 95°
19.50
8.00
3.00 3.00
46.50
5.00 7.00
27.00
24.00
17.00 15.00
10.00
73.00
4 off Drill & Tap to suit M2

BLK/006/03
NOTE ON FINISH:
3rd ANGLE PROJECTION ACRA CONTROL
6082-T6 (Din No: AlMgSi1) Electroless nickel plated
with top surface painted:
TITLE: Plan and Elevations of
TOLERANCES: REINORANGE RAL2004. ACC/MEM/003/E/01/OPEN
DOC Nº: Date:28 Apr '08
1 Decimal places= ±0.02mm ACC/MEM/003/E/01/OPEN
2 Decimal places= ±0.01mm Sheet: 1 of 1
Figure 2: MEM/103 hinged lid
Connector pinout of the KAM/MEM/103

There is no connector pinout for the KAM/MEM/103.
www.acracontrol.com
562 6 Jan. 2009 | DST/U/016

KAD/RTC/003, KAM/RTC/003
A C R A KAM-500 RTC/003
Real-time clock generator with memory status outputs
C O N T R O L
DESCRIPTION
The RTC/003 is used to count time from microseconds to
years inclusive. It is designed to time seed modules where
time tagging of parameters/events is required but IRIG time is
not available or necessary.
The RTC/003 stores time in an 80-bit BCD format. For
example, one microsecond before midnight, 1 March, 2000 is
stored as follows:
2000 03:01 23:59 59.99 9999
The module time is set using kTimeseed running on a
FEATURES programming PC over a SAM/DEC/007 or Ethernet
programming link.
• Counts from microseconds to years
• 3ppm drift when powered The RTC/003 can give the status of a MEM/003 or MEM/004
• 100ppm drift when off (powered by battery) memory module in the same chassis. The TTL status outputs
• Five-year battery back-up are that the memory is logging data, and that the memory is
• Two TTL memory status outputs 80% full.
• Time and Date programmed using kTimeseed
APPLICATIONS
• Time tagging without an external IRIG time
• Indicating memory module status
MEM_STATUS(0) 1 FPGA
MEM_STATUS(1) 2
+
-
TIMER
GND 51
RTC/003
An internal block diagram of the RTC/003
16 Sep. 2008 | DST/R/063 563

Selection Paths
Airborne Data Acquisition → KAM-500 → Modules → Time
KAD/RTC/003 CON/KAD/002/CP RTC/003 module with 52-way double density module top connector
KAM/RTC/003 ACC/CON/008/04 RTC/003 module with 51-way micro-miniature module top connector
Revision History
RTC/003 First release Recommended for new programs
Related Products
Module Details
kTimeseed Time seeding software utility for real-time modules within KAM-500 system
RTC/002 Real-time clock generator for KAM-500 systems
Document Details
www.acracontrol.com
564 16 Sep. 2008 | DST/R/063

Specifications

Mass
– 70 – g
Power consumption
+5V 140 – 148 mA
±7V 0 – 0 mA
±12V 0 – 0 mA
total power 700 – 740 mW
Battery-backed real-time clock

Drift Determined by the temperature compensated crystal oscillator
(TCXO) in controller.
on – – 3 ppm
off – – 100 ppm
Battery duration – 5 10 years To change the battery the unit must be returned to ACRA
CONTROL.
BTTL outputs

Signaling rate Outputs are updated at the start of the acquisition cycle.
MEM_STATUS(0) – – 100 kbps
MEM_STATUS(1) – – 100 kbps
Output voltage
Output resistance – 120 – Ω 120Ω resistor in series with a TTL output.
16 Sep. 2008 | DST/R/063 565

Setting up the RTC/003
For parameter TimeYear

Name TimeYear YEAR The year of the start of the acquisition cycle.
Base Unit Unitless Unitless R[15:0] 1991 - 2099 Count of year
maximum 209916 200616
minimum 190116
Size In Bits 16 16
For parameter TimeDay

Name TimeDay TIME_DAY The month and days of month the start of the acquisition cycle.
Base Unit Unitless Unitless R[15:8] 01-12 Count of month
R[7:0] 01-31 Count of day of month
maximum 123116 100316
minimum 010116
Size In Bits 16 16
For parameter TimeHi

Name TimeHi TIME_HI Hours and minutes time of the start of the acquisition cycle.
Base Unit Unitless Unitless R[15:13] Reserved for future use
R[12:11] Tens of hours, 0-2
R[10:7] Ones of hours, 0-9
R[6:4] Tens of minutes, 0-5
R[3:0] Ones of minutes, 0-9
maximum 11D916 005916
minimum 000016
Size In Bits 16 16
For parameter TimeLo

Name TimeLo TIME_LO Seconds and centiseconds time of the start of the acquisition cycle.
maximum 599916 027916
minimum 0
Size In Bits 16 16
For parameter TimeMicro

Name TimeMicro TIME_MICRO Microsecond time of the start of the acquisition cycle.
Base Unit Unitless Unitless R[15:0] 0000-9999 microseconds
maximum 999916 027916
minimum 0
Size In Bits 16 16
566 16 Sep. 2008 | DST/R/063

This module uses the X-I RIG Time In Out-1.1 XidML schema. (See http://www.xidml.org).

Manufacturer
part reference KAD/RTC/003 KAD/RTC/003 ACRA CONTROL part number.
Getting the most from the RTC/003

When the KAM-500 is operating, the timing of all modules
(including the RTC/003) is controlled by the temperature
compensated crystal on the controller. Therefore the time
need only be read once per acquisition cycle.
When the KAM-500 is switched off, the battery back-up time
continues. This can drift by 100ppm so it is recommended
that kTimeseed is used regularly to set the time and to check
the date recommended for the battery change.
The RTC/003 monitors the performance of a MEM/003 or
MEM/004 module in the same chassis and provides two
status outputs showing whether the MEM is logging or not,
and whether the memory is more than 80% full.
16 Sep. 2008 | DST/R/063 567

Connector pinout of the KAM/RTC/003
1 MEM_STATUS(0) BTTL outputs Set high when MEM module is logging
2 MEM_STATUS(1) BTTL outputs Set high when MEM module is 80% full or more
3 NC Not connected
4 NC Not connected
5 NC Not connected
6 NC Not connected
7 NC Not connected
8 NC Not connected
9 NC Not connected
10 NC Not connected
11 NC Not connected
12 NC Not connected
13 NC Not connected
14 NC Not connected
15 NC Not connected
16 NC Not connected
17 NC Not connected
18 NC Not connected
19 NC Not connected
20 NC Not connected
21 NC Not connected
22 NC Not connected
23 NC Not connected
24 NC Not connected
25 NC Not connected
26 NC Not connected
27 NC Not connected
28 NC Not connected
29 NC Not connected
30 NC Not connected
31 NC Not connected
32 NC Not connected
33 NC Not connected
34 NC Not connected
35 NC Not connected
36 NC Not connected
37 NC Not connected
38 NC Not connected
39 NC Not connected
40 NC Not connected
41 NC Not connected
42 NC Not connected
43 NC Not connected
44 NC Not connected
45 NC Not connected
46 NC Not connected
47 NC Not connected
48 NC Not connected
49 NC Not connected
50 NC Not connected
www.acracontrol.com
568 16 Sep. 2008 | DST/R/063

KAM/TCG/102/C
A C R A KAM-500 TCG/102
C O N T R O L Combined GPS and IRIG input module
DESCRIPTION
The TCG/102 can accept time from an IRIG-B time source,
from its onboard GPS receiver (external antenna required), or
from an external GPS receiver outputting NMEA messages
and a one pulse per second signal. The received time is
written to an internal timer and to a real-time clock that
maintains time during power-down (when an external battery
is connected). The time can be used for synchronization of a
distributed KAM-500 data acquisition system. The module
generates IRIG-B outputs to allow external devices to
synchronize to the KAM-500 system.
FEATURES The module comprises a GPS reader and an IRIG reader
which decode incoming signals. The IRIG reader extracts
• Synchronizes to IRIG-B or Global Positioning System (GPS)
control functions (CF) and straight binary seconds (SBS) as
• Interfaces to onboard L1 GPS receiver or to an external
well as time. The GPS reader parses NMEA messages as
NMEA stream
they are generated by the receiver. Extracted navigation data
• Accepts and generates analog and digital IRIG-B
such as position, altitude, velocity, and heading are available
• 1µs time resolution
as individual parameters. Key NMEA messages are buffered,
• Outputs 1pps or 10pps pulses
and can be sourced from this module.
• Less than 3ppm drift when acting as a generator
• Time is maintained from an external battery during power The timer block is a 4x16-bit BCD counter with microsecond
down resolution. For example, at one microsecond before midnight
• GPS navigation information available on January 1, the timer would read 0001 23:59 59.99 9999.
• Secondary time source input
APPLICATIONS
• System synchronization
• Parameter time tagging
• Global positioning
GPS NMEA message

RF_IN
receiver ONE_PPS
Battery
V_BAT 17 regulator
RTC
Navigation
GPS
RS232_IN 16 reader
NMEA
A_IRIG_IN+ 1 + ANALOG message
AMP →DIGITAL buffer
A_IRIG_IN- 2 -
TTL_IN 10 IRIG STATUS

RS422_IN+ 6 reader CF
SBS
RS422_IN- 7
A_TONE_OUT 5 DIGITAL ←
A_IRIG_OUT 4 ANALOG
TTL_IRIG_OUT 14
IRIG
RS422_OUT+ 11 generator
RS422_OUT- 12
TTL_PPS_OUT 15
A_GND 3
D_GND 9
TCG/102
Inputs and outputs on the TCG/102
1 May 2008 | DST/T/096 569

Selection Paths
Airborne Data Acquisition → KAM-500 → Modules→ GPS
KAM/TCG/102/C CON/KAD/003/CP TCG/102/C module with 19-way mating connector

By default, the standard mating connector and backshell above are included with each module in the shipment. Its part number
will be added to the Confirmation of Order unless an alternative option is specified (see the Cables data sheet).
Revision History
TCG/102/C Improved GPS acquisition time; internal PLL locks faster Recommended for new programs
and makes finer timing adjustments; GPS leap seconds
step-back corrected
TCG/102/B Addition of a secondary time source input Not recommended for new programs
TCG/102 First release Not recommended for new programs
Related Products
Module Details
RFE/AEG/001 Airborne active GPS antenna, with TNC female connector
ASM/TCG/102/192F 16-foot (4.88m) antenna cable
TCG/001/C IRIG-B time code reader and generator with external battery
ACD/BAC/004 Straight angled backshell for CON/KAD/003/CP
Document Details
TEC/NOT/003 IRIG-B
www.acracontrol.com
570 1 May 2008 | DST/T/096

Specifications
Parameter Min. Typ. Max. Units Condition/details
Mass
– 68 – g
bare connector – – 0.43 inch Design metric is millimeters.
Power consumption
+5V – – 230 mA
±7V – – 0 mA
+12V – – 63 mA When driving the recommended antenna RFE/AEG/001.
+12V – – 32 mA With no antenna connected.
-12V – – 28 mA
total power – – 2.24 W
Active antenna inputs

Bias voltage 5.15 – 5.35 V
Bias current – – 50 mA
Signal strength -138 – – dBm
Antenna gain 10 26 50 dB See “GPS antenna” on page 582.
Onboard GPS receiver

Time accuracy – – 1 µs
Position accuracy See “Navigation data accuracy” on page 583.
2D fix 2.5 – 22 m Circular Error Probable (CEP).
3D fix 2.5 – 22 m Spherical Error Probable (SEP).
3D fix 2 – – m With Satellite-Based Augmentation Systems (SBAS).
Satellite acquisition time See “Acquisition” on page 582.
reacquisition 3.5 5 – s
warm power up – 40 – s
cold power up – 60 – s Test carried out with a minimum of four satellites in use.
GPS update rate – 1 1 Hz
Navigation datum – – – – World Geodetic System-84 (WGS-84). See “Datum” on
page 583.
Restrictions Coordinating Committee for Multilateral Export Controls
(COCOM) restrictions apply.
velocity – – 1,854 kph
velocity – – 1000 knots
altitude – – 18000 m
altitude – – 60000 ft
1 May 2008 | DST/T/096 571

Analog IRIG time inputs
Sampling rate
A_IRIG_IN – – 2 Msps Operating as analog IRIG-B input, the following time codes are
supported: IRIG-B 120, 121, 122, 123.
Input voltage
voltage range 0.1 – 10 Vp-p
Time error
offset – – 4 µs
Input resistance
between inputs (off) – 1.1 – MΩ Module powered off.
BTTL inputs
Signalling rate
TTL_IN – – 1 bps Operating as ONE_PPS input.
TTL_IN – – 100 bps Operating as IRIG-B input, the following time codes are
supported: IRIG-B 000, 001, 002, 003.
Input voltage
logic ‘0’ 0 – 0.7 V
logic ‘1’ 2 – 5.25 V
overvoltage protection -0.3 – 6 V Voltage in excess of these values can damage input.
Signalling currents
logic ‘0’ – -0.2 -0.5 mA
logic ‘1’ – 2 5 mA
Input resistance
each input to GND – 27 – MΩ Module powered on.
each input to GND – 53 – kΩ Module powered off.
Time error
offset – – 2 µs Over full operating temperature range. When configured as
primary (TTL_IRIG) input range.
RS-232 inputs
Baud rate
RS232_IN 4800 – 115200 bps The following baud rates are supported: 4800, 9600, 19200,
115200.
Input voltage
logic ‘0’ – – 0.6 V VIN+ - VIN-
logic ‘1’ 2.4 – – V VIN+ - VIN-
overvoltage protection -25 – 25 V Voltage in excess of these values can damage input.
Input resistance
each input to GND – 4.8 – MΩ Module powered on.
each input to GND – 4.7 – kΩ Module powered off.
572 1 May 2008 | DST/T/096

RS-422 inputs
Signalling rate
RS422_IN – – 100 bps Operating as IRIG-B input, the following time codes are
supported: IRIG-B 000, 001, 002, 003.
RS422_IN 4800 – 115200 bps Operating an NMEA data input.
The following baud rates are supported: 4800, 9600, 19200,
115200.
Input voltage
logic ‘0’ – – -0.7 V VIN+ - VIN-
logic ‘1’ 0.7 – – V VIN+ - VIN-
overvoltage protection -7 – 12 V Voltage in excess of these values can damage input.
ESD protection – – 15 kV Human Body Model.
Input resistance
each input to GND (on) – 4.2 – MΩ Module powered on.
Battery inputs
Input voltage
operating range 4.5 – 12 V The KAM-500 must be powered on (or the power should be
cycled) when the battery is connected for the first time.
Otherwise, 10mA will be drawn from the battery, shortening its
life span.
overvoltage -12 – 12 V Voltage in excess of these values can damage input.
Input current
operating range – – 100 µA
Input resistance
battery input 45 – – kΩ
Analog IRIG time outputs

Signaling rate
A_IRIG_OUT – – 1 kHz Operating as analog IRIG-B 123 output with a 1kHz carrier
frequency.
Output voltage
mark amplitude 4 – 20 Vp-p Range: 4, 8, 12, 16, 20
mark to space ratio – 3 – – Space amplitude = mark amplitude/3
1 May 2008 | DST/T/096 573

Tone outputs
Signalling rate
TONE_OUT 500 – 2500 Hz 500Hz, 1000Hz, 1500Hz, and 2500Hz are the permitted values.
Output voltage
operating range 4 – 20 Vp-p
BTTL outputs
Signaling rate
TTL_IRIG_OUT – – 100 bps Operating as IRIG-B 003 digital output.
TTL_PPS_OUT 1 – 10 Hz Operating as a selectable one or ten pulse-per-second output.
Output voltage
logic ‘0’ – – 0.2 V Sinking 0.1mA through 100Ω output resistance.
logic ‘1’ 4.8 – – V Sourcing 0.1mA through 100Ω output resistance.
RS-422 outputs
Signaling rate
RS422_OUT 100 – – bps When providing IRIG-B.
RS422_OUT – – 1 Mbps When providing X-SYNC.
Output voltage
operating voltage -7 – 12 V Absolute voltage of the operating signal must stay within this
range.
logic ‘0’ – – -2 V V0+ - V0- ; RLOAD = 100Ω
logic ‘1’ 2 – – V V0+ - V0- ; RLOAD = 100Ω
574 1 May 2008 | DST/T/096

Setting up the TCG/102
acquisition system

1 May 2008 | DST/T/096 575

576 1 May 2008 | DST/T/096
The following table lists the setup configurations available for the TCG/102:

Manufacturer
Name ACRA CONTROL ACRA CONTROL
PartReference KAM/TCG/102/C KAM/TCG/102/C ACRA CONTROL part number
SerialNumber FE1234 Fixed 6 characters
Connections
GPS-IN No character limit MyGPS-IN Onboard GPS signal in
EXT-GPS-IN No character limit MyEXT-GPS-IN External GPS signal in
ANALOG-IRIG-B-IN No character limit MyANALOG-IRIG-B-IN Analog IRIG-B time code signal in
PPS-IN No character limit MyPPS-IN PPS signal in, required when using
external GPS in over RS-232
DIGITAL-IRIG-B-IN No character limit MyDIGITAL-IRIG-B-IN Digital IRIG-B time code signal in
X-SYNC-OUT No character limit MyX-SYNC-OUT X-SYNC signal out
DIGITAL-IRIG-B-OUT No character limit MyDIGITAL-IRIG-B-OUT Digital IRIG-B time code signal out
ANALOG-IRIG-B-OUT No character limit MyANALOG-IRIG-B-OUT Analog IRIG-B time code signal out
TONE-OUT No character limit MyANALOG-TONE-OUT Analog tone out
PPS-OUT No character limit MyPPS-OUT PPS signal out, can be used with
ANALOG-IRIG-B-OUT
Module-Time-In-Out-1.3
TimeServer Time-Master Time-Master
Free-Running
GPS
MinimumNumberOfSatelites 3 3
4
Rank 0 0 Prioritizes time code signal in; lowest
1 number wins
Inputs: IRIG-B-TIME
IRIGTimePackageReference No character limit MyIRIGTimePackage
IsInverted Yes No
No
Rank 0 -
1
Outputs: TONE
Frequency 500 1000
1000
1500
2000
Amplitude 2 4
4
6
8
10
Outputs: IRIG-B-TIME
IRIGTimePackageReference No character limit MyIRIGTimePackage
Outputs: TTL-PPS
Pulse 1 1
10
1 May 2008 | DST/T/096 577

The following table lists the 14 parameters that are available from the TCG/102:
ControlFunctionHi Unitless BitVector 16 R[15:0] ControlFunction[26:11]
MSB's of the 27 control function bits
received from the IRIG-B input
ControlFunctionLo Unitless BitVector 16 R[15:5] ControlFunction[9:0]
LSB's of the 27 control function bits R[4:0] Reserved for future use
received from the IRIG-B input
StraightBinarySeconds Unitless BitVector 16 R[15:0] StraightBinarySeconds [15:0]
LSB's of the 17 straight binary seconds
received from the IRIG-B input (see
StatusIn for bit 16)
StatusIn Unitless BitVector 16 R(15) 1 indicates a lock to the incoming IRIG-B stream
IRIG status register R(14) StraightBinarySeconds(16) The MSB of the
straight binary seconds received
R(2) 1 when operating from primary time input
R(1) 1 when the timer's PLL is in lock with the input
TIME ONE_PPS source
R(0) Battery (backed timer) error:
0 when no errors detected; 1 when power-on test fails
(battery voltage is not present or the oscillator was not
running)
DayOfYear Unitless BCD 16 R[15:10] Reserved for future use
Day of year at the start of the acquisition R[9:0] DayOfYear [9:0] 1 to 366
cycle
TimeHi Unitless BitVector 16 R[15:13] Reserved for future use
Hours and minutes of the 44 bit time R[12:7] Time[43:38] BCD Hours 0 to 23
register at the start of the acquisition R[6:0] Time[37:31] BCD Minutes 0 to 59
cycle
TimeLo Second BCD 16 R(15) Reserved for future use

Seconds and centi-seconds of the 44 bit R[14:8] Time[30:16] Seconds 0 to 59
time register at the start of the R[7:0] Time[30:16] Centi-seconds 0 to 99
acquisition cycle
TimeMicro Second BCD 16 R[15:0] Time[15:0] Microseconds 0 to 9999
Microseconds of the 44 bit time register
at the start of the acquisition cycle
GPSStatus Unitless BitVector 16 R(15) 1 indicates no error in the incoming GPS data
GPS status register stream (GPSLock BIT)
R(14) 1 indicates that the Fix Flag was not set R(15)=
0, which means that the GPS position is not fully trusted
R(13) 1 indicates that a checksum error was detected
R(15)=0
R(12) 1 indicates that less than the minimum configured
number of satellites are used, which can affect the
quality of the received data
R(11) 1 indicates that one of the DOP (Dilution of
Precision) figures was outside a specified range
R(10) North/South indicator: 0 the latitude read is in the
northern hemisphere; 1 the latitude read is in the
southern hemisphere
R(9) East/West indicator: 0 the longitude read is east of
the Greenwich Meridian; 1 the longitude read is west of
the Greenwich Meridian
R(8)Reserved for future use
R[7:4] Binary n: Number of satellites in view
R[3:0] Binary n: Number of satellites used to calculate
position
LatitudeHi Degree BCD 16 R[15:8] Latitude[35:28] Degrees of latitude 0 to 89
Degrees and minutes of the 36 bit R[7:0] Latitude[27:20] Minutes of latitude 0 to 59
latitude register, representing degrees
and minutes to 5 decimal places, e.g.
53° 44.95472'
578 1 May 2008 | DST/T/096

LatitudeLo Degree BCD 16 R[15:0] Latitude[19:4] 4 decimal places of minutes of
Four decimal places of minutes, of the latitude 0 to 9999
36 bit latitude register, representing
degrees and minutes to 5 decimal
places, e.g. 53° 44.95472'
LatitudeMicroMinutes Degree BCD 16 R[15:4] Reserved for future use
Fifth decimal place of minutes, of the 36 R[3:0] Latitude[3:0] Fifth decimal place of minutes of
bit latitude register, representing latitude 0 to 9
places, e.g. 53° 44.95472'
LongitudeHi Degree BCD 16 R[15:12] Reserved for future use
Degrees of the 37 bit longitude register, R[11:0] Longitude[36:28] Degrees of longitude 0 to 179
representing degrees and minutes to 5
decimal places, e.g. 132° 07.11948’
LongitudeLo Degree BCD 16 R [15:8] Longitude[27:20] Minutes of longitude 0 to 59
Minutes to two decimal places of the 37 R[7:0] Longitude[19:12]: First two decimal places of
bit longitude register, representing longitude 0 to 99
places, e.g. 132° 07.11948’
LongitudeMicroMinutes Unitless BCD 16 R[15:12] Reserved for future use
Third to fifth decimal places of the R[11:0] Longitude[11:0]: Third to fifth decimal places of
minutes of the 37 bit longitude register, longitude 0 to 999
representing degrees and minutes to 5
decimal places, e.g. 132° 07.11948’
VelocityInKn Knots BCD 16 R[15:0] Knots[15:0] 0 to 9999
Velocity in nautical miles per hour
VelocityInKph KPH BCD 16 R[15:0] KPH[15:0] 0 to 9999
Velocity in kilometers per hour
HeadingHi Degree BCD 16 R[15:10] Reserved for future use
Degrees of true course over ground of R[9:0] Heading[17:8] Degrees of true course over
the 18 bit heading register, representing ground 000:359
degrees to two decimal places, for
example 21.44°
HeadingLo Degree BCD 16 R[15:8] Reserved for future use
Two decimal places of degrees, of true R[7:0] Heading[7:0] Two decimal places of degrees, of
course over ground of the 18 bit heading true course over ground 0 to 99
register, representing degrees to two
decimal places, e.g. 21.44°
AltitudeHi Meter BCD 16 R[15:4] Reserved for future use
Tens of thousands of meters of the 20 R[3:0] ALTITUDE[19:16] 0 to 9
bit altitude register, representing the
Height above Mean Sea Level (MSL)
AltitudeLo Meter BCD 16 R[15:0] ALTITUDE[15:0] 0 to 9999
Meters of the 20 bit altitude register,
representing the Height above Mean
Sea Level (MSL)
DilutionOfPrecision Unitless BitVector 16 R[15:12] Reserved for future use
Dilution of precision R[11:8] PDOP[3:0] Binary positional DOP if >15 F16 is
returned
See “Dilution of Precision (DOP)” on
R[7:4] HDOP[3:0] Binary n: horizontal DOP if >15 F16 is
page 583.
returned
R[3:0] VDOP[3:0] Binary vertical DOP if >15 F16 is
returned
Information Unitless BitVector 16 R(15) Reserved for future use
NMEA message info word R(14) 1 indicates this message was read before
MessageData[40:0] Unitless BitVector 16 R[15:8] Even ASCII character received
41 words of NMEA data R[7:0] Odd ASCII character received. For example:
MsgData(0) = “$G”
MsgData(1) = “PG”
MsgData(2) = “GA” for the $GPGGA NMEA message
1 May 2008 | DST/T/096 579

A datalink is a connection for transmitting and receiving data. It defines both the datalink and physical layers of the link.
The following table lists the datalinks supported by the TCG/102:
Non-programmable DataLinks
Name Description
GPS-IN RF Signal in
ANALOG-IRIG-B-OUT IRIG-B compatible output
ANALOG-TONE-OUT Analog sinewave output
X-SYNC-OUT KAM-500 synchronization signal
PPS-IN One pulse per second input
EXT-GPS-IN
Serial NMEA input
Setup data Choice Default Notes
Type RS-422 RS-422
RS-232
Protocol Properties
Bit rate in bits per second 4800 19200
9600
19200
115200
IRIG-B-IN
IRIG-B data input
Type RS-422 Analog
TTL
Analog
PPS-OUT
Pulse output
Protocol Properties
Pulse rate in pulses per second 1 1
10
DIGITAL-IRIG-B-OUT
IRIG-B data output
Type RS-422 RS-422
TTL
580 1 May 2008 | DST/T/096

Setting up packages
A package is a logical description of how data is transmitted across a datalink.
The following table lists the packages supported by the TCG/102.
IRIG-TIME-PACKAGE
IRIG-B time code data

ReferencedToAbsoluteTime Yes No
No
PackageRate 1 1
DataLinkReference No character MyDIGITAL-IRIG-B-IN
limit
Properties
IRIGTimeFormat B123 B123
B003
NMEA-PACKAGE
NMEA data package

ReferencedToAbsoluteTime Yes No
No
PackageRate
DataLinkReference No character MyGPS-IN
limit
Properties
MessageIdentification
StartPattern
String $GPGGA $GPGGA
$GPGLL
$GPGSA
$GPRMC
$GPVTG
$GPGRS
$GPGST
$GPZDA
$GPGSV_0
$GPGSV_1
$GPGSV_2
$GPGSV_3
$GPGSV_4
$GPGSV_5
$GPGSV_6
Character
Content
Parameter
Location
Offset_Words 45:0 0
1 May 2008 | DST/T/096 581

Getting the most from the TCG/102 GPS antenna
The TCG/102 is a combined GPS and IRIG input module. It The recommended antenna RFE/AEG/001 has an antenna
can accept inputs from a number of sources. gain of 26dB with an antenna noise figure of 2.5dB. A
minimum antenna gain of 10 dB is recommended to
Time Seeding compensate for losses in the cable connecting the antenna to
the TCG/102. ACRA CONTROL recommends a maximum
On power up of the DAU, the TCG/102's timer is seeded with antenna noise figure of 1.5 dB for an antenna with a gain of
time from the real-time clock (provided an external battery is 50dB.
connected and the real-time clock is running). Otherwise, the
module resets and begins counting from day 1, time 0. The The GPS receiver calculates the carrier-to-noise ratio for the
timer then synchronizes with the selected time source (GPS antenna at power on. It is therefore important that the GPS
or IRIG). If there is no input to the time reader, the timer antenna is connected to the module before it is powered on.
continues counting while powered on.
GPS receiver
Primary and secondary inputs The TCG/102 uses a civilian-band (L1) receiver. The United
The TCG/102 accepts time from either an IRIG-B stream or a States Department of Defence (DoD) can turn on Selective
GPS receiver via NMEA messages. Availability at any time without warning. This will degrade the
accuracy of the GPS data.
It is possible to use one time source as the primary input and
optionally enable the other time source as the secondary The TCG/102 can extract time and navigation information
input. If the primary time source becomes unavailable from an NMEA data stream. It is fitted with an onboard
(missing or has errors), then after 10 seconds the TCG/102 receiver but can be interfaced to an external L1 or L2 GPS
will fall back to the secondary source. Later if the primary receiver via the 19-way connector.
source becomes available again then the TCG/102 will switch The NMEA messages GGA, GSV, ZDA, GSA, and GLL are
back to the primary time source after 10 seconds. the minimum required for TCG/102 time synchronisation. The
This allows for synchronization to a secondary IRIG source VTG message is required to get velocity and true heading. If
when an aircraft is in the hanger where GPS is not available; it is not provided then registers VELOCITY_KPH,
then for GPS to be used when the aircraft is on the runway or VELOCITY_KN, HEADING will be forced to an illegal state of
in flight, without reprogramming the KAM-500. all 1's.
If the primary source is GPS then the secondary must be GPS is a broad subject and beyond the scope of this data
IRIG and vice versa. For instance, you cannot use an sheet. There are many online guides and GPS dictionaries
external GPS receiver as the primary time input and use the such as at the following links:
onboard GPS receiver as the secondary. Also because the www.gps.oma.be/gb/dic_gb_ok_css.htm
digital pins are used for more than one function there must be
no pin clash between the primary and secondary input pins. www.colorado.edu/geography/gcraft/notes/gps/gps_f.html
The following table shows available combinations of primary GPS time

and secondary time inputs:
The TCG/102 derives time from data received from a
IRIG constellation of satellites. These satellites are in continuous
moving orbit which affects the behavior of the TCG as
RS422_IN
follows:
TTL_IN
Analog
Acquisition
Along with time and navigation data GPS satellites transmit
GPS ephemeris data and GPS almanac data.
On Board Y Y Y Ephemeris data tells the GPS receiver where each GPS
satellite should be at any time throughout the day. Each
GPS
RS422_IN satellite transmits ephemeris data showing the orbital

Y N N information for that satellite and for every other satellite in the
TTL_PPS
system.
RS232_IN
Y N Y Almanac data is constantly transmitted by each satellite. It
TTL_PPS
contains information about the status of the satellite, current
date and time.
Clock synchronization Cold power up
The TCG/102's timer uses a digital phase locked loop (PLL)
When the receiver is powered up for the first time or has no
to synchronize its own clock to an external time source.
backup battery connected, the receiver has no knowledge of
Frequency and phase error are corrected every second. If the
its last position, approximate time and has no ephemeris or
error is greater than 500 micros seconds, the PLL will jump to
almanac data. The receiver starts to search for signals
the correct time immediately. After that it will track the
blindly. This is normal behavior. Cold power up for GPS
external time source. When the PLL is locked to the external
receivers can take several minutes.
time source, R(3) of the IRIG_STATUS register is set to 1.
This is improved operation over the TCG/102/B.
582 1 May 2008 | DST/T/096

Warm power up hardware supports SBAS, it is currently disabled. Contact
ACRA CONTROL for details.
If the receiver was connected to a backup battery before
powering down, the receiver knows its last position,
approximate time and almanac. The ephemeris data is Grounding the IRIG source
cleared. Because the almanac data is retained it can acquire It is important to ground (GND) the source of the IRIG-B
satellites and get a position fix faster than in cold start mode. stream. If the time source is a single-ended analog signal, the
GND should be connected to the negative IRIG-B input
Reacquisition A_IRIG_IN- (see Figure 5 on page 584).
If the receiver was off for less than two hours with battery
backup, the almanac and ephemeris data are used to acquire X-SYNC operation
satellites. Because the ephemeris data is retained it can The TCG/102 can output an X-SYNC stream on pins 11 and
acquire satellites and get a position fix faster than in other 12 (for synchronization of backplane controller modules)
modes. instead of IRIG time on RS422_OUT. This allows the
TCG/102 to be used to synchronize the acquisition cycle to
Navigational data the start of a second. When X-SYNC is in use some
The TCG/102 may be used to record navigation information. restrictions must be placed on the acquisition cycle
The information provided by the TCG/102 is referenced to a frequency; that is, only the following frequencies are
specific datum. supported: 0.5, 1, 2, 4, 5, 8 10, 16, 20, 25, 32, 40, 50, 64, 80,
100Hz.
Datum
Possible configurations
The internal GPS receiver uses WGS-84, which is a
geographic model obtained by referencing the earth's sea The following diagrams illustrate the different configurations
level surface area and applying theoretical mathematical possible with the TCG/102. In each case the time input
calculations. The chart datum is usually defined in the legend source is illustrated in the top half of the diagram, while the
of the chart. available outputs are shown in the bottom half.
Navigation data accuracy

External GPS SMA
Unlike GPS time the position information is subject to a Receiver
number of inaccuracies, due to the inherent behavior of the (L1/L2)
6 RS422_IN+
GPS system. NMEA $GP MESSAGES
7 RS422_IN-
ONE_PPS
10 TTL_IN
Dilution of Precision (DOP) Digital Ground 9 D_GND
DOP is a function expressing the mathematical uncertainty in Analog IRIG-B Out

4 A_IRIG_OUT
a position fix based on the relative positions of the satellites Analog Tone Out
5 TONE_OUT
used to obtain that position fix. In standard GPS applications 11 RS422_OUT+
there are three types of DOP information available. RS_IRIG-B± or X-SYNC± OUT 12 RS422_OUT-
TTL IRIG-B Out
14 TTL_IRIG_OUT
PDOP: Position (3 coordinates) TTL One or Ten PPS Out
15 TTL_PPS_OUT
Analog Ground
HDOP: Horizontal (2 horizontal coordinates) Digital Ground
3 A_GND
13 D_GND
VDOP: Vertical (height only)
Dilution of precision has a best case value of 1; higher Figure 2: Connected to external GPS receiver using RS-422
numbers indicating a greater uncertainty in the precision of and TTL
the position fix. A low DOP value (2) is considered good, a
high number (>7) is considered poor.
Circular Error Probable (CEP) Active GPS

antenna SMA
CEP is the radius of a circle within which there is a 50%
probability of the antenna being located.
Spherical Error Probable (SEP)

Analog IRIG-B Out
SEP is the three-dimensional analog of CEP, it is the radius of 4 A_IRIG_OUT
Analog Tone Out
5 TONE_OUT
a sphere within which there is a 50% probability of being
11 RS422_OUT+
located. RS_IRIG-B± or X-SYNC± OUT 12 RS422_OUT-
TTL IRIG-B Out
14 TTL_IRIG_OUT
Satellite-based augmentation systems (SBAS) TTL One or Ten PPS Out
15 TTL_PPS_OUT
Digital Ground
9 D_GND
The onboard GPS receiver is capable of receiving additional Analog Ground
GPS corrections from SBAS systems. The US Wide Area 3 A_GND
Digital Ground
Augmentation System (WAAS) is operational, but the 13 D_GND
European Geostationary Navigation Overlay Service
(EGNOS) is not yet out of the test phase. The onboard GPS
receiver cannot detect that EGNOS is in test mode, and this Figure 3: Connected to active GPS antenna
could result in large navigation errors. Therefore, while the
1 May 2008 | DST/T/096 583
External GPS SMA
SMA
Receiver External IRIG-B
(L1/L2) Time Code
NMEA $GP MESSAGES Generator
16 RS232_IN
TTL ONE_PPS 10 TTL_IN
Digital Ground RS_IRIG-B±
6 RS422_IN+
9 D_GND 7 RS422_IN-
Analog IRIG-B Out Digital Ground
4 A_IRIG_OUT 9 D_GND
Analog Tone Out
5 TONE_OUT
Analog IRIG-B Out
11 RS422_OUT+ 4 A_IRIG_OUT
RS_IRIG-B± or X-SYNC± OUT Analog Tone Out
12 RS422_OUT- 5 TONE_OUT
TTL IRIG-B Out 11
14 TTL_IRIG_OUT RS422_OUT+
TTL One or Ten PPS Out RS_IRIG-B± or X-SYNC± OUT
15 TTL_PPS_OUT
12 RS422_OUT-
TTL IRIG-B Out
Analog Ground 14 TTL_IRIG_OUT
3 A_GND TTL One or Ten PPS Out
Digital Ground 15 TTL_PPS_OUT
13 D_GND Analog Ground
3 A_GND
Digital Ground 13 D_GND
Figure 4: Connected to external GPS receiver using RS-232

and TTL Figure 7: Connected to external IRIG Time source using
RS422
SMA
External IRIG-B
Time Code
Generator Analog IRIG-B In
1 A_IRIG_IN+
2 A_IRIG_IN-
3 A_GND
Analog IRIG-B Out

4 A_IRIG_OUT
Analog Tone Out
5 TONE_OUT
11 RS422_OUT+
RS_IRIG-B± or X-SYNC± OUT 12 RS422_OUT-
TTL IRIG-B Out
14 TTL_IRIG_OUT
TTL One or Ten PPS Out
15 TTL_PPS_OUT
Figure 5: Receiving analog IRIG Time
SMA
External IRIG-B
Time Code
Generator
TTL IRIG
10 TTL_IN
Digital Ground
9 D_GND
Analog IRIG-B Out

4 A_IRIG_OUT
Analog Tone Out
5 TONE_OUT
11 RS422_OUT+
RS_IRIG-B± or X-SYNC± OUT 12 RS422_OUT-
TTL IRIG-B Out
14 TTL_IRIG_OUT
TTL One or Ten PPS Out
15 TTL_PPS_OUT
Analog Ground
3 A_GND
Figure 6: Connected to external IRIG source using TTL
584 1 May 2008 | DST/T/096

Connector pinout of the KAM/TCG/102
Figure 8: 19-way DD-type connector plus SMA connector
19-way DD-type connector

1 A_IRIG_IN+ Analog IRIG time inputs Analog IRIG-B time in (AM/PWM); 1kHz carrier
2 A_IRIG_IN- Analog IRIG time inputs Analog IRIG-B time in (AM/PWM); 1kHz carrier
3 A_GND Analog ground
4 A_IRIG_OUT Analog IRIG time outputs Analog IRIG-B time out (AM/PWM); 1kHz carrier
5 TONE_OUT Tone outputs 1kHz sine wave, ±4Vp-p
6 RS422_IN+ RS-422 inputs Either IRIG-B time (PWM) or NMEA data
7 RS422_IN- RS-422 inputs Either IRIG-B time (PWM) or NMEA data
8 RS_IRIG_TERM Termination pin for RS-422 Connect to RS422_IN+ if needed
9 D_GND Digital ground
10 TTL_IN BTTL inputs Either IRIG-B or ONE_PPS in from an external
IRIG/GPS source
11 RS422_OUT+ RS-422 outputs Either IRIG-B or X-SYNC out
12 RS422_OUT- RS-422 outputs Either IRIG-B or X-SYNC out
13 D_GND Digital ground
14 TTL_IRIG_OUT BTTL outputs IRIG-B time out (PWM)
15 TTL_PPS_OUT BTTL outputs One or ten pulses per second
16 RS232_IN RS-232 inputs NMEA-183 stream in from external GPS receiver
17 V_BAT Battery inputs Positive battery input
18 D_GND Digital ground Ground return for battery
19 CHASSIS Chassis KAM-500 chassis connection
SMA connector

Center RF_IN Active antenna inputs Excitation output to active antenna and RF input to
module
Outer shell RF_GND Active antenna inputs RF ground reference; isolated from chassis
www.acracontrol.com
586 1 May 2008 | DST/T/096

KAD/VID/103
A C R A KAM-500 VID/103
Single channel MPEG-4 encoder
C O N T R O L
APPLICATIONS
• Video cockpit monitoring
• Video monitoring of control surfaces
• Direct monitoring of video compatible head/up and
head/down displays
DESCRIPTION
The VID/103 is an MPEG-4 video encoder card that converts
one of three composite analog video inputs, or one Y/C
(S-video) analog video input to digital video and compresses
it. Optional ADPCM audio encoding produces a digital audio
FEATURES data stream. The left and right audio channels can be
• MPEG-4 compression of any one of three composite video individually turned on or off.
input channels, or one Y/C input (NTSC or PAL) The compressed video and audio is placed into an MPEG-2
• Supports digital video input formats: CIF, 2CIF, D1 transport stream that can be distributed through the data
• Configurable I-frame to P-frame ratio (GOP): From all acquisition system and can be recorded within a memory
I-frame to 1800 P-frame per I-frame ratio module such as the MEM/003.
• Programmable frame rates: 1 to 30 frames per second
• ADPCM audio encoding (mono or stereo at 64kbps per The VID/103 offers two generator lock (genlock) outputs to
channel) allow synchronization of all four video input signals. When
• MPEG-4 compressed video and audio data presented in multiple synchronized video signals are connected, the
MPEG-2 transport stream format (ISO/IEC 13818-1) VID/103 can switch between the incoming channels via an
• Configurable video data rate from 64kbps to 10Mbps external switch or KAM-500 format switching.
• Time can be overlaid on the picture in any (x,y) location
• Supports built-in self-test and test picture
• Supports 12 and 16-bit samples
CVBS_0_IN 1
CVBS_1_IN 3
CVBS_2_IN 5
Y_IN 7
Video codec
C_IN 9
CAM_SEL_BIT_0 37
CAM_SEL_BIT_1 38
CAM_SEL_BIT_2 39 MPEG-2 TSF
encoding
CAM_2_GENLOCK_OUT 11 MPEG-4 compression
and audio ADPCM
CAM_3_GENLOCK_OUT 13
13 encoding
AUDIO_RIGHT_IN 15
AUDIO_LEFT_IN 17
13
GND 51
52
VID/103
VID/103 block diagram
29 Jul. 2008 | DST/P/045 587

Selection Paths
Airborne Data Acquisition → KAM-500 → Modules → Video
KAD/VID/103 CON/KAD/002/CP VID/103 module with 52-way double density module top connector
Revision History
VID/103 First release Recommended for new programs
Related Products
Module Details
GTS/VID/001 Hardware MPEG-4 decompression card
GSX/VID/001 GSX-500 driver for GTS/VID/001 decompression card
GSX/VID/002 GSX-500 driver performing software MPEG-4 playback
gVideo Real-time video decompression software
KSMv2 This module is supported in KSMv2 from version 2.2.13 onwards
Document Details
www.acracontrol.com
588 29 Jul. 2008 | DST/P/045

Specifications

Slots – – 2 – The VID/103 occupies two user slots. The input connector is the
connector closest to the KAM-500 controller.
Mass
– 132 – g
Power consumption
+5V 620 – 760 mA
±7V 0 – 0 mA
±12V 0 – 0 mA
Video inputs

Encoded video rate
CVBS_[2:0]_IN 0.064 – 10 Mbps One of three possible composite video inputs.
Y_IN/C_IN 0.064 – 10 Mbps Y_IN/C_IN must be used as a pair.
Video input format – NTSC/ – –
PAL
Input level – 1 – Vrms
Input resistance
each input to GND – 75 – Ω Each input is terminated with a 75Ω impedance matching
resistor.
Audio inputs

Encoded audio rate Each audio channel can optionally be encoded at 64kbps.
AUDIO_LEFT_IN 0 – 64 kbps
AUDIO_RIGHT_IN 0 – 64 kbps
Input level – 1 – Vrms
Input resistance
each input to GND – 11 – kΩ
29 Jul. 2008 | DST/P/045 589

Camera select inputs

Input selection
CAM_SEL_BIT_[2:0] – – – – See “Selecting a camera” on page 593.
Input voltage
operating range 0 – 3.3 V Internally pulled high; can be brought low by connecting to GND.
(see “Getting the most from the VID/103” on page 593.)
logic ‘0’ 0 – 0.8 V
logic ‘1’ 2 – 3.6 V
Input resistance
Video outputs

Outputs – – 2 – Camera synchronization output derived from CVBS_0_IN.
Generator lock outputs
CAM_2_GENLOCK_OUT – – – –
CAM_3_GENLOCK_OUT – – – –
Output level – 1 – Vrms
Output resistance – 75 – Ω AC coupled output with a 75Ω resistor in series for impedance
matching.
590 29 Jul. 2008 | DST/P/045

Setting up the VID/103
acquisition system


The following table lists the setup configurations available for the KAD/VID/103.
Manufacturer -
PartReference KAD/VID/103 KAD/VID/103 ACRA CONTROL part number
Settings - - -
Module-Video-In-1.2 -
Compression -
AlgorithmReference No character limit Not Specified -
1, 5, 15, 30, 45, 90, 180,
GopMode 15 P Frame to I Frame ratio
360, 900, 1800
1, 2, 3, 5, 10, 15, 20, 25,
TemporalDecimation 25 Frames per second
30
Source -
TEST
CVBS_0_IN
MultiplexerSelect CVBS_1_IN CVBS_0_IN Video Source
CVBS_2_IN
YC
PAL
InputFormat PAL -
NTSC
CIF CIF: 352x288 (PAL); 352x240 (NTSC)
Resolution 2CIF CIF 2CIF: 704x288 (PAL); 704x240 (NTSC)
D1 D1: 704x576 (PAL); 704x480 (NTSC)
TransportPackageReference No character limit Not Specified -
Stereo
Left -
AudioSetting Stereo
Right
None
Programmable
InputSelection Programmable -
Pin Selectable
29 Jul. 2008 | DST/P/045 591

TextStyles - - -
TextStyle -
The only text colors supported are black or white, i.e. if
you set Red to 255 you must set Green and Blue to 255,
Color
likewise, if you set Red to 0 you must set Green and
Blue to 0
0
Red 0 -
255
0
Green 0 -
255
0
Blue 0 -
255
Background - - -
If 'Solid' is selected the backgrond color will be the
Solid
inverse of the text color selected
Style Shadow Solid
i.e. If the text color has been set to white, the
None
background will be solid black
Placement -
Top Left
Bottom Left
Top Right
Bottom Right
Position Center Bottom Right -
Center Top
Center Bottom
Center Right
Center Left
Pixel -
Horizontal 720:0 720 -
Vertical 576:0 576 -
The following table lists all parameters that are available for the KAD/VID/103.
Report R(2) BIST passed
Unitless BitVector 16
Module Status R(1) Audio input signal connected
R(0) Video input signal connected
Data
MPEG-2 Video and Audio Unitless BitVector 16 R[15:0] 0000:FFFF (hex)
transport stream data
"/><\.
592 29 Jul. 2008 | DST/P/045

Getting the most from the VID/103 Selecting a camera
The VID/103 consists of two units; a video decoder and a Camera selection can be controlled via software or via the
compression unit. The video decoder supports NTSC and CAM_SEL_BIT_[2:0] input signals on the top connector.
PAL, composite and Y/C input signals. The compression unit When the module is programmed for camera selection via the
is a highly configurable MPEG-4 (Simple Profile) compressor top connector input lines, then the behavior is determined as
to suit various applications. GOP mode can be set to pure listed in the “Camera select test sequence format” table.
I-frame mode only, which allows for real-time and quick loss
recovery, and also supports up to 1800 P-frame per I-frame to Camera select test sequence format
achieve a high compression ratio. Furthermore, digital video
C_SEL_BIT_[2:0] Cabling
resolution and the number of frames per second (temporal
decimation) are programmable. 0 0 0 Test screen
0 0 1 CVBS_0_IN
Compression can be fine tuned for the required application.
For example, reducing the P-frame to I-frame ratio shortens 0 1 0 CVBS_1_IN
the decoding latency and with that improves real-time 0 1 1 CVBS_2_IN
characteristics and loss recovery. Increasing the temporal 1 0 0 Y_IN/C_IN
decimation (fps) makes the appearance of movement more
fluid, but this adds significantly to the output data rate. Only one input can be selected at a time by connecting the
Optional ADPCM audio encoding produces a digital audio CAM_SEL_BIT_[2:0] pin to GND on pin 40. These signals
data stream at 64kbps per channel. The left and right channel are internally pulled high.
can be individually turned on or off. The ADPCM is part of a
private stream of the MPEG-2 transport stream. Connecting to the VID/103
The VID/103 has two genlock outputs to allow Controller module
synchronization of all four incoming video input signals.
When multiple synchronized video signals are connected, the
VID/103 can switch between the incoming channels via an
external switch or KAM-500 format switching.
BCD time can be optionally overlaid onto the picture.
Video data transmission

How data is decoded depends on whether it is transmitted or
recorded via Ethernet UDP packets, or embedded within a
PCM stream from the KAM-500 system.
Each video stream consists of MPEG-2 packets of 376 bytes Module Reserved
(188 words x 2). To ensure minimum delay or latency, read inputs
bursts are never more than 188 samples at a time.
KSM-500 tools use specific rules when generating frames or Figure 2: VID/103 top block in a KAM chassis
packets containing video streams. When generating packets
by hand, imagine that the video parameter samples for each The VID/103 has two 52-way connectors on the top block.
stream are distributed as if from 188 or less parameters of the The connector closest to the controller in the chassis is the
same sample rate. analog input connector for video signals. The 52-way digital
connector is an interface for programming and debug. The
If a sample from a particular video stream must appear 500
“Connector pinout of the KAD/VID/103” on page 594 shows
times in a PCM frame, consisting of 10 minor frames, then it
the analog pinout for connecting to a video source.
can be placed in many ways. For example, it can be placed in
the location of one parameter with a 50:1 super-commutation,
in the locations of 50 parameters with 1:1 commutation or
Optimal configuration
100 parameters with a 1:2 sub-commutation. The video Contact ACRA CONTROL to determine the optimal
stream should not be placed in the locations of 250 configuration for specific setups. The following settings are
parameters at a 1:5 sub-commutation as this exceeds the guidelines for optimal operation.
188-word limit.
VID/103 optimal settings
When building Ethernet packets, ensure that the video
samples occur not more than 188 times in a single packet. A Resolution Frame Rate MPEG-4 Bit Rate
video stream sampled at 125ksps (2Mbps) can be packed as Min./Max.
1000 packets per second each containing 125 samples. CIF 1 64K/100K
If a video stream is going to more than one destination, such CIF 15 750K/1.0M
as a memory card, PCM encoder or Ethernet transmitter, CIF 30 1.0M/1.5M
then all samples must go to all destinations. For example, a 2CIF 15 1.0M/1.5M
particular video stream can not be logged to a recorder (such
2CIF 30 2.0M/2.5M
as a MEM/003) at 100ksps and transmitted via Ethernet at
200ksps. Similarly, if transmitting 16-bit samples in the D1 15 2.0M/2.5M
Ethernet packet, 16-bit samples must also be transmitted in D1 30 4.0M/4.5M
the PCM stream.
29 Jul. 2008 | DST/P/045 593

Connector pinout of the KAD/VID/1031
1 CVBS_0_IN Video inputs Composite video input channel 0
2 NC Not connected
4 NC Not connected
6 NC Not connected
7 Y_IN Video inputs Component video input (luminance)
8 NC Not connected
9 C_IN Video inputs Component video input (chrominance)
10 NC Not connected
11 CAM_2_GENLOCK_OUT Video outputs Synchronization output
12 NC Not connected
13 CAM_3_GENLOCK_OUT Video outputs Synchronization output
14 NC Not connected
15 AUDIO_RIGHT_IN Audio inputs Audio input signal
16 NC Not connected
17 AUDIO_LEFT_IN Audio inputs Audio input signal
18 GND
19 NC Not connected
20 GND
21 NC Not connected
22 GND
23 NC Not connected
24 GND
25 NC Not connected
26 GND
27 NC Not connected
28 GND
29 NC Not connected
30 GND
31 NC Not connected
32 GND
33 NC Not connected
34 GND
35 NC Not connected
36 GND
37 CAM_SEL_BIT_0 Camera select inputs Internally pulled high
40 GND
41 NC Not connected
42 NC Not connected
43 NC Not connected
44 NC Not connected
45 NC Not connected
48 NC Not connected
1. This pinout is for the connector that is closest to the controller module in the DAU.
www.acracontrol.com
594 29 Jul. 2008 | DST/P/045

ACRA Accessories and spares
C O N T R O L
595
ACD/BAC/002
A C R A KAM-500 ACD/BAC/002
Electroless nickel-plated aluminum straight-through backshell for KAD connectors
C O N T R O L
DESCRIPTION
The ACD/BAC/002 is an electroless nickel-plated, aluminum
backshell for use with KAD module double-density mating
connectors.
The part is supplied with two pre-assembled, 4-40 UNC,
stainless steel mating screws (ACD/SCW/004) each held in
place by a stainless steel retaining clip (ACD/CLP/003).
FEATURES
• For use with KAD (double-density) mating connectors
APPLICATIONS
• Use with cables and mating connectors
ACD/BAC/002 mechanical drawing
23 Jan. 2008 | DST/R/010 597

Selection Paths
Airborne Data Acquisition → KAM-500 → Accessories
ACD/BAC/002 Electroless nickel-plated aluminum straight-through backshell for use with KAD connectors
Revision History
ACD/BAC/002 First release Recommended for new programs
Related Products
Module Details
Offset 4mm screw- ACRA CONTROL recommends using an offset 4mm screwdriver, P/N: 20740 from WIHA with the
driver ACD/BAC/002. Contact ACRA CONTROL for details.
ACD/BAC/003 Electroless nickel-plated aluminum 30° double density backshell for use with KAD connectors
Document Details
www.acracontrol.com
598 23 Jan. 2008 | DST/R/010

Specifications
Mass
backshell, screw and clip – 15 – g
backshell, screw and clip – 0.52 – oz Design metric is grams.
bend radius – 48.4 – mm 19mm bundle, 26 AWG, 35mm bend radius.
bend radius – 1.9 – in. 0.75in. bundle, 26 AWG, 1.37in. bend radius.
Dimensions
backshell height – 45 – mm
backshell height – 1.77 – in. Design metric is millimeters.
backshell length – 52.78 – mm
backshell length – 2.07 – in.
backshell width – 12.8 – mm
backshell width – 0.50 – in.
screw length – 3.51 – mm Length of threaded insert.
screw length – 0.13 – in. Length of threaded insert.
width of clip – 6.35 – mm
width of clip – 0.24 – in.
Finish
backshell – – – – Electroless nickel plated aluminium.
screw – – – – Stainless steel.
clip – – – – Stainless steel.

ACD/BAC/002
When fitting the ACD/BAC/002, note that the wires/pins must
be threaded through the backshell before the pins are
inserted into the connector shell.
In order to fit the backshell into the KAD connector, the 6. Position the retaining clips over the edges of the side
following procedure should be followed: flanges.
1. Remove the screws (ACD/SCW/003) and retaining clips
(ACD/CLP/002) from the KAD connector to which the
backshell is to be attached. These are no longer needed
as the screw/clip (ACD/SCW/004 and ACD/CLP/003) on
the backshell will be used when the backshell is
assembled onto the KAD connector.
2. Thread the wires/pins to be inserted into the KAD
connector through the backshell.
3. Unscrew the mating screws and retaining clips from the

ACD/BAC/002.
7. Insert the mating screws into the retaining clip and screw
through the combined backshell and connector.
8. Wires can be secured by closing the “clamp-bar”
mechanism on the backshell.
4. Insert the crimped pins into the KAD connector (see the
CON/KAD/002/CP data sheet for details).
5. Join the backshell and KAD connector.
23 Jan. 2008 | DST/R/010 599

The typical bend radius to be expected from using the ACD/BAC/002 is shown below.
Figure 2: ACD/BAC/002 bend radius
www.acracontrol.com
600 23 Jan. 2008 | DST/R/010

ACD/BAC/003
Electroless nickel-plated aluminum 30° double density backshell for KAD connectors
C O N T R O L
DESCRIPTION
backshell for use with KAD module double-density mating
connectors.
The part is supplied with two pre-assembled, 4-40 UNC,
place by a stainless steel retaining clip (ACD/CLP/003).
FEATURES
• For use with KAD (double-density) mating connectors
APPLICATIONS
• Use with cables and mating connectors
17.5
0
PLAN VIEW WITH CLAMP BARS

.35
SCREWS AND HARDWARE OMITTED

11
2.5
7.6
5.5
HARDWARE OMITTED
IN THIS VIEW
5.0
41 MAX
25.4
LEGIBLY AND INDELIBLY MARK AS SHOWN

30°
NO OTHER MARKING TO BE APPLIED

ACD/BAC/003
12.85 47.04
52.78
23 Jan. 2008 | DST/R/011 601

Selection Paths
Airborne Data Acquisition → KAM-500 →Accessories
ACD/BAC/003 Electroless nickel-plated aluminum 30° double density backshell for use with KAD connectors
Revision History
Related Products
Module Details
Offset 4mm screw- ACRA CONTROL recommend using the offset 4mm screwdriver, P/N: 20740 from WIHA with the
driver ACD/BAC/003. Contact ACRA CONTROL for details.
Document Details
www.acracontrol.com
602 23 Jan. 2008 | DST/R/011

Specifications
Mass
bend radius – 47 – mm 19mm bundle, 26 AWG, 35mm bend radius.
bend radius – 1.85 – in. 0.75in bundle, 26 AWG, 1.37in. bend radius.
Dimensions
Finish

ACD/BAC/003
backshell is to be attached. These are no longer needed
the backshell will be used when the backshell is
assembled onto the KAD connector.
2. Thread the wires/pins to be inserted into the KAD
connector through the backshell.

ACD/BAC/003.
8. Wires can be secured by closing the “clamp-bar”
mechanism on the backshell.
23 Jan. 2008 | DST/R/011 603

www.acracontrol.com
604 23 Jan. 2008 | DST/R/011

ACD/BAC/004
C O N T R O L Electroless nickel-plated aluminum double-density backshell for CON/KAD/003/CP
DESCRIPTION
backshell for use with CON/KAD/003/CP mating connectors.
The part is supplied with two pre-assembled, 4-40 UNC
place by stainless steel retaining clip (ACD/CLP/003).
FEATURES
• For use with CON/KAD/003/CP
APPLICATIONS
• Use with cables and mating connector, CON/KAD/003/CP
17 Jan. 2008 | DST/S/043 605

Selection Paths
ACD/BAC/004 Electroless nickel-plated aluminum double-density backshell for use with CON/KAD/003/CP
Revision History
Related Products
Module Details
CON/KAD/003/CP 19-way double-density mating connector
ACD/BAC/003 Electroless nickel-plated aluminum 30° double-density backshell for use with KAD connectors
TCG/102 Combined GPS and IRIG input module
Document Details
www.acracontrol.com
606 17 Jan. 2008 | DST/S/043

Specifications
Mass
bend radius – 48.4 – mm 19mm bundle, 26 AWG, 35mm bend radius.
bend radius – 1.9 – in. 0.75in. bundle, 26 AWG, 1.37in. bend radius.
Dimensions
Finish

ACD/BAC/004
backshell is to be attached. These are no longer needed,
the backshell will be used when the backshell is assem-
bled onto the KAD connector.
2. Thread the wires/pins to be inserted into the KAD con-
nector through the backshell.

ACD/BAC/004.
8. Wires can be secured by closing the “clamp-bar” mecha-
nism on the backshell.
17 Jan. 2008 | DST/S/043 607

ACD/BAC/004
www.acracontrol.com
608 17 Jan. 2008 | DST/S/043

ACD/CJB/001
A C R A KAM-500 ACD/CJB/001
15 channel reference junction block for thermocouples
C O N T R O L
DESCRIPTION
The ACD/CJB/001 is designed to be used with the ADC/003
and is used to terminate up to 15 thermocouples at a
measured temperature.
Each thermocouple has a dual terminal with screws in three
rows of five. The block also includes a sensor with a 12mV/°K
output which is used by the ADC/003 for reference junction
compensation.
FEATURES
• 15 screw junctions for thermocouple (T/C) leads
• Numbered terminals
• Built in temperature reference (12mV/°K)
APPLICATIONS
• Use to terminate thermocouples
To ADC/003/B
First of 15 TC inputs on the ACD/CJB/001
23 Jan. 2008 | DST/P/014 609

Selection Paths
ACD/CJB/001 Thermocouple terminator with 52-way double density mating connector
ACM/CJB/001 Thermocouple terminator with 51-way micro-miniature mating connector
Revision History
ACD/CJB/001 First release Recommended for new programs
Related Products
Module Details
ADC/003 15 channel thermocouple A/D converter with reference compensation
Document Details
www.acracontrol.com
610 23 Jan. 2008 | DST/P/014

Specifications
Channels: 15 plus reference junction
Reference junction: Supply 12V (from ADC/003)

Output 12mV/°K (accuracy ±1.5°K)
Figure 2: ACD/CJB/001 mechanical drawing
Getting the most from the ACD/CJB/001

An ACD/CJB/001 can be mounted at each end of a KAM-500 chassis by removing four screws in the end plate.
23 Jan. 2008 | DST/P/014 611

www.acracontrol.com
612 23 Jan. 2008 | DST/P/014

ACC/TRF/001
A C R A KAM-500 ACC/TRF/001 6-channel power transformer

C O N T R O L
DESCRIPTION
The unit is used to condition 115VAC RMS, 400Hz aircraft
supplies to a voltage level suitable for input to the ACRA
CONTROL three-phase power monitor module, ADC/008.
The unit is capable of accepting and producing outputs for up
to six channels.
FEATURES
• Six transformer-coupled channels
• Rugged aluminum casing
• Designed for use with the ADC/008
APPLICATIONS
• Monitoring of aircraft power supplies
1 2
J1 J3
2 3
ACC/TRF/001
First of six independent transformer channels
21 Jan. 2008 | DST/L/057 613

Selection Paths
ACC/TRF/001 6-channel power transformer
Revision History
ACC/TRF/001 First release Recommended for new programs
Related Products
Module Details
ADC/008 Three-phase power monitor module
Document Details
TEC/NOT/037 Using the ADC/008
www.acracontrol.com
614 21 Jan. 2008 | DST/L/057

SPECIFICATIONS
The unit contains six transformers (one per channel) to condition each channel as follows:
Input signal 115VAC RMS (163Vpeak), 400Hz
Transformation ratio 19.6 : 1 ± 5%
Input protection Each input fused at 100mA primary current
94.00
86.00
118.00
All dimensions shown in 'mm'.

Tolerance ±2mm on last signicant digit
except where otherwise stated.
J1
J3
(3.90)
4.00
60.00
80.00
J2 NOT TO SCALE
7.50 5.40
(7.40) (5.50)
Figure 2: ACC/TRF/001 mechanical drawing
Getting the most from the ACC/TRF/001 J1

At least 80mm (3.14in.) clearance is required at the top of the
Pin Name I/O Comment
unit for connectors and cables.
1 Phase 1 In Goes to voltage 0 on ADC/008
2 Neutral In Goes to voltage 0 on ADC/008
Connector pinout of ACC/TRF/001 3 Phase 2 In Goes to voltage 0 on ADC/008
1
5 6 Neutral In Goes to voltage 0 on ADC/008
6 2
J2
4
3 Pin Name I/O Comment

Figure 3: Pinout for J1 and J2 4 Neutral In Goes to voltage 0 on ADC/008
Mating Connector: Amphenol MS27484E 8A 35SA
21 Jan. 2008 | DST/L/057 615

1 14
2 13
15 12
3
16 21
11
4 17 22
20
10
5 18 19
9
6 8
7
Figure 4: Pinout for J3
Mating Connector: Amphenol MS27484E 12A 22P
J3
Pin Name I/O Comment

1 DNC Out Do not connect
2 Ch. 1+ Out
3 Ch. 1- Out Goes to ground pin 2 on the ADC/008
4 Ch. 2+ Out
5 Ch. 2- Out
6 Ch. 3+ Out
7 Ch. 3- Out
8 DNC Out
9 Ch. 4+ Out
10 Ch. 4- Out
11 Ch. 5+ Out
12 Ch. 5- Out
13 Ch. 6+ Out
14 Ch. 6- Out
www.acracontrol.com
616 21 Jan. 2008 | DST/L/057

ACC/HSK/001/03U, ACC/HSK/001/06U
ACC/HSK/001/09U, ACC/HSK/001/13U
A C R A KAM-500 ACC/HSK/001
C O N T R O L Optional heat sinks for the KAM-500 system
DESCRIPTION
Although the KAM-500 system is power efficient and is
designed to operate at chassis temperatures of up to 85°C,
heat sinks are recommended for all applications where space
permits. One or two heat sinks can be attached to each
chassis.
• ACC/HSK/001/03U is designed for the 3-user-slot chassis
CHS/03U
CHS/06U
FEATURES CHS/09U
• ACC/HSK/001/013U is designed for the 13-user-slot
• Black fins for maximum radiation/convection
chassis CHS/13U
• Comes complete with mounting screws
• Compact
APPLICATIONS
• Chassis heat sink
Width
Length
Height
ACC/HSK/001/03U ACC/HSK/001/06U ACC/HSK/001/09U ACC/HSK/001/13U
23 Jan. 2008 | DST/J/064 617

Selection Paths
Part Number Mounting screw Description
ACC/HSK/001/03U ACC/SCW/001 One or two ACC/HSK/001/03U heat sinks are recommended with each
CHS/03U. Four ACC/SCW/001 are required for each heat sink.
CHS/06U. Four ACC/SCW/001 are required for each heat sink.
CHS/09U. Six ACC/SCW/001 are required for each heat sink.
CHS/13U. Six ACC/SCW/001 are required for each heat sink.
The heat sinks have no ordering options. The heat sinks are recommended where space permits but must be ordered sepa-
rately. By default, the correct number of mounting screws for the heat sinks ordered is included in the shipment. The part num-
ber and quantity will be added to the Confirmation of Order.
Adding a heat sink does not affect the length or height of the KAM-500 chassis but does increase the width by 15mm (0.59in.).
Adding two heat sinks (one on each side) increases the width by 30mm (1.18in.).
Revision History
ACC/HSK/001/03U First release Recommended for new programs
Document Details
www.acracontrol.com
618 23 Jan. 2008 | DST/J/064

Specifications
ACC/HSK/001/03U mechanical specifications

Dimensions
height – 75 – mm
height – 2.95 – in. Design metric is millimeters.
length – 125 – mm
width – 15 – mm
width – 0.59 – in.
Mass
– 140 – g
Finish – – – – Black anodized.

Dimensions
width – 15 – mm
width – 0.59 – in.
Mass
– 195 – g

Dimensions
width – 15 – mm
width – 0.59 – in.
Mass
– 250 – g
23 Jan. 2008 | DST/J/064 619

Dimensions
width – 15 – mm
width – 0.59 – in.
Mass
– 340 – g
www.acracontrol.com
620 23 Jan. 2008 | DST/J/064

ACM/EXT/001/B
A C R A KAM-500 ACM/EXT/001
Extender board for the KAM-500 system
C O N T R O L
DESCRIPTION
The ACM/EXT/001 is used to extend the KAM-500 backplane
so that user-modules can operate external to (above) the
KAM-500 chassis. This card is intended as a debug tool for
customers developing their own KAM-500 user-modules.
The ACM/EXT/001 is for bench testing use only, and can only
be inserted in user-slots. It cannot be used in controller-slot
J2.
FEATURES
• All backplane lines are extended
• LED-indicated power on
APPLICATIONS
• Allows modules to operate above the chassis during bench
testing
23 Jan. 2008 | DST/K/003 621

Selection Paths
ACM/EXT/001/B Extender board for the KAM-500 system
Revision History
ACM/EXT/001/B First release Recommended for new programs
Document Details
Dimensions
width 1.4 1.5 1.6 mm
width 0.05 0.05 0.06 in.
Mass
– 38 – g
www.acracontrol.com
622 23 Jan. 2008 | DST/K/003

ACC/ASY, ACC/CON, CON/DEC
CON/KAD, ASD/MSB, CON/PSU
A C R A KAM-500 Cables
C O N T R O L Standard cables used for KAM-500 system assembly
DESCRIPTION
The connectors and cables are designed to mate with
standard ACRA CONTROL KAM-500 modules.
The cables are not twisted or shielded as standard but it is
strongly recommended that cables be twisted and shielded
for use in a system. Contact ACRA CONTROL for details.
Use recommended tools (see the KIT/001 data sheet) for
working with either KAM or KAD connectors.
The use of third-party double-density mating connectors on
KAD acquisition modules, apart from those approved by
ACRA CONTROL, may result in damage to the mating
FEATURES connector and to the double-density connector on the KAD
• Connector for MIL-STD-1553 module acquisition module. Such damage would incur out of warranty
• Connector for PC card programmer/decoder repair costs.
• Connector for power supply modules
• Single connector for all acquisition modules
• Multiple second sources
• Wire type is MIL-W-16878/4 seven strand
APPLICATIONS
• Assembling data acquisition systems
ACC/ASY/022
ACC/CON/012
CON/PSU/007/FL/100
ACC/CON/009 CON/DEC/001/B
ACRA CONTROL cables
25 Feb. 2009 | DST/J/062 623

Selection Paths
Contact ACRA CONTROL for details concerning special looms, non-standard lengths and terminating connectors.
Part Number Connector Description
ACC/ASY/007/04 9-way micro-miniature PSU/003, PSU/009, PSU/011, and MKM/PSU/001 interface cable
ACC/ASY/021/04 51-way micro-miniature KAM controller module interface cable
ACC/ASY/022 52-way double-density KAD controller module interface cable
ACC/ASY/023 52-way double-density KAD Ethernet controller module interface crossover cable
ACC/CON/008/04 51-way micro-miniature Mating connector for all acquisition modules
ACC/CON/009 51-way micro-miniature KAM MIL-STD-1553 interface cable for monitoring applications with
direct coupling
ACC/CON/029 51-way micro-miniature KAM MIL-STD-1553 interface cable for monitoring applications with
transformer coupling
ACC/CON/020/B 15-way commercial 15-way LAN open to standard 15-way commercial D-type plug
D-type connector cable to interface to the SAM/DEC module
ACC/CON/012 15-way commercial Standard KAM-500 RS-422 programming/data cable, including

D-type termination resistors for the programming lines. The TTL lines are not
connected.
ACC/CON/031/B 52-way double-density JIG/UNI/001/C interface cable
ASD/MSB/001/DC 52-way double-density KAD MIL-STD-1553 interface cable for monitoring applications with
direct coupling
ASD/MSB/001/TC 52-way double-density KAM MIL-STD-1553 interface cable for monitoring applications with
transformer coupling
CON/DEC/001/B 15-way Commercial ACC/CON/012 combined with ACC/CON/020/B cable assemblies

D-type
CON/PSU/007/FL/100 4mm (0.15in.) banana PSU/007 and PSU/012 interface cable

plugs
CON/PSU/007/FL/300 4mm (0.15in.) banana Extended PSU/007 and PSU/012 interface cable
plugs
Related Products
Module Details
CON/KAD/002/CP This is a 52-way double-density mating connector for all KAD acquisition modules with 52 loose
piece crimp pin contacts. Maximum wire size is 24 AWG 1.0mm (0.0397in.) insulation thickness.
CON/KAD/002/SR 52-way double-density connector with 52-piece crimp pin contacts, modified to accommodate the
sensor to the module, without a grommet.
www.acracontrol.com
624 25 Feb. 2009 | DST/J/062

Specifications
ACC/ASY/007/04

Chassis clearance – – – –
Color coding on flying – – – – MIL-STD-681.
leads
Wire type on flying leads 26 AWG PTFE multi-core wire.
flying leads length – 45 – cm
flying leads length – 18 – in. Design metric is millimeters.
Terminator – – – – Terminated at remote end with 4mm (0.15in.) banana plugs.
ACC/ASY/021/04

leads
Terminator – – – – Terminated at remote end with 15-way standard D type.
ACC/ASY/021/10

leads
ACC/ASY/021/20

leads
Wire type on flying leads
ACC/ASY/022

Chassis clearance – – – – See the CON/KAD/002/CP data sheet.
Color coding on flying – – – – MIL-STD-681 and covered with orange sleeving.
leads
25 Feb. 2009 | DST/J/062 625

ACC/ASY/023

Color coding on flying – – – – TIA/EIA 568-B2.
leads
Wire type on flying leads 24 AWG CAT 5E.
Terminator – – – – Terminated at remote end with standard RJ-45 socket
(crossover).
ACC/CON/008/04

leads
Terminator – – – – Not terminated at remote end.
ACC/CON/008/10

leads
ACC/CON/008/20

leads
ACC/CON/009

Color coding on flying – – – –
leads
Wire type on flying leads Each lead contains a twisted pair that is shielded (to the shell);
the shield is connected to pin 22 for Bus 0 and pin 32 for Bus 1
(GND).
Terminator – – – – RG59 TNC 75Ω connectors.
626 25 Feb. 2009 | DST/J/062

ACC/CON/029

leads
(GND).
Terminator – – – – RG59 TNC 75Ω connectors.
ACC/CON/020/B

leads
flying leads length – 17.78 – cm
ACC/CON/012

leads
ACC/CON/031/B

Color coding on flying – – – – MIL-STD-681 and covered with orange sleeving.
leads
Wire type on flying leads 26 AWG multi-core wire.
ASD/MSB/001/DC

leads
(GND).
Terminator – – – – Terminated at remote end with two twinax connectors.
25 Feb. 2009 | DST/J/062 627

ASD/MSB/001/TC

leads
(GND).
Terminator – – – – Terminated at remote end with two twinax connectors.
CON/DEC/001/B

leads
Terminator – – – –
CON/PSU/007/FL/100

leads
CON/PSU/007/FL/300

leads
www.acracontrol.com
628 25 Feb. 2009 | DST/J/062

DRE/CFM/002/3GB, DRE/CFM/002/4GB,
DRE/CFM/002/6GB, DRE/CFM/002/12GB,
DRE/CFM/002/24GB
A C R A KAM-500 DRE/CFM/002
MEM/003 and MEM/103 compatible CompactFlash® cards
C O N T R O L
DESCRIPTION
CompactFlash cards are removable mass storage devices
used in a KAM-500 system, with a MEM/003 or a MEM/103
interface module. The MEM module controls data storage to
the CompactFlash card. Card data is read and erased using
a standard PCMCIA or USB CompactFlash card reader.
On shipment, the CompactFlash card is formatted and
initialized with the ACRA CONTROL file structure format. The
card should be re-initialized before use.
To re-initialize the card, use the ACRA CONTROL flashcard
tool kFlashCardXID, provided with KSM-500.
FEATURES
Any subset of parameters available over the KAM-500
• KAM-500 compatible, removable solid-state memory cards
backplane can be stored to the CompactFlash card via the
• Programmable data capture from KAM-500 system when MEM module. The MEM module controls selection of the
installed in a MEM/003 or MEM/103 module
stored parameters and associated triggering conditions.
• Card data can be read and/or erased using a commercial
off-the-shelf CompactFlash card reader Logged data stored on the CompactFlash card can be
queried, extracted and converted using kFlashCardXID
APPLICATIONS software.
• Standalone data logging
5 Jan. 2009 | DST/R/023 629

Selection Paths
Airborne Data Acquisition → KAM-500 → CompactFlash® cards
DRE/CFM/002/3GB 3GB Type I CompactFlash card, compatible with MEM/003/B, MEM/003/C, MEM/003/D and
MEM/003/E
DRE/CFM/002/4GB 4GB Type I CompactFlash card, compatible with MEM/003/B, MEM/003/C, MEM/003/D,
MEM/003/E and MEM/103
DRE/CFM/002/6GB 6GB Type II CompactFlash card, compatible with MEM/003/C, MEM/003/D, MEM/003/E and
MEM/103
DRE/CFM/002/12GB 12GB Type II CompactFlash card, compatible with MEM/003/D, MEM/003/E and MEM/103
DRE/CFM/002/24GB 24GB Type II CompactFlash card, compatible with MEM/003/D, MEM/003/E and MEM/103
Revision History
DRE/CFM/002 First release Recommended for new programs
Related Products
Module Details
MEM/103 KAM-500 series 100 CompactFlash® memory module
MEM/003 KAM-500 high speed CompactFlash® memory module
kFlashCardXID Utility to extract data form the CompactFlash card
KSMv2 This module is supported by the KSMv2 software
Document Details
TEC/NOT/039 Using the MEM/003
www.acracontrol.com
630 5 Jan. 2009 | DST/R/023

Specifications
CompactFlash specifications

Slots – – 1 – Each MEM/003 supports one CompactFlash card.
Mass
Type I – 14 – g
Type I – 0.49 – oz Design metric is grams.
Type II – 20 – g
Type II – 0.70 – oz
Dimensions – – – – CompactFlash cards compliant with CompactFlash
specifications required for Type I & Type II CompactFlash cards.
Available memory
DRE/CFM/002/3GB – 2.88 – GB
DRE/CFM/002/4GB – 3.82 – GB
DRE/CFM/002/6GB – 5.76 – GB
DRE/CFM/002/12GB – 11.6 – GB
DRE/CFM/002/24GB – 22.8 – GB
Memory type
DRE/CFM/002/3GB – – – – PCMCIA 7.0 CompactFlash Type I.
DRE/CFM/002/4GB – – – – PCMCIA 7.0 CompactFlash Type I.
DRE/CFM/002/6GB – – – – PCMCIA 7.0 CompactFlash Type II.
MEM/003 Sampling rate1
DRE/CFM/002/3GB – – 1 Msps
DRE/CFM/002/4GB – – 650 ksps
DRE/CFM/002/12GB – – 650 ksps
DRE/CFM/002/24GB – – 1 Msps See “Using the DRE/CFM/002/24GB with MEM/003 modules”
on page 632.
MEM/103 Sampling rate1
DRE/CFM/002/3GB – – – Msps DRE/CFM/002/3GB is not recommended for use with the
MEM/103.
DRE/CFM/002/24GB – – 2 Msps See “Using the DRE/CFM/002/24GB with MEM/003 modules”
on page 632.
Erase time Data extracted using kFlashcardXID 1.3 running on PC with
Intel® Pentium® 4, 2.8GHz, 576MB RAM and Windows®
XP/SP2. GTS/MCI/001 connected to the PC via USB 2.0.
DRE/CFM/002/3GB – 19 – min.
DRE/CFM/002/12GB – 75 – min.
DRE/CFM/002/24GB – 140 – min.
Data retention time1 – 10 – yrs
Erase cycles1 – 100 – k Typically.
Warm up time1 – 1 – s Typically.
1. Not individually tested on each CompactFlash card shipped.
5 Jan. 2009 | DST/R/023 631

Getting the most from CompactFlash continuing to fill to 100% of its capacity to 1M samples per
cards second. This is due to the internal architecture of this
CompactFlash card.
When used with the MEM/003 the CompactFlash card must
be formatted as a FAT32 device; PCs with Windows NT, 2000 The CompactFlash card can be filled to 100% of its capacity
or XP operating systems support this formatting. The FAT with no data loss at sample rates of 450 Ksamples or less.
table reduces the amount of memory available.
Using the DRE/CFM/002/24GB with
The erase and data extraction times are dependant on the
MEM/103 modules
CompactFlash reader and computer operating system used.
The MEM/103 can record data at up to 2M samples per
Storage overview second to the DRE/CFM/002/24GB. However, it adjusts the
size of the CompactFlash card and the fill-level indication so
Data is stored contiguously on the CompactFlash card in the that the CompactFlash card appears to be full. This prevents
order in which it is written to the CompactFlash card by the errors and lost data, but means that the data is not recorded
MEM/003. To successfully retrieve this data, the order in to the last 2% of the CompactFlash card.
which this data was written to the CompactFlash card must
be recorded when the KAM-500 system is being
programmed. KSM-500 software stores this information in a Connector pinout of CompactFlash cards
sampling "strategy" file (default name "strategy.txt"). This The CompactFlash cards are fully compatible with the
strategy file is unique to a specific configuration and changing PCMCIA 7.0 standard.
the configuration of the KAM-500 system in any way
(adding/removing modules or chassis, changing parameters,
changing data rates) will result in a new strategy file being
generated when the KAM-500 system is reprogrammed. The
strategy file for the specific configuration with which the data
was logged must be used when extracting data.
CompactFlash card initialization

On shipment, the CompactFlash card is formatted and
initialized with the ACRA CONTROL file structure format. Use
kFlashCardXID to re-initialize the card.
ACRA CONTROL recommends programming the system into
which the CompactFlash card is to be fitted before initializing
the CompactFlash card.
This is so that the strategy file for the configuration can be
saved onto the CompactFlash card when it is being
initialized. See the kFlashCardXID data sheet for more
information.
Logging data
Any subset of parameters available over the KAM-500
backplane can be stored to the CompactFlash card using the
MEM/003 module. The MEM/003 module controls selection
of the stored parameters and associated triggering
conditions.
Reading data
Data logged by MEM/003 modules must be read using
kFlashCardXID. The kFlashCardXID software tool queries,
extracts and converts the logged data stored on the
CompactFlash card. See the kFlashCardXID data sheet for
more information.
Using the DRE/CFM/002/24GB with

MEM/003 modules
The MEM/003 can record data at up to 1M samples per
second to the DRE/CFM/002/24GB for up to 97.9% of its
storage capacity. At this point, the CompactFlash card slows
down and looses approximately 60ms of data before
www.acracontrol.com
632 5 Jan. 2009 | DST/R/023

KAM/DMY/001
A C R A KAM-500 DMY/001
Dummy module for empty KAM-500 chassis user-slot
C O N T R O L
DESCRIPTION
The DMY/001 is a dummy module intended for occupying an
empty user-slot in a KAM-500 chassis.
FEATURES
• Dummy module for empty user-slot in chassis
• Includes blank top-block, lid and backplane connector
APPLICATIONS
• Occupying empty user-slot in chassis
23 Jan. 2008 | DST/U/002 633

Selection Paths
KAM/DMY/001 Dummy module for empty KAM-500 chassis user-slot
Revision History
DMY/001 First release Recommended for new programs
Related Products
Module Details
-- --
Document Details
Specifications

Mass
– 48 – g
www.acracontrol.com
634 23 Jan. 2008 | DST/U/002

JIG/UNI/001/C
A C R A KAM-500 JIG/UNI/001
Universal test jig for KAM-500 modules
C O N T R O L
DESCRIPTION
The JIG/UNI/001 is a universal test jig for KAM-500 modules.
It is designed so that each of the 50 functional pins, plus
ground are exposed. There is a three-way switch which can
connect each of the 50 functional pins to an isolated 2mm
banana connection, the plus side of the test signal bus or the
minus side of the bus.
The test jig can be used as a break-out box for insertion into
existing wiring looms.
FEATURES
• Universal jig supports all KAM 500 modules that have
52-way double density or 51-way micro-miniature
connectors
• External two-wire test signal bus connection by 3 x BNC or
4 x 4mm banana connectors
• The 50 functional module pins each have three-way switch
to: isolated 2mm banana connector, test signal bus and or
test signal bus minus
• Switches negate the need for external jumper wires for
connection to test signals or outputs
• Monitoring of test signal bus possible due to multiple
access points
• PCB designed to minimize RF pickup
APPLICATIONS
• Break-out box for insertion into existing wiring looms
S1 - 2mm banana
Pin 1
Bus +
Bus -
Bus in + 4mm banana
S50 - 2mm banana
Port 1
Bus in - 4mm banana
50 pin D type Pin 50
Bus out + 4mm banana
Bus +
Bus out - 4mm banana
Bus -
BNC C
Port 2 B+ GND
50 pin D type B- GND
BNC B
GND A 2mm banana
GND C 2mm banana
BNC A
GND B 4mm banana
JIG/UNI/001
Ports 1 and 2 of the JIG/UNI/001
21 Oct. 2008 | DST/R/048 635

Selection Paths
JIG/UNI/001/C Universal test jig for KAM-500 modules
Revision History
JIG/UNI/001/C First release Recommended for new programs
Related Products
Module Details
ACC/CON/031/B 52-way male double density to 50-way D Type (plus 2 x 2mm banana for KAM-500 GND and
chassis)
ACC/CON/019 51-way male to 50-way D Type (plus 1 x 2mm banana for KAM-500 GND)
Document Details
Specifications
Maximum current per pin: 100mA
Switch life: 5000 operations
Getting the most from the JIG/UNI/001

The test signal bus can be used as an input or an output. If the negative side of the signal test bus is used as a ground, this may
be connected to JIG/UNI/001 ground via a switch on the JIG/UNI/001.
To ground all pins, switch the signal bus+ to ground, switch the signal bus- to ground and switch each of the 50 pins to bus+ or
bus-. Care should be taken not to connect excitations to outputs when switching.
One ACC/CON/031/B mating cable assembly is supplied with the JIG/UNI/001.
www.acracontrol.com
636 21 Oct. 2008 | DST/R/048

CON/KAD/002/CP
A C R A KAM-500 CON/KAD/002/CP
C O N T R O L 52-way double-density KAD module mating connector
DESCRIPTION
The CON/KAD/002/CP is a 52-way double-density connector
for use with all KAM-500 KAD modules (except the
TDC/002).
The part is supplied as a connector shell (with integral
insulator), and a bag of (52 x size 22 AWG) crimp pins which
may be inserted into the connector shell. The connector is
electroless nickel plated.
The mating screws are stainless steel and are held in place
on the connector shell by stainless steel retaining clips.
FEATURES
• Mating connector for KAD modules
• Includes connector shell, crimp pins and mating screws
APPLICATIONS
• Connecting modules
CON/KAD/002/CP plan, elevation and end view
23 Jan. 2008 | DST/R/008 637

Selection Paths
Airborne Data Acquisition → KAM-500 → Connectors
CON/KAD/002/CP 52-way double-density connector, with 52 loose contacts
Revision History
CON/KAD/002/CP First release Recommended for new programs
Related Products
Module Details
CON/KAD/002/SR 52-way DD connector to accommodate the temperature sensor within the module connector
Document Details
www.acracontrol.com
638 23 Jan. 2008 | DST/R/008

Specifications

Mass
connector, screw and clip – 8.7 – g
connector, screw and clip – 0.30 – oz Design metric is grams.
Dimensions
connector height – 14 – mm
connector height – 0.5 – in. Design metric is millimeters.
connector length – 53 – mm
connector length – 2 – in.
connector width – 12.8 – mm
connector width – 0.5 – in.
Chassis clearance
connector height – 0.9 – in.
bend radius height – 52 – mm Without ACD/BAC/002 or ACD/BAC/003 attached.
bend radius height – 2 – in.
Finish
connector – – – – Electroless nickel plated aluminium.
integral isolator housing – – – – Nylon.
pins – – – – Copper alloy with 1.2µm gold plating.
pins and retaining clips – – – – Stainless steel.
Getting the most from the CON/KAD/002/CP

This 52-way double-density mating connector can be used with all KAM-500 double-density modules except the TDC/002.
The CON/KAD/002/CP is supplied with 52 loose pin contacts. See the KIT/001 data sheet in the KAM-500 Databook for
instructions on how to insert these pins.
When mating and un-mating double-density connectors, jackscrews should be screwed/unscrewed by half a turn alternately on
each side until the connectors are fully mated/un-mated. Failure to mate/un-mate the connectors in this manner may result in
deformation of the module top connector, which can reduce the reliability of the electrical contact of the connector/module with
face.
23 Jan. 2008 | DST/R/008 639

www.acracontrol.com
640 23 Jan. 2008 | DST/R/008

CON/KAD/002/SR
A C R A KAM-500 CON/KAD/002/SR
C O N T R O L 2-way double-density connector for temperature sensor in the module connector
DESCRIPTION
The CON/KAD/002/SR is a 52-way double-density connector
for use with the TDC/002.
insulator), and a bag of (42 x size 22 AWG) crimp pins which
may be inserted into the connector shell. The connector is
electroless nickel plated.
FEATURES
• Mating connector for TDC/002
APPLICATIONS
• Connecting TDC/002 modules
CON/KAD/002/SR plan, elevation and end view
23 Jan. 2008 | DST/R/009 641

Selection Paths
Airborne Data Acquisition → KAM-500 → Connectors
CON/KAD/002/SR TDC/002-only 52-way double density mating connector, with 42 loose contacts
Revision History
CON/KAD/002/SR First release Recommended for new programs
Related Products
Module Details
CON/KAD/002/CP 52-way double-density KAD module mating connector
TDC/002 15 channel thermocouple analog to digital convertor with reference compensation
Document Details
www.acracontrol.com
642 23 Jan. 2008 | DST/R/009

Specifications

Mass
connector, screw and clip – 8.7 – g
Dimensions
connector length – 53 – mm
connector length – 2 – in.
Chassis clearance
Finish
Getting the most from the CON/KAD/002/SR

This mating connector is only for use with the TDC/002.
The CON/KAD/002/SR is supplied with 42 loose pin contacts. See the KIT/001 data sheet in the KAM-500 Databook for
face.
23 Jan. 2008 | DST/R/009 643

www.acracontrol.com
644 23 Jan. 2008 | DST/R/009

CON/KAD/005/CP
A C R A KAM-500 CON/KAD/005/CP
C O N T R O L 52-way double-density KAD module mating connector with rear grommet
DESCRIPTION
The CON/KAD/005/CP is a 52-way double-density connector
for use with all KAM-500 KAD modules (except the
TDC/002).
insulator), and a bag of crimp pins (52 x size 22 AWG) which
may be inserted into the connector shell. A grommet is
attached at the rear. The connector is electroless nickel
plated.
FEATURES
• Mating connector for KAD modules
• Includes connector shell, crimp pins, mating screws and
grommet at the rear
APPLICATIONS
• Connecting modules
CON/KAD/005/CP plan, elevation and end view
23 Jan. 2008 | DST/S/041 645

Selection Paths
Airborne Products → KAM-500 → Connectors
CON/KAD/005/CP 52-way double-density KAD module mating connector with rear grommet
Revision History
CON/KAD/005/CP First release Recommended for new programs
Related Products
Module Details
CON/KAD/005/SR 52-way double-density mating connector for TDC/002 with rear grommet
CON/KAD/002/CP CON/KAD/002/CP
CON/KAD/002/SR 2-way double-density connector for temperature sensor in the module connector
Document Details
www.acracontrol.com
646 23 Jan. 2008 | DST/S/041

Specifications

Mass
connector, screw and clip – 10 – g
Dimensions
connector height – 19.9 – mm
connector length – 53.4 – mm
connector length – 2.1 – in.
Chassis clearance
Finish
grommet – – – – Fluoro silicon rubber.
Getting the most from the CON/KAD/005/CP

This 52-way double-density mating connector can be used with all KAM-500 double-density modules except the TDC/002.
The CON/KAD/005/CP is supplied with 52 loose pin contacts. See the KIT/001 data sheet in the KAM-500 Databook for
the contact face.
23 Jan. 2008 | DST/S/041 647

www.acracontrol.com
648 23 Jan. 2008 | DST/S/041

CON/KAD/005/SR
A C R A KAM-500 CON/KAD/005/SR
C O N T R O L 52-way double-density mating connector for TDC/002 with rear grommet
DESCRIPTION
The CON/KAD/005/SR is a 52-way double-density connector
for use with the TDC/002.
insulator). At the rear of the connector is a rubber grommet
and a bag of crimp pins (42 x size 22 AWG), which may be
inserted into the connector shell. The connector is electroless
nickel plated.
FEATURES
• Mating connector for the TDC/002
• Includes connector shell, crimp pins, mating screws and
grommet at the rear
APPLICATIONS
• Connecting TDC/002 modules
CON/KAD/005/SR plan, elevation and end view
23 Jan. 2008 | DST/T/095 649

Selection Paths
Airborne Products → KAM-500 → Connectors
CON/KAD/005/SR 52-way double-density mating connector for TDC/002 with rear grommet
Revision History
CON/KAD/005/SR First release Recommended for new programs
Related Products
Module Details
CON/KAD/005/CP 52-way double-density KAD module mating connector with rear grommet
CON/KAD/002/CP CON/KAD/002/CP
CON/KAD/002/SR 2-way double-density connector for temperature sensor in the module connector
Document Details
www.acracontrol.com
650 23 Jan. 2008 | DST/T/095

Specifications

Mass
connector, screw and clip – 10 – g
Dimensions
connector height – 19.9 – mm
connector length – 53.4 – mm
connector length – 2.1 – in.
Chassis clearance
Finish
connector – – – – Electroless nickel plated.
grommet – – – – Fluoro silicon rubber.
Getting the most from the CON/KAD/005/SR

This 52-way double-density mating connector is to be used with the TDC/002.
The CON/KAD/005/SR is supplied with 42 loose pin contacts. See the KIT/001 data sheet in the KAM-500 Databook for
deformation of the module top connector, which can reduce the reliability of the electrical contact of the connector/module.
23 Jan. 2008 | DST/T/095 651

www.acracontrol.com
652 23 Jan. 2008 | DST/T/095

ACD/KIT/001, ACM/KIT/01
A C R A KAM-500 KIT/001
Standard tools used for KAM-500 system assembly
C O N T R O L
DESCRIPTION
ACM/KIT/001 consists of:
• ACC/TOL/002 – Black straight blade screwdriver
• ACC/TOL/004 – 2mm Allen key
• ACC/TOL/005 – 2.5mm T-bar Allen key
ACD/KIT/001 consists of:

• ACD/TOL/002 – 24 AWG special thin body insertion tool
• ACD/TOL/005 – Handle for use with ACD/TOL/002 and
ACD/TOL/006
FEATURES • ACD/TOL/006 – Extraction tool for use with ACD/TOL/005
• Complete tool kit for KAM and KAD chassis and module • ACD/TOL/004 – K154 positioner
assembly
APPLICATIONS
• Assembling KAM-500 system
ACM/KIT/001 ACD/KIT/001
ACC/TOL/005
ACD/TOL/006 ACD/TOL/004
ACC/TOL/004 ACC/TOL/002 ACD/TOL/002
26 Mar. 2009 | DST/J/063 653

Selection Paths
ACD/KIT/001 Double-density tool kit including ACD/TOL/002, ACD/TOL/005, ACD/TOL/006 for double-density
connectors
ACM/KIT/001 Micro-miniature toolkit including ACC/TOL/002, ACC/TOL/004, and ACC/TOL/005 for

micro-miniature connectors
Revision History
ACD/KIT/001 Standard double-density tools used for KAM-500 system Recommended for new programs
assembly
ACM/KIT/001 Standard micro-miniature tools used for KAM-500 system Recommended for new programs
assembly
Related Products
Revision Differences
ACC/TOL/002 Screwdriver for KAM-500 module retaining screws and micro-miniature connectors
ACC/TOL/004 Allen key for removal of orange top panels
ACC/TOL/005 Allen keys for chassis disassembly
ACD/TOL/002 Special thin body insertion special tool, silver-colored and explicitly for inserting crimped wires into
the grommet on CON/KAD/005/CP and CON/KAD/005/SR
ACD/TOL/004 K154 positioner
ACD/TOL/005 Handle for use with ACD/TOL/002, and ACD/TOL/006
ACD/TOL/006 Extraction tool for use with ACD/TOL/005
Document Details
www.acracontrol.com
654 26 Mar. 2009 | DST/J/063

Getting the most from KIT/001 tools butt up against the crimp pot. Connector must be firmly
supported during both insertion and extraction operations.
Follow these instructions to assemble the CON/KAD
connector variations.
• The proper crimp tool and locator (if required) must be
used. These tools have been designed for use with this
product. Substitutions of crimping equipment may result in
connector failure at the assembly operation.
• After crimping a contact to a lead it is vital that the proper
tool be used to assure seating the contact in the insulator
in the proper position. Any substitution of insertion tools
may result in over or under insertion of the contact which Using a firm, steady pressure, push the contact into the cavity
will damage the retention system of the insulator. until the resilient internal shoulder in the insulator snaps into
• The female (socket) side of the connector has been the locking groove in the contact. The shoulder of the tool tip
designed with a controlled float to allow for ease of mating. bottoms against the rear of the insulator, preventing
To avoid reducing this float or causing a splaying of the over-insertion. Repeat for balance of contacts.
contacts, any unnecessary strain by clamping too close to
the rear of the connector should be avoided.
Contact extraction
Use of recommended tools and proper assembly techniques
will pay dividends in reliability and reduced costs.
Wire stripping
0.004" (3mm)
For contact extraction, remove the insertion tool tip and
replace it with the proper extraction tool tip. The socket tip will
Cut the wires to length required and strip 0.004" (3mm) of
fit into the socket, and the pin tip will slide over the pin
insulation from the end to be crimped. Check for cut or
bundle. Insert the tool tip into the contact cavity: the pin tip
broken wires and frayed insulation.
will butt up against the shoulder of the pin contact, and the
socket will bottom in the socket contact.
Contact crimping
Apply a firm, steady pressure until the contact is released

from the internal shoulder in the insulator. The shoulder of the
Using the proper crimp tool and locator, insert the contact into tool tip bottoms against the insulator face to prevent damage
the locator. Insert the stripped end of the wire into the contact to the internal shoulder. Remove the tool tip and pull the
crimp pot, and crimp the contact to the wire. Squeeze the contact from the rear of the connector. Repeat for the balance
handles firmly to insure a proper crimp (tool will not release if of contacts to be removed.
crimping is incomplete).
Contact stop must be changed in tool locator when crimping
pin and socket contacts.
Contact insertion
Place the proper insertion tip in the insertion / extraction

handle and put the tip over the wire as shown. The tool tip will
26 Mar. 2009 | DST/J/063 655

www.acracontrol.com
656 26 Mar. 2009 | DST/J/063

ACM/LID/001, ACC/SCW/001
A C R A KAM-500 LID/001
Spare user-slot lids and spare screws for the KAM-500 system
C O N T R O L
DESCRIPTION
ACM/LID/001
The ACM/LID/001 is a lid for empty user-slots. This lid
(labelled SPARE) is recommended for unoccupied user-slots
and is the same shape and color as the lids of user-modules.
Lids are supplied in quantities of ten. The ACM/LID/001
comprises a pack of ten ACC/LID/001s. (ACC/LID/001 is an
internal ACRA CONTROL part number.)
ACC/SCW/001
The ACC/SCW/001 is a pack of M3 x 6mm cap head screws.
FEATURES These spares are offered as a part number for completeness
only. Screws are supplied in quantities of twenty.
• Spare screws for housing
• Spare lid for unused slots
• Screws are standard size (M3 x 6mm)
APPLICATIONS
• Spare chassis parts
Single ACC/LID/001 from pack of ten ACM/LID/001
23 Jan. 2008 | DST/J/061 657

Selection Paths
ACM/LID/001 Spare user-slot lids for the KAM-500 system
ACC/SCW/001 M3 x 6mm cap head screw pack
Revision History
ACM/LID/001 First release Recommended for new programs
Related Products
Module Details
ACC/SCW/001 M3 x 6mm cap head screw pack
Document Details
Dimensions
height – 3 – mm
width – 80 – mm
width – 3.14 – in.
Mass
– 14 – g
Finish – – – – Electroless nickel plated with top surface painted REINORANGE
RAL2004.
www.acracontrol.com
658 23 Jan. 2008 | DST/J/061

A C R A Chapters and controlled lists
C O N T R O L
659
Chapter 1
ACRA Introducing the KAM-500

C O N T R O L
To get the most out of KAM-500 For distributed systems a merger module is inserted in any
data sheets (and the KAM-500 system) it is important to user-slot for every additional pair of KAM-500s. A single
understand some of the key concepts and goals behind the chassis can merge data from up to 26 PCM streams. Up to
KAM-500 system. This section introduces the KAM-500 and 64 chassis can be programmed via two twisted pairs, see
in particular some of the nomenclature and design goals “Distributed data acquisition” on page 662.
associated with the KAM-500 system.
A high level of parts commonality between modules and use
of monolithic devices underpins the reliability of the
Chassis components KAM-500. The KAM-500 uses no microprocessors, which
The KAM-500 is a modular data acquisition system designed means there is no micro code for flight approval, and no
for harsh aerospace applications where space is at a power-up sequences or watch-dog circuitry. Hard-wired state
premium. The system is completely software programmable machines and EEPROM-based setup ensure that when it
and contains no switches, potentiometers, bridges, relays or works once, it works always.
socketed ICs (such as programming EEPROM). Another feature of the KAM-500 is that a parameter (for
A wide range of user-modules is available for analog example, strain from channel 4 of the ADC/109 bridge
input/output, avionics bus monitoring, time tagging, module) can be sent to multiple modules. For example, a
non-volatile (EEPROM) storage and (PCM) transmission. chassis can have multiple PCM streams of different codes,
Any user-module can go into any user-slot (up to 13) in any bit-rates, word lengths, words per minor frame and minor
combination (there is 2.0A of current available for bridge frames per major frame with some parameters going to all
excitation). streams and some parameters going to one stream.
Backplane operation
User module The backplane has a 16-bit bidirectional address/data bus
and control lines which read parameters, write, latch the
address and select the module (including broadcast).
Controller Backplane transfer is synchronized using an 8MHz system
clock from which all module timing is derived.
TO/FROM CONTROLLER
FROM POWER SUPPLY
MSEL4~
Power supply USER SLOT 4
MSEL5~
USER SLOT 5
Chassis
SCLK Rd~ Wr~ ALE BC AD[15:0]
+5V +12V -12V +7V -7V
Figure 1: Isometric view of a single chassis

Figure 2: Backplane operation
The chassis is black aluminum (the top is painted orange).
All modules appear to the backplane as registers to be read
The isolated power supply comprises two sets of
or written. For example the ADC/109, which has 8 analog
components, one at each end of the chassis, and is used to
inputs has 8 read registers.
convert a nominal 28V to that used by the modules.
Apart from data read and write registers, other registers are
Each chassis has a backplane and controller. The controller
transparent to the user for module test, identification and
synchronizes module operation and transfers data from one
synchronization. Figure 3 shows an example of this type of
module to another. The controller also contains the
data flow.
programming interface and is polarized to prevent it being
plugged into a user-slot. The controller/encoder also contains
a complete IRIG-106 PCM generator. Additional/auxiliary
encoders can be added in any user-slot.
11 Sep. 2007 | Chapter 1 661

Figure 3: Data path from an ADC/109 to 4 modules
Figure 4: Timing diagram for parameter transfer
Figure 4 shows an example of the timing associated with this

type of data flow. In this example 875ns is required to transfer Distributed data acquisition
the parameter. Typical data transfer takes 4 clock cycles
(500ns). The theoretical maximum is 16 clock cycles (2µs); To extend a distributed system, up to two additional
for this reason each KAM-500 in a system has an aggregate KAM-500s can be added at any time by inserting a DAC/003
sampling rate specification of 500,000 samples per second merger module in any user-slot of any chassis. Any KAM-500
(sps). The 100 series family of modules has sampling rates system can be placed anywhere in Figure 5.
up to 2Msps.
662 11 Sep. 2007 | Chapter 1

Acquisition cycles and synchronous
sampling
The controller cycles through a format stored in EEPROM.
Any register, channel or parameter that must be read or
written is accessed at least once during this acquisition cycle.
For this reason any glitches are recovered within one of these
acquisition cycles.
An acquisition cycle is the shortest possible time to do
everything at least once. (It is analogous to a PCM major
frame). For example, if the slowest signals are sampled every
10ms and 11ms respectively, the acquisition cycle is 110ms
(the lowest common multiple). If a KAM-500 is generating two
PCM frames with major frame lengths of 10ms and 11ms
respectively the acquisition cycle is 110ms.
In the past, data acquisition systems tended to multiplex
multiple signals to a single A/D according to commutation
sequences determined by the transmission protocol(s). This
meant that to time correlate data, analysis engineers had to
understand the data packet(s) used and add a different time
offset for each signal. Also, multiplexing signals or holding
Figure 5: A distributed system them with sample and hold devices becomes more difficult
with today’s 12, 14 and 16-bit systems.
A PCM stream from the BCU/101 controller/encoder (or from
an auxiliary encoder ENC/005 in any user-slot) in the source In the KAM-500, at the start of every acquisition
chassis (by convention called a SLAVE) is connected to the cycle a command is broadcast causing all signals
to be sampled and the time latched in the timer
merger module in the destination chassis (by convention
module. After that samples are evenly spaced.
called a MASTER). This data transfer requires two twisted
pairs (for clock and data) and ground. In Figure 6 a major frame consisting of two minor frames is
drawn. By convention the minor frames are usually drawn
Up to 64 units can be programmed via a single multi-drop
underneath each other as shown. The diagram also shows
programming link. Each controller has six discrete digital
the two minor frames with respect to time (one after the other)
inputs to set the programming address. This programming
and underneath them the instances that each signal is
link requires an additional twisted pair (for clock and data) to
sampled. If there is only a single PCM stream the acquisition
be connected during programming.
cycle is the same length (of time) as the major frame.
It is recommended that all chassis operate synchronously.
All signals are sampled at the start of the acquisition cycle
Therefore two more twisted pairs have to be added. One is a
(major frame) and all signals with the same sample rate are
1MHz clock connected to a digital PLL on each controller to
always sampled at the same time.
generate the 8MHz system clock. The other is for acquisition
cycle alignment (analogous to a major frame pulse). These In Figure 6, “The relationship between acquisition cycle and
signals are best taken from a single chassis controller. Any major frame for a single stream,” two channels are
chassis can be made the MASTER by setting the address super-commutated at different rates. One is four times per
select lines to zero. acquisition cycle and the other six times.
If a chassis is used for time-tagging events it runs With the KAM-500 the sampling points are not a function of
synchronously with others about the distributed system but the data transmission/logging packet(s) but rather are a
does not have the same absolute time unless seeded (for function of the sampling rates only. To time correlate all data,
example using an IRIG time source). include the acquisition cycle start time (Ts) in the parameter
list and make a note of the acquisition cycle time (Ta).
For a more detailed discussion of how to connect a
distributed system, see “Equipment interface” on page 669. In the KAM-500 this strategy holds even if the signals are in
different chassis at opposite ends of the aircraft.
ACRA CONTROL does not recommend using a
MASTER/SLAVE daisy-chain configuration.
11 Sep. 2007 | Chapter 1 663

Format switching and test-and-type
registers
.
Figure 6: The relationship between acquisition cycle and major frame for a single stream
Format switching
KAM-500 modules contain devices
Up to 15 formats can be stored in a controller, each that require standard ESD precautions
corresponding to one acquisition cycle. Four digital lines are to be observed when handling
available to the user to select between formats. Examples: components that are usually inside the
chassis. Furthermore, in electrostatic
• One format that samples gages on the undercarriage can environments it is strongly
be used while a plane is taking off and another format that recommended that grounds be
does not sample these gages can be switched in when the connected before connecting signals,
undercarriage is retracted. especially high speed digital busses,
• Reserve a format containing only fixed data for such as RS-422, which are difficult to
troubleshooting data links, decommutation hardware and protect.
analysis software.
The KAM-500 switches to a new format only at the end of an
acquisition cycle. If PCM streams are being generated each
can contain a format identifier so that lock is maintained even
if word lengths, meanings and commutations change.
Test and type registers

All modules have test registers so that programming utilities
can check the backplane, RAM and EEPROM address/data
lines. Each module has EEPROM for storing setup
information, 128 Kbytes of which are reserved for
housekeeping information. Module type information is stored
here which allows a programming utility to identify the module
in each slot.
www.acracontrol.com
664 11 Sep. 2007 | Chapter 1

Chapter 2
A C R A Environmental specifications
C O N T R O L
Overview Calibration interval for analog modules
The following table summarizes the main environmental Based on typical use, KAM-500 analog-to-digital (A/D)
specifications for the KAM-500: converter modules are expected to remain in calibration for a
period of 24 months from the date of delivery. It is
General environmental specifications recommended that analog modules are checked for accuracy
Parameter Min. Typ. Max. Units at the end of the initial 24-month period, and at 12-month
intervals thereafter.
Storage life and – – 10 Years
maintenance Most of the newer 100-series analog modules (such as the
Temperature ADC/106) can be factory calibrated for gain/offset error using
operational (case) -40 – 85 °C special test jigs and software. This service is available from
ACRA CONTROL for a standard RMA/calibration charge.
storage (case) -55 – 105 °C
Altitude – 75000 – ft. Some non-100-series analog modules can also be
– 22860 – m
factory-calibrated for offset error, namely the ADC/005,
ADC/009, ADC/013 and TDC/002 modules.
Shock
100g for 11ms In each of the three major axes. However, most older analog modules including the ADC/001,
terminal peak sawtooth, 12 shocks. ADC/002, ADC/003, ADC/006, ADC/010, ADC/011, ADC/012
250g for 6ms In each of the three major axes, half
and ADC/014 do not support factory-calibration. If these
sine, 12 shocks. modules are outside their intended accuracy due to age,
factory-repair may be possible, or gain/offset error can be
Water ingress (drip test) – 280 – l/m2/hr.
(45 min.)
adjusted for either by changing the gain/offset settings using
the KSM software or in post-processing. Note that repairs are
Vibration
handled as RMAs in the normal way.
Random, 0.83g2/Hz peak,
10min/axis.
Design considerations
Random, 0.20g2/Hz peak,
60min/axis. Every effort is made to use components with no particular
Acceleration 16.5g for 1 minute in each direction of performance degrading restrictions. In particular components
three mutually perpendicular axes. that may drift with age such as timers and A/D or D/A
EMI/EMC As per MIL-STD-461E & BS3G100. converters are specified over their lifetime.
Humidity 0 – 95 % It is recommended to always run the auto-configuration utility
Contamination testing 70°C for 93 hours, Propan-2-Ol, after system installation. This utility checks memory and
Ethylene Glycol (50% v/v in water), backplane address/data lines, refreshes EEPROMs and
AVTUR F-34, Aeroshell Turbine Oil detects from the date in EEPROM if the real-time clock
308, Aeroshell Fluid 31, Aeroshell battery (if present) needs to be changed.
F31.
Apart from changing the battery in the real-time clock module
For full details of the specifications and the design and for module malfunction, no part of the system requires
considerations taken by ACRA CONTROL, see the removal from the aircraft. For this reason it is recommended
remainder of this chapter. that an external time source (such as an IRIG time stream)
be used for systems requiring time tagging.
Where possible devices are selected for designs that have
already been tested on other modules. In particular the same
connectors, backplane logic, EEPROMS, RAMS, gate arrays Physical dimensions, weight and mass
and capacitors can be found on all acquisition modules. The KAM-500 is cuboid with only mounting lugs, thumb
The specifications in this chapter apply to all KAM-500 screws, connectors and optional heat sinks protruding. The
modules except where stated in the data sheet. Some KAM-500 has two connector options for modules, a 51-way
modules have been qualified by type. Unless otherwise micro-miniature connector or a 52-way double density
stated, all specifications apply to a fully operating system. connector.
Storage life and maintenance Physical dimensions, weight and mass:

design considerations
The KAM-500 is designed to be kept in storage for up to 10
years before installation. Special conditions such as altitude, The mass of each component or module is kept to a
temperature, humidity, pressure (including air transportation) minimum and large mass components such as power
and ventilation beyond those specified under operating supplies are placed as evenly as possible at each end of the
conditions do not apply during storage. chassis. User-modules can usually be arranged to keep the
QD/HW/SPF/L/0001 | 30 May 2008 665

center of gravity close to the geometric center of the cuboid. Altitude and rapid decompression MIL-STD-810F
Most of the weight (typically more than 75%) is in the chassis, specifications
not the modules.
Parameter Min. Typ. Max. Units
The KAM-500 is a modular system and information on a
Method 500.4
particular configuration's approximate mass, dimensions and
center of gravity may be provided on request. Procedure II Carried out at maximum pressure of
115Kpa (1150mbar) and a minimum
pressure of 3.6Kpa (36mbar).
Temperature Procedure III Carried out from room ambient to
The KAM-500 is designed to operate within specifications at 3.6Kpa (36mbar) at a rate of
temperature extremes. In particular it is designed to operate 218Kpa/minute (2180mbar/min.).
at case temperatures within the range of -40°C to 85°C and Method 500.4
during rates of change in excess of 1°C/min. Procedure IV Procedure II was carried out with the
The KAM-500 has been tested and certified in accordance unit unpowered and a pressure
change from 2,438m (8000ft) to
with MIL-STD-810 specifications, Methods 501.4 and 502.4. 12,192m (40,000ft) was achieved in
78.4ms.
Temperature MIL-STD-810 specifications
Parameter Min. Typ. Max. Units Shock

Methods 501.4 and The KAM-500 has been tested and certified in accordance
502.4, procedure I1 with MIL-STD-810F Method 516.5.
operational -40 – 85 °C
Shock MIL-STD-810F specifications
non-operational -55 – 105 °C
1. Sampled at least 4 hours after stabilization of specimen

temperature. Method 516.5 Procedure
V - modified
Temperature: design considerations severity 100g, 11ms, terminal peak sawtooth
Power consumption is kept to a minimum, the main aluminum
housing is a dull color (to aid thermal radiation) and heat sink No. of shocks 12 (2 in each direction of 3 mutually
fins are recommended where space permits. The KAM-500 perpendicular axes)
has no fans or coolants. However, it is recommended to bolt
the chassis to a good heat conductor in an environment with Shock: design considerations
good airflow away from heat sources. The KAM-500 is designed to endure severe shock
The KAM-500 is a modular system and information on a environments while operating. In particular the following is
particular configuration's power consumption and heating observed:
may be provided on request. 1. Device mass is always kept to a minimum. The power
Because convection is less effective at higher altitudes each supply DC/DC converters, the real-time clock battery, the
module is designed so as to conduct heat to the chassis as ADC/109 and ADC/106 daughter boards and the
quickly as possible (for example, each module has a ground through-hole device on the synchro-to-digital converter
plane). are the largest devices. Special care was taken to
harness/secure these devices.
Care is also taken when choosing components such as 2. Devices with moving parts or liquids are never used. The
capacitors that they are specified for low temperature KAM-500 has no IC sockets, relays, jumpers, switches
operation. or potentiometers.
3. PCB freedom of movement is minimized. The backplane
Altitude and rapid decompression PCB is securely mounted to the chassis base-plate.
The KAM-500 is designed to operate within specifications at Module PCBs are approximately 70mm x 70mm.
high altitudes. The KAM-500 has been tested and certified in
accordance with MIL-STD-810F, Method 500.4. Water ingress (drip test)
The KAM-500 has been tested and certified in accordance
with the following:
Water ingress MIL-STD-810F specifications

Method 506.4,
Procedure III
Precipitation rate 280 l/m2/hr.
Duration 45 minutes, divided equally between
3 faces (one side, one end and one
top)
Water ingress: design considerations

All KAM-500 modules are conformally coated.
666 QD/HW/SPF/L/0001 | 30 May 2008

The only gaps in the data acquisition system are the spaces Acceleration
between the module lids. There are no gaps on the bottom or
sides of the KAM-500 system. The KAM-500 has been tested and certified in accordance
with:
Vibration Aceleration MIL-STD-810F specifications

The KAM-500 has been tested and certified in accordance Parameter Min. Typ. Max. Units
with the following: Method 513.5,
Vibration MIL-STD-810F Sinusoidal frequency sweeps Procedure II
specifications acceleration 16.5g in each direction of three
mutually perpendicular axes.
Parameter Min. Typ. Max. Units duration Minimum of 1 minute in each
Method 514.5, direction.
Procedure I
frequency range 10 – 2000 Hz Acceleration: design considerations
amplitude 20mmp-p from 10 to 16Hz The same design considerations apply as for shock. See
10g pk from 16 to 2000Hz “Shock: design considerations” on page 666 for details.
Sweep rate 1 octave per minute
Duration: One upward sweep from 10 to EMI/EMC
2000Hz and one downward sweep
The KAM-500 is designed to meet, and will be certified in
from 2000 to 10Hz
accordance with the following:
Note: Limitations on shaker
displacement reduced the EU directive 89/336/EEC; E50081-1 & E50082-1.
acceleration level to 5g at 10Hz rising
to 10g at 14Hz
with the following:
Vibration MIL-STD-810F Sinusoidal frequency sweeps BS 3G100 Part 2 Section 2 (Magnetic Influence)
specifications
MIL-STD-461E: CE-101, CE-102, CS-101, CS-114, CS-115,
Parameter Min. Typ. Max. Units CS-116, RE-102, RS-103.
Method 514.5, For EMC compliance all cables should be shielded and all
Procedure I; Sinusoidal shields should be connected to the KAM-500 chassis via the
Frequency Sweeps connector backshell.
frequency range 10 – 2000 Hz
amplitude 20mmp-p from 10 to 16Hz Electromagnetic emissions and
10g susceptibility: design considerations
Sweep rate 1 octave per minute
A particular emphasis is placed on minimizing
Duration: One sweep cycle (10 - 2000 - 10Hz) electromagnetic emissions and susceptibility. In particular the
carried out in 3 mutually following is observed:
perpendicular axes)
Note: Limitations on shaker 1. Where possible power switching devices are not used.
displacement reduced the The power supply modules are the only ones that contain
acceleration level to 5g at 10Hz rising DC/DC converters. These devices are screened and were
to 10g at 14Hz
always present during the tests above.
Vibration MIL-STD-810F random endurance 2. Where possible high frequency oscillators are not used.
specifications
The controller has a screened 64MHz oscillator which is
Parameter Min. Typ. Max. Units quickly divided to an 8MHz system clock from which modules
Method 514.5,
take their timing. The MIL-STD-1553 and STANAG 3910 bus
Procedure I monitors have low-power oscillators for over-sampling the
busses being monitored.
frequency range 15 – 2000 Hz
Spectrum 3. The chassis housing is metallic with no “line of sight”.
0.04g2/Hz from 15 to 30.7Hz The chassis housing is 6mm (0.2in) aluminum with beveled
+4dB/octave from 30.7 to 300Hz joints that ensure no lateral or horizontal “lines of sight”. The
0.83g2/Hz from 300 to 1000Hz modular nature of the system means that there are vertical
lines of sight between modules. These lines were always
-6dB/octave from 1000 to 2000Hz
present during the tests.
Duration: 10 mins per axis
4. The KAM-500 does not contain RF transmitters or
Vibration: design considerations receivers.
5. All PCBs have ground planes.
The same design considerations apply as for shock. See
“Shock: design considerations” on page 666 for details. The
KAM-500 is a modular system and a particular configuration's
resonant frequencies may be specified on request.
QD/HW/SPF/L/0001 | 30 May 2008 667

Electrostatic discharge and handling Humidity
Where appropriate the KAM-500 inputs and outputs have The KAM-500 has been tested and certified in accordance
been certified by design in accordance with the following: with the following:
Electrostatic discharge and handling specifications MIL-STD-810F, Method 507.4
Parameter Min. Typ. Max. Units Parameter Min. Typ. Max. Units
EIAJ IC121: (Machine – 1 – kV Temperature 20 30 60 °C
model) Relative humidity – 95 – %
MIL-STD 3015.7: (Human – 5 – kV
body model)
Relative humidity – 85 – %
(during temperature
IEC 1000-4-2: Direct discharge Level 1. reduction)
The KAM-500 has been tested in accordance with the following: Dwell times (at each – 4 – hours
level)
Electrostatic discharge and handling testing Cycle duration – 24 – hours
specifications
Number of cycles – 5 –
IEC 801-2:1991 15/8 kV MIL-STD-810F, Method 507.4 (Modified)
(EN61000-4-2:1995): Five cycles, each comprising:
(Human body model)
1. +32°C, <15% rh, 10 hours
KAM-500 modules contain devices that require standard ESD 2. +38°C, <2% rh, 4 hours
precautions to be observed when handling components that 3. +32°C, <15% rh, 10 hours
are normally inside the chassis. Also, in electrostatic 4. +27°C, 100% rh, 4 hours
environments it is strongly recommended that grounds be 5. +30°C, 95% rh, 20 hours
connected before connecting signals, especially high speed
digital busses, such as RS-422, which are difficult to protect. Humidity: design considerations
All KAM-500 modules are conformally coated.
Electrostatic discharge and handling:
design considerations Fungus/mold growth: design
A particular emphasis is placed on minimizing ESD considerations
vulnerability. In particular the following is observed: All KAM-500 modules are conformally coated.
1. Digital CMOS devices are never connected directly to an
I/O pin. Internal contamination
2. Where possible inputs have large resistors in series.
3. Slow low-current outputs have large resistors in series.
with the following:
4. RS-422 and digital drivers/receivers are all specified to
the above specifications. BS 3G 100, part 2, section 3, subsection 3.12 class A for
occasional contamination.
Electrical bonding and insulation Temperature: 70°C
The KAM-500 has been tested and certified in accordance Duration: 93 hours.
with the following:
Fluids tested include,
Electrical bonding test; AC/KAM-500-II/SLTP/1.4,
Paragraph 3. • Propan-2-Ol
• Ethylene glycol (50% v/v in water)
Electrical Insulation Test, High Voltage Test; BS3G100, • AVTUR F-34
Part 4, Section 1, Subsection 1, Paragraph 5.1. • AeroShell Turbine Oil 308
Electrical Insulation Test; BS3G100, Part 4, Section 1, • AeroShell Fluid 31
Subsection 1, Paragraph 5.2. Insulation Resistance Test. • AeroShell F31
Electrical Insulation Test; BS3G100, Part 4, Section 1, Internal contamination: design

Subsection 1, Paragraph 5.3
Leakage Current Measurements.
considerations
The KAM-500 does not contain any hydraulics, lubricants,
coolants or battery fluids.
The battery used in the real-time clock module is sealed
nickel-cadmium.
www.acracontrol.com
668 QD/HW/SPF/L/0001 | 30 May 2008

Chapter 3
ACRA Equipment interface

C O N T R O L
Overview Twisted pairs tend to pick up the same electromagnetic

interference so the difference between them stays the same.
This section should be read by any engineer responsible for Analog lines are also more likely to stay at the same
wiring to or from the KAM-500. After reading this the most temperature which may reduce thermal emf differences at
common mistakes made during installation should be connectors and effects due to temperature drifts.
avoided. These include:
Other pairs should also be twisted as illustrated in the
• Incorrect grounding between chassis Figure “Twisting pairs” on page 669:
• Incorrect setting of the chassis address
• Noise due to poor shielding • The supply and return for in-line charge amplifiers.
• Lack of return paths from isolated sources • The excitation and return for bridges (especially if the
sense lines are not used).
• The sense lines for bridges.
General guidelines
This section describes a number of good design practices not
specific to the KAM-500 regarding the following:
• Bus termination
• Twisting differential-ended (D/E) pairs
• Common-mode signal returns
• Connecting aircraft power, grounds, returns and shields
Bus termination
The KAM-500 can be connected to a large variety of busses.
All these busses are differential-ended (D/E), except the eight
RS-232 receivers on the UAR/001 or the four single-ended
inputs on the UAR/102.
The analysis of high speed busses with respect to
propagation delay, power consumption, reflections,
common-mode-pickup and isolation requires some
understanding of wave propagation theory which is beyond
the scope of this book. However the physical layer
specification of all busses specify the recommended
impedances of cables, their terminations at each end and the
impedances of any device connected to it. Figure 1: Twisting pairs
Any KAM-500 device connected to a bus meets the physical Common-mode signal returns
layer specification
for that bus. For a common mistake when connecting signals that float
with respect to the KAM-500, see “Common-mode signal
Busses that allow multiple devices to be connected such as
returns” on page 669.
RS-422 and MIL-STD-1553 usually require the cable
terminations to be added externally. To simplify the wiring
task for the KAM-500, any device that is the only transmitter
on a RS-422 bus has the cable termination internal to the
module. When a bus is terminated internally, this is shown in
the block diagram on the front page of the data sheet and is
mentioned in the connector pinout section of the data sheet.
Twisting differential-ended pairs

Most busses and some signals to the KAM-500 are
differential-ended (D/E). Pin names for these type of lines
have a plus (+) and minus (-) suffix. The difference between
the lines is measured rather than the absolute value of each,
so it is recommended to twist them about each other. After
twisting, the next recommended step is shielding.
Figure 2: Common-mode signal returns
QD/HW/SPF/L/0002 | 29 Jan. 2008 669

Reasons the circuit on Some recommendations:
the left is incorrect:
There are no returns for any This is not an issue with single
leakage/bias currents from the ended (S/E) signals (for
input circuit. These currents example analog signals such as
are typically in the order of nA on the ADC/001) as the return
and any voltage across the is always connected to ground.
return resistor causes a
common-mode voltage which
can be ignored even for large
values of resistance.
The line on the circuit has a If the signal comes from

high (>>1MΩ) input circuitry powered by the
impedance that makes it KAM-500 (for example a
susceptible to electromagnetic bridge) the return resistor is not
interference pick-up. The needed.
smaller the return resistor the
better (0Ω is ideal).
In real-life applications two If the source and destination

floating circuits are at different circuits are grounded together
potentials due to inductive and (for example two devices
capacitive couplings. The communicating via RS-422) the
return resistor makes it easier return resistor is usually not
to pull the floating source needed.
along.
With thermocouple devices (for

example TDC/002) a return
resistor is already provided.
The most common occurrence

of this problem is when using
battery powered devices (for
example calibration sources).
If in doubt use a return resistor.
670 QD/HW/SPF/L/0002 | 29 Jan. 2008

Connecting aircraft power, grounds, returns and shields
“KAM-500 grounding scheme” on page 671 shows the grounding scheme used inside the KAM-500.
KAM-500 grounding scheme
KAM-500 design notes connecting multiple KAM-500s, the programming PC,

• The aircraft power (POWER±) is connected only to the shields and other systems about the plane).
isolated DC/DC converters. • Where possible it is recommended to connect the chassis
• The chassis is not galvanically connected to anywhere externally to GND using the pin on the PSU/012.
(except the I/O connector shells). • It is recommended that the aircraft power return POWER-
• One layer of the backplane PCB is devoted entirely to a remains isolated because it is a current carrying line.
ground plane (GND) that is less than 2mΩ between any However if it must be tied to GND it is recommended that it
two points. This layer is the grounding star center. The be done using the pins POWER- and GND on the
ground pin (GND pin 4) on the PSU/012 goes directly to PSU/012(on one chassis only).
this node (and nowhere else). • It is recommended that all shields be connected to the
• All modules have ground planes (GND) that are connected CHASSIS pin of the PSU/012 only. If the chassis has been
to the backplane via pins on the backplane connector. grounded, shields need only be connected to the I/O
• Occasionally modules have both analog and digital I/O on connector back shells.
the same card (for example the DAC/001). In these cases • KAM-500 inputs tend to have high common mode input
the return for analog circuitry is designated AGND. AGND impedance so return currents are typically measured in mA
is connected to GND at the backplane. or nA. The ground tracks and connector pins typically have
mΩ resistances (the leads tend to be higher) so the
voltages created using the scheme in the left of “Schemes
Notes for the system installer
for external circuit signals” on page 672 are in the order of
• Where possible it is recommended to designate the GND mV for each channel. However where possible the scheme
pin on the power supply unit the star node for all on the right is recommended for signals from external
non-current carrying references (for example when circuits.
QD/HW/SPF/L/0002 | 29 Jan. 2008 671

• For EMC compliance all cables should be shielded and all
shields should be connected to the KAM-500 chassis via
the connector backshell.
Schemes for external circuit signals
Chassis connections
“Recommended wiring diagram for the distributed KAM-500 MASTER-SLAVE system
system” on page 674 shows the recommended wiring
diagram to be used with a distributed KAM-500 system. In PROG_DATA goes from to BCU/101 (of up to 32
this illustration each chassis housing remains isolated as + SAM/DEC/007 pin 25 KAM-500s)
pin 6
does the aircraft power return. “Recommended wiring
diagram for the Ethernet system” on page 675 shows the PROG_DATA goes from pin 8 to BCU/101 (of up to 32
recommended wiring diagram to be used with a Ethernet - pin 26 KAM-500s)
system and “Recommended wiring diagram for the CAIS
system” on page 676 shows the recommended wiring Ethernet system
diagram for a CAIS system. PROG_DATA goes from to BCU/101
_A+ ETH/001 pin 6 pin 25
Connecting aircraft power (POWER±)
PROG_DATA goes from to BCU/101
These lines carry currents up to 3A. _A- ETH/001 pin 7 pin 26
PROG_DATA goes from to BCU/101 for PROG±

_B+ ETH/001 pin 8 pin 25 CHASSIS_I
POWER+ (aircraft 28V) goes to pin 1 of the PSU only
D 32-63
POWER- (aircraft return) goes to pin 2 of the PSU only
PROG_DATA goes from to BCU/101 for PROG±
_B- ETH/001 pin 9 pin 26 CHASSIS_I
Programming lines (PROG_DCLK±, D 32-63
PROG_DATA±)
Each pair must be terminated at the end with a 120Ω resistor.
The programming lines consist of two twisted pairs.
On the SAM/DEC/007 these lines are terminated internally as
standard.
672 QD/HW/SPF/L/0002 | 29 Jan. 2008

These pins are internally connected to other pins on the
BCU/101 connector.
Synchronization Lines (X_SYNC±, X_CLK±)

These lines are used to synchronize the operation of each
KAM-500 chassis. One unit is designated MASTER by
setting the chassis address lines CHASSIS_ID[3:0] low (see
“Setting the Programming Address Select Lines
(CHASSIS_ID[3:0])” on page 9). The MASTER outputs a
signal on two twisted pairs that are connected to all other
KAM-500s (if there are more than 16, or a star wiring
configuration is used then some external buffering may be
required). They consist of two twisted pairs.
X_SYNC+ goes from the MASTER to SLAVE BCU/101 pin

BCU/101 pin 32 13
X_SYNC- goes from the MASTER to SLAVE BCU/101 pin

BCU/101 pin 33 14
Each pair must be terminated at the end of the loop with a

120Ω resistor.
QD/HW/SPF/L/0002 | 29 Jan. 2008 673

SAM/DEC/007/C
GROUND 15 9 BCU/101 CHASSIS_ID(0) 4

CHASSIS 0 CHASSIS_ID(1) 5
PCM DATA+ 3 15 PCM DATA+
CHASSIS_ID(2) 6
28V
PCM DATA- 4 16 PCM DATA-
CHASSIS_ID(3) 7
PCM DCLK+ 12 17 PCM DCLK+
CHASSIS_ID(4) 37
PCM DCLK- 13 18 PCM DCLK-
CHASSIS_ID(5) 38
28V return
PROG_DATA+ 6 25 PROG_DATA+
PROG_DATA- 8 26 PROG_DATA- BVDD 10
28 PROG_DATA+ COPY
29 PROG_DATA- COPY FORMAT(0) 1
32 X_SYNC_OUTA+ FORMAT(1) 2
33 X_SYNC_OUTA- FORMAT(2) 3
FORMAT(4) 8
52 CHASSIS
DEC/003
1 PCM DATA(0)+
2 PCM DATA(0)-
3 PCM DCLK(0)+
4 PCM DCLK(0)-
PSU/012
5 PCM DATA(1)+ POWER+ 1
6 PCM DATA(1)- POWER- 2
8 PCM DCLK(1)+ CHASSIS 3
9 PCM DCLK(1)- GND 4
CHASSIS_ID(0) 4
BCU/101 CHASSIS_ID(1) 5
26 PROG_DATA- CHASSIS 1 CHASSIS_ID(2) 6
25 PROG_DATA+ CHASSIS_ID(3) 7
14 X_SYNC_IN- CHASSIS_ID(4) 37
13 X_SYNC_IN+ CHASSIS_ID(5) 38
16 PCM DATA-
15 PCM DATA+
18 PCM DCLK- BVDD 10
17 PCM DCLK+
28 PROG_DATA+ COPY
29 PROG_DATA- COPY
PSU/012
30 X_SYNC_IN+_COPY POWER+ 1
31 X_SYNC_IN-_COPY POWER- 2
CHASSIS 3
52 CHASSIS GND 4
PCM DATA- CHASSIS 2 CHASSIS_ID(1) 5
16
CHASSIS_ID(2) 6
15 PCM DATA+
CHASSIS_ID(3) 7
18 PCM DCLK-
CHASSIS_ID(4) 37
17 PCM DCLK+
CHASSIS_ID(5) 38
52 CHASSIS
26 PROG_DATA-
BVDD 10
25 PROG_DATA+
27 PROG_DATA_TRM+
Short Betw een 27 and 29 29 PROG_DATA- COPY
14 X_SYNC_IN- PSU/012
13 X_SYNC_IN+ POWER+ 1
POWER- 2
12 X_SYNC_IN_TRM+
Short Betw een 31 and 12 31 X_SYNC_IN-_COPY CHASSIS 3
GND 4
Recommended wiring diagram for the distributed KAM-500 system
674 QD/HW/SPF/L/0002 | 29 Jan. 2008

15 PCM DATA+ BCU/101
To Decom 16 PCM DATA- CHASSIS_ID(0) 4
CHASSIS 0
17 PCM DCLK+ CHASSIS_ID(1) 5
28V
18
CHASSIS_ID(2) 6
PCM DCLK-
CHASSIS_ID(3) 7
26 PROG_DATA- CHASSIS_ID(5) 37
28V return
28 PROG_DATA+ COPY
29 PROG_DATA- COPY BVDD 10
32 X_SYNC_OUTA+ FORMAT(0) 1
33 X_SYNC_OUTA- FORMAT(1) 2
52 CHASSIS FORMAT(2) 3
FORMAT(4) 8
33 TX_B+ ETH/001/C
34 TX_B-
18 TX_A+
19 TX_A-
1 RX_A+
2 RX_A-
7 PROG_A- PSU/012
POWER+ 1
6 PROG_A+
POWER- 2
T o PROG± CHASSIS_ID 32-63 8 PROG_B+ CHASSIS 3
9 PROG_B- GND 4
52 CHASSIS
DEC/003
1 PCM DATA(0)+
2 PCM DATA(0)-
3 PCM DCLK(0)+
4 PCM DCLK(0)-
5 PCM DATA(1)+
6 PCM DATA(1)-
7 PCM DCLK(1)+
8 PCM DCLK(1)-
26 PROG_DATA- CHASSIS_ID(2) 6
14 X_SYNC_IN- CHASSIS_ID(4) 36
13 X_SYNC_IN+ CHASSIS_ID(5) 37
16 PCM DATA-
15 PCM DATA+
BVDD 10
18 PCM DCLK-
17 PCM DCLK+
28 PROG_DATA+ COPY PSU/012
29 PROG_DATA- COPY 1
POWER+
30 X_SYNC_IN+_COPY POWER- 2
31 X_SYNC_IN-_COPY CHASSIS 3
GND 4
52 CHASSIS
CHASSIS_ID(2) 6
16 PCM DATA- CHASSIS_ID(3) 7
15 PCM DATA+
CHASSIS_ID(4) 36
18 PCM DCLK-
CHASSIS_ID(5) 37
17 PCM DCLK+
26 PROG_DATA- BVDD 10
25 PROG_DATA+
X_SYNC_IN- PSU/012
13
14 X_SYNC_IN+ POWER+ 1
POWER- 2
52 CHASSIS
CHASSIS 3
GND 4
Recommended wiring diagram for the Ethernet system
QD/HW/SPF/L/0002 | 29 Jan. 2008 675

BCU/101
15 PCM DATA+ CHASSIS_ID(0) 4
CHASSIS 0
16 PCM DATA- CHASSIS_ID(1) 5
17 PCM DCLK+ CHASSIS_ID(2) 6
28V
T o PCM or Ethernet 18 PCM DCLK- CHASSIS_ID(3) 7
CHASSIS_ID(4) 37
PROG_DATA+ CHASSIS_ID(5) 38
25
28V return
26 PROG_DATA-
BVDD 10
FORMAT(0) 1
FORMAT(1) 2
FORMAT(2) 3
FORMAT(4) 8
52
CHASSIS
13 CMD+ CBC/101
14 CMD-
PSU/012
25 RSP+ POWER+ 1
26 RSP- POWER- 2
CHASSIS 3
52 CHASSIS GND 4
BCU/102 CHASSIS_ID(0)
CHASSIS_ID(0) 4
26 RSP- CHASSIS 1 CHASSIS_ID(1) 5
25 RSP+ CHASSIS_ID(2) 6
CHASSIS_ID(3) 7
14 CMD-
CHASSIS_ID(4) 37
13 CMD+
CHASSIS_ID(5) 38
30 CMD+
31 CMD-
BVDD 10
28 RSP_COPY+
29 RSP_COPY-
52 CHASSIS
PSU/012
POWER+ 1
POWER- 2
CHASSIS 3
GND 4
26 RSP- CHASSIS 2 CHASSIS_ID(1) 5
25 RSP+ CHASSIS_ID(2) 6
CHASSIS_ID(3) 7
14 CMD- CHASSIS_ID(4) 37
13 CMD+ CHASSIS_ID(5) 38
30 CMD+
31 CMD-
BVDD 10
28 RSP+
29 RSP-
52 CHASSIS
PSU/012
POWER+ 1
POWER- 2
78 Ω 78 Ω
CHASSIS 3
GND 4
Recommended wiring diagram for the CAIS system
676 QD/HW/SPF/L/0002 | 29 Jan. 2008

Data transfer lines to SAM/DEC/007 Setting the format select lines
(DATA±, DCLK±) (FORMAT[3:0])
These lines are used to transfer data from one chassis Up to 15 formats can be stored in the controller (BCU/101).
(usually the MASTER) to the programing PC. They consist of Each has a binary address between 0000 to 1110 (1111 is
two twisted pairs. reserved for housekeeping information in the controller).
FORMAT(0) (LSB) is BCU/101 pin 1

DCLK+ goes from BCU/101 or to SAM/DEC/007
BCU/101 pin 17 pin 12 FORMAT(1) is BCU/101 pin 2
DCLK- goes from BCU/101 or to SAM/DEC/007 FORMAT(2) is BCU/101 pin 3

BCU/101 pin 18 pin 13
FORMAT(3) (MSB) is BCU/101 pin 8
DATA+ goes from BCU/101 or to SAM/DEC/007
0 is set by connecting to GND or by leaving the pin open.
DATA- goes from BCU/101 or to SAM/DEC/007 1 is set by connecting to BVDD (buffered 5V).
If multiple chassis and formats are used, the format select
Data transfer lines between chassis lines should be connected to all chassis.
(DATA±, DCLK±)
These lines are used to transfer data from one chassis to
another. They consist of two twisted pairs.
Data can be sent from either the primary or auxiliary
encoders to either channel of the dual decoder (DEC/003).
DCLK+ goes from to DEC/003 (7 for second

BCU/101 pin 17 pin 3 channel)
DCLK- goes from to DEC/003 (8 for second

DATA+ goes from to DEC/003 (5 for second

DATA- goes from to DEC/003 (6 for second

Setting the programming address select

lines (CHASSIS_ID[3:0])
Up to 16 chassis can be connected to the programming lines.
Each must be given a unique binary address from 0000 to
1111.
0000 is reserved for the MASTER.
CHASSIS_ID(0) (LSB) is BCU/101 pin 4
CHASSIS_ID(1) is BCU/101 pin 5
CHASSIS_ID(2) is BCU/101 pin 6
CHASSIS_ID(3) (MSB) is BCU/101 pin 7
0 is set by connecting to GND or by leaving the pin open.

1 is set by connecting to BVDD (buffered 5V).
QD/HW/SPF/L/0002 | 29 Jan. 2008 677

Connectors
Connectors on KAM-500
Pinouts for socket1 Where used Vendors Part no.
Bayonet connector for Townsend Coates MS27499-E-8-F-35PN

power supply Other source:
ABACUS POLAR
9-way micro-miniature Glenair International DCDM-9P-6E5-18-199/214/240

connector for power Other sources:
supply CINCH
52-way double-density Glenair International MRM11898

connector on KAD
modules
51-way Glenair International DCDM-51P-6E5-18-199/214/240

micro-miniature Other source:
connector on KAM ITT Cannon
modules CINCH

mating connector for
TDC/002/C modified so
as to accommodate
the sensor on the
module connector
51-way Glenair International MRM9422

micro-miniature
connector for modules
for MIL-STD-1553
monitoring applications
(direct coupled)
51-way Glenair International MRM11887

micro-miniature
for MIL-STD-1553

for MIL-STD-1553
(direct coupled)

for MIL-STD-1553
Connectors on Acal 61512-011

SAM/DEC/007/C Other source:
Connect Electronics
678 QD/HW/SPF/L/0002 | 29 Jan. 2008

Pinouts for socket1 Where used Vendors Part no.
The charge to digital converter Connectors on Microdot Connectors

module CDC/001/C contains four CDC/001/C Inc.
connectors (10-32 UNF thread jacks)
for use with the low-noise coaxial
connectors commonly used with
piezoelectric charge devices.
Often the cable and plug are part of
the sensor.
1. The connectors are viewed looking into the front face from above.
MIL-STD-681 system 1 color scheme
# Color (boxes) Color (words) # Color (boxes) Color (words)

1 Black 27 Black + Grey
2 Brown 28 Brown + Red
3 Red 29 Brown + Orange
4 Orange 30 Brown + Yellow
5 Yellow 31 Brown + Green
6 Green 32 Brown + Blue
7 Blue 33 Brown + Purple
8 Purple 34 Brown + Grey
9 Grey 35 Red + Orange
10 White 36 Red + Yellow
11 White + Black 37 Red + Green
12 White + Brown 38 Red + Blue
13 White + Red 39 Red + Purple
14 White + Orange 40 Red + Grey
15 White + Yellow 41 Orange + Yellow
16 White + Green 42 Orange + Green
17 White + Blue 43 Orange + Blue
18 White + Purple 44 Orange + Purple
19 White + Grey 45 Orange + Grey
20 Black + Brown 46 Yellow + Green
21 Black + Red 47 Yellow + Blue
22 Black + Orange 48 Yellow + Purple
23 Black + Yellow 49 Yellow + Grey
24 Black + Green 50 Green + Blue
25 Black + Blue 51 Green + Purple
26 Black + Purple 52 Green + Grey
QD/HW/SPF/L/0002 | 29 Jan. 2008 679

Some notes on common digital busses BTTL RS-232 RS-422 RS-485
In this section the physical layer (voltages, currents,
Type S/E S/E D/E D/E
impedances and so on) are discussed with respect to some
digital signal types associated with the KAM-500. This is Termination n/a n/a 100Ωm 60Ωmin
intended to help installation engineers check cable lengths, impedance in
cable impedances, termination impedances and data rate
limits for the various types of digital signal discussed.
10,000 ft 3 km
Buffered TTL RS-422/485
TTL (or Transistor-Transistor-Logic) logic levels are generally 1,000 ft 300 m

used for communication between ICs (Integrated Circuits) on Cable length RS-232
a PCB (Printed Circuit Board).
100 ft 30 m
BTTL or buffered TTL is used on a KAM-500 output
connector when a digital signal is required that will not be
transmitted far (say 30cm (1 ft.)) and does not require much 10 ft 3m
current drive (< 5mA) (for example the 1pps output of a time
code generator). 1 ft BTTL 30cm
BTTL is essentially a single-ended TTL driver/receiver with a 100 1k 10k 100k 1M 10M
100Ω resistance in series.
Data rate (bits/sec)
TTL levels are typically 0 to 0.8V for a logic low and 2.0 to
5.0V for a logic high. Figure 3: Cable length versus data rates
RS-232 Torque settings

RS-232 is generally used for slow (typically 9600bps)
transmission of data to or from a computer close by (typically Torque settings for KAM-500
less than 10m). The following are the recommended torque settings for
RS-232 is single ended. KAM-500 screws:
RS-422/485
Screw type Recommended Location
RS-422 was introduced as a high-speed differential-ended torque setting
(D/E) version of RS-232. RS-485 is similar to RS-422 except
that is designed for more drivers and receivers. Spring-mounted 0.25Nm (0.18 foot On each KAM-500
thumbscrews pound-force) module.
Being differential-ended, RS-422/485 is recommended in
applications requiring long cables (>1m) or fast data rates M3 hex head 0.6Nm (0.44 foot Sides and base plate
(>50kbps). However the start and end of the cable must be stainless steel pound-force) for chassis assembly.
terminated with a termination resistor (120Ω) and any stubs screw
from the bus must be kept less than 25cm (10 inches).
4-40 UNC 0.25Nm (0.18 foot Mating connector on
stainless steel pound-force) CON/KAD/002/CP and
screw CON/KAD/002/SR.
BTTL RS-232 RS-422 RS-485
Type S/E S/E D/E D/E
Maximum 1m 10m 1km 1km

cable length
Maximum data 750k 20k 10M 10M

rate (bps)
Logic LOW (Tx) 0V +5V -2V -1.5V

+15V
Logic HIGH 5V -5V +2V +1.5V

(Tx) -15V
Logic LOW 0.8V +3V +0.2V +0.2V

(Rx)
Logic HIGH 2.8V -3V -0.2V -0.2V

(Rx)
www.acracontrol.com
680 QD/HW/SPF/L/0002 | 29 Jan. 2008

ACRA Appendices
C O N T R O L
Abbreviations DOS
Disk Operating System
A
E
ac
Alternating current EEPROM
Electrically Erasable Programmable Read Only Memory
A/D
Analog to digital converter EMI
Electromagnetic interference
AGND
Analog ground EPROM
Erasable Programmable Read Only Memory
ARINC
Aeronautical Radio Incorporated ESD
Electrostatic discharge
B EU
European Union (directive/standard)
BC
Bus Controller
F
BCD
Binary Coded Decimal Fc
Filter cutoff frequency
BDMA
FIFO
Band Division Multiple Access First in first out
BIφ-(L) FPGA
Bi-phase - (Level) Field Programmable Gate Array
bps Fs
Bits per second Sampling frequency
FTB
C
First transmitted bit
ch.
FTI
Channel
Flight test instrumentation
CMRR
Common Mode Rejection Ratio H
CVSD HBM
Continuously Variable Sigma Delta Human Body Model, most commonly used model for
classifying device sensitivity to ESD
D
D/A I
Digital to analog converter IC
dB Integrated circuit
Decibel ID
dc Identifier
Direct current IEEE
DC/DC Institute of Electrical and Electronic Engineers
Direct current to direct current converter IENA
D/E Installation d’Essais pour les Nouveaux Avions
Differential-ended
I/O
DGND Input and output
Digital ground
IRIG(-B)
Inter-Range Instrumentation Group (standard B)
18 Oct. 2006 681

ISO Q
International Standards Organization
QA
Quality assurance
K
k R
kilo (1000)
RAM
K Random Access Memory
Multiplied by 1024
rms
Root mean square
L
RT
LSB
Remote terminal
Least significant bit
Rx
LTB
Receiv(er)
Last transmitted bit
S
M
S/E
max.
Single ended
Maximum
sps
MIL-STD
Samples per second
Military standard (USA)
min. T
Minimum
TBD
M/S To be determined
Master slave
T/C
MSB Thermocouple
Most significant bit
TTL
Transistor-transistor logic
N
Tx
n/a
Transmit(ter)
Not applicable
typ.
NC
Typical
Not connected (do not connect)
NLSB V
Next least significant bit
V
NMSB
Next most significant bit Volts
NRZ-(L)
Non-return to zero - (Level)
P
PC
Personal computer
PCB
Printed circuit board
PCM
Pulse code modulation
PCMCIA
Personal Computer Memory Card Interface Association, now
commonly called PC card
PLL
Phase locked loop
ppm
Parts per million
pps
Pulses per second
682 18 Oct. 2006

Receiving, inspection & warranties ACRA CONTROL MAKES NO OTHER WARRANTY,
EITHER EXPRESS OR IMPLIED, WITH RESPECT TO THIS
Receiving SOFTWARE, INCLUDING WARRANTIES OF
MERCHANTABILITY OR FITNESS FOR A PARTICULAR
Unpack the instrument and save the carton and packing PURPOSE. ACRA CONTROL MAKES NO WARRANTY,
material in case the instrument must be shipped to another EITHER EXPRESS OR IMPLIED, WITH RESPECT TO THE
site or returned to the factory for service. QUALITY OR PERFORMANCE OF THIS SOFTWARE.
ACRA CONTROL SHALL NOT BE LIABLE FOR
Inspection CONSEQUENTIAL, INCIDENTAL OR CONTINGENT
DAMAGES.
Inspect the exterior of the instrument for any visible signs of
damage that may have occurred during transit. If damaged, Some states do not allow the exclusion or limitation of implied
contact ACRA CONTROL Customer Service warranties or limitation of liability for incidental or
consequential damages, so the above limitation or exclusion
ACRA CONTROL system warranty may not apply to you.
ACRA CONTROL warrants that each product we sell you is
Software copyright protection
free from defects in labor and materials and shall conform to
its product specifications as defined in the product user This software is protected by state, U.S. and international
documentation. If the product does not function as warranted copyright treaty provisions. These copyright provisions apply
during the warranty period, we will repair or replace it without to your use of this software regardless of whether or not you
charge. agree to the following terms. Under law, copyright infringers
may be liable for actual damages sustained by the copyright
Warranty period owner and for punitive damages of up to $100,000 per
infringement. Unauthorized copyright of computer/instrument
The warranty period for hardware products is 12 months. The software, and attempts to do so, are also criminal violations,
warranty period begins on the date of invoice. with penalties that may exceed $100,000 in fines and 10
years in prison.
Limit of warranty
1. Unless restricted by an agreement with ACRA CONTROL,
Misuse, accident, modification, unsuitable physical or you are permitted to:
operating environment, improper maintenance, or damage
caused by a product for which we are not responsible will a.Use this software on only one computer/instrument and by
void the warranty. one user at a time.
Certain components may have separate warranty periods as b.Make one copy of this software, provided that:
stated in the product user documentation. (i)the copy is created as an essential step in the utilization of
THIS WARRANTY REPLACES ALL OTHER WARRANTIES, this software in conjunction with your machine and that it is
EXPRESSED OR IMPLIED, INCLUDING THE IMPLIED used in no other manner, or
WARRANTIES OF THE MERCHANTABILITY AND FITNESS (ii)that the copy is for archival purposes only and that all
FOR A PARTICULAR PURPOSE AND ANY OTHER archival copies are destroyed in the event that your continued
OBLIGATIONS OR LIABILITIES ON THE PART OF ACRA possession of this software should cease to be rightful.
CONTROL WHETHER IN CONTRACT, WARRANTY,
c. Sell this software, or any archival copy, only as part of the
NEGLIGENCE OR OTHERWISE. WE SHALL NOT BE
sale of all of your rights in this software, except that
LIABLE FOR AND DISCLAIM ALL CONSEQUENTIAL,
adaptations may be transferred only with the authorization of
INCIDENTAL AND CONTINGENT DAMAGES.
ACRA CONTROL.
Items not covered by warranty 2. You are not permitted to
We do not warrant uninterrupted or error-free operation of a a. Make copies of this software or documentation except as
product.We provide certain non-ACRA CONTROL products described above.
on an “as is” basis. Non-ACRA CONTROL manufacturers or b. Alter, modify or adapt this software or documentation
suppliers may provide their own warranties to you.Separate except as described above.
software warranty is provided with software user
documentation. c. Distribute, lease, rent or sublicense this software or
documentation.
ACRA CONTROL software warranty
Warning and cautions
ACRA CONTROL warrants that the removable physical
media (for example, diskette) shall be free of defects in labor Mise en garde et précautions
and materials for a period of ninety (90) days from the invoice Warnung und Sicherheitshinweise
date. If the physical media is defective, ACRA CONTROL will
replace it without charge. This WARNING note below is required by the FCC and
relates only to the interference potential of this equipment.
This is your sole remedy for product defects. In no event will This message is a direct quotation.
ACRA CONTROL’s liability exceed the price paid for the
software, regardless of the form of the claim. WARNING: The equipment generates, uses, and can radiate
radio frequency energy and if not installed and used in
ACRA CONTROL does not warrant that the software be accordance with the instructions manual, may cause
uninterrupted or error-free. interference to radio communications. As temporarily
18 Oct. 2006 683

permitted by regulation, it has not been tested for compliance upon the system as a whole and to implement preventive
with the limits for Class A computing devices pursuant to measures as appropriate to ensure that any failure of the
Subpart B or Part 15 of FCC Rules, which are designed to KAM-500 system will not impact on the safety of the aircraft.
provide reasonable protection against such interference.
Operation of this equipment in a residential area is likely to Sensor interfaces and ignition hazards
cause interference in which case the user at his own expense
will be required to take whatever measures may be required KAM-500 contains no moving parts or high voltage
to correct the interference. components (greater than 50V dc.) that could cause a spark.
However, it must be noted that certain KAM-500 modules are
Mise en garde: La notice d’avertissement ci-dessous est designed to provide sensor excitation for several different
exigée par la FCC et concerne uniquement le potentiel sensor types, (e.g. strain gages, accelerometers, resistive
d’interférence de cet appareil. Ce message est une citation temperature devices), taking the form of either voltage or
directe. Cet appareil dégage, utilise et peut produire une current excitation as appropriate.
énergie suffisante pour perturber le réseau de
communication s’il n’est pas utilisé selon les instructions While these excitation outputs are designed with output
données dans le manuel. Ayant obtenu une autorisation limiting functionality, in some circumstances dedicated barrier
temporaire par la règlementation, il n’a pas été testé or isolation devices may need to be inserted. It is the
comformément aux limites de la Class A des dispositifs responsibility of the end-user to analyze potential failure
informatiques suivant le sous-alinéa B ou l’alinéa 15 des modes of these external sensor interfaces and to implement
règles de la FCC, qui sont designées pour fournir une preventative measures as appropriate to ensure that any
protection raisonnable contre de telles inrterférences. failure of the KAM-500 system will not impact on the safety of
L’utilisation de cet appareil dans une zone résidentielle peut the aircraft.
provoquer des interférences et seul l’utilisateur est tenu de
prendre les précautions nécessaires pour corriger celles-ci. Power supplies
Warnung: Die erste unten aufgeführte Warnung wird von der The power supplies present in the KAM-500 are designed to
FCC gefordert und bezieht sich ausschließlich auf mögliche be fault tolerant, and incorporate current limiting in the event
Störungen, durch dieses Gerät verursacht. Der Text ist ein of short circuit developing on their outputs. A KAM-500
direktes Zitat. Die in diesem Gerät erzeugten verwendeten system should always be provided with power from a
und eventuell auch abgegebenen Radiowellen können, wenn dedicated, fused power bus, separate to other flight critical
das Gerät nicht entsprechend den Anweisungen im systems with appropriate circuit breakers to protect the power
Bedienungshandbuch installiert und eingesetzt wird, bus in the event of overload or the drawing of excessive
Störungen im Funkverkehr verursachen. Entsprechend einer transient or inrush current. It is the responsibility of the end-
einstweiligen Erlaubnis durch entsprechende Bestimmungen, user to analyze potential failure modes of the power supply
wurde das Gerät nicht auf die Einhaltung der Grenzwerte für and to implement preventative measures as appropriate to
Klasse A Computer-Einrichtungen gemäß Unterabschnitt B ensure that any failure of the KAM-500 system will not affect
oder Teil 15 der FCC Bestimmungen getestet, die einen the safety of the aircraft.
ausreichenden Schutz vor solchen Störungen gewährleisten
sollen. Bei Betrieb dieses Gerätes in Wohngebiet ist eine Heating effects
solche Störung möglich. Der Anwender wird in diesem Fall
KAM-500 is designed to operate in the temperature range of -
aufgefordert, auf eigene Kosten die notigen Maßnahmen zu
40ºC to +85ºC, where the quoted temperature is the
ergreifen, um diese Störungen zu beheben.
temperature of the KAM-500 chassis. The internal
temperature during normal operation can be approximately
General hazard statement 15ºC to 20ºC above chassis temperature depending on
module configuration. To prevent overheating during normal
Materials operation the, ensure the operating environment can
dissipate the heat generated by KAM-500. It is the
The KAM-500 contains no material that could be considered
responsibility of the KAM-500 end-user to analyze potential
hazardous to the operator during installation, operation, or
failure modes due to overheating and to implement
disposal of the unit. Furthermore it does not contain any
preventative measures as appropriate to ensure that any
hydraulic fluid, lubricant, coolant or battery fluid.
failure of the KAM-500 system will not impact on the safety of
the aircraft.
Bus interfaces
KAM-500 is flight test equipment and as such is not intended
for direct connection to flight critical avionics control busses
or flight critical instrumentation busses. Appropriate methods
of isolation in the event of KAM-500 failure must be employed
by the end user. To minimize the risk of interference with
avionics busses, modules that are avionics bus monitors use
interfaces where the transmission portion of the interface is
disabled using a hardwired method. For any modules that are
connected to a data bus either as bus monitors or to transmit
data on an instrumentation bus, it is the responsibility of the
end-user to analyze potential failure modes and their effect
www.acracontrol.com
684 18 Oct. 2006

ACRA Revision histories
C O N T R O L
Controlled document revision histories

The following data sheet for handling procedures for KAM-500 modules has been added to the KAM-500 Databook:
• Handling precautions
The content of the following data sheets has been revised since the last release of the KAM-500 Databook:
• ARI/103
• EBM/101
• ETH/101
• KIT/001
• MSB/103/B
Updated documents are marked by a in the Controlled document revision histories.
HW/BK/0002 | 1 Apr. 2009 685

Modules are arranged by alpha-numeric order of their titles.
DST/J/064 ACC/HSK/001 DATA SHEET

Date Action Reason
23 Jan. 2008 Updated table format.
1 Dec. 2006 Updated specifications tables.
18 Oct. 2006 Reformatted data sheet.
14 Jul. 2006 Clarified ACC/SCW/001 ordering options.
13 Apr. 2006 Updated ordering options to include ACC/SCW/001
10 Feb. 2006 Reformatted data sheet
3 Jul. 2003 Changed product number for heatsinks Part numbers renamed IAW ACRA CONTROL’s part numbering
scheme.
1 May 2002 Specifications: Updated to show new widths and 009/QB3 of Specification change.
heat sinks
1 Nov. 2000 Issued preliminary data sheet
DST/L/057 ACC/TRF/001 DATA SHEET

Date Action Reason
9 Nov. 2007 Updated specifications.
6 Jul. 2007 Corrected connector part number. Documentation error.
1 Mar. 2004 Added names of mating connectors. Customer feedback.
1 Oct. 2003 Corrected input and output specifications Documentation error.
1 Aug. 2002 Connector pinouts: added diagram of connector pinouts Customer feedback. To aid wiring of module.
1 Feb. 2002 Issued first release of data sheet
DST/R/010 ACD/BAC/002 DATA SHEET

Date Action Reason
18 Oct. 2006 Updated ordering information & reformatted data sheet.
10 Feb. 2006 Removed mechanical drawing of screw Documentation error
7 Sep. 2005 Enlarged mechanical drawing Customer feedback. Drawing was enlarged for clarity.
1 Jun. 2005 Issued first release of data sheet
DST/S/043 ACD/BAC/003 DATA SHEET

Date Action Reason
18 Oct. 2006 Updated ordering information & reformatted data sheet.
7 Sep. 2005 Enlarged mechanical drawing Customer feedback. Drawing was enlarged for clarity.
686 HW/BK/0002 | 1 Apr. 2009

DST/S/043 ACD/BAC/004 DATA SHEET
Date Action Reason
17 Jan. 2008 First release.
DST/P/014 ACD/CJB/001 DATA SHEET

Date Action Reason
13 Apr. 2006 Updated mechanical drawing for clarity Documentation error
7 Sep. 2005 Enlarged mechanical drawing. Customer feedback. Drawing was enlarged for clarity.
4 May 2004 Issued first release of data sheet
DST/K/003 ACM/EXT/001/B DATA SHEET

Date Action Reason
18 Oct. 2006 Reformatted data sheet and updated features.
7 Sep. 2005 Replaced reference to ACM/EXT/001 with reference to Specification change. New extender board released.
ACM/EXT/001/B
4 Jan. 2005 Removed references to ACC/EXT/002 Documentation error.
1 Apr. 2004 Changed ACC/EXT/001 to ACM/EXT/001 IAW part numbering

scheme
1 Feb. 2002 Title: Changed title of data sheet from “ACC/EXT/001” to Specification change. A second extender board was released.
“Extender boards”
Added details of ACC/EXT/002 Specification change. A second extender board was released.
1 Apr. 2001 Features: Added photograph of ACC/EXT/001
DST/R/053 ADC/002/C DATA SHEET

Date Action Reason
10 Jun. 2008 Updated specifications and module setup.
18 Oct. 2006 Updated Module setup, and reformatted data sheet.
13 Apr. 2006 Added Specifications table & Module Setup Documentation error.
1 Dec. 2005 Issued first release of data sheet.
DST/N/053 ADC/008 DATA SHEET

Date Action Reason
3 Nov. 2008 Updated “Getting the most from...”. Documentation error
HW/BK/0002 | 1 Apr. 2009 687

6 Jul. 2007 Updated parameter definition.
1 Jun. 2004 Updated Ordering Information to show that CON/KAD/002/CP Specification change.
is the default mating connector.
3 Nov. 2003 Removed all reference to the TOTAL output register.
1 Oct. 2003 Corrected block level diagram. Style consistency.
3 Jul. 2003 Updated ordering information to show new part number for Part number renamed IAW ACRA CONTROL’s part numbering
connector. scheme.
1 Apr. 2003 Issued first release of data sheet. KAD version (KAM version was DST/033)

Date Action Reason

Date Action Reason
11 Aug. 2008 Updated description for understanding filter delays.
10 Jun. 2008 Updated specifications and module setup; corrected filter

delay equation.
6 Jul. 2007 Updated specifications.
14 Jul. 2006 Corrected features Documentation error
13 Apr. 2006 Corrected ordering options Documentation error
7 Sep. 2005 Specifications: Clarified description of delay between Ch0- Documentation error.
Ch23 and Ch24-Ch47
Setup: Changed Settings for filter cutoff to 0.125Hz to 2.125Hz
8 Aug. 2005 Features: Changed Programmable gain, offset and filter Documentation error.
cutoff for each channel to Programmable digital gain offset
and filter cutoff for each channel
Description: Changed last paragraph to read: The signal Customer feedback.
conditioning on KAD/ADC/011/C consists of unity gain buffer
with the optional attenuation resistor at the input stage such
that the input options are ±10V or ±40V. Secondary gain and
offset are achieved digitally according to requested range.
Specifications: Changed Sampling restrictions: the maximum Customer feedback.
sampling rate per channel is 8500sps to Sampling restrictions:
maximum sampling rate per channel: 8.5kHz
Minimum sampling rate:0.5kHz
Maximum aggregate sampling rate: 408kHz
Updated sampling rates
Setup: Changed Offset to Secondary offset
Changed comment to read: For example if there is no
attenuation, a range from 5V to 10V can be set at the second
Documentation error.
stage (gain = 4, offset = 7.5V).
Customer feedback.
Removed references to linearization tables.
1 Jul. 2005 Issued first release of data sheet.

Date Action Reason
12 Sep. 2007 Added ADC/012/C/1V ordering option.
6 Jul. 2007 Updated specifications.
688 HW/BK/0002 | 1 Apr. 2009

13 Apr. 2006 Corrected ordering options Documentation error
8 Aug. 2005 Issued first release of data sheet. KAD version (KAM version was DST/N/002).
DST/R/022 ADC/014/D DATA SHEET

Date Action Reason
6 Jul. 2007 Corrected ordering options.
15 Sep. 2006 Added new Module setup format
13 Apr. 2006 Corrected features for 14-bit sampling Documentation error.
10 Feb. 2006 Corrected Ordering options, added paragraph on Adjust line to

the specifications table.
7 Sep. 2005 Getting the most from the KAD/ADC/014/D: Added Customer feedback.
description of KAD/ADC/014/D shared excitations
8 Aug. 2005 Issued first release of data sheet.
DST/U/028 ADC/105/B DATA SHEET

Date Action Reason
DST/U/033 ADC/106/C DATA SHEET

Date Action Reason
14 Jan. 2009 Issued first release of data sheet.
DST/U/032 ADC/109/C/QB120 DATA SHEET

Date Action Reason
DST/U/030 ADC/109/C/QB350 DATA SHEET

Date Action Reason
25 Feb. 2009 Renamed "Single ended analog inputs" table to "Three-wire Documentation error.
quarter-bridge inputs" table. Added offset drift as a
specification; removed gains <100.
31 Oct. 2008 Issued first release of data sheet.
DST/R/061 ADC/109/C/S1 DATA SHEET

Date Action Reason
DST/U/031 ADC/109/C/S2 DATA SHEET

Date Action Reason
DST/T/055 ADC/113 DATA SHEET

Date Action Reason
28 Jul. 2008 Updated specifications tables.
22 Jan. 2008 First release.
HW/BK/0002 | 1 Apr. 2009 689

DST/S/083 ADC/116 DATA SHEET
Date Action Reason
23 Oct. 2007 First release.
DST/U/034 ADC/117/B DATA SHEET

Date Action Reason
DST/P/065 ADC/118 DATA SHEET

Date Action Reason
6 Jul. 2007 Updated specification tables.
13 Apr. 2006 Corrected features & specifications for accuracy Documentation error.
8 Mar. 2006 Issued first release of data sheet.
DST/R/006 ADC/120 DATA SHEET

Date Action Reason
6 Jul. 2007 Updated specification tables.
13 Apr. 2006 Corrected features & specifications for accuracy Documentation error.
DST/P/030 ARI/001/B DATA SHEET

Date Action Reason
4 Sep. 2008 Updated specifications and “Getting the most from...” section
14 Jul. 2006 Updated Output registers Documentation error.
26 May 2006 Added CheckParity to Module Setup Documentation error.
17 Nov. 2005 Updated Output registers Documentation error.
7 Sep. 2005 Error codes: Reformatted table and added footnote Customer feedback.
1 Apr. 2005 Output Registers: Updated description of DATA_HI2 to show Documentation error.
that R[12:3] is Data [18:10]
1 Dec. 2004 Added Selection Guide Customer feedback.
DST/N/071 ARI/002 DATA SHEET

Date Action Reason
3 Sep. 2008 Updated specifications and circuit diagram.
10 Feb. 2006 Reformatted data sheet.
690 HW/BK/0002 | 1 Apr. 2009

connector. scheme.
1 Apr. 2003 Issued first release of data sheet. KAD version (KAM version was DST/L/044).
DST/R/018 ARI/103 DATA SHEET

Date Action Reason
24 Mar. 2009 ARI/103 modified to handle 64, 128, 256 and 512 words per
minor frames; updated data sheet accordingly.
3 Sep. 2008 Updated specifications.
DST/S/087 BCU/101/C DATA SHEET

Date Action Reason
29 Aug. 2008 Updated specifications tables.
9 Jun. 2008 Added requirement in revision history of data sheet for

BCU/101/B
13 Nov. 2007 Issued first release of data sheet.
DST/U/006 BCU/105/B DATA SHEET

Date Action Reason
11 Feb. 2009 Updated “Getting the most from...” section to include

paragraphs relating to Category 5 cable, Fragmentation and
Networked KAM-500 system.
30 Sep. 2008 Issued first release of data sheet.
DST/R/015 BIT/101 DATA SHEET

Date Action Reason
30 Sep. 2008 Updated specifications tables.
26 May 2008 Corrected formula condition for “Measuring the temperature of Documentation error.
the chassis” section, from
“...less than 50°C...”
to
“...more than 50°C...”
18 Oct. 2006 Updated circuit diagram and reformatted data sheet.
14 Jul. 2006 Updated Getting the Most from section.
26 May 2006 Moved Chassis temperature equation to ‘Getting the Most

from BIT/101’.
13 Apr. 2006 Corrected Register definition. Documentation error.
8 Mar. 2006 Reformatted data sheet.
DST/J/062 CABLES DATA SHEET

Date Action Reason
25 Feb. 2009 Updated the description of ACC/ASY/023 in Ordering

Information and replaced images of ACC/ASY/007/04 and
ACC/ASY/008/04 with images of CON/PSU/007/FL/100 and
ACC/ASY/022.
16 Jan. 2009 Updated Ordering Information and added a specification table

for ACC/ASY/023.
9 Oct. 2008 Updated Ordering Information and added a specification table ACC/CON/031/B was released.
for ACC/CON/031/B.
12 Sep. 2007 Added CON/PSU/007/FL/300.
HW/BK/0002 | 1 Apr. 2009 691

1 May 2007 Added new cables, and removed redundant cables. Added
Specifications tables.
14 Jul. 2006 Added cables & photos. Documentation error.
26 May 2006 Updated list of cables.
13 Apr. 2006 Added Cables
7 Sep. 2005 Removed references to CON/DEC/001 as it is no longer Customer feedback.

recommended for new programs.
Added Selection guide for CON/DEC/001/B.
8 Aug. 2005 Added CON/DEC/001/B cable Specification Change.
1 Aug. 2004 Description: Updated to show that the 15-way LAN open to Documentation error.
standard 15-way commercial D-type plug connector cable is
called the CON/DEC/001
1 Jun. 2004 Added description of CON/KAD/002/CP. Specification Change.
1 Mar. 2004 Added description of ACD/PIN/001. Customer feedback.
3 Nov. 2003 Corrected error in Description table. Documentation error.
1 Sep. 2003 Updated ordering information to show new part number for Part number renamed IAW ACRA CONTROL’s part numbering
connector. scheme.
3 Jul. 2003 Added descriptions of new double-density connectors.
1 Apr. 2003 Description: Added description of CON/051/M and Specification change. These double density connectors are now
CON/055/M. standard.
4 Mar. 2003 Description: Added description of ACC/CON/029. Specification change.
3 Dec. 2002 Description: Added the following text to the description of the Customer feedback.
ACC/CON/009 “The shield is connected to pin 22 for Bus 0
and pin 32 for Bus 1 (GND).”
1 May 2002 Description: Added description of ACC/CON/020. Specification change. The ACC/CON/020 was released.
1 Feb. 2002 Description: Added description of ACC/CON/016. Specification change. The ACC/CON/016 was released.
1 Jun. 2001 Description: ACC/CON/012, Added the text “The TTL lines Customer feedback.
are not connected”
1 Apr. 2001 Ordering information: Changed to show that cables no Customer feedback. Mating connectors required vary according to
longer come as standard with each system but must now be application.
ordered separately
Description: Changed to show that the following part Style consistency.
numbers have changed:
ACC/CON/006 changed to ACC/CON/013
ACC/CAB/004 changed to ACC/CON/012
ACC/CON/007 changed to ACC/CON/007/04
ACC/CON/008 changed to ACC/CON/008/04
DST/P/046 CBC/101 DATA SHEET

Date Action Reason
11 Nov. 2008 Reformatted circuit diagram.
18 Oct. 2006 Updated ordering information and reformatted data sheet.
8 Aug. 2005 Corrected status words Documentation error.
1 Jun. 2005 Issued first release of data sheet.
DST/P/064 CBM/101 DATA SHEET

Date Action Reason
692 HW/BK/0002 | 1 Apr. 2009

7 Sep. 2005 Error codes: Reformatted table and added footnote. Customer feedback.
DST/L/043 CBM/102 DATA SHEET

Date Action Reason
1 May 2008 Issued first release of data sheet.
DST/R/017 CDC/002 DATA SHEET

Date Action Reason
DST/S/032 CDC/101 DATA SHEET

Date Action Reason
DST/P/062 CHS/03F DATA SHEET

Date Action Reason
15 Apr. 2008 Corrected dimensions/width of module.
17 Nov. 2005 Added Weight of chassis Documentation error
DST/S/024 CHS/03U/D DATA SHEET

Date Action Reason
30 May 2008 Removed redundant cross-reference to “Power consumption” “Power consumption” chapter was removed from Databook.
chapter.
6 Jul. 2007 Updated power specifications.
15 Sep. 2006 Updated chassis schematic.
8 Mar. 2006 Issued first release of data sheet
DST/N/043 CHS/04L/B DATA SHEET

Date Action Reason
26 May 2008 Updated description.
1 Jul. 2005 Issued first release of data sheet
HW/BK/0002 | 1 Apr. 2009 693

Date Action Reason
12 Nov. 2008 Updated drawing on page 3.
chapter.
10 Feb. 2006 Issued first release of data sheet.

Date Action Reason
chapter.
DST/S/029 CHS/12R/D DATA SHEET

Date Action Reason
26 May 2006 Updated chassis weight. Documentation error

Date Action Reason
chapter.
1 May 2007 Reformatted data sheet.
DST/R/008 CON/KAD/002/CP DATA SHEET

Date Action Reason
11 Sep. 2007 Corrected selection path.
694 HW/BK/0002 | 1 Apr. 2009

DST/R/009 CON/KAD/002/SR DATA SHEET

Date Action Reason
11 Sep. 2007 Corrected selection path.
10 Feb. 2006 Removed mechanical drawing of screw and corrected number Documentation error
of pins supplied with CON/KAD/002/SR
1 Jun. 2005 Issued first release of data sheet.
DST/S/041 CON/KAD/005/CP DATA SHEET

Date Action Reason
30 Oct. 2007 Corrected module short description.
11 Sep. 2007 Issued first release of data sheet.
DST/T/095 CON/KAD/005/SR DATA SHEET

Date Action Reason
DST/N/077 DAC/001 DATA SHEET

Date Action Reason
3 Sep. 2008 Updated specifications and “Getting the most from...” section.
1 Mar. 2005 Updated to show that discretes update at the speed of the Documentation error.
fastest output rate.
Description: Updated description of Data transfer for clarity Customer feedback.
Removed list of discrete outputs
Specifications: Removed Sampling restrictions from table
Setup: Removed WINDOW_A and WINDOW_B from Setup
Input registers: Removed MEM_STS, TCG_STS, BUS_STS,
PAR_A, PAR_B from table. Added DISCRETE to table.
1 Mar. 2004 Updated description of KAD/DAC/001. Customer feedback.
connector. scheme.
1 Apr. 2003 Issued first release of data sheet. KAD version (KAM version was DST/031).
HW/BK/0002 | 1 Apr. 2009 695

DST/N/039 DEC/003 DATA SHEET
Date Action Reason
27 Nov. 2008 Updated specifications tables.
1 Apr. 2005 Connector pinout: Updated to show that pins 9 and 10 are Documentation error.
DNC.
3 Nov. 2003 Features: Updated to show that the KAD/DEC/003 accepts Documentation error. Typographical error.
D/E RS-422 not D/E 442.
connector. scheme.
4 Mar. 2003 Issued first release of data sheet. KAD version (KAM version was DST/020).
DST/U/002 DMY/001 DATA SHEET

Date Action Reason
23 Jan. 2008 Reformatted data sheet.
DST/N/067 DPI/002 DATA SHEET

Date Action Reason
22 Dec. 2008 Reformatted circuit diagram and pinout table.
connector. scheme.
1 Apr. 2003 Issued first release of data sheet. KAD version (KAM version was DST/L/046).
DST/R/023 DRE/CFM/002 DATA SHEET

Date Action Reason
5 Jan. 2009 Updated Description, Specifications and “Getting the most Data sheet updated to include MEM/103-related information.
from...” sections.
25 Jul. 2008 Updated module setup.
25 Oct. 2007 Added MEM/003/E.
1 May 2007 Added 12GB card.
18 Oct. 2006 Reformatted and renamed data sheet.
7 Sep. 2005 Added footnote stating the KAM/MEM/003 and Customer feedback.
KAM/MEM/003/B are not recommended for new programs
8 Aug. 2005 Issued first release of data sheet
DST/N/068 DSI/002 DATA SHEET

Date Action Reason
29 Sep. 2008 Updated specifications tables.
18 Oct. 2006 Added new Module Setup section and reformatted data sheet.
696 HW/BK/0002 | 1 Apr. 2009

connector. scheme.
DST/N/091 DSI/003/B DATA SHEET

Date Action Reason
29 Jan. 2009 Updated specifications tables.
26 Sep. 2008 Updated specifications, “Getting the most from...” and “Setting
up instrumentation” sections.
4 Oct. 2005 Corrected errors in Output Registers table. Documentation error.
1 Aug. 2004 Corrected errors in Output Registers table. Documentation error.
1 Jul. 2004 Changed “Product evolution” to “Selection guide”. Customer feedback.
Description: Amended description to describe size of FIFO Documentation error.
(8K)
1 Apr. 2004 Setup: Removed Hysteresis from setup section. Documentation error. Hysteresis cannot be setup directly from the
KSM GUI.
2 Feb. 2004 Added section on Product Evolution. Customer feedback.
DST/R/049 EBM/101 DATA SHEET

Date Action Reason
25 Mar. 2009 Updated notes in the “Getting the most from...” section to
explain limitations to PING replies.
26 Jan. 2009 Updated “Getting the most from...” section.
18 Mar. 2008 Added “AFDX monitoring” section; updated specifications.
27 Nov. 2007 Updated module setup section.
DST/P/005 ENC/005/B DATA SHEET

Date Action Reason
3 Nov. 2008 Updated specifications tables.
14 Jul. 2006 Corrected Features. Documentation error.
1 Dec. 2005 Clarified number of words which can be written to EEPROM Documentation error
1 Sep. 2004 Input Registers: Rewrote for clarity. Customer feedback.
1 Aug. 2004 Updated circuit diagram to show termination resistors on the Documentation error.
DATA and DCLK outputs.
HW/BK/0002 | 1 Apr. 2009 697

DST/S/092 ENC/106 DATA SHEET
Date Action Reason
10 Nov. 2008 Corrected typo. Documentation error.
3 Sep. 2008 Updated specifications and “Getting the most from...” section.
7 Jan. 2008 Updated module photo.
DST/T/052 ETH/101 DATA SHEET

Date Action Reason
2 Mar. 2009 Updated 'Getting the most from...' section to include recently
approved text for fragmentation and Category 5 cable.
26 Nov. 2008 Updated “Getting the most from...” section. “Getting the most from...” section updated to include details on
Ethernet fragmentation and reference to Category 5 cable.
DST/N/027 FBM/001/B DATA SHEET

Date Action Reason
23 Jul. 2008 Updated circuit diagram.
4 Oct. 2004 Issued first release of data sheet
DST/P/052 FBM/102 DATA SHEET

Date Action Reason
30 Jul. 2008 Updated error code table.
2 May 2005 Description: Updated to show that traffic refers to words on the Documentation error.
bus, and tags refer to associated information (time tags,
counts or INFO words).
Updated to correct error in reference to IEEE Std. 1384b- Documentation error.
2002, 4.2.1B.5.1.
1 Apr. 2005 Issued first release of data sheet.
DST/U/055 HANDLING PRECAUTIONS

Date Action Reason
DST/T/085 FBM/103/B DATA SHEET

Date Action Reason
698 HW/BK/0002 | 1 Apr. 2009

DST/R/048 JIG/UNI/001/C DATA SHEET
Date Action Reason
21 Oct. 2008 Updated Related Information and “Getting the most from...”
sections.
10 Feb. 2006 Added Circuit diagram
DST/J/063 KIT/001 DATA SHEET

Date Action Reason
26 Mar. 2009 Updated images of ACD/KIT tools.
21 Mar. 2008 Corrected length of wire to be stripped. Customer feedback.
18 Oct. 2006 Reformatted data sheet and renamed data sheet.
4 May 2004 Updated description of ACD/TOL/002 Customer feedback.
1 Oct. 2003 Corrected figure caption from cm to mm Documentation error
1 Sep. 2003 Removed reference to ACD/TOL/004. Customer feedback.
1 Aug. 2003 Added “Getting The Most From ACx/TOL/00x” section Customer feedback.
3 Jul. 2003 Added descriptions of new tools
1 Feb. 2002 Ordering information: Corrected Ordering information
1 Apr. 2001 Features: Changed to show that one set of tools is supplied Customer feedback. Customers ordering multiple systems only
with each order and not with each system. wanted one set of tools.
Description: Replaced tools ACC/TOL/001, ACC/TOL/002, Customer feedback.
ACC/TOL/003 with tools ACC/TOL/002, ACC/TOL/004,
ACC/TOL/005
DST/P/048 LDC/101 DATA SHEET

Date Action Reason
18 Dec. 2008 Reformatted specifications tables and ‘Getting the most...’

section.
26 May 2006 Reformatted Specifications table & updated selection path
13 Apr. 2006 Updated ordering options
DST/J/061 LID/001 DATA SHEET

Date Action Reason
1 Dec. 2006 Updated specifications tables. Renamed as LID/001, was Chassis Accessories
1 Mar. 2004 Updated description of chassis accessories. Customer feedback.
3 Jul. 2003 Added description of ACD/PIN/001. Specification change. New pins for double-density connectors.
HW/BK/0002 | 1 Apr. 2009 699

1 Jul. 2002 Photograph: Added photograph of placeholder lid
1 Feb. 2002 Description: Added description of new lid ACC/LID/002 Specification change. A new lid was released.
1 Apr. 2001 Ordering information: Changed to show that spare user-slot Customer feedback. A set for each chassis delivered was excessive.
lids and spare screws are no longer delivered as standard with One per program is generally preferable.
each system but must be ordered separately
DST/P/019 MBI/001/B DATA SHEET

Date Action Reason
18 Dec. 2008 Reformatted specifications tables and pinout table.
DST/T/087 MEM/003/E DATA SHEET

Date Action Reason
5 Jan. 2009 Removed Data retensions time row from CompactFlash

interface spec table.
1 Dec. 2008 Updated General specifications table. Values for power consumption updated.
DST/U/016 MEM/103 DATA SHEET

Date Action Reason
DST/T/054 MEM/004/B DATA SHEET

Date Action Reason
6 Apr. 2007 Issued first release of data sheet.
DST/N/150 MDC/002 DATA SHEET

Date Action Reason
3 Nov. 2008 Updated circuit diagram.
1 May 2007 Corrected parameter setup. Documentation error.
1 Dec. 2006 Corrected block diagram description and setting up Documentation error.
instrumentation.
18 Oct. 2006 Added new Module setup format and reformatted data sheet.
8 Mar. 2006 Corrected Getting the Most from section. Documentation error.
1 Dec. 2005 Issued first release of data sheet. KAD version (KAM version was DST/053).
DST/S/052 MDC/103 DATA SHEET

Date Action Reason
3 Sep. 2008 Updated specifications and data sheet summary.
DST/N/079 MSB/001/B DATA SHEET

Date Action Reason
700 HW/BK/0002 | 1 Apr. 2009

2 May 2005 Output Registers: Corrected error in description of REPORT. Documentation error.
1 Aug. 2004 Circuit diagram, updated to show that the FIFO is 16K deep. Documentation error.
Output Registers, added description of REPORT Documentation error.

Ordering information: Changed description of connectors to
specify that they are for MIL-STD-1553
1 Oct. 2003 Corrected pinout information for pin 46. Style consistency.
1 Sep. 2003 Corrected pinout information for pin 50. Documentation error.
connector. scheme.
1 Apr. 2003 Issued first release of data sheet. KAD version (KAM version was DST/N/005).
DST/S/053 MSB/103/B DATA SHEET

Date Action Reason
25 Mar. 2009 Updated power consumption figures in General specifications

table.
29 Jan. 2009 Updated specifications tables.
DST/N/074 PBM/001 DATA SHEET

Date Action Reason
26 May 2006 Updated MSB of output registers.
connector. scheme.
1 Apr. 2003 Issued first release of data sheet. KAD version (KAM version was DST/J/058).
DST/N/126 PBM/002 DATA SHEET

Date Action Reason
14 Jul. 2006 Corrected pinout. Documentation error.
3 Jul. 2003 Issued first release of data sheet. KAD version (KAM version was DST/J/058).
HW/BK/0002 | 1 Apr. 2009 701

DST/S/026 PSU/011 DATA SHEET
Date Action Reason
6 Nov. 2008 Updated circuit diagram, Electrical specifications table and

Related documents section.
15 Sep. 2006 Updated circuit diagram.
DST/R/098 PSU/012 DATA SHEET

Date Action Reason
6 Nov. 2008 Updated circuit diagram, Electrical specifications table and

Related documents section.
15 Sep. 2006 Updated circuit diagram.
DST/R/063 RTC/003 DATA SHEET

Date Action Reason
DST/R/083 SAM/DEC/007/C DATA SHEET

Date Action Reason
29 Oct. 2008 Updated circuit diagram and specifications tables.
DST/J/059 SBM/001 DATA SHEET

Date Action Reason
18 Dec. 2008 Reformatted specifications tables.
26 May 2006 Updated MSB of output registers. Consistency
26 May 2006 Updated MSB of output registers
1 Aug. 2003 Added section on Environmental restrictions. Customer feedback.
1 Oct. 2001 Updated photographs of module and connector Specification change. Two screws added to the lid.
1 Sep. 2001 Output registers: Changed Info bits from R(3) to R(13) Documentation error.
Specifications: Added the following text to Physical Customer feedback.
restrictions: “Due to the high power consumption, if using
more than two KAM/SBM/001 modules per chassis please
consult factory.”
1 Aug. 2001 Features: Changed the number of words that the module Documentation error.
parses traffic and tags for from up to 8191 to up to 8192
702 HW/BK/0002 | 1 Apr. 2009

1 Jun. 2001 Features: Changed the number of words that the module Documentation error.
parses traffic and tags for from up to 8192 to up to 8191
Output registers: Changed MES_COUNT to Style consistency. Changed to make consistent with the software.
MESSAGE_COUNT, MES_COUNT to MSG_CNT, Specification change.
TIME_MICRO to MICRO_TAG, TIME_LO to LO_TAG and
TIME_HI to HI_TAG
Report: Changed R[14:7] to R[14:5] and R[6:4] to R[4]
7 Feb. 2001 Features: Added photograph of KAM/SBM/001

Connector: Added photograph of connector
1 Nov. 2000 Features: Added Specification change.

z LED indication for traffic (green) and errors (red) for each
bus
z Detects CRC/FC/WC and invalid PA/DA errors Specification change.
Description: Changed the text of the description Style consistency. Table layout changed for new databook.
Specifications: Changed table layout Style consistency. Table layout changed for new databook.
Setup: Changed table layout Specification change.
Error codes: Added a table of Error codes
DST/N/064 SDC/001 DATA SHEET

Date Action Reason
25 Sep. 2008 Update to circuit diagram and specification tables.
18 Oct. 2006 Added new module Setup section and reformatted data sheet.
1 Sep. 2004 Setup: Updated to show that Offset is configurable, and that Documentation error.
the Angle range is -180º to +360º
connector. scheme.
1 Apr. 2003 Issued first release of data sheet. KAD version (KAM version was DST/034)
DST/N/069 SDI/001 DATA SHEET

Date Action Reason
23 Dec. 2008 Updated circuit diagram.
connector. scheme.
1 Apr. 2003 Issued first release of data sheet. KAD version (KAM version was DS/J/056).
DST/U/015 SDI/103 DATA SHEET

Date Action Reason
DST/P/033 TCG/001/C DATA SHEET

Date Action Reason
19 Dec. 2008 Reformatted circuit diagram and pinout table.
14 Jul. 2006 Updated output register. Consistency
13 Apr. 2006 Corrected register definition. Documentation error.
HW/BK/0002 | 1 Apr. 2009 703

1 Feb. 2005 Specifications: Input considerations, updated to show that Documentation error.
Input current is <20μA.
DST/T/096 TCG/102/C DATA SHEET

Date Action Reason
1 May. 2008 Updated specifications tables.
DST/M/056 TDC/001 DATA SHEET

Date Action Reason
15 Dec. 2008 Reformatted pinout table.
18 Oct. 2006 Added Module Setup section and reformatted data sheet.
14 Jul. 2006 Corrected Specifications. Documentation error.
DST/P/059 TDC/002/D DATA SHEET

Date Action Reason
1 May 2007 Corrected mating connector ordering information.
1 Mar. 2007 Removed KAM ordering option. Documentation error.
14 Jul. 2006 Corrected description. Documentation error.
26 May 2006 Added B & T99 Thermocouple options Documentation error.
DST/N/076 UAR/001 DATA SHEET

Date Action Reason
26 May 2006 Updated MSB of output registers Consistency
1 Sep. 2004 Setup: Updated to show that Stop bits are configurable Documentation error.
connector. scheme.
DST/N/133 UAR/002/C DATA SHEET

Date Action Reason
22 Dec. 2008 Updated Description section and reformatted pinout table.
14 Jul. 2006 512 characters corrected to 511 characters. Customer feedback.
26 May 2006 Updated MSB of output registers Consistency.
704 HW/BK/0002 | 1 Apr. 2009

4 Jan. 2005 Description: added resistor to DATA(0)± input on circuit Documentation error.
diagram.
Output registers: Corrected errors in description of DATA Documentation error.
(ODD) and DATA (EVEN).
1 Dec. 2004 Output registers: replaced description of parser with Documentation error.
description of DATA (ODD) and DATA (EVEN).
2 Feb. 2004 Added Product Evolution section. Customer feedback.
DST/R/004 UAR/102 DATA SHEET

Date Action Reason
2 Feb. 2009 Corrected typo. Documentation error
18 Dec. 2008 Updated circuit diagram and reformatted pinout table.
28 May. 2008 In Module setup, changed “LBT” to “First Bit Transmitted”
1 Mar. 2007 Corrected table formats. Documentation error.
1 Dec. 2006 Updated Specifications tables and Module Setup
13 Apr. 2006 Updated description.
DST/T/071 UAT/101 DATA SHEET

Date Action Reason
4 Oct. 2007 Updated Getting the Most from section.
DST/N/065 VDC/001 DATA SHEET

Date Action Reason
25 Sep. 2008 Updated specification tables and pinout table.
15 Sep. 2006 Added new Module setup format.
1 Mar. 2005 Setup: Added the following text: The KAD/VDC/001 places Customer feedback.
the CVSD data in the most significant bits of the 16-bit
KAD/VDC/001 parameter. The least significant bits are set to
zero. For example, if a 12-bit CVSD is selected, bit 15 to bit 4
of the KAD/VDC/001 parameter will contain the audio data,
where bit 15 is the oldest bit; and bits 3 to 0 will contain zeros.
1 Sep. 2004 Setup: Updated to show that Bits per Word can be set from 8 Documentation error.
to 16
1 Aug. 2004 Clarified description of sampling rates Customer feedback.
connector. scheme.
HW/BK/0002 | 1 Apr. 2009 705

1 Apr. 2003 Issued first release of data sheet. KAD version (KAM version was DST/J/054).
DST/P/045 VID/103 DATA SHEET

Date Action Reason
29 Jul. 2008 Updated module setup; changed input labels to match pinout
table.
QD/HW/SPF/L/0001 ENVIRONMENTAL SPECIFICATIONS

Date Action Reason
30 May 2008 Removed redundant cross-reference to “Power consumption” “Power consumption” and “Masses & dimensions” chapters were
and “Masses & dimensions” chapters. removed from Databook.
11 Sep. 2007 Added calibration interval for analog modules.
1 Dec. 2006 Added explosive decompression test.
2 May 2005 Rewritten for clarity. Customer feedback.
4 Jan. 2005 3.1 Overview: Updated description of altitude to show that the Documentation error.
KAM-500 is operational at 75,000 feet (22,860 meters)
4 Oct. 2004 3.10 Electromagnetic emissions and susceptibility Documentation error.

Corrected to show that RS-103 measures radiated
susceptibility between 400MHz and 18GHz
4 May 2004 3.10 Electromagnetic emissions and susceptibility Customer feedback.

Added the following text:
For EMC compliance all cables should be shielded and all
shields should be connected to the KAM-500 chassis via the
connector backshell.
1 Apr. 2004 3.4 Temperature: Corrected error in text. Documentation error.
1 Mar. 2004 Updated Environmental Specifications to include details of Specification change.

new certifications obtained
1 Apr. 2003 3.6 Shock, Design considerations Specification change. The KAD/ADC/006 and KAD/ADC/009 have
Changed to reference the KAD/ADC/006 and KAD/ADC/009 replaced “KAM” modules as standard.
1 Oct. 2002 3.6 Shock, Design considerations Documentation error.

Changed reference to resolver to synchro
1 Aug. 2002 Overview: Updated to show that MIL-STD-810F Method Specification change.
514.1 Procedure I certification has been obtained
4 Jun. 2002 Updated Environmental Specifications to include details of Specification change.

new certifications obtained, i.e.
MIL-STD-810F Method 514.1 Procedure I
Electrical Bonding Test AC/KAM-500-II/SLTP/1.4, Paragraph
3
Electrical Insulation Test, High Voltage Test BS3G100, Part 4,
Section 1, Subsection 1, Paragraph 5.1
Electrical Insulation Test, Insulation Resistance Test
BS3G100, Part 4, Section 1, Subsection 1, Paragraph 5.2
Electrical Insulation Test, Leakage Current Measurements
BS3G100, Part 4, Section 1, Subsection 1, Paragraph 5.3
1 May 2002 Updated Environmental Specifications to include details of Specification change.

MIL-STD-810F Method 516.5 Procedure V - modified
MIL-STD-810F Method 506.4, Procedure III
1 Mar. 2002 Updated Environmental Specifications to include details of Specification change.

BS 3G100 Part 2 Section 2
CS101
EN61000-4-2:1995
GAMME-EG-13
IEC 801-2:1991 (ESD)
MIL-STD-810F Methods 500.4 Procedure II and III
MIL-STD-810F Methods 501.4 and 502.4 Procedure I
MIL-STD-810F Method 507.4
706 HW/BK/0002 | 1 Apr. 2009

1 Aug. 2001 3.8 Electromagnetic emissions and susceptibility: Documentation error.
Changed text to “The KAM-500 is designed to meet, and will
be certified in accordance with” from “The KAM-500 has been
certified in accordance with”
1 Apr. 2001 3.7 Vibration: In the random vibration; functional, the Documentation error. The earlier document had a typographical error.
spectrum changed from 0.4g2/Hz from 15 to 89.2Hz
+4dB/octave from 89.2 to 300Hz to 0.04g2/Hz from 15 to
89.2Hz +4dB/octave from 89.2 to 300Hz.
In the random vibration: endurance, the spectrum changed
from 0.4g2/Hz from 15 to 30.7Hz +4dB/octave from 30.7 to
300Hz to 0.04g2/Hz from 15 to 30.7Hz +4dB/octave from 30.7
to 300Hz
1 Jan. 2001 Issued preliminary data sheet
QD/HW/SPF/L/0002 EQUIPMENT INTERFACE

Date Action Reason
14 Jul. 2006 Corrected 'Recommended wiring diagram for the Documentation error.
distributed KAM-500 system'.
13 Apr. 2006 Updated to include new PSU modules
7 Sep. 2005 4.3 Chassis Connections: Corrected error in Figure 1.5 Documentation error.
1 Apr. 2005 4.4.1 Connectors on KAM-500: Corrected error in part Documentation error. Typographical error.
number for Bayonet connector for power supply.
1 Mar. 2005 Figure 1.5: Corrected error on wiring diagram for distributed Documentation error.
KAM-500 system.
1 Dec. 2004 4.4.1 Connectors on KAM-500: added footnote: “The Customer feedback.
connectors are viewed looking into the front face from above.”
Added section 4.6 Torque Settings Customer feedback.
1 Aug. 2004 4.4.1 Connectors on KAM-500: Added description of the Specification change.
CON/KAD/001/SR
4 May 2004 Added the following text: Customer feedback.

For EMC compliance all cables should be shielded and all
shields should be connected to the KAM-500 chassis via the
connector backshell.
Replaced references to KAM/PSU/003 and KAM/PSU/005 KAM/PSU/007 is standard power supply offered to customers.
with KAM/PSU/007
1 Aug. 2003 4.3.2 Programming Lines (PROG_DCLK±, PROG_DATA±)

Updated description to show that the SAM/DEC/007 is ACRA
CONTROL’s standard decoder card.
1 Apr. 2003 Updated to include wiring diagram for the KAD/ENC/004 and Specification change.
to describe new double-density connectors.
1 Oct. 2001 Programming lines: Added the text “On the SAM/DEC/005 Style consistency. Changed to make termination clearer.
these lines are terminated internally as standard.”
1 Apr. 2001 Note, Removed the text: In 2001, ACRA CONTROL will offer Specification change.
a controller with less inter-chassis wires. In particular
FORMAT[3:0], X_CLK±, PROG_CLK± and IRIG time
connections to multiple chassis will be combined into the
X_SYNC± pair. Please contact ACRA CONTROL for details.
Notes for the System Installer: Replaced Specification change.
“KAM/PSU/003” by “KAM/PSU/003 or
KAM/PSU/005”
Connectors on KAM/CDC/001: Added the following: Specification change.
CONNECTORS ON KAM/CDC/001
The charge to digital converter module KAM/CDC/001
contains 4 connectors (10-32 UNF thread jacks) for use with
the low-noise co-axial connectors commonly used with
piezoelectric charge devices.
Often the cable and plug are part of the sensor. One source of
mating connector is Microdot Connectors Inc.
1 Jan. 2001 4.5.1 Buffered TTL: Added: TTL levels are typically 0 to 0.8V Specification change.
for a logic low and 2.0 to 5.0V for a logic high.
HW/BK/0002 | 1 Apr. 2009 707

LIST OF CONTROLLED DRAWINGS
Ref. Title Issue date Reason for change
KAM/CHS/03U Plan, elevation and end-view of CHS/03U 3 Dec. 2004
KAM/CHS/12R Plan and end-view of CHS/12R 3 Dec. 2004
DRW/J/005 Plan, elevation and end-view of thermocouple block 1 Dec. 1999 Drawings were changed for hardware manual
DRW/J/006 Plan, elevation and end-view of generic user-module 3 Dec. 2004
DRW/J/007 Isometric view of chassis with protruding module 16 Jul. 2004
DRW/J/008 Recommended wiring for distributed system 1 Mar. 2005
KAM/500 End-view of KAM-500 illustrating cabling bend radius 3 Dec. 2004
Other data sheets available from ACRA CONTROL

Data sheets are available for the following legacy modules which are not recommended for new programs.
Ref. Description
ADC/002/B 2-ch. D/E analog to digital converter at 100ksps
ADC/003 15-ch. thermocouple A/D converter with reference compensation
ADC/003/B 15 channel thermocouple A/D convertor module with reference compensation
ADC/005 8-ch. D/E analog to digital converter with signal conditioning
ADC/006 6-ch. S/E accelerometer (ICP) A/D converter with signal conditioning
ADC/009/S1 8-ch. bridge A/D conv. with excitation and signal conditioning
ADC/009/QB/120 8 channel A/D conv. module, with exc. and sig. cond. for ¼-bridge 120Ohm strain gages
ADC/010 2-ch. D/E analog to digital converter. 14-bits at 100ksps
ADC/010/B 2-ch. D/E analog to digital converter. 14-bits at 100ksps
ADC/011 48 channel S/E analog to digital convertor
ADC/011/B 48 channel S/E analog to digital convertor
ADC/012 24 channel D/E analog to digital convertor
ADC/012/B 24 channel D/E analog to digital convertor
ADC/013 16-ch. ¼-bridge A/D conv. with excitation and sig. con for PT100s
ADC/013/B 16-ch. ¼-bridge A/D conv. with excitation and sig. con for PT100s
ADC/013/C 16 channel ¼-bridge A/D convertor with excitation and signal conditioning for PT100
ADC/013/D 16 channel ¼-bridge A/D convertor with excitation and signal conditioning for PT100
ADC/013/E 16 channel ¼-bridge A/D converter with excitation and signal conditioning for PT100
ADC/014 16 channel bridge A/D convertor with voltage excitation and signal conditioning
ADC/014/B 16 channel bridge A/D convertor with voltage excitation and signal conditioning
ADC/014/C 16 channel bridge A/D convertor with voltage excitation and signal conditioning
ADC/018 12-ch. bridge A/D conv. with excitation, balancing and signal conditioning
ADC/020 12-ch. bridge A/D conv. with excitation, balancing and signal conditioning
ADC/105 8 channel D/E analog-to-digital converter with signal conditioning
ADC/106/B 6-channel S/E accelerometer (ICP) analog-to-digital converter with sig. conditioning
708 HW/BK/0002 | 1 Apr. 2009

Ref. Description
ADC/109/B/QB120 8-ch. A/D converter, with current exc. and sig. cond. for ¼-bridge 120Ω strain gages
ADC/109/B/QB350 8-ch. A/D converter, with current exc. and sig. cond. for ¼-bridge 350Ω strain gages
ADC/109/B/S1 8-ch. bridge A/D converter module, with voltage excitation and signal conditioning
ADC/109/B/S2 8-ch. bridge A/D converter with voltage excitation, sense lines and signal conditioning
ADC/117 8 channel A/D converter with bridge signal conditioning & constant current excitation
ARI/001 8 Channel ARINC-429 Bus Monitor
BCU/002 A CAIS compliant backplane controller for any KAM-500 chassis
BCU/102 A CAIS backplane controller for any KAM-500 chassis
CHS/03U/B KAM-500 chassis with 3 user-slots
CHS/03U/C KAM-500 chassis with 3 user-slots
CHS/12R/B KAM-500 circular form chassis with 12 user slots
CHS/12R/C KAM-500 circular form chassis with 12 user-slots
DSI/003 24 channel bi-level input module with counters and time tagging
ENC/004/B KAM-500 controller with IRIG-106 PCM encoder
ETH/001/B A 100 Base TX Ethernet interface for programming and data acquisition in KAM-500 systems
ETH/001/C A 100 base Tx ethernet interface for programming and data acquisition
MBI/001 A MIL-STD-1553 remote terminal
MBI/102 A MIL-STD-1553 remote terminal
MDC/001 8 x 64-ch. external multiplexing A/D converter
MEM/001 8M parameter EEPROM memory module
MEM/002 64 million parameter EEPROM memory module
MEM/003/B KAM-500 CompactFlash® memory module
MEM/003/C KAM-500 high speed CompactFlash® memory module
MEM/003/D KAM-500 high speed CompactFlash® memory module
MSB/001/B Dual redundant MIL-STD-1553 bus monitor
MSB/003 Dual redundant MIL-STD-1553 bus monitor with Mode Code 17 support
MSB/003/B Dual redundant MIL-STD-1553 bus monitor with Mode Code 17 support
MSB/103 Dual redundant MIL-STD-1553 bus monitor with Mode Code 17 support
PSU/007 +5V, ±7V, and ±12V power supply unit for KAM-500 chassis
PSU/009 +5V, ±7V, and ±12V power supply unit for KAM-500 chassis
PSU/010 +5V, ±7V and ±12V power supply unit for KAM-500 chassis
RTC/002 Real-time clock generator for KAM-500 systems
SAM/VAD/001 Video compression replay unit
SDC/001 2-ch. synchro to digital converter
TCG/102/B Combined GPS and IRIG input module
VID/001 Single-channel video interface to external video encoder
HW/BK/0002 | 1 Apr. 2009 709

Ref. Description
KAM/ADC/005/5KHZ 8-ch D/E analog to digital converter with signal conditioning
KAM/ADC/009/S1/5KHZ 8-ch. bridge A/D conv. with excitation and signal conditioning
KAM/ADC/009/S4 8-ch. bridge A/D conv. with excitation and signal conditioning
KAM/ADC/009/S5 8-ch. bridge A/D conv. with excitation, sense and signal conditioning
KAM/CBC/001 CAIS bus controller
KAM/UAR/003 A 2-channel RS-422 (sync-bit=address) parser
KAM/ISO/001 4-ch. D/E input signal isolated 4-ch. S/E output
KAM/MBC/001 A MIL-STD-1553 bus controller for FTI applications
KAM/MEM/003 CompactFlash™ memory module
KAM/MSB/002/B Dual redundant MIL-STD-1553 bus monitor with mode code 17 support
Data sheets are available for the following non-standard modules.
Ref. Description
ADC/001 32-ch. S/E analog to digital (A/D) converter
ADC/005/5KHZ 8-ch D/E analog to digital converter with signal conditioning
ADC/005/C1 32-ch. S/E analog to digital (A/D) converter
ADC/009/QB/100 8-ch. ¼-bridge A/D conv. with excitation and sig. con for PT100s
ADC/009/QB/350 8-ch. ¼-bridge A/D conv. with excitation and sig. con for ¼-bridge 350W strain gages
KAM/ADC/009/S1/5KHZ 8-ch. bridge A/D conv. with excitation and signal conditioning
ADC/009/S1/NF 8-ch. bridge A/D conv. with excitation and signal conditioning
ADC/009/S2 8-ch. bridge A/D conv. with excitation, sense and signal conditioning
ADC/009/S2/ET 8-ch. bridge A/D conv. with excitation, sense and signal conditioning
ADC/009/S4 8-ch. bridge A/D conv. with excitation and signal conditioning
ADC/009/S5 8-ch. bridge A/D conv. with excitation, sense and signal conditioning
ADC/011/X1 48 channel S/E analog to digital convertor with X1 option
ADC/011/C/X1 48 channel S/E analog to digital convertor with X1 option
ADC/014/R2 12-ch. ¼-bridge 350-ohm A/D convertor with current excitation and 4-ch. 32 volt D/E
ADC/017 8-ch. bridge A/D conv. with constant excitation current and signal conditioning
ADC/021 16 channel multiplexing D/E analog-to-digital converter
ADC/017/AB1/ET 8-ch. bridge A/D conv. with constant excitation current and signal conditioning
ADC/019/100 8-ch. ¼-bridge A/D conv. with excitation and sig. con for PT100s
BCU/001 A CAIS compliant backplane controller for any KAM-500 chassis
BCU/001/B KAM-500 backplane controller with IRIG-106 PCM encoder
BCU/001/CX KAM-500 Backplane Controller With IRIG-106 PCM Encoder
BCU/003 KAM-500 backplane controller with T-BUS Interface
BCU/003/3SB KAM-500 backplane controller with Tbus interface (3 bits)
BCU/101 KAM-500 backplane controller with IRIG-106 PCM encoder
CBC/001 CAIS bus controller
CDC/001 4-channel charge-to-digital converter for piezoelectric devices
710 HW/BK/0002 | 1 Apr. 2009

Ref. Description
CDI/101 Interface module for the cockpit display unit (OBE/CDU/001)
CHS/03F/MB1 KAM-500 chassis with 3 non-standard user-slots
CHS/04L/AB1/ET KAM-500 chassis with 4 user-slots
CHS/04L/ET KAM-500 chassis with 4 user-slots
CHS/05F/SC KAM-500 Chassis with 5 user-Slots
CHS/06U/B/AB1 KAM-500 chassis with 6 user-slots
CHS/06U/C/AB1 KAM-500 chassis with 6 user-slots with AB1 option
CHS/06U/D/AB2 KAM-500 chassis with 6 user-slots with AB2 option
CHS/09U/C/MB2 KAM-500 chassis with 9 user-slots and MB2 option
CHS/09U/D/MB2 KAM-500 chassis with 9 user-slots and MB2 option
CHS/09U/MB1 KAM-500 chassis with 9 user-slots
CHS/12R/AG2 KAM-500 system with 12 user-slots
CHS/12R/B/AG2 KAM-500 system with 12 user-slots
CHS/13U/B/CA1 KAM-500 chassis with 13 user-slots
DEC/002 2-ch. IRIG-106 PCM decoder/merger
DPI/001 8K x 64-bit external dual port RAM reader
DPI/002 16K x 16-bit external dual port RAM reader
DSI/004 24 channel optoisolated digital module
ENC/003 KAM-500 controller with IRIG-106 PCM encoder
ENC/004/B/ET KAM-500 controller with IRIG-106 PCM encoder
ENC/004/ET KAM-500 controller with IRIG-106 PCM encoder
ENC/006/HA IRIG-106 PCM encoder with pre-modulation filter (PMF) output
FBM/001 A single EF-2000 FCS bus monitor module
JAM/ADC/009/QB/100R Test jig for calibrating quarter bridges
JAM/ADC/009/QB/250R Test jig for calibrating quarter bridges
JAM/ADC/009/S1 Test jig for balancing (offset nulling) KAM/ADC/009/S1
LDC/001 2-ch. LVDT/RVDT to digital converter
LRU/001/MB1 Meteor ALD DAU for use in EIM-F location
LRU/001/MB2 Meteor ALD DAU for use in EIM-F location
MAT/001/B An SAF-C167-CR-LM Microcontroller-based module for FTI applications
MBC/001 Command-only MIL-STD-1553 bus controller
MEM/001 8M parameter EEPROM memory module
MEM/002 64 million parameter EEPROM memory module
MSB/001/B/TC Dual redundant MIL-STD-1553 bus monitor
MSB/002 Dual redundant MIL-STD-1553 bus monitor with mode code 17 support
MSB/002/B/TC Dual redundant MIL-STD-1553 bus monitor with mode code 17 support
PBM/002/BA1 A Parser for the MC (and ENMC) Link with BA1 options
PDC/001 14-channel pressure acquisition module with temperature compensation
HW/BK/0002 | 1 Apr. 2009 711

Ref. Description
PDC/001/ET 14-channel pressure acquisition module with temperature compensation
PSU/003 Power supply unit for KAM-500 systems
PSU/005 Power supply unit for 3-user-slot KAM-500 system
PSU/006 Power supply unit for KAM-500 chassis
PSU/006/ET Power supply unit for KAM-500 chassis
PSU/007/AG2 Power supply unit for KAM-500 chassis
PSU/007/NC +5V, ±7V and ±12V power supply unit for KAM-500 chassis with NC option
PSU/008/B Power supply unit for KAM/CHS/03F chassis
PSU/013/SC +5V and ±12V power supply unit for KAM-500 chassis
RTC/001 A real-time clock module for KAM-500 systems
SAM/DEC/005 IRIG-106 PCM decoder card with KAM-500 programming interface
SAM/DEC/007/B/UT KAM-500 programming interface with IRIG-106 PCM decoder
SAM/DEC/007 KAM-500 programming interface with IRIG-106 PCM decoder
SAM/DEC/007/P KAM-500 programming interface
SDC/001 2-ch. synchro to digital converter
SIG/101 Versatile signal generator controlled via RS-232/RS-422 link
TCG/001 IRIG-B time code reader and generator
TCG/001/B IRIG-B time code reader and generator
TDC/002/B 15-ch. thermocouple A/D converter with reference compensation
TDC/002/B/ET 15-ch. thermocouple A/D converter with reference compensation
TDC/002/C 15-ch. thermocouple A/D converter with reference compensation
TDC/002/C/ET 15-ch. thermocouple A/D converter with reference compensation
TDC/002/D/MB1 15-ch. thermocouple A/D converter with reference compensation
TDC/002/D/10M 15 channel thermocouple analog-to-digital converter with reference compensation
TDC/004 12-ch. A/D conv. with excitation and sig. con for PT100s
TDC/004/ET 12-ch. A/D conv. with excitation and sig. con for PT100s
TDC/005 15-ch. thermocouple A/D converter with external temperature sensor
TDC/006 15 channel thermocouple analog-to-digital converter with reference channel
UTL/001 IRIG-B time code reader, XSYNC generator and BIT module
UTL/102 Format select line sequencing module
VID/002 MPEG-2 encoder for KAM-500
UAR/003 A 2-channel RS-422 (sync-bit=address) parser
www.acracontrol.com
712 HW/BK/0002 | 1 Apr. 2009

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KAM-500 Databook

Data sheets Data sheets (continued)

ACC/HSK/001 23 Jan. 2008 | DST/J/064 CBM/101 5 Sep. 2008 | DST/P/064

ACC/TRF/001 21 Jan. 2008 | DST/L/057 CBM/102 1 May 2008 | DST/L/043

ACD/BAC/002 23 Jan. 2008 | DST/R/010 CDC/002 18 Oct. 2006 | DST/R/017

ACD/BAC/003 23 Jan. 2008 | DST/R/011 CDC/101 10 Jun. 2008 | DST/S/032

ACD/BAC/004 17 Jan. 2008 | DST/S/043 CHS/03F 15 Apr. 2008 | DST/P/062

ACD/CJB/001 23 Jan. 2008 | DST/P/014 CHS/03U/D 30 May 2008 | DST/S/024

ACM/EXT/001/B 23 Jan. 2008 | DST/K/003 CHS/04L/B 26 May 2008 | DST/N/043

ADC/002/C 10 Jun. 2008 | DST/R/053 CHS/06U/D 12 Nov. 2008 | DST/S/013

ADC/008 3 Nov. 2008 | DST/N/053 CHS/09U/D 30 May 2008 | DST/S/014

ADC/010/C 10 Jun. 2008 | DST/R/046 CHS/12R/D 28 Jan. 2008 | DST/S/029

ADC/011/C 11 Aug. 2008 | DST/R/044 CHS/13U/D 30 May 2008 | DST/S/028

ADC/012/C 10 Jun. 2008 | DST/R/045 CON/KAD/002/CP 23 Jan. 2008 | DST/R/008

ADC/014/D 10 Jun. 2008 | DST/R/022 CON/KAD/002/SR 23 Jan. 2008 | DST/R/009

ADC/105/B 18 Aug. 2008 | DST/U/028 CON/KAD/005/CP 23 Jan. 2008 | DST/S/041

ADC/106/C 14 Jan. 2009 | DST/U/033 CON/KAD/005/SR 23 Jan. 2008 | DST/T/095

ADC/109C/QB120 22 Aug. 2008 | DST/U/032 DAC/001 3 Sep. 2008 | DST/N/077

ADC/109/C/QB350 25 Feb. 2009 | DST/U/030 DEC/003 27 Nov. 2008 | DST/N/039

ADC/109/C/S1 22 Aug. 2008 | DST/T/097 DMY/001 23 Jan. 2008 | DST/U/002

ADC/109/C/S2 22 Aug. 2008 | DST/U/031 DPI/002 22 Dec. 2008 | DST/N/067

ADC/113 28 Jul. 2008 | DST/T/055 DRE/CFM/002 5 Jan. 2009 | DST/R/023

ADC/116 10 Jun. 2008 | DST/S/083 DSI/002 29 Sep. 2008 | DST/N/068

ADC/117/B 22 Aug. 2008 | DST/U/034 DSI/003/B 29 Jan. 2009 | DST/N/091

ADC/118 28 Jul. 2008 | DST/P/065 EBM/101 25 Mar. 2009 | DST/R/049

ADC/120 28 Jul. 2008 | DST/R/006 ENC/005/B 3 Nov. 2008 | DST/P/005

ARI/001/B 4 Sep. 2008 | DST/P/030 ENC/106 10 Nov. 2008 | DST/S/092

ARI/002 3 Sep. 2008 | DST/N/071 ETH/101 2 Mar. 2009 | DST/T/052

ARI/103 24 Mar. 2009 | DST/R/018 FBM/001/B 27 Nov. 2008 | DST/N/027

BIT/101 30 Sep. 2008 | DST/R/015 FBM/102 10 Nov. 2008 | DST/P/052

BCU/101/C 29 Aug. 2008 | DST/S/087 FBM/103/B 5 Feb. 2008 | DST/T/085

BCU/105/B 11 Feb. 2009 | DST/U/006 Handling precautions 3 Mar. 2009 | DST/U/055

Cables 25 Feb. 2009 | DST/J/062 JIG/UNI/001/C 21 Oct. 2008 | DST/R/048

CBC/101 11 Nov. 2008 | DST/P/046 KIT/001 26 Mar. 2009 | DST/J/063

LDC/101 18 Dec. 2008 | DST/P/048

MDC/002 3 Nov. 2008 | DST/N/150 Environmental QD/HW/SPF/L/0001 | 30 May 2008

MSB/103/B 25 Mar. 2009 | DST/S/053

PBM/001 10 Nov. 2008 | DST/N/074

PBM/002 18 Oct. 2006 | DST/N/126

PSU/011 6 Nov. 2008 | DST/S/026

PSU/012 6 Nov. 2008 | DST/R/098

RTC/003 16 Sep. 2008 | DST/R/063

SAM/DEC/007/C 29 Oct. 2008 | DST/R/083

SBM/001 18 Dec. 2008 | DST/J/059

SDC/001 25 Sep. 2008 | DST/N/064

SDI/001 23 Dec. 2008 | DST/N/069

SDI/103 20 Jan. 2009 | DST/U/015

TCG/001/C 19 Dec. 2008 | DST/P/033

TCG/102/C 1 May 2008 | DST/T/096

TDC/001 15 Dec. 2008 | DST/M/056

TDC/002/D 28 Jul. 2008 | DST/P/059

UAR/001 10 Nov. 2008 | DST/N/076

UAR/002/C 22 Dec. 2008 | DST/N/133

UAR/102 2 Feb. 2009 | DST/R/004

UAT/101 4 Oct. 2007 | DST/T/071

VDC/001 25 Sep. 2008 | DST/N/065

VID/103 29 Jul. 2008 | DST/P/045

Suggested Reading Paths

Engineers responsible for installing KAM-500 modules “Handling precautions”