Kdi 572 Kdi 573 Kdi 574
Kdi 572 Kdi 573 Kdi 574
Kdi 572 Kdi 573 Kdi 574
MAINTENANCE MANUAL
KDI 572/573/574
DME INDICATORS
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RELEASED FOR THE EXCLUSIVE USE BY: AVIOINGENIERIA SAS
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Where R & R appears in the action column, remove the page now in the maintenance
manual and replace it with the enclosed page; otherwise, ADD or DESTROY pages as
listed. Retain these instructions in the front of the maintenance manual as a Record of
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______________________________________________________________________
PAGE ACTION REASON FOR CHANGE
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SECTION IV
THEORY OF OPERATION
Paragraph Page
SECTION V
MAINTENANCE
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Paragraph Page
SECTION VI
ILLUSTRATED PARTS LIST
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APPENDIX S
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INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . S-1
HARDWARE/SOFTWARE CONFIGURATION DIAGRAMS . . . . . . . . . . . . . . . S-1
LIST OF ILLUSTRATIONS
Figure Page
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Figure Page
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Figure Page
LIST OF TABLES
Table Page
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SECTION IV
THEORY OF OPERATION
The KDI 572, KDI 573, and KDI 574 are panel mounted DME indicators
designed to work with the KN 63 and KDM 706 remote mounted DME's. All
the indicators have a gas discharge display that simultaneously indicates
range, speed, and time-to-station. An automatic dimming circuit adjusts the
brightness of the display to compensate for changes in ambient light level.
All the indicators contain an LSI. The indicators receive DME information in
the form of digital, serial data from the remote mounted DME. The indica-
tors are also capable of displaying RNAV data received in serial form. With
the exception of the KDI 572, -0015, All the indicators receive power,
+9.25VDC and +192VDC, from the remote mounted DME. The -0015 has
an internal Power Supply, 200-06522-00XX, which is powered from +28
VDC Aircraft power.
The KDI 572 master indicator accepts channeling data from either of two
external NAV control heads. A rotary switch on the KDI 572 selects N1,
HOLD or N2 channeling and also provides a system power switch. The KDI
572 will accept parallel tuning data in shifted BCD, ARINC 2 x 5, or slip
code. It can also accept tuning information in the form of digital serial data
from an RNAV or control head. The KDI 572 converts the tuning informa-
tion received into digital serial data which is sent to the remote mounted
DME.
The KDI 574 master indicator is similar to the KDI 572 except that it doesn't
have a rotary switch. It must be used with an external system power switch.
Any selection of tuning sources must also be done with an external switch.
The KDI 573 slave indicator (optional) provides a duplicate display of the
information shown on the KDI 572 or KDI 574. It has no rotary switch and
neither receives nor sends tuning data.
Refer to Figures 4-1 and 4-2, the Indicators Block Diagrams, while reading
the simplified circuit theory.
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2. It receives DME information (range, speed, and time-to-station) from the re-
mote mounted DME and RNAV information from an external RNAV in the
form of digital serial data. It converts this information into a parallel multi-
plexed form that is suitable for driving the display circuitry.
3. It controls the channeling source (N1, HOLD, or N2) and determines which
information is displayed (DME or RNAV data).
The multiplex LSI can receive BCD, slip, or 2 x 5 parallel channeling codes or
BCD serial channeling data. The LSI is programmed for the particular code it
receives by the logic levels on the three code program lines. It then converts the
code to BCD serial data. The serial tuning data, along with a reference clock
signal, goes to the remote mounted DME.
Serial data in the DME system is transferred on two lines: the data buss and the
clock buss. The data buss carries the serial data itself, while the clock buss car-
ries a reference clock signal needed to "read in" the serial data. The clock and
data buss lines carry DME data from the remote mounted DME to the indica-
tors, RNAV data from an external RNAV to the indicators, serial tuning data
from a control head to the KDI 572, and serial tuning data from the KDI 572 to
the remote mounted DME. In order to keep the various types of data separated,
the multiplex LSI alternately requests DME data and RNAV data by means of a
logic "1" on the DME and RNAV request lines, respectively. The DME and
RNAV then put data on the line only during their respective request periods. If
a control head is used that puts out serial tuning data, it is put on the line instead
of RNAV data during the RNAV request period. The KDI 572 sends out serial
tuning data to the DME when all the request lines are low. The clock/data gating
prevents the serial tuning data from going on the line at any other time.
The function switch in the KDI 572 has four positions: OFF, N1, HOLD, and N2.
In the OFF position, the remote DME and the indicators are shut down. In N1
position, the multiplex LSI receives channeling information from the control
head connected to Channel 1 Common. In N2 position, the multiplex LSI re-
ceives channeling information from the control head connected to Channel 2
Common. In HOLD position, the LSI continues to receive channeling informa-
tion from the last -selected control head.
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It also continues to send the channeling information from that control head to
the DME as serial tuning data. Actual holding of the channeling information
takes place inside the DME in response to a logic "0" on the Hold output from
the KDI 572.
The KDI 574 is similar to the KDI 572 except that the function switch is exter-
nal to the unit.
In the KDI 573 the multiplex LSI neither receives nor sends channeling data.
However, it does receive the same DME and RNAV data received by the
master indicator and convert it into parallel multiplexed form to provide a du-
plicate display. The KDI 573 also has no function switch.
The indicator has a photocell activated dimming circuit that adjusts the bright-
ness of the display to compensate for changes in ambient light level. Dimming
is accomplished by varying both the duty cycle of the cathode driving signals
and the cathode current.
4.2.3 Master 1KHz Oscillator and Slave Sync Circuit (KDI 572, 573, and 574)
In order to function properly, the multiplex LSI in the KDI 573 must look for DME
and RNAV serial data at the proper times - during the DME and RNAV request
periods, respectively, as determined by the multiplex LSI in the master indica-
tor. Consequently, the multiplex LSI's in the master and slave indicators must
be synchronized. The multiplex clock for both master and slave is derived from
a 1KHz master oscillator in the master indicator. Synchronization is accom-
plished by the slave sync circuit in the slave indicator. It contains logic gating
that compares the altitude request output from the master multiplex LSI to the
altitude request output from the slave multiplex LSI. Whenever the two altitude
request lines are at opposite logic levels, the multiplex clock in the slave indica-
tor is turned off until they are at the same logic level.
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This allows the master indicator to "catch up" with the slave if they are out of
sync. The slave sync circuit also works with the display blanking circuit to blank
the display in the slave indicator whenever it is out of synchronization with the
master.
The following is a detailed description of the KDI 572, 573, and 574 circuit
operation. Timing diagrams, circuit schematics, and individual components
are referred to extensively as an aid in understanding the theory.
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S901 POSITION
*When S901 is in the HOLD position, the D1 and D2 logic levels will remain
what they were just prior to going into HOLD.
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108 X 0 0 0 0 X 0 1 1 0 X 1 1 0 1
109 X 0 0 0 1 X 0 0 1 1 X 1 1 1 0
110 X 0 0 1 0 X 1 0 1 1 X 0 1 1 1
111 X 0 0 1 1 X 0 1 1 1 X 0 0 1 1
112 X 0 1 0 0 X 0 1 0 1 X 0 0 0 1
113 0 0 1 0 1 0 1 1 0 1 0 1 0 0 0
114 0 0 1 1 0 0 1 1 1 0 0 0 1 0 0
115 0 0 1 1 1 0 1 1 0 0 0 1 0 1 0
116 X 1 0 0 0 X 1 0 0 1 X 0 1 0 1
117 X 1 0 0 1 X 1 0 1 0 X 0 0 1 0
133 1 0 1 0 1 1 1 1 0 1 1 1 0 0 0
134 1 0 1 1 0 1 1 1 1 0 1 0 1 0 0
135 1 0 1 1 1 1 1 1 0 0 1 1 0 1 0
.0X 0 0 0 0 1 0 1 1 0 0 1 1
.1X 0 0 0 1 0 1 1 1 0 0 0 1
.2X 0 0 1 0 0 1 0 1 0 0 0 0
.3X 0 0 1 1 1 1 0 1 1 0 0 0
.4X 0 1 0 0 1 1 1 0 1 1 0 0
.5X 0 1 0 1 1 1 0 0 0 1 1 0
.6X 0 1 1 0 1 0 0 1 1 0 1 1
.7X 0 1 1 1 1 0 1 0 1 1 0 1
.8X 1 0 0 0 0 1 1 0 1 1 1 0
.9X 1 0 0 1 0 0 1 1 0 1 1 1
.X0 1 1 1
.X5 0 0 0
X = don’t care
Table 4-2 DME Parallel Channeling Codes
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I801 can accept serial tuning data in a 10-bit format or as the last
10 bits of a 50 bit RNAV word. In either case, the data is received
during the RNAV request period. Refer to Figures 4-2 and 4-3, the
10-bit Tuning Data and RNAV Data Timing Diagrams. A logic "1"
on the 10-bit frequency input (pin 36 of I801) programs I801 to re-
ceive 10-bit serial tuning data while a logic "0" programs it to re-
ceive 50-bit RNAV data.
I801 converts whatever form of channeling data it receives into
BCD serial data that is sent to the remote mounted DME. Refer to
Figure 4-4, the Serial Tuning Data Timing Diagram.
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The clock/data gating insures that the DME tuning data will go onto the
clock and data busses only during the interval when all three request lines
are low. The RNAV, DME and altitude request lines from I801 are con-
nected to the inputs of a 3-input "nor" gate, I804C. The output of I804C
goes high only when all three request lines are low. The high at the output
of I804C enables I805A and D, allowing the DME tune clock and DME
tune data from 1801 to pass on to Q801 and Q802.
Q801 and Q802 form an interface circuit to put the DME tune clock and
DME tune data on the clock buss and data buss. The serial clock and
data are inverted by I805A and D and then inverted again by Q801 and
Q802. Q801 and Q802 provide active pull-up on the clock and data buss
lines. Pull-down is provided by R835 and R834.
The signals on the clock and data busses pass through Schmitt triggers
(I803F and A) before going to the inputs of I801 in order to improve noise
immunity.
The indicators have a gas discharge display, DS901, that is driven in a multiplexed
fashion. DS901 contains eight 7-segment digits, one decimal point, and messages.
Each anode of DS901 corresponds to an entire digit plus any message next to it.
Each cathode is a particular segment of a digit, the decimal point, or one letter in
the messages. The corresponding segments of each digit are wired together to
form the "a", "b", "c", "d", "e", "f", and "g" cathode inputs. For example, the "a" cath-
ode input (pin 4 of DS901) is connected to the top segment of all eight digits. The
decimal point is another cathode input. The letters and numbers in the messages
are wired together to form three addition[ cathode inputs. The "1TVI" input (pin 10
of DS901) is connected to "1" of "1H2", "T" of "KT", "V" of RNV", and "I" of "MIN".
The "N2KNN" input (pin 11 of DS901) is connected to "N" of "NM", "2" of "1H2" "K"
of "KT", "N" of "RNV", and "N" of "MIN". The "MHRM" input (pin 25 of DS901) is
connected to "M" of "NM", "H" of "1H2:, "R" of "RNV", and "M" of "MIN".
When they are not selected, the anodes of DS901 sit at about +130 volts and the
cathodes at about +70 volts. The resulting 60 volts of anode to cathode voltage in-
side the tube is not sufficient to ionize the gas and ignite the tube.
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For example, in order to make a "1" appear as the first digit on the left, the "b" and
"c" cathode inputs would have to be pulled low while anode 1 is pulled high. To-
display the message "NM", the "N2KNN" and "MHRM" cathode inputs would have
to be pulled low while anode 3 is pulled high.
In order to insure that the display will ignite quickly, two keep-alives inside DS901
remain ionized continuously. The keep-alive anodes (pins 2 and 21 of DS901) are
connected to +190 volts through 820K resistors, R907 and R908. The keep-alive
cathodes (pins 1 and 22 of DS901) are connected to ground through 820K resis-
tors, R909 and R910. As a result, approximately 30ua of current continuously flows
through each keep-alive.
Q901 limits the current delivered on the +192 volt line to about 25ma. This provides
protection for the display and the anode and cathode drivers in the event of a mo-
mentary short inside the display.
The digit segments and decimal point of DS901 are selected at the
proper time by I901. I901, in turn, is driven by the "a", "b", "c", "d", "e",
"f", "g", and "decimal point" outputs of I801. A logic "1" on any of
these outputs of I801 causes the corresponding output of I901 to pull
low. Thus, I801 controls the numerical information displayed. DME
information is normally displayed. DME range is displayed to the
nearest 0.1NM from 0-99.9NM and to the nearest 1NM from 100 to
389NM on the 1st-3rd digits. Ground speed is displayed to the near-
est knot from 0-999 knots on the 4th-6th digits. Time-to-station is dis-
played to the nearest minute from 0-99 minutes on the 7th and 8th
digits. Dashes are displayed on all digits if the DME is in search. If
RNAV data is received with the 10 bit/50 bit select line low, it will be
displayed instead of the DME data. RNAV range, speed, and time-to-
station are displayed in the same format as the DME information. In
place of speed and time-to-station, the RNAV can put out bearing in-
formation. Bearing is then displayed to the nearest degree from 0-
359 degrees on the 4th-6th digits; the 7th digit is blank; and an "F" is
displayed in the 8th digit.
Dashes are displayed on all digits if the RNAV is in search. Refer to
Figure 4-8, the Display Circuitry Timing Diagram.
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The message cathodes are selected at the proper time by I908. I908
is driven by the message logic gating (I905, I906, and I907) which, in
turn, is driven by I904, an eight bit ring counter. I904 counts synchro-
nously with I902, the eight bit ring counter that selects the anodes.
The two ring counters and the multiplex LSI use the same clock sig-
nal and are kept synchronized with one another by a positive reset
pulse from pin 32 of I801 that occurs once every eight counts. This
reset pulse forces I902 and I904 to pass through the "0" count state
at the proper time. "NM", "KT", and "MIN" are lit continuously when-
ever the unit is on. "RNAV" is lit only when RNAV data is being re-
ceived. "1", "2", "1H", or "H2" is lit, depending on the position of the
function switch. The lighting of "RNAV" and "1H2" is controlled by the
logic levels on the following four inputs to the message logic gating:
The logic levels on these lines are controlled by the master indicator.
See Table 4-1. The NAV 1 and NAV 2 common outputs of the master
indicator are connected to the NAV 1 and NAV 2 common inputs, re-
spectively, of the slave indicator. In both master and slave, the lines
are inverted by I810E and C before driving the message logic gating.
The logic level on the hold line is determined by I801 in the master
indicator. See Table 4-1. The hold line is inverted by Q902 in the
master indicator to produce the hold output, which is connected to
the hold input of the slave indicator. In the slave indicator, the hold
input is inverted again by Q902 to produce the hold line.
Refer to Table 4-3, the Message Logic Gating Truth Table and Figure 4-
8, the Display Circuitry Timing Diagram.
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Note
"1", "H", and "2" do not light in the 066-01069-0003 version of the KDI
573 or in the 066-01069-0005 version of the KDI 574. This is accom-
plished by omitting CJ905 and adding CJ906.
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The RNAV annunciate lines indicate when RNAV data is being re-
ceived and whether the RNAV is NAV 1 or NAV 2 tuning source. The
channel 1 RNAV annunciate line is pulled low whenever RNAV data
is received from a "NAV 1" RNAV. The channel 2 RNAV annunciate
tine is pulled tow whenever RNAV data is received from a "NAV 2"
RNAV. Both lines are high when RNAV data is not received. The cor-
responding RNAV annunciate lines of the master and slave indica-
tors are connected together.
The logic level on the hold line is controlled by the master indicator.
See Table 4-1.
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In both the master and slave indicators the display blanking circuit
blanks the digits in the display during the first few seconds after initial
turn-on and during reception of RNAV data in frequency hold or
cross-channeled modes. In addition, in the slave indicator, the dis-
play blanking circuit blanks the digits whenever the slave is out of
synchronization with the master indicator. I801 blanks the digits
whenever the power delay input (pin 27) is low. It is pulled low by
Q805 whenever a logic "0" is presented at either input to I806B. It is
also pulled low by CR810 whenever power is off. Once pin 27 of I801
has been pulled low, it requires several seconds for C820 to charge
back up through an internal resistor in the LSI.
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This current is used as the programming current for the cathode driv-
ers, I901 and I908. It is split by R924 and R925 so that roughly 58%
of the current goes to I908 and 42% goes to I901. Each output of the
cathode drivers acts as a constant current source that delivers neg-
ative current equal to twice the magnitude of the programming cur-
rent. The outputs are activated by a logic "1" at the corresponding in-
puts.
The input signals to I901 have the same duty cycle as the multiplex
clock signal from I909. Thus, as the ambient light level increases, the
cathode "on" time increases from 100us to .92ms and the cathode
current to the segments and decimal points increases from 240ua to
720ua. The input signals to I908 have a constant 1ms duty cycle -
equal to the anode "on" time.
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Both the multiplex LSI and the display circuitry require a 1KHz clock signal. In both
master and slave indicators, this clock signal is derived from a 1KHz oscillator in
the master. In order to function properly, the slave indicator must be synchronized
with the master. Synchronization is accomplished by the slave sync circuit. Refer
to Figure 4-9, the Slave Sync Timing Diagram.
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4.3.4 Power Supply Theory (KDI 572 -0015 Only, See Figure 4-10)
The KDI 572 Power Supply produces the three supply voltages from the aircraft
power bus (input voltage range 9 to 32Vdc). The Power Supply is protected from
voltage spikes on the aircraft DC Power Bus by L404 and CR410. When the ON/
OFF switch is in the ON position, power is applied to the Power Supply contol cir-
cuitry I401, I402, I403 through Q401. During the start-up of the Power Supply,
I403D holds the system reset line low until the microprocessor reset line goes high.
The switching regulators (+5 and +9.25Vdc) operate as follows: A sawtooth volt-
age, which swings from 1/3Vin to 2/3Vin is produced by I402D. This sawtooth is
compared, by I403A and I403B to a DC error signal from I402A and I402B respec-
tively. This results in a pulse width modulated signal which controls Q402 and
Q404, the series switching transistors. L402, C409 and L403, C413 smooth the
output from the switching transistors, providing a steady DC voltage with little rip-
ple.
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SECTION V
MAINTENANCE
CAUTION
This section contains test, alignment, inspection, cleaning, repair, and troubleshooting
procedures for the KDI 572, 573, and 574. Included are detailed assembly/disassembly
instructions and troubleshooting flowchart.
CAUTION
The test procedures of Section 5.2.2 may be followed to determine if the KDI 572, 573,
and 574 are operating properly. If they are not, refer to the troubleshooting procedures
in Section 5.4.
A. Power Supply
B. Oscilloscope
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D. Digital Voltmeter
KN 63 or KDM 706
The KDI 572, 573, and 574 indicators must be tested with either the KN 63
or KDM 706 remote mounted DME. The KDI 572 and KDI 574 master
indicators may be tested with or without a KDI 573 slave indicator.
Unless otherwise noted, the switches in the DME test panel should be set
as follows:
S1 - BCD or 2 x 5 position
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S6 - Either position
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To use the test panel shown in Figure 5-1, place the function switch on
the KDI 572 in N1 position. If a KDI 574 is used, place S7 on the panel in
N1 position. S1 on the panel may then be used to select BCD or 2 x 5
channeling. S1 should not be placed in SLIP CODE position. To select
slip code, place the function switch on the KDI 572 or S7 for the KDI 574
in N2 position. To channel 108.XX through 117.XX, S3 on the panel
should be in NORMAL position. To channel 133.XX, 134.XX, or 135.XX,
set the frequency selector to 113.XX, 114.XX, or 115.XX, respectively,
and S3 to the "+20MHz" position.
NAV 1 NAV 2
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5.2.2.3 Frequency Hold Feature (KDI 572 and KDI 574 only)
Place the KDI 572 function switch in N1 position and allow the DME to
lock up to the DME test set. If a KDI 574 is used, place S7 on the test
panel in N1 position and allow the DME to lock up. Then place the KDI
572 function switch or S7 for the KDI 574 in HOLD position and
rechannel the NAV 1 control head. The DME should remain locked.
Place the KDI 572 function switch or S7 for the KDI 574 i n N2 position
and allow the DME to lock up. Then place the KDI 572 function switch or
S7 for the KDI 574 in HOLD position and rechannel the NAV 2 control
head. The DME should remain locked.
Allow the DME to lock up to the DME test set. Both the master and stave
indicators should property display DME range, speed, and time-to-
station. Range should be displayed on the 1st - 3rd digits to the nearest
0.1NM from 0 to 99.9NM and to the nearest 1NM from 100 to 389NM.
Speed should be displayed to the nearest knot from 0 to 999 knots on
the 4th - 6th digits. Time-to-station should be displayed to the nearest
minute from 0-99 minutes on the 7th and 8th digits. Dashes should be
displayed on all digits if the DME is in search.
Distance ______________(OK)
Speed ______________(OK)
Time-to-station _________(OK)
DME Search ___________(OK)
a. "NM", "KT", and "MIN" should all be lit on both Master and Slave
Indicators whenever the system is on.(OK)
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The function should be selected using the function switch on the KDI 572
or S7 on the test panel when using a KDI 574. "1H" is displayed in hold
mode if the function switch was previously in N1 position; "H2" is
displayed in hold mode if the function switch was previously in N2
position.
Note
"1H2" does not light at all in the 066-1069-03 version of the KDI 573 nor in
the 066-1069-05 version of the KDI 574.
c. "RNV" should be lit and the numerical display should blank as follows
on both master and slave indicators:
The Master Indicator function should be selected using the function switch on the KDI
572 or S7 on the test panel when using a KDI 574.
Dimming ___________(OK)
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When the KDI 572 function switch is in "off" position, the voltage on the
"on" line should be at least 90% of the A+ voltage supplied to the DME.
When the KDI 572 function switch is in N1, HLD, or N2 position, the
voltage on the "on" line should be no higher than 20% of the A+ voltage
supplied to the DME.
a. DME Request (width = 32 +6ms, low level <.5V, high level >8V)
________(OK)
b. Altitude Request (width = 24 +Sms, low level <.5V, high level >8V)
_________(OK)
c. RNAV Request (width = 48 +9ms, low level <.5V, high level >8V)
_________(OK)
d. Display Clock (frequency = 1 + .2KHz, low level <.5V, high level >8V)
_________(OK)
_________(OK)
f. Serial data (on data buss, low level <.5V, high level >7.5V)
_________(OK)
g. Serial clock (on clock buss, low level <.5V, high level >7.5V)
_________(OK)
5.2.3 Alignment
The only alignment in the KDI 572, 573, and 574 indicators is the dimming
adjustment pot, accessible through a hole in the right side rail.
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Note
5.3 OVERHAUL
5.3.1 Inspection
A. Capacitors, Fixed
Inspect capacitors for case damage, body damage, and cracked, broken, or
charred insulation. Check for loose, broken, or corroded terminal studs, lugs
or leads. Inspect for loose, broken, or improperly soldered connections.
B. Chassis
Inspect the chassis for deformation, dents, punctures, badly worn surfaces,
damaged connectors, damaged fastener devices, component corrosion, and
damage to the finish.
C. Connectors
Inspect connectors for broken parts, deformed shells or clamps, and other
irregularities. Inspect for cracked or broken insulation and for contacts that
are broken, deformed, or out of alignment.
Also, check for corroded or damaged plating on contacts and for loose,
improperly soldered, broken, or corroded terminal connections.
Inspect covers and shields for punctures, deep dents, and badly worn
surfaces. Also, check for corrosion and damage to finish.
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E. Insulators
F. Jacks
Inspect all jacks for corrosion, rust, loose or broken parts, cracked insulation,
bad contacts, or other irregularities.
G. Potentiometers
H. Resistors, Fixed
Inspect the fixed resistors for cracked, broken, blistered, or charred bodies
and loose, broken, or improperly soldered or corroded terminal connections.
I. Wiring
Inspect wiring for breaks in insulation, conductor breaks, and improper dress
in relation to adjacent wiring or chassis.
5.3.2 Cleaning
B. Using a hand controlled dry air jet (not more than 15psi), blow the dust’ from
inaccessible areas. Care should be taken to prevent damage by the air blast.
C. Clean the receptacles and plugs with a hand controlled dry air jet (not more
than 25psi), and a clean, lint-free cloth lightly moistened with an approved
cleaning solvent. Wipe dry with a clean, dry, lint-free cloth.
5.3.3 Repair
This section describes the procedure, along with any special techniques, for
replacing damaged or defective components of the KDI 572, 573, and 574.
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A. Diodes
Diodes used in the KDI 572, 573, and 574 are silicon and germanium. Use
long nose pliers as a heatsink under normal soldering conditions. Note the
diode polarity before removal.
B. Integrated Circuit
The large scale integrated circuit (LSI) used in the KDI 572, 573, and 574 is
mounted in a socket for easy replacement. Use the insert/extract tool included
in the LSI Insertion/Extraction Kit (KPN 050-1671-00) for removing or
replacing the LSI. Refer to the instructions included in the kit. Be careful to
avoid breaking the IC package during removal and insertion. Carefully line up
the pins of the IC with the holes in the socket when replacing it. Be sure pin 1
(marked with a dot on the case or slot in the pin) is oriented properly.
The medium scale integrated circuits are soldered to the PC boards. Refer to
the integrated circuit maintenance section in the Appendix for removal and
replacement instructions. The LSI and CMOS integrated circuits may be
damaged by static electricity and should be kept in conductive packaging
when not installed.
C. PC Boards
Use a low wattage soldering iron to avoid damaging the boards by excessive
heat. A path that has opened up on the top or bottom of a board can be
replaced with insulated hookup wire.
D. Transistors
The KDI 572, 573, and 574 indicators have been constructed so that all
parts are visible after removing the two covers. The entire assembly can
then be separated into two parts - one consisting of the connector board
(top PC board), rear connector, and rear plate; the other consisting of the
display board (bottom PC board), two side rails, and the front plate. All
components except the display can then be replaced with no further
disassembly. The front bezel must be removed to replace the display.
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5.3.4.1Disassembly
a. Remove the 8 screws (KPN 089-5434-03) holding the top and bottom
covers in place............ Then remove the two covers.
c. In order to remove the front bezel, the knob must first be removed on
the KDI 572. Use a spline wrench to loosen the set screw.
d. Remove the four screws (KPN 089-6360-02) holding the front bezel in
place. Then remove the front bezel. The display can now be removed
from its socket.
5.3.4.2 Assembly
b. Before replacing the bezel, make sure the two spacers (KPN 187-
1156-00/01) are installed behind it.
c. Before plugging the two PC boards together, reinstall the insulator that
was between them.
5.4 TROUBLESHOOTING
Parts A and B of the troubleshooting flowchart apply to KDI 572, 573, and D
apply to KDI 572 and 574 indicators only.
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C. If a short circuit occurs on the 192V line on the collector side of Q901, it must
be replaced. Q901 is a current limiter that prevents momentary shorts inside
the display from blowing out the anode and cathode drivers. Q901 may be
checked by monitoring pin 10 of 1903 with a DC coupled oscilloscope and
momentarily connecting a 3.3K resistor from pin 10 of 1903 to ground. When
the 3.3K resistor is connected, the voltage on pin 10 of 1903 should
momentarily drop from about +190 volts to about +90 volts. Do not connect the
resistor for more than 1 second or it will blow out Q901. If the voltage stays
above 140 volts when the resistor is connected, replace Q901.
E. If the display messages do not light up at the proper time, check the message
logic gating and RNAV message logic. Truth tables for the logic are given in
Tables 4-3 and 4-4.
F. Refer to Sections 4.3.2 and 4.3.3 of the Theory of Operation and parts A and B
of the troubleshooting flowchart.
5.4.2 Channeling Troubleshooting (KDI 572 and 574 Master Indicators only)
A. The Master Indicators will accept shifted BCD, 2 x 5, or slip code from an
external control head. These tuning codes are given in Table 4-2.
B. If a parallel control head does not have an M20 (or 10MA) output, the M20
input to the Master Indicator must be tied to the NAV 1 or NAV 2 common line.
If a parallel control head without M20 (or 10MA) tunes property on all channels
except 113.00-115.95, it probably means the M20 tine wasn’t connected to
one of the control common lines. Check CR806, CR807, and the external
interconnect wiring.
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C. The Master Indicators can also accept either 10-bit serial tuning data or 50-bit
RNAV data from an external control head or RNAV. The formats for the 10
and 50-bit data are given in Figures 4-2 and 4-3.
D. The Master Indicators put out serial tuning data to tune the DME. The format
of that serial data is given in Figure 4-4.
E. Refer to Section 4.3.1 of the Theory of Operation and parts C and D of the
troubleshooting flowchart.
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APPENDIX S
HARDWARE/SOFTWARE CONFIGURATIONS
Introduction
Hardware and software unit configuration options are presented in the Appendix s. The
appendix provides a means for identifying the compatability between particular hardware
and specific software configurations. Additionally, the hardware version and software
revisions of a unit are reflected by the appendix.
Hardware is defined as the cicuit boards and assemblies used to configure the complete
unit of a particular version. Software is defined as the ROM’s or other programmed
devices containing programs which are used in the particular version of the complete
unit. Firmware is defined as programmed devices that provide a hardware function inde-
pendent of the unit software programming. Because firmware is independent of the unit
software programming it may be a sub-assembly of non-software hardware board
assembly or a sub-assembly of a hardware/software set depending on the particular
application.
Each drawing in Appendix S is assigned a figure number, commencing with Figure S-1
and progressing sequentially.
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The last four digits of the unit part number (XXX-XXXXX-HHSS) define the
hardware/software version of the equipment (the first two digits defining the
hardware version and the last two digits defining the software version).
The first three digits of a part number is a part number designator that
defines the type of part assigned to the part number. A 200 part number des-
ignator (200-XXXXX-XXXX) defines a part as a hardware assembly. A 206
part number designator (206-XXXXX-VVRR) defines a part as a system
hardware/software set.
The last four digits of a part number with a 206 part number designator (206-
XXXXX-VVRR) trcks the software version/revision level of the systemhard-
ware/software set. The first two digits correspond to the system software ver-
sion identified by the number on the software ID tag on the outside of the
unit. The last two digits correspond to the revision level of the software ver-
sion. (Note: a part number with a 206 designator may not be ordered and are
for reference only.)
A block on the next tier corresponds to a software set or firmware set. A part
number with a 125 part number designator (125-XXXXX-00RR) defines a
part as a firmware set. Note: a part number with a 125 or 126 part designator
may not be ordered and is for reference only.)
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F. Drawing Titles
The drawing titles identify the unit by: nomenclature; unit version part num-
ber; and software ID tag.
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APPENDIX A
1.1 General
Due to the wide utilization of semiconductors in this electronic equipment, somewhat dif-
ferent techniques are necessary in maintenance procedures. In solid state circuits the
impedances and resistances encountered are of much lower values than those encoun-
tered in vacuum-tube circuits. Therefore, a few ohms discrepancy can greatly affect the
performance of the equipment. Also, coupling and filter capacitors are of larger values
and usually are of the tantalum type. Hence, when measuring values of capcitors, an
instrument accurate in high ranges must be employed. Capacitor polarity must be
observed when measuring resistance. Usually more accurate measurements can be
obtained if the semiconductors are removed or disconnected from the circuits.
B. Line Filter
It is still possible to damage semiconductors from line current, even though the test
equipment has a power transformer in the power supply, if the test equipment is pro-
vided with a line filter. This filter may function as a voltage divider and apply half the
line voltage to the semiconductor. To eliminate this condition, connect a ground wire
from the chassis of the test equipment to the chassis of the equipment under test be-
fore making any other connections.
C. Low-Sensitivity Multimeters
Another cause of semiconductor damage is a multimeter that requires excessive cur-
rent to provide adequate indications. Multimeters with sensetivities of less than
20,000 ohms-per-volt should not be used on semiconductors. When in doubt as to
the amount of current supplied by a multimeter, check the multimeter circuits on all
scales with an external, low-resistance multimeter connected in series with the mul-
timeter leads. If more than one milliampere is drawn on any range, this range cannot
be safely used on small semiconductors.
D. Power Supply
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When using a battery-type power supply, always use fresh batteries of the proper
value. Make certain that the polarity of the power supply is correct for the equipment
under test. Do not use power supplies having poor voltage regulation.
A. PNP Transistor
To check a PNP transistor, connect the positive lead of the multimeter to the base of
the transistor, and the negative lead to the emitter or collector. Generally, a resis-
tance reading of 50,000 ohms or more should be obtained. Reconnect the multimeter
with the negative lead to the base. With the positive lead connected to the emitter or
collector a resistance value of 500 ohms or less should be obtained.
B. NPN Transistor
Similar tests made on a NPN transistor should produce the following results:
With the negative lead of the multimeter connected to the base of the transistor the
value of resistance between the base and the collector or emitter should be high.
With the positive lead of the multimeter connected to the base, the value of resis-
tance between the base and the collector or emitter should be low. If these results
are not obtained, the transistor is probably defective and should be replaced.
CAUTION
IF A TRANSISTOR IS FOUND TO BE DEFECTIVE, MAKE CER-
TAIN THAT THE CIRCUIT IS IN GOOD OPERATING ORDER
BEFORE INSTALLING A REPLACEMENT TRANSISTOR. IF A
SHORT CIRCUIT EXISTS IN THE CIRCUIT, PUTTING IN
ANOTHER TRANSISTOR WILL MOST LIKELY RESULT IN
BURNING OUT THE NEW COMPONENT. DO NOT DEPEND
UPON FUSES TO PROTECT THE TRANSISTORS.
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A. Use only a low heat soldering iron when installing or removing soldered-in semicon-
ductors. Grasp the lead to which heat is applied between the solder joint and the
semiconductor.
This will dissipate some of the heat that would otherwise be conducted into the semi-
conductor from the soldering iron. Make certain that all wires soldered to semicon-
ductor terminals have first been properly tinned so that the necessary connection can
be made quickly. Excessive heat will permanently damage a semiconductor.
B. In some cases, power transistors are mounted on heat-sinks that are designed to dis-
sipate heat away from them. In some power circuits, the transistor must also be in-
sulated from ground. This insulating is accomplished by means of an insulating
washer. When replacing transistors mounted in this manner, be sure that the insulat-
ing washers are replaced in proper order. After the transistor is mounted, and before
making any connections, check from the case of the transistor to ground with a mul-
timeter to see that the insulation is effective.
1.2.1 General
A knowledge of integrated circuit fundamentals is necessary when testing digital logic cir-
cuits involving IC’s.
1.2.2 Terminology
Several terms are used whenever logic circuits are discussed:
A. A logic state is defined as a high or low level voltage applied to the input or seen at
the output of a device. A high level voltage is called a logic “1”. A low level voltage is
called a logic “0”. Logic threshold voltage of a device is the input voltage required at
an input to change the output state.
B. A truth table is a list of input logic states that will yield certain output logic states. A
digital logic element should be thought of as a circuit element with its output level be-
ing either HI or LO as programmed by the levels present on its inputs.
A logic element may be tested by verifying that it is performing per the Truth Table
of that logic element.
C. Logic elements which have multiple inputs and a single output are known as gates.
The OR gate produces a HI output when one or more of the inputs are HI. With all
inputs LO, the output is LO. The AND gate produces a HI output only when all inputs
or HI. When any input is LO the output is LO. A small circle at the output of a gateon
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the schematics indicates “negation”, which means that the sense of the gate logic is
reversed. An OR gate with negation is called a NOR gate and an AND gate with ne-
gation is called a NAND gate. A NOR gate produces a LO output when one or more
of the inputs are HI and a NAND gate produces a LO output only when all inputs are
HI.
D. The Flip-Flop logic element is the basic data storage element of digital logic. It has
two outputs that are always at oposite logic levels. That is, when one output is HI the
other is LO. The Flip-Flop will remain in a particular state until that state is changed
by an input signal.
The operation of these Flip-Flops is controlled by the signals on their inputs, and is
best understood by a careful study of their Truth Tables. It should be kept in mind
that a small circle on either the input or the output indicates negation. Also, a circle
on a clock input indicates that a HI to LO transition causes the Flip-Flop to function.
E. Besides the gates and Flip-Flops, two other commonly used logic elements are in-
verters and expanders. Inverters are merely switching transistors such that if a logic
“1” is the input to a device, a logic “0” will be the output and vice-versa. An expander
is a set of parallel switching transistors that depends upon another resistor to provide
their supply voltage. Generally, these devices are used to expand the number of in-
puts available to a standard gate.
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The minimum high and maximum low input levels which are guarenteed to be correctly
interpreted are:
When checking input and output levels of a logic element under question it should be
remembered that an input or output may not agree with its truth table not because it has
malfunctioned but because some other component connected to the same point has
shoted to ground or to the supply voltage (Vcc). This is not common when an output on
one element is connected to an input of another. A majority of digital IC failures can be
grouped into three catagories:
An open ground pin would not allow a LO on the output. An open Vcc pin would not allow
a HI on the output. (Remember to isolate the device from other components connected
to it). Two or more inputs shorted together can be checked by grounding one of the
inputs under question. If the other input also goes to ground they are probably shorted.
Caution
IF AN IC IS FOUND TO BE DEFECTIVE, VERIFY THAT PROPER
POWER SUPPLY VOLTAGES ARE PRESENT BEFORE
INSTALLING A REPLACEMENT IC.
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one by one. This is preferrable over removing the IC intact because attempts to remove
the IC intact may result in damage to the printed circuit board.