TH E ANALOG M IN D

Behzad Razavi

The Design of An LDO Regulator

M
Many mixed-signal systems incorpo-
rate LDO regulators to generate local
supply voltages for various building
blocks. LDOs isolate the circuits from
one another’s noise and from the
within a PLL. We assume the VCO
is designed for a phase noise of
–110 dBc/Hz at a 1-MHz offset and
must incur no more than 1 dB of
noise penalty due to the LDO. The
where f denotes the frequency off-
set from the carrier. At a 1-MHz off-
set, this value must be sufficiently
below −110 dBc/Hz so as to intro-
duce only 1 dB of penalty. That is,
noise on the global supply, VDD. For VCO implementation is shown in we must have
optimum performance, the design of Figure 1, along with the LDO. The for- 2
each LDO is tailored to the particu- mer employs two capacitor banks, K VCO
S V, LDO + 10 -110/10
4r 2 f 2
lar cell that it feeds. For example, an B 1 and B 2, for digital tuning, and 10
log = 1dB
10 -110/10
LDO developed for a flash analog-to- MOS varactors, M V1 and M V2, for (2)
digital converter is quite different analog control. As phase-noise opti-
from one serving a VCO. mization dictates a PLL bandwidth at f = 1MHz. It follows that S V, LDO #
In this article, we design an LDO of no more than a few megahertz, 32 nV/ Hz .
for a 5-GHz LC VCO and target the the VCO gain, K VCO, should typically The PSRR is defined as ; Vout /VDD ;
following specifications: not exceed 2r (50 MHz/V). Noting in Figure 1 and must remain less
■■ Input voltage: 1.2 V that low-frequency perturbations than −40 dB. The −40-dB require-
■■ Output voltage: 1 V on Vout and Vcont have approxi- ment translates to two assumptions
■■ Maximum output current: 5 mA mately the same effect on the VCO as to how “clean” VDD should be.
■■ Power supply rejection> 40 dB up output phase, we express the phase First, its random noise must be less
to 10 MHz noise due to the LDO random noise, than 100 # 32 nV/ Hz . Second, any
■■ Output noise voltage 150 nV/ Hz S V, LDO, as periodic perturbation on VDD must
at 1 MHz. be so small that, with 40 dB of atten-
The PSRR and tolerable output K 2VCO uation, it introduces sufficiently low
S zn (f ) = S V, LDO, (1)
noise are chosen according to the 4r 2 f 2 spur levels at the VCO output. If we
VCO’s supply sensitivity. We elaborate
on these points in the next section.
We also target a maximum LDO power VDD
consumption of 1 mW beyond the Vout
LDO
5 mA # 1.2 V = 6 mW that it provides
to the load. The design is carried out
in the slow-slow corner of 28-nm tech- L1 L1
nology at T = 75c C. The reader is
B1 B2
referred to the LDO literature for back- X Y
ground information [1]–[5].
M1 M2
LDO/VCO Interface
We wish to regulate the supply volt- Mv1 IVCO Mv2
age of a 5-GHz VCO that operates
Vcont
Digital Object Identifier 10.1109/MSSC.2022.3167308
Date of current version: 25 June 2022 FIGURE 1: A VCO circuit fed by an LDO.

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approximate the VDD perturbation For analysis and design of the LDO, tor’s overdrive must not exceed this
by Vm cos ~ m t, the normalized spur we wish to attach to its output a sim- value. For ; I D0 ; . 6 mA, this trans-
level is equal to 0.01K VCO Vm / (2~ m) plified model of the VCO. Returning lates to (W/L) 0 $ 100 nm/30 nm.
at an offset frequency of ~ m. For to Figure 1, we observe that the LDO As explained in [5], the coupling of
example, a spur level 60 dB below provides a bias current equal to I VCO VDD through this transistor’s output
the carrier at ~ m = 2r (10 MHz) and sees the two capacitor banks, resistance, rO0, to Vout negligibly
requires that Vm be less than 40 mV varactors, and common-mode (CM) affects the PSRR, allowing the mini-
if K VCO = 2r (50 MHz/V). parasitics at X and Y. We then model mum length for this device. Such a
the VCO as depicted in Figure 2(b), length is preferable as the capaci-
General Considerations where C VCO = 2C B + 2C var + 2C CM and tances of M 0 contribute to poles at
With a drop of only 200 mV from C B, C var, and C CM denote the bank, both P and X in Figure 2(a).
VDD to Vout, the LDO must employ varactor, and CM capacitances,
a pass transistor that acts as a cur- respectively. We assume I VCO # 5 mA Op-Amp Requirements
rent source (rather than a source and C VCO = 0.5 pF. The LDO’s performance hinges upon
follower) [5]. The basic topology that of the op amp. The low-fre-
is displayed in Figure 2(a), where Pass Transistor Design quency PSRR is given by
operation amplifier (op amp) A 1 Transistor M 0 in Figure 2(a) must
Vout c
regulates Vout by adjusting the gate provide a maximum load current of . 1 + R 1 m 1 , (3)
VDD R2 A1
voltage of M 0. For Vout = 1 V, we have 5 mA plus that which flows through
VREF = (1V) R 2 / (R 1 + R 2); this is the R 1 and R 2. We should then select wher e t he lo op g a in is a ssu med
general case. If VREF = 1 V is avail- (W/L) 0 large enough so as to obtain t o b e muc h g r e ate r t h a n u n it y
able, we can omit R 1 and R 2 and tie a reasonable VGS for this device. Spe- [5]. If, for example, VREF = 0.9 V, we
the op-amp input directly to Vout. cifically, as ; VDS0 ; = 0.2 V, the transis- have 1 + R 1 /R 2 = 1/0.9 and hence
A 1 2 100/0.9 . 110 / 41dB f o r
PSRR = - 40 dB.
As the LDO is to provide a rejection
X Vout of 40 dB up to 10 MHz, we conclude
VDD
that the op amp’s open-loop 3-dB BW
M0 VCO
must exceed this value. For a one-pole
R1
design, therefore, the unity-gain BW
+ VCO IVCO amounts to 110 # 10 MHz = 1.1 GHz.
P A1 CVCO
– It is interesting that a seemingly low-
VREF R2
frequency LDO demands a fairly
wideband op amp. For this reason,
(a) (b) we prefer to use only thin-oxide (low-
voltage) transistors in the op amp’s
signal path.
FIGURE 2: (a) A basic LDO topology and (b) the VCO model. The feedback loop consisting of the
pass transistor and the op amp con-
tains several poles, possibly requiring
frequency compensation. The output
A1
node in Figure 2(a) presents several
VDD = 1.2 V
tradeoffs in this regard. First, if we
M5 M3 M4 M6 M0
add capacitance to X so as to improve
Vout = 1 V the supply rejection at high frequen-
A Ra Rb B P X cies, the loop becomes less stable,
VCO exhibiting peaking in the PSRR. Sec-
M1 M2
R1 ond, if we reduce R 1 + R 2 and hence
IVCO raise the associated pole frequency,
100 µA ISS CVCO
Q
power consumption climbs. In the
R2
M7 M8 VCO example of interest here, C VCO
W 25 µm and (R 1 + R 2) < rO0 appear to establish
= an upper bound for the pole freq­
L 120 nm
Ra = Rb = 40 kΩ uency at X. For example, C VCO = 0.5 pF
a n d (R 1 + R 2) < rO0 = 1 kX y i e l d
~ X = 2r (318 MHz). If ~ X is the
FIGURE 3: A two-stage op amp used in the LDO. first nondominant pole of the loop,

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 80 50

0
60
–50
Magnitude (dB)

40

Phase (°)
–100
20
–150
0
–200

–20 Loop Gain

–250
Op Amp Gain
–40 –300
104 106 108 1010 104 106 108 1010
Frequency (Hz) Frequency (Hz)
(a) (b)

FIGURE 4: The magnitude and phase response of the uncompensated op amp.

the unity-gain bandwidth cannot tively, while minimally loading these the gates of M 1 and M 2 to node P.
exceed this value after frequency nodes. This topology avoids cas- From this, we me make two obser-
compensation is applied. It then codes and creates well-defined bias vations. 1) The loop gain falls to
appears that the 1.1-GHz target stipu- currents for both stages (e.g., I D5 is unity at f = 4.1GHz, where the
lated previously is far from reach. For- copied from I D3), thus serving as a
tunately, pole splitting and pole-zero robust solution. A transistor length of
cancellation resolve this issue. 120 nm provides a high voltage gain,
VDD
and a large channel area reduces the M6 M0
Op-Amp Design flicker noise. The op amp draws a
To obtain the widest bandwidth for a supply current of 200 nA. P
X
given gain, we should incorporate a The LDO loop consisting of A 1
Rc Cc
cascode op amp, but, in view of the and M 0 contains poles at A (and B),
low supply voltage, we opt for a sim- Q, P, and X. We therefore predict the 500 Ω 1 pF IVCO CVCO
ple two-stage structure. The circuit need for frequency compensation.
R1
consists of a differential pair and a We simulate the open-loop LDO
stage with a current-mirror load, as circuit and arrive at the frequency
shown in Figure 3. Resistors R a and response depicted in Figure 4. Also FIGURE 5: The op-amp frequency-
R b set the CM level at A and B, respec- shown is the op-amp gain, i.e., from compensation network.

80 0

60
–50
Phase (°)
Magnitude (dB)

40
–100
20
–150
0

–200
–20

–40 –250
104 106 108 1010 104 106 108 1010
Frequency (Hz) Frequency (Hz)
(a) (b)

FIGURE 6: The magnitude and phase response of the compensated op amp.

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 Our principal task at this point
10
is to compensate the op amp, e.g.,
0 for a phase margin (PM) of approxi-
mately 60°. The dominant pole at
–10 node P should be lowered. This can
Magnitude (dB)
–20 be accomplished as shown in Fig-
ure 5, where C c both establishes a
–30 dominant pole at P and causes pole
slitting. That is, the magnitude of
–40
the pole at X now rises to roughly
–50 g m0 /C VCO. We also insert R c so as to
introduce a zero that cancels the first
–60 nondominant pole. The new response
104 106 108 1010
Frequency (Hz) is plotted in Figure 6, exhibiting a
unity-gain bandwidth of 2 GHz and a
FIGURE 7: The LDO PSRR versus frequency. PM of 53°.
The Miller compensation method
illustrated in Figure 5 is sensitive to
the capacitance at node X. We must
× 10–7 then ponder what happens if the VCO’s
1
discrete capacitor units are switched
out so as to increase its oscillation fre-
0.8
quency. In such a scenario, the pole at
Output Noise (V/ Hz)

X rises in magnitude, improving the

0.6 PM. Thus, the worst-case scenario
occurs when the tank capacitances
0.4 are at their maximum.
The closed-loop PSRR is plotted
0.2 in Figure 7. We observe that the
LDO maintains a rejection of at least
40 dB up to 23 MHz.
0
104 106 108 1010
Frequency (Hz) Output Noise
As explained in the previous section,
FIGURE 8: The output noise spectrum of the LDO. the output noise voltage of the LDO
must be no more than 32 nV/ Hz at
1 MHz for a 1-dB penalty in the VCO
phase noise. At low frequencies, the
noise is given by
1
V 2n, out . c 1 + R 1 m V 2nA1, (4)
2

0.8
R2
Output Voltage (V)

0.6 where V 2nA1 denotes the op-amp input-

referred noise [5]. Figure 8 plots the
0.4
output noise spectrum, revealing that
0.2 it is less than 20 nV/ Hz beyond a
few hundred kilohertz. The phase-
0 noise penalty is therefore negligible.
–0.2
0 5 10 15 Transient Response
Time (ns) Although our design has achieved an
adequate small-signal PM, we must
FIGURE 9: The LDO output voltage in response to a ramp on VDD.
still examine the circuit’s large-sig-
nal response. Specifically, we should
phase reaches −230°. The closed- gain of 54 dB and, according to (3), study the output when the global
loop LDO is thus unstable. 2) The a corresponding PSRR of 53 dB if
op amp provides a low-frequency 1 + R 1 /R 2 = 1/0.9. (continued on p. 17)

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 Quantum computing is one ing blocks are digital- transistor circuits to manipulate elec-
of the next frontiers ahead of us, What is to-analog converters, trons; and to communicate informa-
but this area, too, is all about important here analog-to-digital con- tion, we use circuits to create waves
is that, in the
controlling electrons. Here, verters, low-pass filters, along a wire or in the air. Finally, to
semiconductor
we are interested in control- VCOs, mixers, and ampli- put electrons in good use, please
spin qubit, we
ling the state of a quantum use the charge fiers. What is important scan the QR code in this article with
bit, or qubit for short. There of electrons here is that, in the semi- your cell phone to explore videos
are many types of qubits to control and conductor spin qubit, we from Circuit Insights on the SSCS You-
around today. Figure 12 read the spin use the charge of electrons Tube channel [1].
shows the electronics we of a single to control and read the spin
use to control a super- electron carrying of a single electron carry- References
conducting qubit [3]. information. ing information. It is, again, [1] SSCS, Circuit Insights Playlist. (2022). [On-
line Video]. Available: https://www.you-
The qubit can also be in about controlling electrons, tube.com/IEEESolidStateCircuitsSociety/
playlists
the form of the spin of a their charge, and their spin! [2] A. Sheikholeslami, “A circuit to remember
single electron that we trap in a semi- To summarize, we define electron- [Circuit Intuitions],” IEEE Solid-State Cir-
cuits Mag., vol. 14, no. 1, pp. 13–83, Winter
conductor well. However, the electron- ics as the art of controlling electrons
2022, doi: 10.1109/MSSC.2021.3127066.
ics that control their state are similar. for the purpose of information stor- [3] J. Bardin, “Cryogenic CMOS integrated
Here, the blocks in red are used to con- age, processing, and commu­­nication. circuits for control of superconducting
quantum computers: Status and chal-
trol the state of the qubit. The blocks in To store information, we trap elec- lenges,” in Proc. Forum 4, ISSCC, 2021,
green are used to interrogate the qubit, trons on a floating gate or capaci- pp. 1–62.

that is, to read the qubit. These build- tor; to process information, we use 

TH E A N A LO G M I N D (continued from p. 10)

References
1.05 [1] G. A. Rincon-Mora and P. E. Allen, “Optimized
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Output Voltage (V)

[2] H. J. Shin, S. K. Reynolds, S. Gowda, and

1 D. J. Pearson, “Low-dropout on-chip volt-
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FIGURE 10: The LDO output voltage in response to a ramp in IVCO. 1742, A u g . 20 07, d o i: 10.110 9/JS S C .
2007.900281.
[5] B. Razavi, “The low-dropout regulator,”
supply or the VCO’s tail current source voltage settles. Similarly, Figure 10 IEEE Solid-State Circuits Mag., vol. 11, no.
ramps from zero to its nominal value. shows the momentary change in Vout 2, pp. 8–13, Spring 2019, doi: 10.1109/
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Figure 9 plots Vout as VDD goes as I VCO jumps from zero to 5 mA in
from zero to 1.2 V in 10 ns, suggest- 1 ns. The loop corrects the perturba- 
ing a small amount of ringing as this tion in approximately 2 ns.

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