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Development Guide of DWIN OS Platform Based on T5L CPU

Contents
1. DWIN OS Platform Structure ........................................................................................................................ 2
2. DWIN OS Debugging Port（UART2） ....................................................................................................... 4
3. Storage Space ................................................................................................................................................ 5
3.1 Users Data Library ....................................................................................................................................... 5
3.2 Data Variable Space .................................................................................................................................... 5
3.3 Register.......................................................................................................................................................... 6
3.4 Port Register ................................................................................................................................................. 6
4. DWIN OS Assembly Instruction Set ............................................................................................................ 9
4.1 Data Exchange ............................................................................................................................................. 9
4.2 Computation ................................................................................................................................................ 10
4.3 Logic Operation .......................................................................................................................................... 12
4.4 Data Processing ......................................................................................................................................... 12
4.5 Process Controlling .................................................................................................................................... 14
4.6 Peripheral Operation .................................................................................................................................. 15
5. Appendix ........................................................................................................................................................ 17

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1. DWIN OS Platform Structure

(1) DWIN OS Code Space Definition

Code Address Definition Description

0x0000-0x0FFF L2_Cache The space of program dynamically loads and calls, 4KB.

The start address of program operating when reset, place one GOTO command to
0x1000 RESET
jump to the main program.

The entrance address of T0 INT program, applying GOTO command to jump to T0

0x1004 T0 _INT
interrupting service program.

The entrance addressT1 INT program, applying GOTO command to jump to T1

0x1008 T1 _INT
interrupting service program.
The entrance address T2 INT program, applying GOTO command to jump to T2
0x100C T2 _INT interrupting service program.
program.
0x1020-0x107F Reserved Reserved.

0x1080-0x7FFF Main Code Main program code space.

(2) The max nested call of subroutine including interrupted program, up to grade 127.

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(3) Typical program structure.

ORG 1000H
GOTO MAIN
; The first command must GOTO.
GOTO T0INT ; When interrupt, jumping to T0 to interrupting program, must use
GOTO, can not use CALL.
NOP ; T1 Discontinuity not be used.
GOTO T2INT ; Discontinuity produces, jumping to T2 to interrupting service
program.
ORG 1080H
MAIN: NOP ; Main program
GOTO MAIN

T0INT: NOP ; T0 interrupt handling

RET1 ; Use RETI end, can not use RET.

T1INT: NOP ; T1 interrupt handling

RET1

If interrupts were not adopted(closed the interrupt), the code space of 0x1004-0x107F could be
used at will.

If the main program is needed to operate breakpoint simulation, the interrupt shall be closed.
otherwise, the timer keeps running under simulation status, opening interrupt would cause the main
program to fail operating breakpoint simulation.

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2. DWIN OS Debugging Port（UART2）

System debug serial port UART2’s mode is 8N1, baud rate can be installed, data frame is made up by
5 parts.

Data 1 2 3 4 5

Definition CRC Check

Frame Header Data Length Command Data
(Optional)
Data Length 2 1 1 n 2

0x5AA5 Including command,

Description 0x80/0x81/0x82//0x83
data and check

Example
(without 5A A5 04 83 00 10 04
check)

Example
(with check) 5A A5 06 83 00 10 04 25 A3

Explanation of UART2 debug port instruction below:

Instruction Data Description

Issue: ADR(0x00-0x08)+ADR(0x00-0xFF)+Data_Pack Write data in designated addresses in register.

0x80
Respond: 0x4F 0x4B Write command respond.
Issue: ADR (0x00-0x08)+ADR(0x00-0xFF)+ RD_LEN （ 0x01-
0x81 Read data in designated addresses in register.
0xFB)
Respond: ADR(0x00-0x08)+ADR(0x00-
Response with data.
0xFF)+RD_LEN+Data_Pack
Write data in designated addresses in variable
Issue: First ADR(0x0000-0xFFFF)+Data_Pack
0x82 SRAM.
Respond: 0x4F 0x4B Write Instruction respond.
Read the specified length of word data from the
0x83 Issued: First ADR (0x0000-0xFFFF) + RD_LEN (0x01-0x7D)
specified address in the variable space.
Respond: First ADR + variable data word length + read variable
Response with data.
data

Data respond register page is defined as follow:

Register Page ID Definition Description

0x00-0x07 Data Register Each group 256, R0-R255

DR0-DR255
0x08 Port Register Details in DWIN OS development guide basing on T5L, 3.4 port register definition
description.

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3.Storage Space
3.1Users Data Library
Include two parts:
(1) The flash in the T5L chip can be accessed by system variable interface and all DWIN OS based on
T5 can be supported.
(2) A large database or data store located on an off-chip flash, accessed through a system variable
interface, depending on the hardware platform.

3.2 Data Variable Space

The data variable space is a 128kbytes double-port RAM, the separated of T5L core can exchange
data, the definition as below:
Variable Interval
Definition Description
Port Interval （K words）
Hardware, storage visit control, data exchange. detailed definition
0x0000-0x03FF 1.0 System variable port
is related to hardware platform.
0x0400-0x07FF 1.0 Reserved Users do not apply.

0x0800-0x0BFF 1.0 Reserved Users do not apply.

0x0C00-0x0FFF 1.0 Reserved Users do not apply.

Users variable Users variable, storage read, write buffer and so on, users
0x1000-0xFFFF 60 program by themselves.
data/space

At all DWIN OS platform based on T5L CPU, the first 16-word definition of system variable port is
unified, shown as follows:

Address Definition Length Description

0x00 Reserve 4

0x04 System_Reset 2 0x55AA 5AA5=reset T5L;

D3: 0x5A first updates DWIN OS program(inserting into ram Flash), clearing after CPU
operation finish.
0x06 OS_Update_CMD 2 D2: Fixing as 0x10, DWIN OS code should be start from 0x1000.
D1: 0:The initial data variation space address of store-and-update code 0x1000-
0x0C7E should be even.
D7: operation mode 0x5A=read 0xA5=write, clearing after CPU operation finished.
D6: 4: the initial address of ram Nor Flash data base should be even. 0x000000-0x02:
NOR_
0x08 4 FFFE, 256KWords.
Flash_RW_CMD
D3: 2: the initial data variation space address should be even.
D1: 0: the length of read and write word should be even.
D3=0x5A means UART2 serial mode setting, only used for GUI CPU setting, UART2
UART2_Set mode after reset, OS can not operate itself.
0x0C 2
D2=serial mode, 0x00=8N1.
D1: D0=baud rate value, baud rate value=3225600/set baud rate.

0x0E Reserve 1

Application software version. D1 refers to CPU0 soft version, D0 refers to CPU1

0x0F Ver 1
software version.

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Since variable memory is shared by two CPU cores, too frequent continuous reading and writing
variable memory will seriously affect the processing efficiency of the CPU. Therefore, a 1mS timer
interrupt is used to periodically query the data update of variable memory.

3.3 Register
DWIN OS based on T5L has a total of 2048 registers, divided into 8 pages for access, each page has
256 registers, corresponding to R0-R255.

3.4 Port Register

Based on T5L, DWIN OS has a port register page, with 256 port registers, as a quick visit port for
hardware resources.

DR# Length R/W Definition Description

0 1 R/W REG_Page_Sel 8 register pages of OS change, DR0=0x00-0x07

System status register, bitwise definition:

1 1 R/W SYS_STATUS .7 CY carry flag.
.6 DGUS screen variation automatic uploading control 1=close 0=open

2 14 -- System Reserve Access forbidden.

16 1 R UART3_TTL_Status

17 1 R UART3_TTL_Status
Serial received frame overtime timer status:
18 1 R UART4_TTL_Status 0x00= received frame overtime timer overflowing others=no overflowing.
It should be done first that applying RDXLEN command reads received length,
19 1 R UART5_TTL_Status when length is not 0, then checking overtime timer status.

20 1 R UART6_TTL_Status

20 1 R UART7_TTL_Status

21 1 -- Reserve

UART3 the applying depth(Bytes) of buffer sending buffer size is 256Bytes,

22 1 R UART3_TX_LEN
users read only.

UART4 the applying depth(Bytes) of buffer sending buffer size is 256Bytes,

23 1 R UART4_TX_LEN
users read only.
UART5 the applying depth(Bytes) of buffer sending buffer size is 256Bytes,
24 1 R UART5_TX_LEN
users read only.
UART6 the applying depth(Bytes) of buffer sending buffer size is 256Bytes,
25 1 R UART6_TX_LEN
users read only.
UART7 the applying depth(Bytes) of buffer sending buffer size is 256Bytes,
26 1 R UART7_TX_LEN
users read only.

27 1 -- Reserve

UART3 the time of received frame overtime timer. Unit 0.5mS, 0x01-0xff,
28 1 R/W UART3_TTL_SET
power-on set as 0x0A.

UART4 the time of received frame overtime timer. Unit 0.5mS, 0x01-0xff,
29 1 R/W UART4_TTL_SET
power-on set as 0x0A.

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UART5 the time of received frame overtime timer. Unit 0.5mS, 0x01-0xff,
30 1 R/W UART5_TTL_SET
power-on set as 0x0A.

UART6 the time of received frame overtime timer. Unit 0.5mS, 0x01-0xff,
31 1 R/W UART6_TTL_SET
power-on set as 0x0A.

UART7 the time of received frame overtime timer. Unit 0.5mS, 0x01-0xff,
32 1 R/W UART7_TTL_SET
power-on set as 0x0A.

33 1 -- Reserve

34 1 R/W T0 8bit user timer 0, ++counting, datum 10uS.

35 2 R/W T1 16bit user timer 1, ++ counting, datum 10uS.

16bit user timer 2, ++ counting, datum designed by users through CONFIG
37 2 R/W T2
command.
16bit user timer 3, ++ counting, datum designed by users through CONFIG
39 2 R/W T3
command.
Relevant position 1 choosing related I/O to counting changes, corresponding
41 1 R/W CNT0_Sel
IO7-IO0.

Relevant position 1 choosing related I/O to counting changes, corresponding

42 1 R/W CNT1_Sel
IO7-IO0.

Relevant position 1 choosing related I/O to counting changes, corresponding

43 1 R/W CNT2_Sel
IO15-IO8.

Relevant position 1 choosing related I/O to counting changes, corresponding

44 1 R/W CNT3_Sel
IO15-IO8.

Interrupting control register.

.7=Interrupt main switch 1= enable(open or not depending on single
interrupting control position) 0=ban.
.6=Timer INT0 Enable 1=interrupt timer 0 interrupt on 0=interrupt timer 0
45 1 R/W Int_Reg interrupt off.
.5=Timer INT1 Enable 1=interrupt timer 1 interrupt on 0=interrupt timer 1
interrupt off.
.4=Timer INT2 Enable 1=interrupt timer 2 interrupt on 0=interrupt timer 2
interrupt off.
8Bit timer interrupt 0 settings value, interrupt time=timer_INT0_Set*10uS,
46 1 R/W Timer INT0 Set
0x00=256.
8Bit timer interrupt 1 setting value, interrupt time=timer_INT1_Set*10uS,
47 1 R/W Timer INT1 Set
0x00=256.
48 2 R/W Timer INT2 Set 16Bit timer interrupt 2 setting value, interrupt time=timer_INT2_Set+1*10uS.

The firstly IO0-IO15 scans output configuration timely, 10 bites each.

D9(DR50): 0x5A=scan output applying, other as no applying.
D8: Outputting register page of data, 0x00-0x07.
D7: Outputting start and end address of data, 0x00-0xFF
D6: Outputting the word length of data, 0x01-0x80, each data 2 Bytes
50 10 R/W Polling_Out0_Set corresponding to IO15-IO0.
D5-D4: IO15-IO0 output aisle choosing, needing output aisle, corresponding bit
set as 1.
D3-D2: single outputting interval T, unit as（T+1）*10uS.
D1-D0: Outputting cycle counting designed, it minus 1 after finishing 1 cycle
every time, then outputting 0 till minus to 0.

60 10 R/W Polling_Out1_Set The second IO0-IO15 scans output configuration timely.

70 9 -- Reserve

D5=0x5A means that an IO 6 falling edge trigger is captured.

D4: D3=IO15-IO0’s condition when triggered.
80 6 R/W IO6 Trigger time
D2: D0=the catching time of system timer 0x000000-0x00FFFF cycle, unit as
1/41.75uS.

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D5=0x5A means that an IO7 falling edge trigger is captured.
D4: D3=IO15-IO0’s condition when triggered.
86 6 R/W IO7 Trigger time
D2: D0=the catching time of system timer 0x000000-0x00FFFF cycle, unit as
1/41.75uS.
92 37 -- Reserve

129 3 R/W IO_Status The real-time status of IO19-IO0’s

132 2 R/W CNT0 CNT0 changing counting value, resetting to 0x0000 when counting to 0xFFFF.

134 2 R/W CNT1 CNT1 changing counting value, resetting to 0x0000 when counting to 0xFFFF.

136 2 R/W CNT2 CNT2 changing counting value, resetting to 0x0000 when counting to 0xFFFF.

138 2 R/W CNT3 CNT3 changing counting value, resetting to 0x0000 when counting to 0xFFFF.

140 116 -- Reserve

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4. DWIN OS Assembly Instruction Set

(1) R# means DWIN OS in present register page, any or any group of 256 register, R0-R255;
(2) DR# means one or any group of 256 port register, DR0-DR255;
(3) < >means Immediate number, in the Assembly code,100, 0x64, 64H, 064H all means 10 hex data
100.
(4) Pseudo directives: ORG DB DW.
(5) Use; as a comment symbol.
(6) Description of variable and data type can be visited by DWIN OS as following:

Variable Type Mark Type Space Description

DWIN OS register R0-R255 Byte 2048 Bytes Divided into 8 pages, control page by DR0 port register.

Port register DR0-DR255 Byte 256 Bytes

Data variable space XRAM Word 64K Words Range of address: 0x0000-0xFFFF

Depend on
User data library LIB Word
hardware

(7) When T5L CPU runs at the speed of 200MHz, the average operating time of one DWIN OS
command is about 125nS (8MIPS).

4.1Data Exchange
Command Function Code Number Description
R#:Register or Register group.
<MOD>: 0=Register to variable 1=Variable to register.
Data exchange
R#, <MOD>, <NUM>: exchange data word（Word）length, 0x00-0x80;
between Variables & MOVXR
<NUM> When<NUM>is 0x00, data length depends on R9.
Registers
Data variable pointer is defined by R0: R1 register.
MOVXR R20, 0, 2
R#: Register or Register group.
Load N 8bit
R#, <DATA>, <DATA>: Data need loading.
Immediate number to LDBR
<NUM> <NUM>: Number of Register need loading, 0x00 means 256.
register group
LDBR R8, 0x82, 3
R#: Register group.
Load 1 16 bit <DATA>: Number of that loading
LDWR R#, <DATA>
numbers to Registers LDWR R8,1000.
LDWR R8, -300
Load address code Load <Address> to R5: R6: R7 LDADR TAB
LDADR <Address>
space LDADR 0x123456

Look up in Program R#: Register or Register group.

Space (Program <NUM>: byte data length Look up table return Address pointer is
MOVC R#, <NUM>
Space to DWIN_OS defined by R5: R6: R7 register MOVC R20,10
Registers) Attention, code after 0x1000 can not read code content before 0x1000.

R#S: Origin register or register group R#T: goal register or register

Data transfer from group.
R#S, R#T,
Register to DGUS MOV <NUM>: Font data length exchanged, 0x00 means length is defined by
<NUM>
Register R9 register.
MOV R8, R20, 3

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R#: Register or Register group; DR#:Port Register or Register group;
Register to port R#, DR#, <NUM>: Font data length exchanged, 0x00 means length is defined by
MOVRD
register <NUM> R9 register.
MOVRD R10, 3, 2

R#: Register or register group; DR#:port register or register group;

Port register to DR#, R#, <NUM>: Font data length exchanged, 0x00 means length is defined by
MOVDR
register <NUM> R9 register.
MOVDR 3, R10, 2

<NUM>: exchange（Word）length of data.

<NUM> 0 means length is defined by R8: R9 register Origin variable
Exchange data address length is defined by R0:R1 register. Goal variable address is
defined by R2:R3.
between MOVXX <NUM>
When the distance between source address and target address is
data variable
shorter than the length of moving data, the later length shall not longer
than 32.
MOVXX 100
Register data exchange, according to register paging access:
R2 stipulate origin address of register（group）
Without or 0x00 R3 stipulate rule goal address of register group R9 stipulate data length
exchanged, bytes.
MOVA or MOVA 0x00
Registers Indexed Register data exchange, all registers as a 2KB data area to access:
MOVA
addressing R0: R1stipulate origin address of register, 0x0000-0x7FF;
R2: R3stipulate rule goal address of register, 0x0000-0x7FF;
0x01 R9 stipulate date length exchanged, bytes, 0x00-0xFF, 0x00 show 256.
Address high byte = source or destination register DR0 low byte =
source or destination register address.
MOVA 0x01

Save the <NUM> register data starting with R# to the data stack.
PUSH R#<NUM>
PUSH R8, 4
Register stack
256 bytes
Fetch data from the data stack to the <NUM> registers starting with R#.
POP R#<NUM>
POP R8, 4

4.2 Computation
Command
Code Number Description
Function
C=A+B, A, B are 32bit integers, C is 64bit integer.
32bit integers addition ADD R#A, R#B, R#C
E.g. ADD R10, R20, R30
32bit integers C=A-B, A, B are 32bit integers, C is 64bit integer.
SUB R#A, R#B, R#C
subtraction E.g. SUB R10, R20, R30

64bit MAC for long C=(A*B+C), A, B are 32bit integers, C is 64bit integer.
MAC R#A, R#B, R#C
integers E.g. MAC R10, R20, R30

A/B, A is quotient, B is reminder. A and B are 64bit register.

R#A, R#B, <MOD>: 0: The quotient will not be rounded. 1: The quotient WILL BE
64bit integers division DIV
<MOD> ROUNDED.
E.g. DIV R10, R20, 1
Expand the data in R#S to 32bit and save to R#T R#S: Source
register(s)
Expand variable to R#S, R#T, R#T: Target register
EXP
32bit <MOD> <MOD>: Data type of R#S.
0=8Bit unsigned; 1=8bit signed 2=16bit unsigned 3=16bit integer.
E.g. EXP R10, R20, 2
C=A*B+C
32bit unsigned MAC R#A, R#B, R#C A and B are 16bit unsigned integer, C is 32bit unsigned integer.
SMAC
E.g. SMAC R10, R20, R30
R#, R#=R#+NUM, unsigned self-increasing calculation,<NUM>0x00-0xFF.
Register self-increase <MOD>, <MOD>: Data type of R#; 0=8bit 1=16bit
INC
<NUM> E.g. INC R10, 1, 5

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R#=R#-NUM, unsigned self-decreasing calculation,<NUM>0x00-0xFF.
Register R#, <MOD>,
DEC <MOD>: Data type of R#; 0=8bit; 1=16bit.
self-decrease <NUM>
E.g. DEC R10, 0, 1
Count a 64 bit unsigned R#A’s Square root and reserve it into R#B.
R#A: Reserve 8 Bytes unsigned;
Square root count SQRT R#A, R#B
R#B: Reserve 4 Bytes unsigned result.
E.g. SQRT R80, R90

Implement 1 floating point number and 1 64bit fixed point integer

conversion.
R#F: The r egister that holds the floating-point number, 32bit or 64bit;
R#I : Register to store fixed-point integer, 64bit;
<MOD>:
Floating-point and
R#F, R#I, .7 Represents the floating-point number format: 0=32bit single precision
fixed-point integer FINT
<MOD> 1=64bit double precision.
conversion
.6 Conversion type 0=Convert floating-point number to fixed-point
integer 1=Convert fixed-point integer to floating-point number.
.5 Undefined, write 0
.4-.0 The number of decimal places for fixed-point integers, 0x00-0x1F,
up to 31 decimal places.

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4.3 Logic Operation

Command
Code Number Description
Function
A=A AND B, Logical “AND” calculation for series of Registers.
Logical calculation: R#A, R#B,
AND <NUM>: Data length of R#A, R#B in BYTES.
AND <NUM>
E.g. AND R10, R20, 1
A=A OR B, Logical “OR” calculation for series of Registers.
Logical calculation: R#A, R#B,
OR <NUM>: Data length of R#A, R#B in BYTES.
OR <NUM>
E.g. OR R10, R20,1
A=A XOR B, Logical “XOR” calculation for series of Registers.
Logical calculation: R#A, R#B,
XOR <NUM>: Data length of R#A, R#B in BYTES
XOR <NUM>
E.g. XOR R10, R20, 1
R#, <NUM>, Turn R#point<NUM> register left and ring move<BIT_NUM>bit.
Left ring move SHL
<BIT_NUM> E.g. SHL R10, 2, 1

R#, <NUM>, Turn R#point <NUM>register right and ring move<BIT_NUM>bit.

Right ring move SHR
<BIT_NUM> E.g. SHR R10, 2, 1

4.4 Data Processing

Command
Code Number Description
Function

Compare the values in R#A and R#B by sequence.

If not match, return the current address of R#A to R0 register; If match,
return 0x00 to R0 register.
Sequence comparison TESTS R#A,R#B, R#A: Starting register for register series A; R#B: Starting register for
<NUM> register series B;
<NUM>: max length for data comparison.
E.g. TESTS R10, R20, 16
Calculate the Y value according to the given X value, which is a point
on the line defined by (X0, Y0) and (X1, Y1) in 16bit integer.
Integer linear equation ROOTLE Input: X=R10, X0=R14, Y0=R16, X1=R18, Y1=R20
Output: Y=R12
E.g. ROOTE
Perform ANSI CRC-16 calculation on series of Registers. ANSI CRC-
16(X16+X15+X2+1).
R#S: Registers for Input.
ANSI CRC-16 CRCA R#S, R#T, R#N
R#T: Registers to hold the result, 16bit, LSB mode.
R#N: Save the length for CRC byte data, 8bit.
E.g. CRCA R10, R80, R9
Perform CCITT CRC-16 calculation on series of Registers. CCITT
CRC-16(X16+X12+X5+1).
R#S: Registers for Input.
CCITT CRC-16 CRCC R#S, R#T, R#N
R#T: Registers to hold the result, 16bit, MSB mode.
R#N: Save the length for CRC byte data, 8bit.
E.g. CRCC R10, R80, R9
R#S: 32bit Integer needed transfering; R#T: ASCII string register group
transfered;
<MOD>: Transfer mode,high 4bit is length of Integer bit, low 4bit is
number of Decimal.
ASCII string transfered with symbol, Right alignment, empty is filled
HEX transfer ASCII R#S, R#T,
HEXASC with 0x20.
string <MOD>
To data 0x12345678,
<MOD>=0x62 transfered result is+054198.96
<MOD>=0xF2 transfered result is+3054198.96
HEXASC R20, R30, 0x62

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Convert ASCII string to signed 64-bit HEX data.

R#S: Starting address for registers stored ASCII Strings.
Convert ASCII string R#T: A 64bits register to hold the output 64-bit Hex data.
ASCHEX R#S, R#T, <LEN>
to HEX characters <LEN>: The length for ASCII string, include sign bit and decimal point.
0x01-0x15.
E.g. ASCHEX R10, R80, 0x05

Process the data in the data storage area, and the data is a 16-bit
unsigned number.
R#P: 7 register data D0-D7 starting from R#P.
D0The start address of the register where the processing result is
saved.
D1: D2 The next (future) data is at the first address (relative address,
data location) of the data buffer the historical data will be read forward
from the current position during processing).
D3: D4 The start address of the data buffer area in the data storage
area.
D5: D6 The word length of a D6 data buffer area must not be less than
the value of R#N.
R#N: The number of data processing points (1-N words per point),
0x00-0xFF, 0x00 means 256.
<MOD>=0x00
Calculate the average value, and the result is a 32-bit unsigned number
with a unit of 1/65536.
<MOD>, R#P, <MOD>=0x01
Data processing MATH
R#N Calculate the max value, and the result is a 16bit unsigned number.
<MOD>=0x02
Calculate the min value, and the result is a 16-bit unsigned number.
<MOD>=0x03
Calculate the root mean square (RMS), and the result is a 32-bit
unsigned number with a unit of 1/65536.
<MOD>=0x04
According to y=k*x+b, carry out least square method parameter
estimation.
The data storage format is (x0, y0)...(xn, yn), and the return format is (k,
b).
k, b The returned result is a 32-bit integer, and the unit is 1/65536.
<MOD>=0x05
Not support.
<MOD>=0x06
Calculate the standard deviation (RMSE), and the result is a 32-bit
unsigned number with a unit of 1/65536.
MATH 0, R0, R10

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4.5 Process Controlling
Command
Code Number Description
Function
None of operation.
None NOP
NOP
Evaluate the <bit> in R# register. If 1, jump to <NUM>; if 0, proceed to
next instruction, jump range +/-127 instructions.
R#: the register contains data to be evaluated.
<Bit>: the index of the bit to be evaluated. 0x00-0x0F (MSB).
Conditional bit jump JB R#, <Bit>, <TAB>
<TAB>: jump position.
E.g.JB R10, 15, TEST1
NOP
TEST1: ADD R8, R12, R16

Compare the value of 2 8-bit registers (R#A and R#B). If equal, proceed
Variable conditional R#A, R#B, to the next instruction; if not equal, jump to<NUM>.
CJNE
jump (not equal) <TAB> E.g. TEST1: NOP
INC R10, 0, 1 CJNE R10,R11, TEST1

16bit Integer Compare the value for 2-bit integer in R#A and R#B. If A>=B, proceed
R#A, R#B,
conditional jump (less JS to the next instruction; If A<B, jump to <NUM>
<TAB>
than) E.g. JS R10, R12, TEST1 NOP TEST1: NOP
Compare A, B 16bit the unsigned, A>=B carry out next command, A<B
16bit comparison, R#A, R#B, jumping, range of jumping +/-127 commands.
JU
<jumping <TAB> JU R10, R12, TEST1 NOP
TEST1: NOP
Compare the value in 8-bit Register and a instant Number <INST>. If
Value conditional jump R#, <INST>, equal, process to next instruction; if not equal, jump to <NUM>.
IJNE
(number and Variable) <TAB> E.g. IJNE R10, 100, TEST1 NOP
TEST1: NOP
R#is 16bit, every count R#=R#-<NUM>, if R#> 0 jumping,
In contrast, carry out next command, range of jumping +/-
R#, <NUM>,
Decrement> 0 jumping DJNZ 127commands.
<TAB>
TEST1: NOP
DJNZ R10, 1, TEST1
Return to the main program by calling this function in the sub-program.
Return RET
E.g.RET
Interrupt program Interrupting program and return.
REIT
return RETI
Call sub-program in a position of program counter max support 32
Call sub-function CALL <PC> levels of program nesting.
E.g. CALL TEST
Program jump.
If <PC>=0xFFFF, it means taking the position of <R5:R6:R7> as the
reference, and R1: R0 as the relative PC.
Direct jump GOTO <PC>
Pointer to jump.
E.g. GOTO TEST1 NOP
TEST1: NOP
DWIN OS program over command after carrying out this command, PC
Program end END pointer reset to 0x1000, run again. same as software reset.
END

Notice:
Interrupting program should apply GOTO, RETI command.
Subprogram calling must use CALL and RET commands in pairs, transferring the program with GOTO
and RET command will result in an abnormal stack overflow.

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4.6 Peripheral Operation
Command
Code Number Description
Function

Set serial port mode:

<MODE>: high 4bit choose serial port needed to be set, 3=UART3
… 5=UART5
low 4bit choice mode. 0x*0=N81, 0x*1=E81,
0x*2=O81, 0x*3=N82 mode.
<BS>: baud rate setting value,
2Bytes.
For UART3,
<MODE/R#>,
Serial setting COMSET Setting value= 6451200/ set baud,
<BS> rate. setting value range = 1-1023.
To UART4-UART5, setting value= 25804800/ set, range of setting
value 1-65535.
Corresponding UART’s transceiver buffer will be cleared during each
setting procedure.
If<BS>=0x0000, then<MODE>will be register pointer, pointing
3 registers, in sequence corresponded to<MODE>, <BS>
value. COMSET 0x30, 136

Dispatching data to specified port.

<COM>: choose port, 0-2 no support 3=UART3…
<COM>, 5=UART5
Serial send COMTXD R#S: data register group to be sent.
R#S, R# N
R#N: bytes register to be sent, 8bit, register data 0x00 refers to sending
256 Bytes data. COMTXD 3, R10, R9

Returning to COM, receiving buffer area (FIFO) and data bytes

length (0-255) to R# register.
Check 0x00 refers to no data.
RDXLEN <COM>, R#
COM_Rx_FIFO <COM>: choose port, 0-2 no support 3=UART3…
5=UART5 RDXLEN 3, R10

Receiving buffer (FIFO) from COM, then reading R#B bytes (01-
<COM>, 255) to R#A register.
Read COM_Rx_FIFO RDXDAT <COM>: choose serial port, 0-2 no support, 3=UART3…
R#A, R#B
5=UART5 RDXDAT 3, R11, R10

<NUM> register content with R# points sent to COM.

<COM>, <COM>: choose serial port, 0-2 no support, 3=UART3… 5=UART5
Direct serial transmit COMTXI COMTXI 3, R20,16
R#, <NUM>

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<TYPE>: hardware type choice, just low 7bit effective.
TYPE.7=0 refers to D1, D0 as immediate values.
TYPE.7=1 refers to D1 will be register pointer, pointing 2 registers.
TYPE.6-TYPE.0 select the hardware type,
0x00: Setting I/O port mode.
D1 chooses IO port, 0x00-0x02 corresponds P0-P2, among them P0.7-
P0.0 corresponds IO7-IO0
P1.7-P1.0 corresponds IO15-IO8 P2.1-
P2.0 corresponds IO17-IO16 D0 is
corresponds setting value.
D0.X=1 as output (Push-Pull) D0.X=0 as input (Open Drain)
<TYPE>, 0x01: Setting timer.
Hardware setting CONFIG <D1/R#>, D1 chooses timer, and 0x02-0x03 corresponds T2, T3. D0
sets timer datum, unit as 1ms, 0x00 refers to 256.
<D0> 0x02: LIB code loading. As variable space address, D1: D0 should
be even.
Loading to code space starting as 0x0000, adopting CALL 0x0000 to
transfer.
0x03: DWIN OS code loading. As variable space address, D1: D0
should be even.
0x04: Unencrypted 512-byte OS code loading (program call or process
management); D1: 00 is the variable space word address of the stored
code, and D0: 00 is the code space byte address.
Loading code should be encrypted in advance by DWIN specialized
tool, loading time is about 200uS.
CONFIG 0, 0, 0x0F
Outputting to a specified IO port（8-bit or 1bit）.
<P#>: A serial number of IO port. 0x00-0x02 corresponds to P1-P3.
<MOD>: outputting mode
0x00=8 bit output, output is immediate number
<OUT>.
<P#>, 0x01=8 bit output, output is R# specified value.
0x*2=output R#.0, then put R# right ring shift once, <MOD> high 4bit
IO operation: output OUTPUT <MOD>, as IO position.
R#/<OUT> 0x*3=output R#.7, then put R# left ring shift once, <MOD> high 4bit
as IO position.
OUTPUT 0, 0, 0x55; P0（IO7-IO0）port outputs 01010101
OUTPUT 1, 0x32, R2; R2.0 outputs to IO11, and R2 right ring shift
once.

Read the content of specified IO port（8-bit or 1bit) to register.

<P#>: The serial number of IO port, 0x00-0x02 corresponds P1-P3.
<MOD>: Inputting mode
0x00=8 bit parallel
inputting.
<P#>, 0x*2=R# right ring move once, reading R#.7, <MOD> high 4bit as
IO position.
IO operation: input INPUT <MOD>, 0x*3=R# left ring move once, read R#.0, <MOD> high 4bit as
R# IO position.
R#: Register ID read from IO port data.
INPUT 1, 0, R20; IO15-IO8 outputs R20 register value
INPUT 1, 0x32, R2; R2 right ring move once, reading R2.7 as IO11
status.

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5. Appendix
Software
Date Content Revision
version

2019.02.12 First Issuance V1.0

If there is any question when you using this file or DWIN product, or willing to know more about DWIN
product news, feel free to contact us:
Hotline: 86-4000189008
Mail: [email protected]

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