Basis for

UMA NUMA
comparison
Basic Uses a single memory controller Multiple memory controller
Type of buses used Single, multiple and crossbar. Tree and hierarchical
Memory accessing Changes according to the distance of
Equal
time microprocessor.
General purpose and time-sharing
Suitable for Real-time and time-critical applications
applications
Speed Slower Faster
Bandwidth Limited More than UMA.

Definition of UMA

UMA (Uniform Memory Access) system is a shared memory architecture for the
multiprocessors. In this model, a single memory is used and accessed by all the processors
present the multiprocessor system with the help of the interconnection network. Each processor
has equal memory accessing time (latency) and access speed. It can employ either of the single
bus, multiple bus or crossbar switch. As it provides balanced shared memory access, it is also
known as SMP (Symmetric multiprocessor) systems.

The typical design of the SMP is shown above where each processor is first connected to the
cache then the cache is linked to the bus. At last the bus is connected to the memory. This UMA
architecture reduces the contention for the bus through fetching the instructions directly from the
individual isolated cache. It also provides an equal probability for reading and writing to each
processor. The typical examples of the UMA model are Sun Starfire servers, Compaq alpha
server and HP v series.

Definition of NUMA
NUMA (Non-uniform Memory Access) is also a multiprocessor model in which each processor
connected with the dedicated memory. However, these small parts of the memory combine to
make a single address space. The main point to ponder here is that unlike UMA, the access time
of the memory relies on the distance where the processor is placed which means varying memory
access time. It allows access to any of the memory location by using the physical address.

As mentioned above the NUMA architecture is intended to increase the available bandwidth to
the memory and for which it uses multiple memory controllers. It combines numerous machine
cores into “nodes” where each core has a memory controller. To access the local memory in a
NUMA machine the core retrieves the memory managed by the memory controller by its node.
While to access the remote memory which is handled by the other memory controller, the core
sends the memory request through the interconnection links.

Page Replacement Algorithm

Page Replacement Algorithm decides which page to remove, also called swap out when a new
page needs to be loaded into the main memory. Page Replacement happens when a requested
page is not present in the main memory and the available space is not sufficient for allocation to
the requested page.

When the page that was selected for replacement was paged out, and referenced again, it has to
read in from disk, and this requires for I/O completion. This process determines the quality of the
page replacement algorithm: the lesser the time waiting for page-ins, the better is the algorithm.
A page replacement algorithm tries to select which pages should be replaced so as to minimize
the total number of page misses. There are many different page replacement algorithms. These
algorithms are evaluated by running them on a particular string of memory reference and
computing the number of page faults. The fewer is the page faults the better is the algorithm for
that situation.

Some Page Replacement Algorithms :

 First In First Out (FIFO)

 Least Recently Used (LRU)
 Optimal Page Replacement

RAM

The RAM memory is the fastest but is a volatile memory. That means to retain its content the
RAM memory has to be provided with a constant power supply. Once the power supply to this
memory chip is switched off this memory chip loses all its content.

It is easy to read data from and write data into the RAM memory. The data is read or written into
the RAM memory using the electric signals. Further, the RAM memory has two other forms
DRAM and SRAM.

Short for double data rate three, DDR3 is a type of DRAM (dynamic random-access memory) released in
June 2007 as the successor to DDR2. DDR3 chips have bus clock speed of 400 MHz up to 1066 MHz,
range in size from 1 to 24 GB, and consume nearly 30% less power than their predecessors. DDR3 RAM
sticks for a desktop computer have 240 pins. For a laptop computer, DDR3 RAM sticks have 204 pins.

Flynn's Classification of Computer Architecture

In this tutorial, we are going to learn about the Flynn's Classification of Computer
Architecture in Computer Science Organization.
Submitted by Uma Dasgupta, on November 21, 2019

Classification of computer architecture

According to Flynn's there are four different classification of computer architecture,

1) SISD (Single Instruction Single Data Stream)

Single instruction: Only one instruction stream is being acted or executed by CPU during one
clock cycle.

Single data stream: Only one data stream is used as input during one clock cycle.
A SISD computing system is a uniprocessor machine that is capable of executing a single
instruction operating on a single data stream. Most conventional computers have SISD
architecture where all the instruction and data to be processed have to be stored in primary
memory.

2) SIMD (Single Instruction Multiple Data Stream)

A SIMD system is a multiprocessor machine, capable of executing the same instruction on all the
CPUs but operating on the different data stream.

IBM 710 is the real life application of SIMD.

3) MISD (Multiple Instruction Single Data stream)

An MISD computing is a multiprocessor machine capable of executing different instructions on

processing elements but all of them operating on the same data set.

4) MIMD (Multiple Instruction Multiple Data Stream)

A MIMD system is a multiprocessor machine that is capable of executing multiple instructions

over multiple data streams. Each processing element has a separate instruction stream and data
stream.
Conclusion:

In the above article, we discussed Flynn's classification of computer architecture in brief with
illustrative diagrams in a very easy manner. Don’t forget to go through the diagrams as well.

What is Inter Process Communication?

In general, Inter Process Communication is a type of mechanism usually provided by the
operating system (or OS). The main aim or goal of this mechanism is to provide communications
in between several processes. In short, the intercommunication allows a process letting another
process know that some event has occurred.

Let us now look at the general definition of inter-process communication, which will explain the
same thing that we have discussed above.

Definition

"Inter-process communication is used for exchanging useful information between numerous

threads in one or more processes (or programs)."
To understand inter process communication, you can consider the following given diagram that
illustrates the importance of inter-process communication:

Role of Synchronization in Inter Process Communication

It is one of the essential parts of inter process communication. Typically, this is provided by
interprocess communication control mechanisms, but sometimes it can also be controlled by
communication processes.

These are the following methods that used to provide the synchronization:

1. Mutual Exclusion
2. Semaphore
3. Barrier
4. Spinlock

MOBILE PROCESSOR

A CPU chip designed for laptops, tablets, smartphones and other portable devices. Mobile
processors use lower voltages and are designed to run cooler than the CPUs in desktop
computers. They typically have more "sleep modes" that enable sections of the chip to be
throttled down or turned off when not used. The most widely used mobile processors are ARM
chips. See ARM, Intel Atom, mobile platform.

Virtual Processor

A virtual processor is more likely amount of processing time spent on the CPU. If we use technical
terminology;  Virtual processors are mapped to available logical processors in the physical computer and
are scheduled by the Hypervisor software to allow you to have more virtual processors than you have
logical processors. People may have misconception that 1 vCPU equals to 1 core. But there is no one to
one relationship between vCPU and core in any virtualization software.

Basis for Tightly Coupled

Loosely Coupled Multiprocessor System
Comparison Multiprocessor System
Processors have shared
Basic Each processor has its own memory module.
memory modules.
Efficient when tasks running on different Efficient for high-speed or
Efficient
processors, has minimal interaction. real-time processing.
It generally, do not encounter memory It experiences more memory
Memory conflict
conflict. conflicts.
Interconnection networks
Interconnections Message transfer system (MTS).
PMIN, IOPIN, ISIN.
Data rate Low. High.
Expensive Less expensive. More expensive.

Definition of Loosely Coupled Multiprocessor System

Multiprocessor is one which has more than two processors in the system. Now when the degree
of coupling between these processors is very low, the system is called loosely coupled
multiprocessor system. In loosely coupled system each processor has its own local memory, a
set of input-output devices and a channel and arbiter switch (CAS). We refer to the processor
with its local memory and set of input-output devices and CAS as a computer module.

Processes that execute

on different computer modules communicate with each other by exchanging the messages
through a physical segment of message transfer system (MTS). The loosely coupled system is
also known as distributed system. The loosely coupled system is efficient when the processes
running on different computer module require minimal interaction.

If the request fo accessing MTS of two or more computer module collide, the CAS responsibly
chooses one of the simultaneous requests and delay other requests until selected request is
serviced completely. The CAS has a high-speed communication memory which can be
accessed by all the processors in the system.The communication memory in CAS is used to
buffer the transfers of messages.

Definition of Tightly Coupled Multiprocessor System

The throughput of the loosely coupled system may be too low for some of the applications that
require fast access time. In this case, Tightly coupled microprocessor system must be used.
The tightly coupled system has processors, shared memory modules, input-output channels.

The above
units of the tightly coupled system are connected through the set of three interconnection
networks, processor-memory interconnection network (PMIN), I/O-processor
interconnection network (IOPIN) and the interrupt-signal interconnection network (ISIN).
The use of these three interconnection networks is as follow.

 PMIN: It is a switch which connects each processor to every memory module. It can
also be designed in a way that a processor can broadcast data to one or more memory
module.
 ISIN: It allows each processor to direct an interrupt to any other processor.
  IOPIN: It allows a processor to communicate with an I/O channel which is connected
to input-output devices.

What is a multicore System?

A multicore processor is an integrated circuit that has two or more processor cores attached for
enhanced performance and reduced power consumption. These processors also enable more
efficient simultaneous processing of multiple tasks, such as with parallel processing and
multithreading. A dual core setup is similar to having multiple, separate processors installed on a
computer. However, because the two processors are plugged into the same socket, the connection
between them is faster.

The use of multicore processors or microprocessors is one approach to boost processor

performance without exceeding the practical limitations of semiconductor design and fabrication.
Using multicores also ensure safe operation in areas such as heat generation.

INTERRUPT PROCESSING:

An interrupt is an event that alters the sequence in which a processor executes instructions. It is
generated by the Hardware of the computer system. When an interrupt occurs.

1.  The operating system gains control.

2.  The operating system saves the state of the interrupted process. In many systems this
information is stored in the interrupted process’s PCB.
3.  The operating system analyzes the interrupt and passes control to the appropriate routing
to handle the interrupt.
4.  The interrupt handler routine processes the interrupt.
5.  The state of the interrupted process is restored.
6.  The interrupted process executes.

An interrupt may be initiated by a running process called a trap and said to be synchronous with
the operation of the process or it may be caused by some event that may or may not be related to
the running process it is said to be asynchronous with the operation of the process.