Digital Integrated circuits

UNIT 4
 Overview
• Integration, Moore’s law
• Early families (DL, RTL)
• TTL
• Evolution of TTL family
• ECL
• CMOS family and its evolution
• Overview
 Integration Levels
• Gate/transistor ratio is roughly 1/10
– SSI < 12 gates/chip
– MSI < 100 gates/chip
– LSI …1K gates/chip
– VLSI …10K gates/chip
– ULSI …100K gates/chip
– GSI …1Meg gates/chip
 Moore’s law
• A prediction made by Moore (a co-founder of Intel) in
1965: “… a number of transistors to double every 2
years.”
 In the beginning…
Diode Logic (DL)
•simplest; does not scale
•NOT not possible (need an =

active element)

Resistor - Transistor Logic (RTL)

•replace diode switch with a
transistor switch
•can be cascaded
=
•large power draw
Diode-Transistor Logic (DTL)
•essentially diode logic with transistor
amplification
•reduced power consumption
•faster than RTL

DTL AND gate Saturating inverter

 Logic families: V levels
VOH(min) – The minimum voltage level at an output in
the logical “1” state under defined load conditions

VOL(max) – The maximum voltage level at an output in the

logical “0” state under defined load conditions

VIH(min) – The minimum voltage required at an input

to be recognized as “1” logical state

VIL(max) – The maximum voltage required at an input that

still will be recognized as “0” logical state

VOH VIH VOL VIL

 Logic families: I requirements

IOH – Current flowing into an output in the logical “1” state under specified load
conditions
IOL – Current flowing into an output in the logical “0” state under specified load
conditions
IIH – Current flowing into an input when a specified HI level is applied to that
input IIL – Current flowing into an input when a specified LO level is applied to
that input

IOH IIH IOL IIL

VOH VIH VOL VIL

 Logic families: fanout
Fanout: the maximum number of logic inputs (of the
same logic family) that an output can drive reliably

DC fanout = min( IOH ), IOL

I
I H IL I
Logic families: propagation delay

TPD,HL TPD,LH

TPD,HL – input-to-output
propagation delay from HI
to LO output TPD,LH – input-
to-output propagation delay
from LO to HI output

Speed-power
product: TPD  Pavg
Logic families: noise margin
HI state noise margin:
VNH = VOH(min) – VIH(min)

LO state noise margin:

VNL = VIL(max) – VOL(max)

Noise margin:
VOH(min)
VN = min(VNH,VNL)
VNH
VIH(min)

VNL VIL(max)

VOL(max)
TTL
Bipolar Transistor-Transistor Logic (TTL)
•first introduced by in 1964 (Texas Instruments)
•TTL has shaped digital technology in many ways
•Standard TTL family (e.g. 7400) is obsolete
•Newer TTL families still used (e.g. 74ALS00)

Distinct features
• Multi-emitter transistors
•Totem-pole transistor
arrangement
2-input NAND
TTL evolution
Schottky series (74LS00) TTL
•A major slowdown factor in BJTs is due to
transistors going in/out of saturation

•Shottky diode has a lower forward bias (0.25V(

•When BC junction would become forward biased, the

Schottky diode bypasses the current preventing the
transistor from going into saturation
 TTL family evolution

Legacy: don’t use in new

designs Widely used today
 ECL
Emitter-Coupled Logic (ECL)
•PROS: Fastest logic family available (~1ns)

•CONS: low noise margin and high power

dissipation

•Operated in emitter coupled geometry (recall differential

amplifier or emitter-follower), transistors are biased and
operate near their Q- point (never near saturation!)

• Logic levels. “0”: –1.7V. “1”: –0.8V

•Such strange logic levels require extra effort when

interfacing to TTL/CMOS logic families.
CMOS
Complimentary MOS (CMOS)
• Other variants: NMOS, PMOS (obsolete)

• Very low static power consumption

• Scaling capabilities (large integration all MOS)

• Full swing: rail-to-rail output

• Things to watch out for:

– don’t leave inputs floating (in TTL these will float
to HI, in CMOS you get undefined behaviour)
–susceptible to electrostatic damage (finger of death)
 Combinational Logic Circuits

Combinational
Logic Circuits

18
What is a Combinational circuit?
At instant, the output of the logic circuit depends on present
inputs. (MEMORY-NOT REQ..)

Design procedure:

1. Identify the number of inputs and outputs required for the

design of the circuit.
2. Derive the truth table.
3. Write the expression for the output either in SOP or POS
form.
4. Simplify the expression for the output.
5. Draw the logic circuit for the simplified expression.
 Applications of combinational circuits
1. Multiplexer
are
2. Demultiplexer
3. Encoder
4. Decoder
5. Seven Segment Decoder
6. Half Adder
7. Full Adder
8. Binary Adder
9. Half Subtracter
10. Full Subtracter

20
ADDERS
Logic circuit which performs the addition of binary numbers
Adders of two types:
1. Half Adder (H.A)
2. Full Adder (F.A)

Half Adder

It is a combinational logic
circuit which performs
addition of two binary bits.
22
A B Sum(S) Carry(C)
0
0
0
1
0
1
0
0
S  AB  A B
1
1
0
1
1
0
0
1 C  AB
Full Adder
It is a combinational logic circuit which performs addition
of three binary inputs.

S  A BC in  AB C in  A B C in  ABC in
 A ( BC in  B C in )  A ( B C in  BC in )
 A ( B  C in )  A ( B  C in )
 A  B  C in

C out  ABC in  A BC in  AB C in  ABC in

 C in ( AB  A B )  AB (C in  C in )
 C in ( A  B )  AB
Realizing Full Adder with two Half Adders and one OR gate
SUBTRACTORS
Logic circuit which performs subtraction of binary numbers.
Subtractors are of two types: A B Difference(D) Borrow(B0)
1. Half Subtractor (H.S) 0 0 0 0
0 1 1 1
2. Full Subtractor (F.S)
1 0 1 0
Half Subtractor 1 1 0 0

A D
Half
Subtra
ctor
B BOUT

D  AB  A B
B 0  AB
Full Subtractor
Combinational circuit which performs subtraction on three
binary digits.
A D
D  ABBin  ABBin  ABBin  ABCin
Half
B Subtra
ctor
 A(BBin  BBin )  A(BBin  BBin )
Bin
BOUT
 A(B  Bin )  A(B  Bin )
A B Bin D BOUT
0 0 0 0 0  A  B  Bin
0 0 1 1 1
0 1 0 1 1
0 1 1 0 1 Bout  ABBin  ABBin  ABBin  ABBin
1 0 0 1 0
1 0 1 0 0
 Bin ( AB  AB)  AB (Bin  Bin )
1 1 0 0 0
 Bin ( A  B)  AB
1 1 1 1 1
Realizing Full Subtractor using two Half Subtractors & one OR gate

Half Half D
Subtractor Bin Subtractor
B

Bout
4-Bit Binary Parallel Adder
Each stage output in the parallel adder depends on
the previous stage carry and Delay time is additive.

4-Bit Binary Parallel SUBTRACTOR ((r’s

r’s and rr--1’s)
r’s = 1 + r-
r-1’s ( r-
r-1’s is complement all 1s and 0s in number)
r’s complement : if carry comes neglect the carry- if carry note comes result once again r’s
complement and place minus sign front.
M=1010100 and N=1000100 -----2’s complement of N 0111100
M - N = 1010100 + 0111100 = 1carry, ans 001OOOO (correct answer it is ,carry neglect)

M=1000100 and N= 1010100 -----2’s complement of N 0101100

M - N = 1000100 + 0101100 = no carry, 1110000 (not correct answer no carry)
Answer: -10000 = -(2’s complement of 1110000 )
(r-1)’s complement : if carry comes add the carry- if carry note comes result once again (r-1)’s
complement and place minus sign front.
M=1010100 and N=1000100 -----1’s complement of N 0111011
M - N = 1010100 + 0111011 = 1carry, 0001111 (not correct answer)
(correct answer is 0001111 +1= 0010000, add carry for correct answer)

M= 1000100 and N= 1010100 -----1’s complement of N 0101011

M - N = 1000100 + 0101011 = no carry, 1101111 (not correct answer no carry)
Correct Answer: -10000 = -(1’s complement of 1101111 )
1’s Complement Subtractor

It requires two stages of addition. When the end carry is 1, it has to be added with the
LSB adder. If the end carry is zero, single stage of addition produces the result but the
answer is negative.
2’s Complement Adder/Subtractor

Adder -- if M=0
Subtractor--if M=1

When the control input, M is 0 the output of XOR gates are

B3B2B1B0 and the circuit functions as a 2’s complement adder. When
the control input is 1 the output of XOR gates are B3’ B2’ B1’ B0’ which
is the 1’s complement of the subtrahend. Since the control input is 1,
the binary 1 is added with the LSB added with B3’ B2’ B1’ B0’ which
produces 2’s complement of the subtrahend. Therefore the circuit
behaves as an 2’s complement subtractor.
CO MPARATORS
A comparator is a logic circuit use to compare the magnitudes
of two binary numbers. It provide an output that is active when the
two numbers are equal, or additionally provide outputs that signify
which of the numbers is greater when equality does not hold.

The XNOR gate (coincide gate) is a basic comparator, because

its output is a 1 only if its two input bits are equal.

Two binary numbers are equal, if and only if all their

corresponding bits coincide. For instance, two 4-bit binary numbers
A3A2A1A0 and B3B2B1B0 are equal. To implement this logic

Equality  ( A 3  B 3 )( A 2  B 2 )( A1  B 1 )( A 0  B 0 )
1 - B i t M a g n i t u d e C o m p a ra
ratto
or
The logic for a 1-bit comparator:
let the 1-bit numbers be A=A0 and B=B0
If A 0  1 and B 0  0, then A  B
therefore, A  B :G  A 0 B 0

If A 0  0 and B 0  1, then A  B
therefore, A  B :L  A 0 B 0

If A 0 and B 0 coincide , then A  B

therefore, A  B :E  A0 B 0

A0 B0 L E G A0
0 0 0 1 0
0 1 1 0 0
1 0 0 0 1
B0
1 1 0 1 0
2-bit Magnitude Comparator

The logic for a 2-bit magnitude comparator:

1. If A1 = 1 and B1 = 0, then A > B or

2. If A1 and B1 coincide and A0 = 1 and B1 = 0, then A > B. So
the logic for A > B is
A  B : G  A1 B 1  ( A1  B1 ) A0 B 0
1. If A1 = 0 and B1 = 1, then A < B or
2. If AJ1 and B1 coincide and A0 = 0 and B0 = 1, then A < B.
So the logic for A < B is

A  B : L  A 1 B 1  ( A1  B1 ) A 0 B 0
If A1 and B1 coincide and if A0 and B0 coincide then A = B.
So the logic for A = B is
A  B : E  ( A 1  B 1 )( A 0  B 0 )

A1
B’1
A >B
A0
A1 B’0
B1
A0 A= B
B0
A’0
B0
A <B
A’1
B1
 4-Bit Magnitude Comparator

The logic for a 4-bit magnitude comparator:

1. If A3 = 1 and B3 = 0, then A > B or
2. If A3 and B3 coincide, and if A2 = 1 and B2 = 0, then A > B or
3. If A3 and B3 coincide, and if A2 and B2 coincide, and if A1=1
and B2 = 0, then A > B or
4. If A3 and B3 coincide, and if A2 and B2 coincide, and if A1
and B1 coincide, A0=1 and B1 = 0, then A > B or
So the logic for A > B is

A  B : G  A3 B 3  ( A3  B 3 ) A2 B 2 
( A3  B 3 )( A2  B 2 ) A1 B 1  ( A3  B 3 )( A2  B 2 )( A1 B1 ) A0 B 0
The logic for A < B is:
1. If A3 = 0 and B3 = 1, then A < B or
2. If A3 and B3 coincide, and if A2 = 0 and B2 = 1, then A < B or
3. If A3 and B3 coincide, and if A2 and B2 coincide, and if A1=0
and B2 = 1, then A < B or
4. If A3 and B3 coincide, and if A2 and B2 coincide, and if A1
and B1 coincide, A0=0 and B1 = 1, then A < B or
So the logic for A < B is
A  B : L  A 3 B 3  ( A3  B3 ) A 2 B 2 
( A3  B3 )( A2  B 2 ) A1 B1  ( A3  B3 )( A2  B 2 )( A1 B1 ) A 0 B0

A  B : E  ( A3  B 3 )( A 2  B 2 )( A1  B1 )( A0  B 0 )
MULTIPLEXERS
A Multiplexer (MUX) or data selector is a logic circuit that accepts several data inputs and
allows only one of them at a time to get through to the output.

The routing of the desired data input to the output is controlled by SELECT lines.

A MUX selects 1-out-of-N input data sources and transmits the selected data to a single
output channel. This is called Multiplexing.

MUX is also known as Many to One device.

2n X n
2n
i/p s MUX
o/p

n select lines
Multiplexer & Demultiplexer
Demultiplexer

Applications of Multiplexers

1. Data selection
2. Data routing
3. Operation sequencing
4. Waveform generation Multiplexer
5. Parallel to serial conversion
6. Logic function generation 39
 Quadruple 2-to-1 Line Multiplexer

E S Y
(Enable) (Select) (Output)

0 X All 0’s
1 0 A
1 1 B

Used to supply four bits to the output. In this case two inputs four bits
each.
Logic Function Generator
•A multiplexer can be used in place of logic gates to implement a
logic expression.
•It can generate any Boolean algebraic function of a set of input
variables.
•A single IC can perform a function.
•It is very easy to change the logic function implemented, if and
when redesign of a system becomes necessary.
Multiplexers can be used to implement a logic function directly
from the function table without the need for simplification. The
select inputs of the multiplexer are used as the function variables.
The inputs of the multiplexer are connected to logic 1 and 0 to
represent the missing and available terms.
4 X 1 MUX

Y  S1S0I0  S1S0I1  S1S0I2  S1S0I3

S1 S0

I0

S1 S0 Y
I1
0 0 I0
0 1 I1 I2 Y
1 0 I2
1 1 I3 I3
Ex: Implementation of F(A,B,C) = Σm(1,3,5,6) using 8 : 1 MUX

1 0

0
1
2
3 8:1
MUX
4 Y

5
6
7
S2 S1 S0

A B C
Ex: Implementation of F(A,B,C) = Σm(1,3,5,6) using 4 : 1 MUX

Step 1: Select the MSB variable as input and the remaining as

selector lines variables to the MUX. If the function has n variables,
then the size of the required MUX is 2n-1 – to – 1.

Step 2: Draw the truth table for the given function.

Step 3: Complete the function table.

a) if both the minterms are circled, apply 1 to the
corresponding MUX input.
b) if both are not circled, apply 0 to the corresponding
MUX input.
c) if the top is circled and bottom is not circled, apply A1
to the corresponding MUX input.
d) if the top is not circled and bottom is circled, apply A
to the corresponding MUX input.
 I0 I1 I2 I3
A B C F A1 0 1 2 3
A 4 5 6 7
0 0 0 0
0 0 1 1 0 1 A A1

0 1 0 0
0 1 1 1
1 0 0 0 0 I0
1 0 1 1 1 I1 4:1
MUX Y
1 1 0 1 A I2
1 1 1 0 I3 S1 S0
A1

B C
DEMULTIPLEXER
Demultiplexer,
DEMUX does the reverse
operation of a MUX. It
receives the message over
one input line and directs
the message to of the
many output lines. Hence
it known as One to Many
1 X 2n
device. 2n
DEMUX o/p s
i/p

n select lines
S1 S0 D Y0 Y1 Y2 Y3
0 0 1 1 0 0 0
0 1 1 0 1 0 0
1 0 1 0 0 1 0
1 1 1 0 0 0 1

S0 S1

Y0  S 1 S 0 D
D AND Y0
Y1  S 1 S 0 D
AND Y1

Y2  S1 S 0D AND
Y2
Y3  S1S 0 D AND Y3
Encoder & Decoder

Decoder
 Accepts a value and decodes it
 Output corresponds to value of n inputs
 Consists of:
 Inputs (n)
 Outputs (2n , numbered from 0  2n -1)

 Selectors / Enable (active high or active low) 48

2-to-4 Decoder The truth table of 2-to-4 Decoder
The truth table of 3-to-8 Decoder

A2 A1 A0 D0 D1 D2 D3 D4 D5 D6

0 0 0 1
0 0 1 1
0 1 0 1
0 1 1 1
1 0 0 1
1 0 1 1
1 1 0 1
1 1 1
3-to-8 Decoder with Enable
 Decoder Expansion
 Combine two or more small decoders with
enable inputs to form a larger decoder
 3-to-8-line decoder constructed from two 2-to- 4-
line decoders
 The MSB is connected to the enable inputs
 if A2=0, upper is enabled; if A2=1, lower is enabled.
Combining two 2-4 decoders to form one 3-
8 decoder using enable switch (WHY and HOW)

The highest bit is used for the enables

How about 4-16 decoder

 Use how many 3-8 decoder?

 Use how many 2-4 decoder?
Encoders
Perform the inverse operation of a decoder . 2n (or less) input lines and n
outputlines

Encoders with OR gates

TRUTH TABLE: 8 to 3 encoder
Priority Encoder
 Accepts multiple values and encodes them
 Works when more than one input is active

 Consists of:
 Inputs (2n)

 Outputs
 when more than one output is active, sets
output to correspond to highest input
 V (indicates whether any of the inputs are active)
 Selectors / Enable (active high or active low)
 TRUTH TABLE
D3 D2 D1 D0 A1 A0 V
Priority Encoder
0 0 0 0 x X 0
0 0 0 1 0 0 1
0 0 1 0 0 1 1
0 0 1 1 0 1 1
0 1 0 0 1 0 1
0 1 0 1 1 0 1
0 1 1 0 1 0 1
0 1 1 1 1 0 1
1 0 0 0 1 1 1
1 0 0 1 1 1 1
1 0 1 0 1 1 1
1 0 1 1 1 1 1
1 1 0 0 1 1 1
1 1 0 1 1 1 1
1 1 1 0 1 1 1
1 1 1 1 1 1 1
 Multiplexers versus decoders

•A Multiplexer uses n binary select bits to choose from a

maximum of 2n unique input lines.

•Decoders have 2^n number of output lines while

multiplexers have only one output line.

•The output of the multiplexer is the data input whose index is

specified by the n bit code.
 Multiplexer Versus Decoder
I3

I2

I1

I
0
S1

S
0
4-to-1 Multiplexer 2-to-4 Decoder

Note that the multiplexer has an extra OR gate.A1 andA0 are the two inputs
in decoder. There are four inputs plus two selecs in multiplexer.
Cascading multiplexers
Using three 2-1 MUX
to make one 4-1 MUX

S1 S0 F
0 0 I0
0 1 I1
1 0 I2
1 1 I3
Example: Construct an
8-to-1 multiplexer using I0
2-to-1 multiplexers. I1

S2 S1 S0 F
0 0 0 I0
I2
0 0 1 I1 I3
2-1
F
MUX
0 1 0 I2
S E

0 1 1 I3 I4 S2 E

1 0 0 I4 I5

1 0 1 I5

1 1 0 I6
I6
1 1 1 I7
I7
Example : Construct 8-to-1 multiplexer using one 2-to-1 multiplexer
and two 4-to-1 multiplexers

S2 S1 S0 X
0 0 0 I0

0 0 1 I1

0 1 0 I2

0 1 1 I3

1 0 0 I4

1 0 1 I5

1 1 0 I6

1 1 1 I7
 Decoders

• A decoder is a multiple-input, multiple-output logic circuit that

converts coded inputs into coded outputs, where the input and output
codes are different. The input code generally has fewer bits than the
output code, and there is a one-to one mapping from input code
words into output code words
 BINARY DECODER

TRUTH TABLE

The most common decoder

circuit is an n-to-2n decoder or
binary decoder.
Such a decoder has an n-bit
binary input code and a 1-out-
of-2n output code.
A binary decoder is used
when you need to activate
exactly one of 2n outputs
based on an n-bit input value.
 2 to 4 decoder logic symbol

The input code word I1,I0

represents an integer in the
range 0–3.
The output code word
Y3,Y2,Y1,Y0 has Yi equal to
1 if and only if the input code
word is the binary
representation of i and the
enable input EN is 1.
If EN is 0, then all of the
outputs are 0.
The 74x139 Dual 2-to-4
Decoder
A gate-
level circuit
for the 2-to-
4 decoder is
shown in
Figure
=>
Each AND
gate
decodes
one
combinatio
n of the
input code
word I1,I0.
The 74x139 dual 2-to-4 decoder: (a) traditional logic symbol (b ) logicdiagram,
including pin numbers for a standard 16-pin dual in-line package
Logic symbol of Figure-7
74X138
The 74x138 is a commercially
available MSI 3-to-8 decoder
whose gate-level circuit
diagram and symbol are
shown in Figure 7; its truth
table is given in Table 5-7.
Like the 74x139, the 74x138
has active-low outputs, and it
has three enable inputs (G1,
/G2A, /G2B), all of which
must be asserted for the
selected output to be asserted
Table 5-7
• Multiple binary decoders can be used to decode larger code words. Figure
shows how two 3-to- 8 decoders can be combined to make a 4-to-16
decoder. The top decoder (U1) is enabled when N3 is 0, and the bottom one
(U2) is enabled when N3 is 1.
Design of a 5-to-32 decoder using 74x138s.
 UNIT-5
Sequential Circuits
Combinational Logic

 Combinational Logic:
 Output depends only on current input
 Has no memory

Sequential Logic
 Sequential Logic:
 Output depends not only on current input but also
on past input values, e.g., design a counter
Need some type of memory to remember the past
input values
 Sequential Circuits

Circuits that we Information Storing

have learned Circuits
so far

Timed “States”
 Sequential Logic: Concept

1. Sequential Logic circuits remember past

inputs and past circuit state.

2. Outputs from the system are “fed

back” as new inputs

3. With gate delay and wire delay

4. The storage elements are circuits that are

capable of storing binary information:
memory.
 Synchronous vs. Asynchronous
Synchronous sequential circuit: circuit output changes only at some
discrete instants of time. This type of circuits achieves synchronization by
using a timing signal called the clock.
Asynchronous sequential circuit: circuit output can change at any time
(clockless).
 Clock Period

F F
F Combinational F
Circuit

F
F

Smallest clock period = largest combinational circuit delay between any two
directly connected FF, subjected to impact of FF setup time.
Flip-flops are the basic building blocks of Sequential Circuits which can be converted from one
form to another capable of storing a single bit of data
There are basically four different types of flip
flops and these are:
1. Set-Reset (SR) flip-flop or Latch
2. JK flip-flop
3. D (Data or Delay) flip-flop
4. T (Toggle) flip-flop

Basic NAND and NOR SR Flip-flops

Active HIGH Flip-flops
 SR Latch
0 X Y NAND
S’ Q 1 00 1
01 1
0 10 1
R’ Q’ 1 11 0

S’ R’ Q Q’
0 0 1 1 Disallowed
1 0 Set
0 1
1 0 1 1 Reset
1 1 2 0 Hold
0 1 Hold
JK FLIP FLOP
 D Latch
One way to eliminate the undesirable indeterminate
state in the RS flip flop is to ensure that inputs S and R
are never 1 simultaneously. This is done in the D latch:

Q(t+1)=D
Q(t+1) = TQ’ +T’Q
 Characteristic Tables
1. Defines the logical properties of a flip-flop (such as a truth table
does for a logic gate).
2. Q(t) – present state at time t AND Q(t+1) – next state at time t+1
LATCHES AND FLIPFLOPS

LATCHES : FLIPFLOPS
1. LATCH DOES NOT REQUIRED CLOCK SIGNAL. 1. FLIPFLOP REQUIRED CLOCK SIGNAL.
2. It is LEVEL SENSITIVE DEVICE. 2. It is EDGE SENSITIVE DEVICE.
3. LATCH IS ASYNCHRONOUS DEVICE. 3. FLIPFLOP IS SYNCHRONOUS DEVICE.
4. LESS POWER IS REQUIRED. 4. MORE POWER IS REQUIRED.
5. LATCH OUTPUT IS BASED ON ENABLE 5. FLIPFLOP OUTPUT IS BASED ON CLOCK
SIGNAL. SIGNAL.
6. CONSTRUCTED WITH BASIC GATES. 6. CONSTRUCTED WITH LATCHES.
D Flip-Flop Timing Parameters

Setup time
 ROM
MEMORY PROM
EPROM
RAM ROM EEPROM
SRAM PROM (PROM)
DRAM FLASH MEMORY
 Memory
 Sequential circuits all depend upon the presence of memory.
 A flip-flop can store one bit of information.
 A register can store a single “word,” typically 32 or 64 bits.

 Memory allows us to store even larger amounts of data.

 Read Only Memory (ROM)
 Random Access Memory (RAM)
 Static RAM (SRAM)

 Dynamic RAM (DRAM)

 Address Data
Picture of Memory 00000000
00000001
You can think of memory as being one big array of
0000000
data. 2
 The address serves as an array index. .
 Each address refers to one word of data. .
.
 You can read or modify the data at any given
.
memory address, just like you can read or modify
.
the contents of an array at any given index.
.
.
. Word
.
.
FFFFFFF
D
FFFFFFFE
FFFFFFFF
 Memory Signal Types
 Memory signals fall into three groups
 Address bus - selects one of memory locations
 Data bus
 Read: the selected location’s stored data is put on the data bus

 Write (RAM): The data on the data bus is stored into the selected
location
 Control signals - specifies what the memory is to do
 Control signals are usually active low

 Most common signals are:

 CS: Chip Select; must be active to do anything

 OE: Output Enable; active to read data

 WR: Write; active to write data

Memory Address, Location and size
 All bits in location are read/written together
 Cannot manipulate single bits in a location
 For k address signals, there are 2k locations in memory device
 Each location contains an n bit word
 Memory size is specified as
 #loc x bits per location
 224 x 16 RAM - 224 = 16M words, each 16 bits long

 24 address lines, 16 data lines

 #bits
 The total storage capacity is 224 x 16 = 228 bits
 Size matters!
 Memory sizes are usually specified in numbers of bytes (1 byte= 8 bits).
 The 228-bit memory on the previous page translates into:

228 bits / 8 bits per byte = 225 bytes

 With the abbreviations below, this is equivalent to 32 megabytes.

Prefix Base 2 Base 10

K Kilo 2 = 1,024
10
10 = 1,000
3

M Mega 220 = 1,048,576 106 = 1,000,000

G Giga 230 = 1,073,741,824 109 = 1,000,000,000
 Read-only memory (ROM)
2k x n ROM • Non-volatile
k – If un-powered, its content retains
ADRS Data n
Out
• Read-only
CS – normal operation cannot change
OE contents
• k-bit ADRS specifies the address or location to read from
• A Chip Select, CS, enables or disables the RAM
• An Output Enable, OE, turns on or off tri-state output buffers
• Data Out will be the n-bit value stored at ADRS
ROM PROGRAMMING

 Programmed ROM (PROM): contents loaded at the factory

 hardwired - can’t be changed

 embedded mass-produced systems

 OTP (One Time Programmable): Programmed by user

 UVPROM: reusable, erased by UV light
 EEPROM: Electrically erasable; clears entire blocks with single
operation
ROM Usage
 ROMs are useful for holding data that never changes.

 Arithmetic circuits might use tables to speed up computations of logarithms

or divisions.
Many computers use a ROM to store important programs that should not be
modified, such as the system BIOS.
 Application programs of embedded systems,PDAs, game machines, cell
phones, vending machines, etc., are stored in ROMs
ROM Structure
32Kx8 ROM
Typical commercial EEPROMs
Microprocessor EPROM application
ROM Timing
 Memories and functions
Address Data
 ROMs are actually combinational devices, not A2A1 A0 V2V1V0
sequential ones! 000 000
001 100
 You can store arbitrary data into a ROM, so
010 110
the same address will always contain the 011 100
same data. 100 101
101 000
 You can think of a ROM as a combinational 110 011
circuit that takes an address as input, and 111 011

produces some data as the output.

 A ROM table is basically just a truth table.

 The table shows what data is stored at each
ROM address.
 You can generate that data combinationally,
using the address as the input.
Logic-in-ROM Example
 EXAMPLE :Reading RAM
• 50 MHz CPU – 20 ns clock cycle time
• Memory access time= 65 ns
• Maximum time from the application of the address to the
appearance of the data at the Data Output
 WRITING RAM

2k x n memory
k ADDRESS DATA n
IN/OUT
RD/WR’
CS

 Enable the chip by setting CS = 1.

 Select the write operation, by setting RD/WR’ = 0.
 Send the desired address to the ADRS input.
 Send the word to store to the DATA IN/OUT.
WRITING RAM
• 50 MHz CPU – 20 ns clock cycle time
• Write cycle time= 75 ns
• Maximum time from the application of the address to the
completion of all internal memory operations to store a word
 Static memory
 How can you implement the memory chip?
 There are many different kinds of RAM.
 We’ll start off discussing static memory, which is most commonly used in
caches and video cards.
 Later we mention a little about dynamic memory, which forms the bulk of a
computer’s main memory.
 Static memory is modeled using one latch for each bit of storage.

 Why use latches instead of flip flops?

 A latch can be made with only two NAND or two NOR gates, but a flip-
flop requires at least twice that much hardware.
 In general, smaller is faster, cheaper and requires less power.
 The tradeoff is that getting the timing exactly right is a pain.
RAM Cell with SR Latch
RAM Bit Slice Model
8x2 RAM Using a 4x4 RAM Cell Array
SRAM Devices
 DRAM Cell

• DRAM cell: One transistor and one capacitor

• 1/0 = capacitor charged/discharged
• SRAM cell: Six transistors – Costs 3 times more (cell complexity)
• Cost per bit is less for DRAM – reason for why large memories are
DRAMs
DRAM Bit Slice
DRAM Including Refresh Logic
 Dynamic memory
 Dynamic memory is built with capacitors.
 A stored charge on the capacitor represents a logical 1.
 No charge represents a logic 0.

 However, capacitors lose their charge after a few milliseconds. The memory
requires constant refreshing to recharge the capacitors. (That’s what’s
“dynamic” about it.)

 Dynamic RAMs tend to be physically smaller than static RAMs.

 A single bit of data can be stored with just one capacitor and one
transistor, while static RAM cells typically require 4-6 transistors.
 This means dynamic RAM is cheaper and denser—more bits can be
stored in the same physical area.
What is a Counter? EXAMPLE: 74LS163 SYNCHRONOUS 4BIT COUNTER
A counter is a device which count and store the number of time any particular event or process
have occurred, depending on a clock signal. Each clock pulse either increase the number or
decrease the number.

The counter is mainly composed of flip-flops. According to the flip order of flip-flops, the
counter can be divided into synchronous and asynchronous (Ripple counters).

In a synchronous counter, all flip-flops flip at the same time when the count pulse is input;
while in an asynchronous counter, the flip-flops at all levels are not flipped simultaneously.

If increase or decrease of the number in the counter ---up/down counter .

The advantages of the Synchronous counter is as follows-
1. It’s easier to design than the Asynchronous counter.
2. It acts simultaneously.
3. No propagation delay associated with it.
4. Count sequence is controlled using logic gates, error chances are
lower.
5. Faster operation than the Asynchronous counter.
6. Although there are many advantages, one major disadvantage of
working with Synchronous counter is that it requires a lot of extra
logic to perform.

Use of Synchronous Counter

Few applications where Synchronous counters are used-
1. Machine Motion control
2. Motor RPM counter
3. Rotary Shaft Encoders
4. Digital clock or pulse generators.
5. Digital Watch and Alarm systems.
 Synchronous Up Counter

Synchronous Down Counter

4 bit-Synchronous Decade Counter

SHIFT REGISTER
• Basic shift register functions
• Serial in/serial out shift registers
• Serial in/parallel out shift registers
• Parallel in/serial out shift registers
……..74HCT165 - 8-bit parallel-in/serial out shift register
• Parallel in/parallel out shift registers
• Bidirectional shift registers
– Data storage and
– Data movement
• The storage capacity of a register is the total number of bits it can retain.
• Shift registers consists of an arrangement of flips-flops
– Each stage (flip-flop) in a shift register represents one bit of storage capacity.
– The shifting capacity permits the movement of data from stage to stage within the register or
into or out of the register upon application of clock pulses.
• The basic difference between a register and a counter is that a register has no
specified sequence of states, except in certain very specialized applications.
• A register is used only for STORING AND SHIFTING DATA
 Serial in/serial out shift registers
• It accepts data serially, one bit at a time on a
single line, and produces the sorted
information on its output also in a serial form
 Serial in/serial out shift registers
• 4 bit register
• It needs 4 clock pulses to store 4 bits
• Example:
– Illustrate entry of the 4 bits 1010 into the register.
– Illustrate serially shifting the 4 bits out of the register, i.e. clearing the
register.
Example: Show the states of the 5-bit shift register for the specified
data input and clock waveforms. The registered is initially cleared.
Serial in/parallel out shift registers
• Data bits are entered serially as illustrated
before
• Once the data are stored, the output of each
stage is available on its output line.
Serial in/parallel out shift registers
• 4-bit register
Serial in/parallel out shift registers
• Example: Show the state of the 4-bit register foe
the data input and clock waveforms. The register
initially contains all 1s.
 Serial In/Parallel Out Shift Registers
• 8-bit serial in/parallel out
 Parallel In/Serial Out Shift Registers
– The bits are entered simultaneously into their respective
stages.
– The serial output appears bit by bit per clock pulse.
– To store 4 bits, we need 1 clock pulse
– To shift them out them, we need another 3 clock pulses.
• 4-bit parallel in/serial out
Parallel In/Serial Out Shift Registers
4-bit parallel in/serial out
• 4-bit parallel in/serial out
 Parallel In/Parallel Out Shift Registers
• The bits are entered simultaneously into their respective
stages.
• Immediately, the bits appear on the parallel outputs.

4-bit version
 Parallel In/Parallel Out Shift Registers
• 4-bit version
 Parallel In/Parallel Out Shift Registers

• 4-bit version
 Bidirectional Shift Register
• A bidirectional shift register is one in which
the data can be shifted either left or right.

4-bit version
Bidirectional 4-bit Shift Register
Bidirectional 4-bit Shift Register
Universal Shift Register

S0=0, s1=0,