2822 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 39, NO.

10, OCTOBER 2020

GAN-OPC: Mask Optimization With

Lithography-Guided Generative Adversarial Nets
Haoyu Yang , Shuhe Li, Zihao Deng, Yuzhe Ma , Bei Yu , Member, IEEE, and Evangeline F. Y. Young

Abstract—Mask optimization has been a critical problem in

the VLSI design flow due to the mismatch between the lithog-
raphy system and the continuously shrinking feature sizes.
Optical proximity correction (OPC) is one of the prevailing res-
olution enhancement techniques (RETs) that can significantly
improve mask printability. However, in advanced technology
nodes, the mask optimization process consumes more and more
Fig. 1. Conventional OPC flow and lithography process, where OPC is very
computational resources. In this article, we develop a genera- time consuming.
tive adversarial network (GAN) model to achieve better mask
optimization performance. We first develop an OPC-oriented
GAN flow that can learn target-mask mapping from the improved
architecture and objectives, which leads to satisfactory mask be obtained with subresolution assist features (SRAF) [16].
optimization results. To facilitate the training process and ensure Awad et al. [5] proposed a pattern fidelity aware mask
better convergence, we propose a pretraining scheme that jointly optimization algorithm that optimizes core polygons by simul-
trains the neural network with inverse lithography technique taneously shifting adjacent segmentations. Su et al. [7] signif-
(ILT). We also propose an enhanced generator design with a
U-Net architecture and a subpixel super-resolution structure icantly accelerated the OPC flow by extracting representative
that promise a better convergence and a better mask quality, process corners while maintaining a good wafer image qual-
respectively. At convergence, the generative network is able to ity. However, the model-based OPC flows are highly restricted
create quasi-optimal masks for given target circuit patterns and by their solution space, and hence, lacking in reliability for
fewer normal OPC steps are required to generate high quality complicated designs. On the other hand, ILTs minimize the
masks. The experimental results show that our flow can facil-
itate the mask optimization process as well as ensure a better error between the wafer image and the target with lithography
printability. constraints. Because ILTs conduct pixel-based optimization on
layout masks, they are expected to offer better lithography con-
Index Terms—Convolutional neural networks, generative
model, inverse lithography, optical proximity correction. tour quality, which although comes with additional challenges
on mask manufacturability problems, including manufacturing
cost and mask design rules. Recently, Ma et al. [14] adopted
ILT to simultaneously perform mask optimization and layout
I. I NTRODUCTION decomposition that brings a better solution of multiple pat-
ITH the VLSI technology node continuously shrink- terning mask design. Although the model-based method and
W ing down, the mask optimization process becomes
a great challenge for designers [1]–[4]. Conventional mask
the ILT-based method behave well on a variety of designs,
they take the wafer image as a mask update criterion in each
optimization process is illustrated in Fig. 1, where optical iteration of the OPC process. In other works, multiple rounds
proximity correction (OPC) aims at compensating lithography of lithography simulation are indispensable in the optimization
proximity effects through correcting mask pattern shapes and flow which is drastically time consuming.
inserting assist features. OPC methodologies include model- The explosion of machine-learning techniques has dramat-
based techniques [5]–[7], [7]–[11] and inverse lithography- ically changed the way to solve design for manufacturability
based technique (ILT) [12]–[15]. problems. Recently, both shallow and deep learning models
In model-based OPC flows, pattern edges are fractured have been successfully utilized to estimate mask printabil-
into segments which are then shifted/corrected according to ity, accurately, and efficiently (e.g., [17]–[21]). There are also
the mathematical models. A high printability mask can then several attempts on mask optimization problems that con-
tain more complex regression or classification procedures.
Manuscript received January 4, 2019; revised April 20, 2019 and July 4, Matsunawa et al. [22] conducted segment-based pattern cor-
2019; accepted August 24, 2019. Date of publication September 4, 2019; date rection with hierarchical Bayes model. Gu and Zakhor [23]
of current version September 18, 2020. This work was supported in part by the introduced discrete cosine transform (DCT) features and lin-
Research Grants Council of Hong Kong under Project CUHK24209017. The
preliminary version has been presented at the Design Automation Conference ear regression to predict fragment movement. Luo [24] and
(DAC) in 2018. This article was recommended by Associate Editor S. Held. Choi et al. [25] incorporated artificial neural networks to
(Corresponding author: Haoyu Yang.) estimate mask patterns. However, existing machine-learning
The authors are with the Department of Computer Science and Engineering,
Chinese University of Hong Kong, Hong Kong. models can only perform pixel-wise or segment-wise mask
Digital Object Identifier 10.1109/TCAD.2019.2939329 calibration that is not computationally efficient.
0278-0070 
c 2019 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See https://www.ieee.org/publications/rights/index.html for more information.

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YANG et al.: GAN-OPC: MASK OPTIMIZATION WITH LITHOGRAPHY-GUIDED GENERATIVE ADVERSARIAL NETS 2823

TABLE I
Generative adversarial networks (GANs) have shown pow- S YMBOLS AND N OTATIONS U SED T HROUGHOUT T HIS A RTICLE
erful generality when learning the distribution of a given
dataset [26]–[28]. The basic optimization flow of GAN con-
tains two networks interacting with each other. The first
one is called generator that takes random vectors as input
and generates samples which are as much closer to the true
dataset distribution as possible. The second one is called dis-
criminator that tries to distinguish the true dataset from the
generated samples. At convergence, ideally, the generator is
expected to generate samples that have the same distribution
as true dataset. Inspired by the generative architecture and
the adversarial training strategy, in this article, we propose a
lithography-guided generative framework that can synthesize
quasi-optimal mask with single round forwarding calculation.
The quasi-optimal mask can be further refined by few steps
of normal OPC engine. It should be noted conventional GAN
cannot be directly applied here, due to the following two 4) We enhance the GAN-OPC flow by integrating a U-Net
reasons. and an SPSR structure into the generator that promise
1) Traditional DCGANs [28] are trained to mimic a dataset better model convergence and generated mask quality.
distribution which is not enough for the target-mask 5) The experimental results show that our framework can
mapping procedure. significantly facilitate the mask optimization procedure
2) Compensation patterns or segment movements in the as well as generating mask that has better printability
mask are derived-based upon a large area of local pat- under nominal condition.
terns (e.g., 1000 × 1000 nm2 ) that brings much training The rest of this article is organized as follows. Section II
pressure on the generator. lists basic concepts and problem formulation. Section III
In accordance with these problems, we develop customized discusses the details of GAN-OPC framework, ILT-guided
GAN training strategies for the purpose of mask optimization. training strategies, and enhanced GAN-OPC (EGAN-OPC)
Besides, since layout topology types are limited within spe- framework with the U-Net and SPSR techniques. Section IV
cific area, we automatically synthesize local topology patterns presents the experimental results, followed by the conclusion
based on size and spacing rules. The benefits of the arti- in Section V.
ficial patterns are twofold: 1) we avoid to train the neural
network with large images and facilitate the training procedure II. P RELIMINARIES
significantly and 2) automatically designed patterns are dis-
In this section, we will discuss some preliminaries of the
tributed uniformly and to some extent alleviate the over-fitting
mask optimization and the generative adversarial nets. Major
problem. Observing that most ILTs update the mask through
math symbols with their descriptions are listed in Table I. In
steepest descent that resembles the training procedure in neu-
order to avoid confusion, all the norms || · || are calculated
ral networks, we connect an ILT structure with the generative
with respect to flattened vectors.
networks and pretrain the generator through backpropagat-
The Hopkins theory of the partial coherence imaging system
ing the lithography error to neuron weights. With the above
has been widely applied to mathematically analyze the mask
pretraining phase, the generative model converges faster than
behavior of lithography [31]. Because the Hopkins diffraction
training from random initialized neuron weights. Observe that
model is complex and not computational friendly, [32] adopts
GANs are typically much deeper than regular neural networks
the singular value decomposition (SVD) to approximate the
which bring inevitable training challenges. We further enhance
original model with a weighted summation of the coherent
the framework with an advanced generator design that inte-
systems
grates the U-Net [29] and the subpixel super-resolution (SPSR)
2
structure [30] which are more computationally efficient, 
N
promise faster convergence, and provide better mask image I= wk |M ⊗ hk |2 (1)
quality. The main contributions of this article are listed as k=1
follows. where hk and wk are the kth kernel and its weight. As sug-
1) We synthesize training patterns to enhance the compu- gested in [13], we pick the Nhth order approximation to the
tational efficiency and alleviate the over-fitting problem. system. Equation (1) becomes
2) We propose an ILT-guided pretraining flow to initialize
the generator which can effectively facilitate the training 
Nh

procedure. I= wk |M ⊗ hk |2 . (2)
3) We design new objectives of the discriminator to make k=1

sure the model is trained toward a target-mask mapping The lithography intensity corresponds to the exposure level
instead of a distribution. on the photoresist that controls the final wafer image. In real

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2824 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 39, NO. 10, OCTOBER 2020

Fig. 2. Different types of defects. Same lithography images result in different

EPE violation counts due to different choices of measurement points. Some
defects are not detectable through merely checking EPE.

design and sign-off flow, it is far from enough to use con-

stant threshold model to analyze resist images, especially for Fig. 3. Conventional GAN architecture.
advanced technology node. For the methodology verification
purpose only and for simplicity, we still adopt the simple con-
stant threshold resist model throughout the experiments, which the PV bands. Following above terminologies, we define the
is consistent with the ICCAD 2013 CAD contest settings [33]. mask optimization problem as follows.
In the constant threshold resist model [34], only area with Problem 1 (Mask Optimization): Given a target image Zt ,
intensity greater than a certain threshold will contribute to the the objective of the problem is generating the corresponding
final wafer image, as mask M such that remaining patterns Z after lithography pro-
 cess is as close as Zt or, in other word, minimizing the squared
1, if I(x, y) ≥ Ith L2 error of lithography images.
Z(x, y) = (3)
0, if I(x, y) < Ith .
III. F RAMEWORKS
Mask quality is evaluated through the fidelity of its wafer
A. GAN-OPC
image with respect to the target image. Edge placement error
(EPE), bridge, and neck are three main types of defect detec- A classical GAN architecture comprises a generator and a
tors that are adopted in a layout printability estimation flow. discriminator. The generator accepts random vectors z ∼ pz as
As shown in Fig. 2, EPE measures horizontal or vertical dis- the input and generates samples G(z; W g ) that follows some
tances from the given points (i.e., EPE measurement sites) on distribution pg , where G is a convolutional neural networks
target edges to lithography contours. Neck detector checks the parameterized by W g . The discriminator acts as a classifier that
error of critical dimensions of lithography contours compared distinguishes G(z; W g ) and the instance drawn from a data dis-
to the target patterns, while bridge detector aims to find unex- tribution pd . The output D(x; W d ) represents the probabilities
pected short of wires. Note that unlike EPE violations, bridge, of x drawn from pd and pg . It should be noted that the origi-
and neck defects can appear in any directions. Because EPE nal settings are not well suitable for the mask optimization
violations could happen with good critical dimension and neck problem. In this section, we will introduce the details of
or bridge occurs with small EPE, none of these defect types our framework, including OPC-oriented GAN architecture and
individually can be an ideal representation of mask printabil- advanced training strategies.
ity. Considering the objective of mask optimization is to make 1) Generator Design: From the previous discussion, we
sure the remaining patterns after lithography process are as can notice that the generator learns a distribution of a given
close as target patterns, we pick the squared L2 error as the dataset, which is originally designed as a mapping function
metric of lithography quality since a smaller L2 indicates a G : pz → pg , where pz is a distribution that input vectors are
better wafer image quality. drawn and pg denotes the distribution of the training set. The
Definition 1 (Squared L2 Error): Let Zt and Z as target objective of the generator is to generate samples that deceive
image and wafer image, respectively, the squared L2 error of the discriminator as much as
Z is given by ||Zt − Z||22 . max Ez∼pz [ log(D(G(z)))] (4)
In real manufacturing scenario, lithography conditions
(e.g., focus, dose) are usually not fixed as we expected, which which maximizes the log-likelihood of the discriminator giving
results in variations of wafer images. To measure the robust- predictions that generated samples are real. Correspondingly,
ness of the designed mask, process variation (PV) bands are the generator comprises a deconvolutional architecture that
proposed [35]. The mathematical definition can be found as casts 1-D vectors back to 2-D images through stacked decon-
follows. volution operations, as shown in Fig. 3.
Definition 2 (PV Bands): Given the lithography simulation Our framework, however, is expected to perform mask
contours under a set of process conditions, the PV bands is optimization on given target circuit patterns and obviously vio-
the area among all the contours under these conditions. lates the deconvolutional architecture. To resolve this problem,
In this article, for simplicity, we use the XOR between the we design a generator based on autoencoder [36] which con-
innermost and the outermost images as an approximation of sists of an encoder and a decoder subnets. As depicted in

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YANG et al.: GAN-OPC: MASK OPTIMIZATION WITH LITHOGRAPHY-GUIDED GENERATIVE ADVERSARIAL NETS 2825

Fig. 4, the encoder is a stacked convolutional architecture Algorithm 1 GAN-OPC Training

that performs hierarchical layout feature abstractions and the 1: for number of training iterations do
decoder operates in an opposite way that predicts the pixel- 2: Sample m target clips Z ← {Zt,1 , Zt,2 , . . . , Zt,m };
based mask correction with respect to the target based on key 3: W g ← 0, W d ← 0;
features obtained from the encoder. 4: for each Zt ∈ Z do
2) Discriminator Design: The discriminator is usually an 5: M ← G(Zt ; W g );
ordinary convolutional neural networks that perform classifica- 6: M∗ ← Groundtruth mask of Zt ;
tion to distinguish the generated samples from the given data 7: lg ← − log(D(Zt , M)) + α||M∗ − M||22 ;
samples as 8: ld ← log(D(Zt , M)) − log(D(Zt , M∗ ));
∂lg ∂ld
max Ex∼pd [ log(D(x))] + Ez∼pz [ log(1 − D(G(z)))]. (5) 9: W g ← W g + ; W d ← W d + ;
∂W g ∂W g
In this article, the discriminator predicts whether an input 10: end for
λ λ
instance is the generated mask M or the reference mask M∗ 11: W g ← W g − W g ; W d ← W d − W d ;
which is the ground truth OPC’ed mask generated by a state- m m
12: end for
of-the-art academic OPC tool [13]. However, the discriminator
in (5) is necessary but not sufficient to ensure generator to
obtain a high quality mask (Fig. 3). Consider a set of target
patterns Z = {Zt,i , i = 1, 2, . . . , N} and a corresponding ref-
erence mask set M = {M∗i , i = 1, 2, . . . , N}. Without loss of
generality, we use Zt,1 in the following analysis. Suppose the
above GAN structure has enough capacity to be well trained,
the generator outputs a mask G(Zt,1 ) that optimizes the objec-
tive function as in (4). Observe that log(D(G(Zt,1 ))) reaches
its maximum value as long as
G(Zt,1 ) = M∗i , ∀i = 1, 2, . . . , N. (6)
Therefore, a one-to-one mapping between the target and the
reference mask cannot be guaranteed with current objectives.
To address above concerns, we adopt a classification scheme
that predicts positive or negative labels on target-mask pairs
that inputs of the discriminator will be either (Zt , G(Zt ))
or (Zt , M∗ ), as illustrated in Fig. 4. Claim that G(Zt ) ≈
M∗ at convergence with new discriminator. We still assume
enough model capacity and training time for convergence. The
discriminator now performs prediction on target-mask pairs Fig. 4. Proposed GAN-OPC architecture.
instead of masks. Because only pairs {Zt,i , M∗i } are labeled as
data, the generator can deceive the discriminator if and only if
G(Zt,i ) ≈ M∗i , ∀i = 1, 2, . . . , N, where N is the total number The previous analysis shows that the generator and the
of training instances. discriminator have different objectives, therefore, the two sub-
3) GAN-OPC Training: Based on the OPC-oriented GAN networks are trained alternatively, as shown in Fig. 5(a) and
architecture in our framework, we tweak the objectives of G Algorithm 1. In each training iteration, we sample a mini-batch
as follows: of target images (line 2); gradients of both the generator and
max EZt ∼Z [ log(D(Zt , G(Zt )))] (7) the discriminator are initialized to zero (line 3); a feed forward
G
calculation is performed on each sampled instances (lines 4
and for the discriminator D, we have and 5); the ground truth mask of each sampled target image is
max EZt ∼Z [ log(D(Zt , M∗ ))] obtained from OPC tools (line 6); we calculate the loss of the
D
generator and the discriminator on each instance in the mini-
+ EZt ∼Z [1 − log(D(Zt , G(Zt )))]. (8)
batch (lines 7 and 8); we obtain the accumulated gradient of
In addition to facilitate the training procedure, we minimize losses with respect to neuron parameters (lines 9 and 10);
the differences between generated masks and reference masks finally, the generator and the discriminator are updated by
when updating the generator as descending their mini-batch gradients (lines 11 and 12). Note
minEZt ∼Z ||M∗ − G(Zt )||n (9) that in Algorithm 1, we convert the min–max problem in (10)
G into two minimization problems such that gradient ascending
where || · ||n denotes the ln norm. Combining (7)–(9), the operations are no longer required to update neuron weights.
objective of our GAN model becomes Algorithm 1 differs from traditional GAN optimization flow
on the following aspects.
min max EZt ∼Z [1 − log(D(Zt , G(Zt ))) + ||M∗ − G(Zt )||nn ]
G D 1) The generator plays as a mapping function from target
+ EZt ∼Z [ log(D(Zt , M∗ ))]. (10) to mask instead of merely a distribution, therefore, the

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2826 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 39, NO. 10, OCTOBER 2020

gradient of L2 loss is backpropagated along with the Algorithm 2 ILT-Guided Pretraining

information from the discriminator. 1: for number of pre-training iterations do
2) The discriminator functions as an alternative of ILT 2: Sample m target clips Z ← {Zt,1 , Zt,2 , . . . , Zt,m };
engine that determines only the quality of generated 3: W g ← 0;
masks without any calibration operations. Besides, our 4: for each Zt ∈ Z do
combined input ensures that the discriminator will make 5: M ← G(Zt ; W g );
positive prediction if and only if the generated mask is 6: Z ← LithoSim(M) Equations (2)–(3)
much close to the ground truth, which also helps train 7: E ← ||Z − Zt ||22 ;
the generator better. ∂E ∂M
8: W g ← W g + ; Equation (14)
∂M ∂W g
9: end for
B. ILT-Guided Pretraining λ
10: W g ← W g − W g ; Equation (15)
Although with the OPC-oriented techniques, GAN is able m
11: end for
to obtain a fairly good performance and training behavior,
it is still a great challenge to train the complicated GAN
model with satisfactory convergence. Observing that ILT and
neural network training stage share similar gradient descent
techniques, we develop an ILT-guided pretraining method to
initialize the generator, after which the alternative mini-batch
gradient descent is discussed as a training strategy of GAN (a)
optimization. The main objective in ILT is minimizing the
lithography error through gradient descent

E = ||Zt − Z||22 (11)

where Zt is the target and Z is the wafer image of a given mask. (b)
Because mask and wafer images are regarded as continuously
Fig. 5. (a) GAN-OPC training and (b) ILT-guided pretraining.
valued matrices in the ILT-based optimization flow, we apply
translated sigmoid functions to make the pixel values close to
either 0 or 1 the input layer while neural weights are updated as follows:
Z=
1 λ
1 + exp [−α × (I − Ith )]
(12) Wg = Wg − W g (15)
m
1 where W g is accumulated gradient of a mini-batch of
Mb = (13)
1 + exp(−β × M) instances and m is the mini-batch instance count. Because (15)
where Ith is the threshold matrix in the constant resist model is naturally compatible with ILT, if we create a link between
with all the entries being Ith , Mb is the incompletely binarized the generator and the ILT engine, the wafer image error can
mask, while α and β control the steepness of relaxed images. be backpropagated directly to the generator as presented in
Combining (1)–(3), (11)–(13), and the analysis in [12], we Fig. 5.
can derive the gradient representation as follows: The generator pretraining phase is detailed in Algorithm 2.
In each pretraining iteration, we sample a mini-batch of target
∂E layouts (line 2) and initialize the gradients of the generator
= 2αβ × Mb  (1 − Mb )
∂M W g to zero (line 3); the mini-batch is fed into the generator
(((Z − Zt )  Z  (1 − Z)  (Mb ⊗ H∗ )) ⊗ H to obtain generated masks (line 5). Each generated mask is
+ ((Z − Zt )  Z  (1 − Z)  (Mb ⊗ H)) ⊗ H∗ ) (14) loaded into the lithography engine to obtain a wafer image
(line 6); the quality of wafer image is estimated by (11)
where H∗ is the conjugate matrix of the original lithography (line 7); we calculate the gradient of lithography error E with
kernel H. In traditional ILT flow, the mask can be optimized respect to the neural networks parameter W g through the chain
through iteratively descending the gradient until E is below a rule, i.e., (∂E/∂M)(∂M/∂W g ) (line 8); finally, W g is updated
threshold. following the gradient descent procedure (line 10).
The objective of mask optimization problem indicates the Compared to the training toward ground truth (i.e., directly
generator is the most critical component in GAN. Observing backpropagating the mask error to neuron weights), ILT-
that both ILT and neural network optimization share simi- guided pretraining provides step-by-step guidance when
lar gradient descent procedure, we propose a jointed training searching for a solution with high quality, which reduces
algorithm that takes advantages of ILT engine, as depicted in the possibility of the generator being stuck at local mini-
Fig. 5(b). We initialize the generator with lithography-guided mum region in an early training stage. Because ILT contains
pretraining to make it converge well in the GAN optimization complicated convolutions and matrix multiplications that are
flow thereafter. The key step of neural network training is computational expensive, we approximate the pretraining stage
backpropagating the training error from the output layer to through backpropagating errors of intermediate masks, which

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YANG et al.: GAN-OPC: MASK OPTIMIZATION WITH LITHOGRAPHY-GUIDED GENERATIVE ADVERSARIAL NETS 2827

a tensor with shape H × W × r2 C into shape rH × rW × C as

hr
ti,j,k = tilr ,j ,k (16a)
i
i =   (16b)
r
j
j =   (16c)
r
k = C · r · mod(j, r) + C · mod(i, r) + k (16d)

where · is the math floor operator, mod(x, y) finds the

Fig. 6. New generator architecture with concatenation of intermediate feature
i ,j ,k denotes the (i, j, k)
hr , and tlr
remainder of x divided by y, ti,j,k
maps and an SPSR structure.
  
and (i , j , k ) entry of high resolution images (or feature maps)
and low resolution images (or feature maps), respectively. It
should be noted that (16) represents only a reshape operation
“guides” the generator toward optimality. We only adopt the
which is still differentiable as other convolution layers. SPSR
ILT engine in the pretraining stages and replace it with the
has several advantages compared to Fig. 7(a).
discriminator in the main training stage, where the generator
1) SPSR is ideally r2 times faster than the strided deconvo-
is optimized in an adversarial style.
lution operation. As shown in Fig. 7, same convolution
kernels have to scan over a r2 larger feature maps in
traditional deconvolution layers to achieve same output
C. Enhanced GAN-OPC Framework
tensor size as SPSR layers.
In this section, we will introduce the EGAN-OPC frame- 2) SPSR layers reduce noises in generated masks by a sig-
work, which significantly improves the training efficiency nificant amount, as can be seen in Fig. 8. Such results
in a more elegant way compared to pretraining with ILT can be explained by the fact that explicit interpolations
engine. The EGAN-OPC framework includes a U-Net struc- are removed in SPSR structure, where the upscaling and
ture that allows gradients to be easily backpropagated to early rendering are automatically learned during the network
layers and an SPSR architecture for better generated mask training.
quality. Traditional deconvolution layers, on the other hand, have to
1) U-Net: We have noticed the GANs are typically deeper apply padding or zero insertion to increase the feature map
than traditional neural networks, which brings more challenges size before feeding them into next level convolution layer for
due to a longer gradient backpropagation path. A common rendering, which in turn results in noises (as empty dots) in
solution is creating shortcut links that allow addition or stack- the generated masks because it is hard for limited number
ing of feature maps in different layers [29], [37], [38], such of convolution layers to smooth such noise. On the contrary,
that gradients can be more efficiently backpropagated from SPSR directly organizes the low resolution feature maps into
output layer to early layers. Here, we enhance our genera- the high resolution space, where every pixels are informative,
tive design with a U-Net-like structure where intermediate compared to manually inserted zeros in deconvolution layers.
feature maps in the encoder are stacked at corresponding 3) Enhanced GAN-OPC Architecture: We follow the basic
layers in the decoder, as shown in Fig. 6. Such architec- convolutional autoencoder architecture for the generator
ture has two good properties: 1) the inevitable information design with additional shortcut links for U-Net feature map
loss in strided convolution layer can be drastically reduced sharing and SPSR layers for upscaling. The detailed architec-
and 2) the gradient vanishing problem can be alleviated ture can be found in Table II, where column “Layer” includes
with multiple shortcut links bypassing intermediate feature layer types and layer ID, columns “Filter” and “Stride” list
maps. configurations for convolution layers, “Output” lists the output
2) Subpixel Super-Resolution: In the previous designs, low tensor shape of corresponding layers, and “Parameter” rep-
level features in intermediate generator layers are cast back to resents the total number of trainable parameters of a given
mask images by standard strided deconvolution operation that layer. The proposed generator architecture contains five reg-
can be visualized as in Fig. 7(a). In detail, zeros are inserted ular convolution layers for feature extraction and five SPSR
among existing pixels such that the output dimension after layers for mask image construction. It should be noted that the
a convolution operation reaches the desired value. However, input tensor of the ith SPSR layer has 2× channel numbers
such mechanism requires multiple convolution operations on as the output tensor of the (i − 1)th SPSR layer, because of
high resolution space which is not computational efficient and the existence of U-Net concatenation.
might induce additional noises. The discriminator design is detailed in Table III. The neural
SPSR [30] is another upsampling solution that has been network architecture resembles VGG [39] with more layers
widely used in super-resolution tasks. It conducts convolution and smaller kernels. “repeat2” and “repeat3” indicate two
operations in lower resolution space and generates additional and three consecutive convolution layers with the same con-
feature maps such that the number of feature map entries figurations. We replace all the pooling layers with strided
matches the desired size of target image, as shown in Fig. 7(b). convolution layers to attain information as much as possi-
The major step of SPSR is called periodic shuffling that casts ble. Three densely connected layers are connected following

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2828 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 39, NO. 10, OCTOBER 2020

(a) (b)

Fig. 7. Visualization of (a) standard deconvolution operation and (b) SPSR.

(a) (b)

Fig. 8. Patterns generated from (a) deconvolution layers and (b) SPSR layers.

TABLE II
G ENERATOR C ONFIGURATION

Fig. 9. Framework summary.

D. Framework Summary and Discussion

The proposed GAN-OPC family is summarized in Fig. 9.
With the given training data that includes target patterns and
mask patterns, we propose three alternative solutions to obtain
a trained generator that include direct GAN-OPC proposed in
Section III-A, GAN-OPC with ILT-guided pretraining as in
Section III-B, and the EGAN-OPC solution with U-Net and
SPSR techniques as in Section III-C.
TABLE III Although ILT engines are, to some extent, suffering mask
D ISCRIMINATOR C ONFIGURATION manufacturability (e.g., violation of mask notch rule and mask
spacing rule [7], [11] which are not considered in this arti-
cle) and runtime issues compared to traditional model-based
OPC, our framework still takes advantage of such methodol-
ogy with the following reasons. Our framework is built upon
the structure of conditional GAN that learns a pixel-to-pixel
mapping from the target pattern to the OPC’ed pattern. The
optimization scheme is in a continuous form that compensa-
tion patterns can appear in any shapes and any places within
the clip. Thus, the patterns generated by GAN are inconsistent
with the model-based OPC results (e.g., [6] and [7]), where
compensations are made by moving polygon segments inward
or outward. However, we observe that the mask patterns are
naturally compatible with the process of ILT, which becomes
one reason that we choose ILT for our refinement tasks. As
can be seen in the previous works [13], [14], ILT is asso-
ciated with a highly nonconvex optimization problems that
means the mask initialization affects the final results. The ILT
the last convolution layer for final class prediction. The total refinement results outperform direct ILT optimization and also
number of trainable parameters of the discriminator are inten- experimentally demonstrate the effectiveness of the proposed
tionally designed much larger than the generator (88M versus GAN-OPC framework. Another reason that we choose ILT is
39M) in case of model collapsing. that theoretically and intuitively ILT provides a larger solution

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YANG et al.: GAN-OPC: MASK OPTIMIZATION WITH LITHOGRAPHY-GUIDED GENERATIVE ADVERSARIAL NETS 2829

TABLE IV
D ESIGN RULES U SED

(a) (b)

Fig. 10. Example of (a) target and (b) reference mask pair.

space in mask optimization problems and tends to offer better

mask quality. There are two major advantages of our proposed
framework.
1) Compared to ILT itself, the GAN-OPC family offers a
better starting point for ILT optimization that promises Fig. 11. GAN-OPC flow: generator inference and ILT refinement.
faster convergence and better mask quality.
2) Compared to the model-based OPC, the proposed frame-
work attains good properties of ILT, i.e., a lager solution with size 2048 × 2048. Therefore, we perform 8 × 8 average
space that has the potential to generate better pattern pooling on layout images before feeding them into the neu-
compensation for better mask printability. ral networks. In the generation stage we adopt simple linear
Although we did not consider the mask notch and spacing interpolation to convert the layout images back to their original
rule in our framework, it is straightforward to conduct mask resolution.
manufacturability rule check on the generated masks, and fix
the violated region by making minor pixel changes in the gen- B. Evaluation of GAN-OPC and PGAN-OPC
erated masks. Actually, if the ground truth masks used for The proposed GAN-OPC flow is illustrated in Fig. 11,
training can meet the mask manufacturability requirements, the where we first feed target patterns into the generator and obtain
GAN-OPC framework is supposed to capture these rules dur- the quasi-optimal masks, followed by refinement through an
ing training, because the discriminator is specifically designed ILT engine. In the first experiment, to verify the effective-
to tell whether the generated masks are good or not. Here, a ness of ILT-guided pretraining algorithm, we record training
“good” mask refers to the mask that has good printability and behaviors of two GANs which are denoted by GAN-OPC and
good manufacturability. PGAN-OPC. Here, “GAN-OPC” and “PGAN-OPC” denote
GAN-OPC flow without generator pretraining and GAN-OPC
IV. E XPERIMENTAL R ESULTS flow with ILT-guided pretraining, respectively. “ILT” corre-
sponds to MOSAIC_fast in [13]. The training procedure is
The GAN for mask optimization is implemented based
depicted in Fig. 12, where x-axis indicates training steps and
on Tensorflow [40] library and tested on single
y-axis is L2 loss between generator outputs and ground truth
Nvidia Titan X. The lithography engine is based on the
masks, as in (9).
lithosim_v4 package from ICCAD 2013 CAD con-
The training time for both GAN and PGAN are around
test [33], which also provides ten industrial M1 designs on
10 h on our platform. Although L2 loss of GAN-OPC drops
32-nm design node. We pick Nh = 24, α = 50, and β = 4
slightly faster before 3000 iterations, the training curve shows
for the lithography simulation procedure. The ILT refinement
that PGAN-OPC is a more stable training procedure and
will be stopped if the average gradient per pixel as calcu-
converges to a lower loss. Besides, it takes much more
lated in 14 is smaller than 5 × 10−4 . Related parameters are
efforts for GAN-OPC to search a direction to descending the
chosen according to the experimental results on one test case.
gradient fast, while the training loss of PGAN-OPC drops
The OPC framework applies 8-nm resolution during the initial
smoothly and converges at a lower L2 loss than GAN-OPC,
mask generation stage and 1-nm resolution for refinement.
which indicates ILT-guided pretraining indeed facilitates mask-
optimization-oriented GAN training flow. We will also show
A. Synthesizing Training Data that PGAN-OPC exhibits better mask optimization results in
As a type of deep neural networks, GAN can be hardly the following section.
well trained with only ten instances. To verify our framework, In the second experiment, we optimize the ten layout masks
we synthesize a training layout library with 4000 instances in ICCAD 2013 contest benchmark [33] and compare the
based on the design specifications from existing 32 nm M1 results with the previous work, as listed in Table V. Here,
layout topologies. We adjust the wire sizes to make sure the the wafer images are calculated from the simulation tool
shapes in synthesized layouts are similar to those in the given (lithosim_v4) in the contest [33]. Note that all the GAN-
benchmark. To generate experimental cells, all the shapes are OPC and PGAN-OPC results are refined by an ILT engine
randomly placed together based on simple design rules, as which generates final masks to obtain wafer images. Column
detailed in Table IV. An example of such synthesized target- “L2 ” is the squared L2 error between the wafer image and the
reference mask pair can be found in Fig. 10. In addition, most target image under nominal condition. Column “PVB” denotes
generative models have shown obvious weakness in image the contour area variations under ±2% dose error and defo-
details, which makes it extremely hard to optimize images cus range of ±25 nm settings as in the contest. It is notable

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2830 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 39, NO. 10, OCTOBER 2020

TABLE V
C OMPARISON W ITH S TATE - OF - THE -A RT

(a) (b)

Fig. 14. Some wafer image details of (a) ILT [13] and (b) PGAN-OPC.

Fig. 12. Training curves of GAN-OPC and PGAN-OPC.

Fig. 15. Training behavior of the EGAN-OPC framework with faster and
better convergence.

Fig. 13. Average runtime comparison of different methods.

takes 0.2 s for each image which is ignorable, therefore, run-
time of our flow is almost determined by ILT refinements.
Runtime of different frameworks are illustrated in Fig. 13.
that GAN-OPC significantly reduces squared L2 error of wafer Items ILT, “Model-Based,” GAN-OPC, and PGAN-OPC list
images under the nominal condition by 9% and with the the average mask optimization time of [6] and [13], GAN-
ILT-guided pretraining, squared L2 error is slightly improved OPC, and PGAN-OPC, respectively. For most benchmark
and PVB is further reduced by 1%. We also compared this cases, GAN-OPC and PGAN-OPC show a earlier stop at a
article with one academic state-of-the-art model-based OPC smaller L2 error and, on average, reduce the optimization run-
engine [6], which exhibits larger L2 error (42 196.4) and worse time by more than 50%. We also observe that model-based
PVB (59 828.3 nm2 ) compared to GAN-OPCs. OPC engine shows advantages on execution time at the cost of
Because we only focus on the optimization flow under the wafer image quality as well as PVB area, as shown in Table V.
nominal condition and no PVB factors are considered, our For most test cases, [13] exhibits a smaller PV band area pos-
method only achieves comparable PVB areas among ten test sibly because the printed images are more likely to have large
cases. Additionally, feed-forward computation of GAN only wafer image CD and shorter wire length, which makes masks

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YANG et al.: GAN-OPC: MASK OPTIMIZATION WITH LITHOGRAPHY-GUIDED GENERATIVE ADVERSARIAL NETS 2831

Fig. 16. Result visualization of PGAN-OPC, EGAN-OPC, and ILT. Columns correspond to ten test cases from ICCAD 2013 CAD contest. Rows from top
to bottom are: (a) masks of [13]; (b) wafer images by masks of [13]; (c) masks of PGAN-OPC; (d) wafer images by masks of PGAN-OPC; (e) masks of
Enhanced GAN-OPC; (f) wafer images by masks of Enhanced GAN-OPC; and (g) target patterns.

suffer less proximity effects while inducing bridge or line-end results can also be found in column “EGAN-OPC” of Table V.
pull back defects, as shown in Fig. 14. EGAN-OPC outperforms PGAN-OPC and GAN-OPC on most
test cases with better L2 error (39 500 versus 39 948) and
C. Evaluation of Enhanced GAN-OPC smaller PVB area (48 917 nm2 versus 49 957 nm2 ) with only
70% average runtime of PGAN-OPC (see Fig. 13), which
Here, we show the effectiveness and the efficiency of the demonstrates the efficiency of EGAN-OPC framework. It
EGAN-OPC framework. In the first experiment, we illustrate should be also noted that EGAN-OPC can be trained end-to-
the training behavior of PGAN-OPC and the EGAN-OPC end without any interaction with the lithography engine which
frameworks as shown in Fig. 15. Red curve stands for the induces a large amount of computational cost in PGAN-OPC.
original PGAN-OPC model, which fluctuates fiercely around
a large value. Dark curve refers to the results with U-Net gen-
erator. Blue curve represents the complete version of enhanced
GAN model with both U-net structure and the embedded SPSR D. On the Scalability of GAN-OPC Family
structure. It is encouraging to see that U-net alone can already In order to verify the scalability of our frameworks, we
ensure a good convergence in terms of L2 loss. As we have conduct further experiments on ten additional testcases that
pointed out in algorithm section, such structure attains the neu- contain more patterns and larger total pattern areas. Similar
ral network capacity with significantly lower computational to [7], these ten testcases are created from the original IBM
cost, which is consistent with the trends of L2 error during benchmarks with additional geometries. The results of one
training. example can be found in Fig. 17. It can be seen that our frame-
In the second experiment, we compare the mask work generalizes to more complex patterns. We also visualize
optimization results of the EGAN-OPC with original GAN- the ILT convergence in terms of different mask initialization
OPC and PGAN-OPC, as depicted in Fig. 16. The quantitative in Fig. 18. Here, we use testcase 18 as an example. It can be

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2832 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 39, NO. 10, OCTOBER 2020

TABLE VI
E XPERIMENTS ON L ARGER B ENCHMARKS

(a) (b) (c)

Fig. 17. Larger-case example of (a) mask pattern, (b) its wafer image, and
the (c) corresponding target pattern.

Fig. 19. Average runtime comparison on larger benchmarks.

V. C ONCLUSION
In this article, we have proposed a GAN-based mask
optimization flow that takes target circuit patterns as input
and generates quasi-optimal masks for further ILT refinement.
(a) (b) We analyze the specialty of mask optimization problem and
design OPC-oriented training objectives of GAN. Inspired by
Fig. 18. Visualization of convergence during ILT refinement. (a) L2 and
(b) PV band. the observation that ILT procedure resembles gradient descent
in backpropagation, we develop an ILT-guided pretraining
algorithm that initializes the generator with intermediate ILT
seen that ILT converges much faster when using the mask ini- results, which significantly facilitates the training procedure.
tialized by EGAN-OPC as input, with only ignorable PV band We also enhance the GAN-OPC flow by integrating U-Net and
penalty. We did not compare the performance with the model- SPSR layers in the generator that ensures better model conver-
based OPC as the binary release in [6] encounters unknown gence and mask quality. The experimental results show that
failure on the new benchmarks. our framework not only accelerates ILT but also has the poten-
We list the detailed optimization results in Table VI, where tial to generate better masks through offering better starting
columns are defined exactly the same as Table V. It can points in ILT flow.
be seen that GAN-OPC exhibits tradeoffs on nominal image
quality and PVB compared to pure ILT, while both PGAN- R EFERENCES
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in Proc. IEEE/ACM Int. Conf. Comput.-Aided Design (ICCAD), 2016, with the Department of Computer Science and
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hotspot detection: A deep learning approach,” J. Micro Nanolithography He has interned with ASML, San Jose, CA,
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received the 2019 Nick Cobb Scholarship by SPIE
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May 2008. 2019, where he is currently pursuing the M.Sc.
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2834 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 39, NO. 10, OCTOBER 2020

Zihao Deng received the B.Sc. degree (First Class Bei Yu (S’11–M’14) received the Ph.D. degree from
Hons.) in computer science from the Chinese the University of Texas at Austin, Austin, TX, USA,
University of Hong Kong, Hong Kong, in 2019. in 2014.
His current research interests include machine He is currently an Assistant Professor with the
learning algorithms, deep neural networks, and Department of Computer Science and Engineering,
information theory. Chinese University of Hong Kong, Hong Kong.
Dr. Yu was a recipient of the five Best Paper
Awards from Integration, the VLSI Journal in 2018,
the International Symposium on Physical Design in
2017, the SPIE Advanced Lithography Conference
in 2016, the International Conference on Computer
Aided Design in 2013, and the Asia and South Pacific Design Automation
Conference in 2012, and five ICCAD/ISPD Contest Awards. He is the
Editor-in-Chief of the IEEE Technical Committee on Cyber-Physical Systems
Newsletter. He has served as the TPC Chair for ACM/IEEE Workshop on
Machine Learning for CAD, many journal editorial boards, and conference
committees.

Evangeline F. Y. Young received the B.Sc. degree

in computer science from the Chinese University
of Hong Kong (CUHK), Hong Kong, and the
Ph.D. degree from the University of Texas at Austin,
Austin, TX, USA, in 1999.
She is currently a Professor with the Department
of Computer Science and Engineering, CUHK. She
was actively on floorplanning, placement, routing,
DFM, and EDA on physical design in general. Her
current research interests include optimization, algo-
rithms, and very large-scale integration CAD.
Yuzhe Ma received the B.E. degree from Prof. Young’s research group has won several championships and prizes
the Department of Microelectronics, Sun Yat-sen in renown EDA contests, including the 2016, 2015, 2013, and 2012 CAD
University, Guangzhou, China, in 2016. He is Contests at ICCAD, DAC 2012, and ISPD 2011 Routability-driven Placement
currently pursuing the Ph.D. degree with the Contests and ISPD 2010 High-Performance Clock Network Synthesis Contest.
Department of Computer Science and Engineering, She also served on the Editorial Boards for the IEEE T RANSACTIONS
Chinese University of Hong Kong, Hong Kong. ON C OMPUTER -A IDED D ESIGN OF I NTEGRATED C IRCUITS AND S YSTEMS ,
He has interned with Cadence Design Systems, ACM Transactions on Design Automation of Electronic Systems and
San Jose, CA, USA, and NVIDIA Research, Austin, Integration, and Very Large Scale Integration Journal. She has served on
TX, USA. His current research interests include very the organization committees for ISPD, ARC, and FPT and on the program
large-scale integration design for manufacturing, committees of conferences, including DAC, ICCAD, ISPD, ASP-DAC, SLIP,
physical design, and machine learning on chips. DATE, and GLSVLSI.

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